Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and an electronic device, and the method comprises the steps: providing a semiconductor substrate, and forming a to-be-etched material layer on the semiconductor substrate; forming a plurality of discrete axes arranged along the first direction on the to-be-etched material layer, wherein the plurality of axes at least comprise a plurality of first axes; a side wall material layer covering the axes is formed, and the distance between the surfaces, facing each other, of every two adjacent first axes is smaller than or equal to two times of the thickness of the side wall material layer; the side wall material layer is etched so that side walls can be formed on the side walls of the multiple discrete axes, the side walls comprise independent side walls and combined side walls, and gaps between the adjacent first axes are filled with the combined side walls; etching is executed to remove the first axis; and etching the to-be-etched material layer by taking the side wall as a mask. According to the invention, more available key sizes can be provided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] In semiconductor manufacturing processes, sidewall image transfer (SIT) is typically used in conjunction with immersion lithography to combine photoresist patterning and form the gate pattern. In this process, sidewalls are first formed on the sidewalls of the axis, then the axis is removed, and etching is performed using the sidewalls as a mask to form the gate structure. The critical dimension of the resulting gate structure is the same as the width of the sidewalls, leaving limited usable critical dimensions. Summary of the Invention

[0003] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0004] To address the existing problems, one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0005] A semiconductor substrate is provided, on which a material layer to be etched is formed;

[0006] A plurality of discrete axes are formed on the material layer to be etched, arranged along a first direction, wherein the axes include at least a plurality of first axes;

[0007] A sidewall material layer is formed covering the axis, wherein the distance between two adjacent surfaces of the first axis facing each other is less than or equal to twice the thickness of the sidewall material layer;

[0008] The sidewall material layer is etched to form sidewalls on the sidewalls of the plurality of discrete axes, the sidewalls including individual sidewalls and merged sidewalls, the merged sidewalls filling the gaps between adjacent first axes;

[0009] Perform etching to remove the first axis;

[0010] The material layer to be etched is etched using the sidewall as a mask.

[0011] For example, along the first direction, the size of the merged sidewall is larger than the size of the individual sidewall.

[0012] Exemplarily, the axis also includes a second axis;

[0013] The process of forming sidewalls on the sidewalls of the plurality of separate axes further includes forming the independent sidewall on the sidewall of the second axis.

[0014] During the etching process, the second axis is retained, and the second axis and the independent sidewall formed on the sidewall of the second axis together serve as a mask to etch the material layer to be etched.

[0015] For example, along the first direction, the size of the second axis is larger than the size of the first axis.

[0016] For example, the etching process includes:

[0017] A first covering layer is formed covering the first axis and the second axis;

[0018] A first photoresist layer is formed on the first cover layer, the window of the first photoresist layer exposes the first axis, and the projection of the second axis on the surface of the material layer to be etched is located inside the projection of the first photoresist layer on the surface of the material layer to be etched.

[0019] Etching is performed using the first photoresist layer as a mask to remove the first axis.

[0020] For example, after removing the first axis and before etching the material layer to be etched using the sidewall as a mask, the method further includes:

[0021] The target sidewalls among the plurality of said sidewalls are etched to reduce the size of the target sidewalls along the first direction, the target sidewalls including at least one of the said independent sidewalls and / or at least one of the said merged sidewalls.

[0022] For example, etching the target sidewall among the plurality of sidewalls includes:

[0023] Forming a second covering layer that covers the multiple sidewalls;

[0024] A second photoresist layer is formed on the second cover layer, and the window of the second photoresist layer exposes the target merging sidewalls to be etched.

[0025] Etching is performed using the second photoresist layer as a mask to reduce the size of the target merged sidewall along the first direction;

[0026] Remove the second photoresist layer and the second capping layer;

[0027] And / or, forming a third covering layer covering the plurality of said sidewalls;

[0028] A third photoresist layer is formed on the third cover layer, and the window of the third photoresist layer exposes the independent sidewall of the target to be etched.

[0029] Etching is performed using the third photoresist layer as a mask to reduce the size of the target independent sidewall along the first direction;

[0030] Remove the third photoresist layer and the third capping layer.

[0031] For example, etching the target sidewall among the plurality of sidewalls includes:

[0032] A fourth covering layer is formed, covering the multiple sidewalls;

[0033] A fourth photoresist layer is formed on the fourth cover layer, and the window of the fourth photoresist layer exposes the target merged sidewall and the target independent sidewall to be etched.

[0034] Etching is performed using the fourth photoresist layer as a mask to reduce the dimensions of the target merged sidewall and the target independent sidewall along the first direction;

[0035] Remove the fourth photoresist layer and the fourth cover layer.

[0036] A second aspect of the present invention provides a semiconductor device, which is manufactured using the method described above.

[0037] A third aspect of the present invention provides an electronic device, the electronic device comprising the semiconductor device described above.

[0038] According to the semiconductor device manufacturing method provided by the present invention, by reducing the distance between the first axes to form a merged sidewall, and using the merged sidewall together with the independent sidewall as a mask to etch the material layer to be etched, more usable critical dimensions can be provided. Attached Figure Description

[0039] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0040] In the attached image:

[0041] Figures 1A to 1F A schematic cross-sectional view of a semiconductor device obtained by sequentially performing the steps of a semiconductor device manufacturing method according to the related art is shown.

[0042] Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0043] Figures 3A to 3J A schematic cross-sectional view of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0045] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] The definition of gate patterning begins with the formation of the core layer through photolithography. In existing technologies, to complement SADP (Self-aligned double patterning) processes, the core layer employs specific critical dimensions. Specifically, such as... Figure 1A As shown, a gate material layer 101 and a gate hard mask layer 102 are first formed on a semiconductor substrate 100, and multiple axes 103 are formed on the gate hard mask layer through processes such as photolithography and etching. Then, as... Figure 1B As shown, a sidewall material layer is deposited on the surface of axis 103 using techniques such as atomic layer deposition, and the top of the sidewall material layer is opened; then as... Figure 1C As shown, the internal axis is removed. Based on this, a photoresist pattern 105 is formed by photolithography to define the pattern of the large critical size gate.

[0050] During the gate etching process, the sidewalls 104 and the photoresist pattern 105 must first be transferred to the lower gate hard mask layer 102, such as... Figure 1E As shown; then the gate material layer 101 is etched through the gate hard mask layer 102, as follows. Figure 1FAs shown. Because the photoresist pattern 105 contains carbon-based materials such as SOC, it easily generates a large number of byproducts. Therefore, an additional in-situ resist removal step is required, which easily leads to defects caused by byproducts and affects the control over the gate morphology. Simultaneously, due to the material difference between the sidewall 104 and the photoresist pattern 105, the loss of the gate hard mask layer 102 caused by the photoresist pattern 105 is greater than the loss caused by the sidewall 104. This also leads to process limitations in the subsequent gate hard mask etching process, preventing the use of a process with a more vertical morphology after etching but relatively poor etching selectivity. Only a process architecture with relatively good etching selectivity but a more slanted morphology can be used.

[0051] In view of the aforementioned technical problems, embodiments of the present invention propose a method for fabricating a semiconductor device. The following refers to... Figure 2 and Figures 3A to 3J The method for fabricating the semiconductor device according to embodiments of the present invention will be described in detail, wherein, Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. Figures 3A to 3J A schematic cross-sectional view of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0052] First, execute step S201, such as Figure 3A As shown, a semiconductor substrate 301 is provided, on which a material layer to be etched is formed. The material of the semiconductor substrate 301 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI).

[0053] The material layer to be etched includes a gate material layer 302 formed on a semiconductor substrate 301 and a gate hard mask layer 303 formed on the gate material layer 302. Exemplarily, the material of the gate material layer 302 can be various materials commonly used in the art, including, but not limited to, doped or undoped polysilicon, polysilicon-germanium alloy materials, and polysilicon metal silicide materials. In this embodiment, the material of the gate material layer 302 is polysilicon, and its formation method includes, but is not limited to, chemical vapor deposition or physical vapor deposition. The gate hard mask layer 303 includes a silicon nitride hard mask layer 303A and a silicon oxide hard mask layer 303B formed on the silicon nitride hard mask layer 303A. The gate hard mask layer can be formed by one or more of the following methods: thermal oxidation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, low-pressure chemical vapor deposition, and selective epitaxial growth.

[0054] Next, step S202 is performed to form a plurality of discrete axes arranged along a first direction on the material layer to be etched. Each axis includes at least a plurality of first axes. When the material layer to be etched includes a gate material layer, the first direction is parallel to the surface of the semiconductor substrate and perpendicular to the direction in which the gate structure extends. Exemplarily, an axis material layer can be formed on the material layer to be etched, and the axis material layer can be etched to form a plurality of discrete axes. The material of the axis material layer may include polycrystalline silicon, amorphous silicon, amorphous carbon, etc.

[0055] In some embodiments, the plurality of shafts further includes a second shaft 304B and / or a third shaft 304C. Exemplarily, the distance between adjacent first shafts 304A is smaller than the distance between the remaining shafts, such as... Figure 3A As shown, the distance D1 between adjacent first axes 304A is less than the distance D1 between adjacent second axes 304B (if there are multiple second axes 304B), the distance D2 between adjacent first axes 304A and second axes 304B, the distance between adjacent third axes 304C (if there are multiple third axes 304C), and the distance D3 between adjacent first axes 304A and third axes 304C. Here, "distance" refers to the distance between the mutually facing surfaces of two adjacent axes. First axes 304A are used to merge sidewall patterns. Further, the width of the second axis 304B is greater than the width of the first axis 304A and greater than the width of the third axis 304C. The width of an axis is its dimension along the first direction. The larger second axis 304B is used for subsequent transfer of large-critical-size gate patterns. The widths of the first axes 304A and the third axes 304C can be equal or unequal.

[0056] Next, proceed to step S203, as follows: Figure 3BAs shown, a sidewall material layer 305 covering the axis is formed, and the distance between the surfaces of two adjacent first axes 304A facing each other is less than or equal to twice the thickness of the sidewall material layer 305. Figure 3B In this structure, a sidewall material layer 305 covers a first axis 304A, a second axis 304B, and a third axis 304C. The sidewall material layer 305 has a high etching selectivity with respect to the axes. As an example, the sidewall material layer 305 is made of silicides, such as silicon oxides, silicon nitrides, or silicon oxide nitrides. Its formation methods include deposition methods commonly used in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Since the distance between two adjacent first axes 304B is less than or equal to twice the thickness of the sidewall material layer 305, the sidewall material layer 305 fills the gap between the two adjacent first axes 304B.

[0057] Next, proceed to step S204, as follows: Figure 3C As shown, the sidewall material layer 305 is etched to form sidewalls on the sidewalls of multiple discrete axes. The sidewalls include independent sidewalls 305A and merged sidewalls 305B, with the merged sidewalls 305B filling the gap between adjacent first axes 304A.

[0058] Specifically, the sidewalls include independent sidewalls 305A and merged sidewalls 305B. The merged sidewall 305B fills the gap between adjacent first axes 304A, while the independent sidewalls 305A are connected to the sidewalls of the axes on only one side. Exemplarily, a dry etching process can be used to etch the sidewall material layer 305. Figure 3C In this design, the sidewall between two adjacent first axes 304A is a merged sidewall 305B. The sidewalls on both sides of the second axis 304B and the third axis 304C are independent sidewalls. The sidewall of the first axis 304A closest to the second axis 304B and the sidewall of the first axis 304A closest to the third axis 304C are independent sidewalls 305A. The merged sidewall 305B is formed by merging two sidewalls, and its width is typically greater than the width of the independent sidewall 305A, but less than or equal to twice the width of the independent sidewall 305A. The width of the sidewall is the dimension of the sidewall along the first direction.

[0059] Next, step S205 is performed to remove the first axis 304. For example, while removing the first axis 304A, the second axis 304B is retained as a mask layer for the subsequent formation of a large critical-size gate. If a third axis 304C is also formed, then the third axis 304C is removed simultaneously.

[0060] Specifically, firstly, as Figure 3DAs shown, a first capping layer is formed covering the first axis 304A, the second axis 304B, and the third axis 304C. The first capping layer includes a first SOC layer 306 (Spin on carbon, spin-coated carbon hard mask) and a first SiARC layer 307 (Silicon-based anti-reflection coating). A first photoresist layer 308 is then formed on the first capping layer. The projection of the second axis 304B onto the surface of the material layer to be etched is located inside the projection of the first photoresist layer 308 onto the surface of the material layer to be etched, that is, the window of the first photoresist layer 308 exposes the first axis 304A and the third axis 304C.

[0061] Next, etching is performed using the first photoresist layer 308 as a mask to remove the first axis 304A and the third axis 304C. Specifically, dry etching is first used to expose the first capping layer of the first photoresist layer 308, revealing the first axis 304A and the third axis 304C. Then, an etching process with high selectivity for the axis and sidewalls removes the first axis 304A and the third axis 304C. Finally, an in-situ resist stripping step removes any remaining carbonaceous material. Figure 3E As shown, the pattern on the material layer to be etched includes: 1. Independent sidewall 305A; 2. Combined sidewall 305B; 3. Combination of independent sidewall 305A and second axis 304B. The combination of independent sidewall 305A and second axis 304B replaces the traditional photoresist layer as the mask for etching large critical size gates. This avoids differences in the amount of gate hard mask loss caused by the difference in materials between the photoresist pattern and the sidewalls; simultaneously, it avoids the generation of byproducts due to etching the gate hard mask layer with photoresist, thereby preventing etching defects caused by byproducts.

[0062] For example, after removing the first axis 304A and the third axis 304C, the target sidewall among the multiple sidewalls can be etched to reduce the width of the target sidewall, thereby achieving more usable critical dimensions. The target sidewall may include at least one independent sidewall 305A and / or at least one merged sidewall 305B. When the target sidewall includes both independent sidewall 305A and merged sidewall 305B, at least one independent sidewall 305A can be etched first, followed by at least one merged sidewall 305B; alternatively, at least one merged sidewall 305B can be etched first, followed by at least one independent sidewall 305A; or both can be etched simultaneously.

[0063] In the example where at least one merged sidewall 305B is etched first, followed by at least one independent sidewall 305A, the process begins as follows: Figure 3FAs shown, a second capping layer is formed covering multiple sidewalls, and a second photoresist layer 311 is formed on the second capping layer, exposing the target merged sidewalls to be etched. The second capping layer includes a second SOC layer 309 and a second SiARC layer 310.

[0064] Next, as Figure 3G As shown, etching is performed using the second photoresist layer 311 as a mask to thin the target merged sidewalls. Specifically, firstly, dry etching is used to expose the second capping layer of the second photoresist layer 311, revealing the target merged sidewalls to be etched. Then, a more isotropic etching step is used to reduce the critical dimensions of this target merged sidewall. Subsequently, wet etching is used to remove the remaining second capping layer. At this point, the pattern on the material layer to be etched mainly includes four parts: 1. Independent sidewall 305A; 2. Unetched merged sidewall 305B; 3. Etched merged sidewall 305B; 4. The combination of the second axis 304B and the independent sidewall 305A.

[0065] Next, the target's independent sidewall is etched. First, as... Figure 3H As shown, a third capping layer is formed covering multiple sidewalls, and a third photoresist layer 314 is formed on the third capping layer, exposing the target merged sidewalls to be etched. The third capping layer includes a third SOC layer 312 and a third SiARC layer 313.

[0066] Next, as Figure 3I As shown, etching is performed using the third photoresist layer 314 as a mask to thin the target independent sidewall. Specifically, firstly, the first capping layer exposed by the third photoresist layer 314 is opened by dry etching to expose the target independent sidewall to be etched. Then, a more isotropic etching step is used to reduce the critical dimension of this target independent sidewall. Subsequently, the remaining second capping layer is removed by wet etching. At this point, the pattern on the material layer to be etched mainly includes five parts: 1. Unetched independent sidewall 305A; 2. Etched independent sidewall 305A; 3. Unetched merged sidewall 305B; 4. Etched merged sidewall 305B; 5. The combination of the second axis 304B and the independent sidewall 305A. By etching the independent sidewall 305A and the merged sidewall 305B separately, the etching amount of the independent sidewall 305A and the merged sidewall 305B can be flexibly set, thereby obtaining more usable critical dimensions.

[0067] For example, if both the independent sidewall 305A and the merged sidewall 305B are etched simultaneously, a fourth capping layer covering multiple sidewalls is first formed; a fourth photoresist layer is formed on the fourth capping layer, exposing the target merged sidewall and the target independent sidewall to be etched; then, etching is performed using the fourth photoresist layer as a mask to reduce the width of the target merged sidewall and the target independent sidewall; finally, the fourth photoresist layer and the fourth capping layer are removed. Etching both the independent sidewall 305A and the merged sidewall 305B simultaneously simplifies the process flow.

[0068] Finally, step S206 is performed, using the sidewalls and the second axis as masks to etch the material layer to be etched, resulting in the following: Figure 3J The structure shown.

[0069] Specifically, the five different widths of patterns obtained through the aforementioned process are combined with a dry etching process. First, the patterns are transferred to the lower silicon oxide hard mask layer 303B, then to the silicon nitride hard mask layer 303A. Then, the gate material layer 302 is etched using the silicon oxide hard mask layer 303B and the silicon nitride hard mask layer 303A as barriers. Finally, gate patterns with multiple different key dimensions and relatively consistent remaining amount of gate hard mask layer are obtained.

[0070] Thus, the process steps of the semiconductor device manufacturing method according to the first aspect embodiment of the present invention are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0071] The semiconductor device manufacturing method provided by the embodiments of the present invention can provide more available critical dimensions: in existing processes, there are two main categories of choices for defining critical dimensions, the first category is sidewall patterns, and the second category is large-size photoresist patterns; the embodiments of the present invention additionally introduce a third type of critical dimension pattern formed by merging two sidewall patterns, which can make the gate size definition more diverse and meet more design requirements.

[0072] The embodiments of the present invention can also reduce the difference in the amount of gate hard mask remaining: In existing processes, since the pattern definition of large critical dimensions uses photoresist materials, which are less resistant to plasma dry etching than sidewalls, and require the introduction of an additional in-situ resist removal step, the final amount of gate hard mask remaining will vary greatly, which may affect subsequent process windows (such as planarization processes). The embodiments of the present invention use a combination of axis and sidewalls instead of photoresist patterns, avoiding the problem of large differences in etching rate during the etching process, making the final amount of gate hard mask remaining in different regions more similar, and allowing the use of etching processes with more vertical etching morphology, which is beneficial for morphology control.

[0073] A second aspect of the present invention also provides a semiconductor device that can be prepared by the method described in the first embodiment above.

[0074] Below, for reference Figure 3J The semiconductor device of the present invention will be described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as in the foregoing Embodiment 1. For specific explanations and descriptions, please refer to the description in Embodiment 1.

[0075] Specifically, such as Figure 3J As shown, the semiconductor device of this embodiment includes a semiconductor substrate 301, a gate material layer 302, and a gate hard mask layer 303 stacked sequentially from bottom to top. The gate hard mask layer 303 includes a silicon nitride hard mask layer 303A and a silicon oxide hard mask layer 303B above it. The gate material layer 302 and the gate hard mask layer 303 constitute a gate structure. The gate structure has five different key dimensions, defined by unetched independent sidewalls, etched independent sidewalls, unetched merged sidewalls, etched merged sidewalls, and a combination of a second axis and independent sidewalls.

[0076] The semiconductor devices of this invention are prepared using the method described in Example 1, and therefore have more critical dimensions and better etching morphology.

[0077] A third aspect of the present invention also provides an electronic device including the aforementioned semiconductor device, which is prepared according to the aforementioned method.

[0078] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned semiconductor devices, has better performance.

[0079] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, on which a material layer to be etched is formed; A plurality of discrete axes are formed on the material layer to be etched, arranged along a first direction, wherein the axes include at least a plurality of first axes; A sidewall material layer is formed covering the axis, wherein the distance between two adjacent surfaces of the first axis facing each other is less than or equal to twice the thickness of the sidewall material layer; The sidewall material layer is etched to form sidewalls on the sidewalls of the plurality of discrete axes, the sidewalls including individual sidewalls and merged sidewalls, the merged sidewalls filling the gaps between adjacent first axes; Perform etching to remove the first axis; The material layer to be etched is etched using the sidewall as a mask.

2. The manufacturing method as described in claim 1, characterized in that, Along the first direction, the size of the merged sidewall is larger than the size of the independent sidewall.

3. The manufacturing method as described in claim 1, characterized in that, The axis also includes a second axis; The step of forming sidewalls on the sidewalls of the plurality of separate axes further includes: forming the independent sidewall on the sidewall of the second axis; During the etching process, the second axis is retained, and the second axis and the independent sidewall formed on the sidewall of the second axis together serve as a mask to etch the material layer to be etched.

4. The manufacturing method as described in claim 3, characterized in that, Along the first direction, the size of the second axis is larger than the size of the first axis.

5. The manufacturing method as described in claim 3, characterized in that, The etching process includes: A first covering layer is formed covering the first axis and the second axis; A first photoresist layer is formed on the first cover layer, the window of the first photoresist layer exposes the first axis, and the projection of the second axis on the surface of the material layer to be etched is located inside the projection of the first photoresist layer on the surface of the material layer to be etched. Etching is performed using the first photoresist layer as a mask to remove the first axis.

6. The manufacturing method as described in claim 1, characterized in that, After removing the first axis and before etching the material layer to be etched using the sidewall as a mask, the method further includes: The target sidewalls among the plurality of said sidewalls are etched to reduce the size of the target sidewalls along the first direction, the target sidewalls including at least one of the said independent sidewalls and / or at least one of the said merged sidewalls.

7. The manufacturing method as described in claim 6, characterized in that, The etching of the target sidewall among the plurality of sidewalls includes: Forming a second covering layer that covers the multiple sidewalls; A second photoresist layer is formed on the second cover layer, and the window of the second photoresist layer exposes the target merging sidewalls to be etched. Etching is performed using the second photoresist layer as a mask to reduce the size of the target merged sidewall along the first direction; Remove the second photoresist layer and the second capping layer; And / or, forming a third covering layer covering the plurality of said sidewalls; A third photoresist layer is formed on the third cover layer, and the window of the third photoresist layer exposes the independent sidewall of the target to be etched. Etching is performed using the third photoresist layer as a mask to reduce the size of the target independent sidewall along the first direction; Remove the third photoresist layer and the third capping layer.

8. The manufacturing method as described in claim 6, characterized in that, The etching of the target sidewall among the plurality of sidewalls includes: A fourth covering layer is formed, covering the multiple sidewalls; A fourth photoresist layer is formed on the fourth cover layer, and the window of the fourth photoresist layer exposes the target merged sidewall and the target independent sidewall to be etched. Etching is performed using the fourth photoresist layer as a mask to reduce the dimensions of the target merged sidewall and the target independent sidewall along the first direction; Remove the fourth photoresist layer and the fourth cover layer.

9. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device as described in claim 9.

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