Process method for thinning poly layer of photovoltaic cell by combined chemical method

Abstract

The invention discloses a process method for thinning a poly layer of a photovoltaic cell by a combinatorial chemical method. The process method comprises the following steps of: performing graphical mask on a metal electrode area on the back surface of a Poly silicon wafer; carrying out acid etching on the PSG layer in the non-mask area of the silicon wafer by adopting an acid etching mixed solution, and removing the PSG layer and the poly layer in the non-mask area; cleaning the silicon wafer by using overflow water; alkali etching is carried out on the poly layer of the non-mask area of the silicon wafer by using alkali etching mixed liquid; and carrying out subsequent treatment on the silicon wafer after alkali etching. According to the method, a PSG layer and a poly layer in a non-mask area of a silicon wafer are pre-etched by using an acid solution and then the poly layer in a non-metal electrode area is thinned or removed by using an alkaline solution in an etching mode of a combined chemical method of graphical mask, acid etching and alkaline etching, so that the problem of insufficient etching or excessive etching of the poly layer can be avoided, a BSG layer on the front side cannot be damaged, batch production is facilitated, and the production cost is reduced. And the preparation efficiency and the yield of the battery piece are improved.

Description

Technical Field

[0001] This invention relates to the fields of photovoltaic and semiconductor technology, and in particular to a process method for thinning or removing the poly layer in the non-metallic electrode region on the back of a topcon cell. Background Technology

[0002] Existing crystalline silicon topcon solar cells primarily employ a tunneling oxide passivation structure on the back side, consisting mainly of an ultrathin nano-oxide layer and a doped amorphous silicon layer. Because the doped amorphous silicon layer (poly layer) in topcon cells absorbs near-infrared light, it causes light loss on the back side of the cell, and this loss increases with the thickness of the thin film. Therefore, selectively doped amorphous silicon layer (poly layer) structures are the optimal choice for topcon cells. Current poly-finger processes mainly involve laser thinning; however, during laser processing, excessively high energy densities can cause thermal damage such as microcracks in the poly layer, reducing cell efficiency and yield. In production trials, patterned masks and acid etching have also been used to thin the poly layer in the non-metallic electrode areas to avoid thermal damage such as microcracks caused by laser processing. However, using acid etching to chemically thin the poly layer in the non-metallic electrode region has the following problems: 1. It is difficult to control the acid etching concentration range. If it is too low, the poly cannot be completely removed, and if it is too high, it will easily over-etch and damage the front BSG and the textured surface; 2. After the front boron expansion of the silicon wafer, the thickness of the BSG (borosilicate glass) layer fluctuates greatly, and the thickness of the PSG (phosphosilicate glass) layer formed during the poly doping process also fluctuates greatly. This results in a relatively narrow time and concentration range for acid etching of poly, which is not conducive to mass production on the production line and can easily cause losses in cell efficiency and yield.

[0003] Therefore, how to overcome the problems that easily occur when thinning or removing the poly layer of the non-metallic electrode area on the back of the topcon cell in the existing process, such as insufficient or excessive etching, damage to the front BSG and texturing surface, which is not conducive to mass production on the production line and affects the preparation efficiency and quality of the cell, is a problem that needs to be solved in this technical field. Summary of the Invention

[0004] To address the problems of insufficient or excessive etching and damage to the front BSG and texturing surface that easily occur when thinning or removing the poly layer of the non-metallic electrode region on the back of a topcon cell in existing processes, which are detrimental to mass production and affect the efficiency and quality of cell fabrication, this invention provides a process method for thinning the poly layer of a photovoltaic cell using a combinatorial chemical approach.

[0005] This invention provides a process for thinning the poly layer of photovoltaic cells using a combinatorial chemical method, comprising the following steps: Step 1: Pattern the metal electrode area on the back side of the polysilicon wafer using a mask; Step 2: Use an acid etching mixture to etch the PSG layer in the non-mask area of ​​the silicon wafer to remove the PSG layer or PSG layer and part of the poly layer in the non-mask area. Step 3: Rinse the silicon wafer after acid etching with overflow water; Step 4: Perform alkaline etching on the poly layer of the non-mask area of ​​the silicon wafer using an alkaline etching mixture; Step 5: Perform subsequent processing on the silicon wafer after alkaline etching.

[0006] Preferably, the poly-polymerized silicon wafer is a PE-poly-polymerized silicon wafer or an LP-poly-polymerized silicon wafer.

[0007] Preferably, the acid etching mixture is a mixture of HF, HF and HNO3 or HF and an additive, and deionized water.

[0008] Preferably, in step 2, the volume fraction of HF in the acid etching mixture is 6%, and the reaction time of immersing the silicon wafer in the acid etching mixture at room temperature is 60-100s.

[0009] Preferably, the alkaline etching mixture is a mixture of NaOH and deionized water or NaOH, additives, and deionized water, wherein the volume fraction of NaOH is 5% to 10%, the alkaline etching temperature is 70 to 80°C, and the alkaline etching time is 90 to 300 seconds.

[0010] Preferably, in step 1, the PSG layer deposited on both sides and the front side of the silicon wafer after Poly is removed first, and then the patterned mask is applied.

[0011] Preferably, the PSG layer is first removed using an HF solution with a volume ratio of HF to deionized water of 1:4.8, and the treatment is carried out at 25°C for 100-120 seconds.

[0012] Preferably, in step 2, the volume fraction of HF in the acid etching mixture is 1%, and the reaction time of immersing the silicon wafer in the acid etching mixture at room temperature is 40-60 seconds.

[0013] Preferably, the subsequent processing of step 3 includes the following steps: The silicon wafer after acid etching is cleaned once using overflow water; the silicon wafer is then cleaned with an alkaline mixture to remove the patterned mask layer; the silicon wafer is cleaned a second time using overflow water; the silicon wafer is cleaned with hydrofluoric acid solution; the silicon wafer is cleaned a third time using overflow water; the silicon wafer is slowly pulled up to pre-dehydrate the surface; and the pre-dehydrated silicon wafer is then dried.

[0014] Preferably, the washing time is 120s; the alkaline solution is a mixture of NaOH, H2O2 and deionized water, wherein the volume ratio of NaOH to H2O2 is 1:4, the temperature of the subsequent alkaline wash is 70℃, and the time is 90s; the solubility of the hydrofluoric acid solution is: the volume ratio of HF to water = 1:4.8, the temperature of the HF acid wash is 25℃, and the time is 280s; the speed of slowly lifting the deionized water is 3mm / s, the temperature during pre-dehydration is 48-50℃; the drying temperature is 95℃, and the time is 600s.

[0015] This invention presents a novel process for thinning or removing poly layers in the non-electrode regions of topcon solar cells. The process primarily utilizes a patterned mask + acid etching + alkaline etching approach. Specifically, a mask pattern is applied as a protective layer to the PSG layer in the metal electrode region. First, an acid solution is used to selectively etch the PSG layer or a combination of the PSG layer and a portion of the poly layer in the non-masked areas of the topcon silicon wafer—this is pretreatment. Then, alkaline etching is used to thin or remove the poly layer in the non-metallic electrode regions. This effectively avoids the problems of insufficient or excessive etching of the poly layer, while also preventing damage to the front-side BSG (borosilicate glass) layer. This facilitates mass production on the production line and improves the efficiency and yield of cell fabrication. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the process flow for the first preparation scheme, which involves removing PSG, patterning mask, acid etching, water washing, alkaline etching, and subsequent processing of the silicon wafer after PE-poly. Figure 2 This is a schematic diagram of the process flow for the first preparation scheme, which involves removing PSG, patterning mask, acid etching, water washing, alkaline etching, and subsequent processing of the silicon wafer after LP-poly. Figure 3 This is a schematic diagram of the process flow for the second preparation method, which involves patterning a silicon wafer after PE-poly etching, acid etching, water washing, alkaline etching, and subsequent processing. Figure 4 This is a schematic diagram of the process flow for the second preparation scheme, which involves patterning masking, acid etching, water washing, alkaline etching, and subsequent processing of the silicon wafer after LP-poly etching. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the following specific embodiments are only used to explain the invention and do not constitute a limitation thereof.

[0018] This invention provides a process method for thinning the poly layer of a photovoltaic cell using a patterned mask, which has two fabrication schemes. The first fabrication scheme includes the following steps: Step 1: Remove the PSG (phosphosilicate glass) layer coated on both sides and the front side of the polysilicon wafer. The PSG layer is removed using an HF solution with a volume ratio of HF to deionized water of 1:4.8, and the treatment is carried out at 25°C for 100-120 seconds.

[0019] The poly-polymerized silicon wafer can be either a PE-poly-polymerized silicon wafer or an LP-poly-polymerized silicon wafer.

[0020] Step 2: Pattern the metal electrode area on the back side of the polysilicon wafer using a mask.

[0021] Step 3: Etch the PSG layer in the non-mask area of ​​the silicon wafer using an acid etching solution. This involves removing the PSG layer or a portion of the PSG layer and poly layer in the non-mask area, including both sides and the front of the wafer. The acid etching solution is a mixture of hydrofluoric acid and deionized water, with an HF volume fraction of 1%. At room temperature, the silicon wafer is immersed in the acid etching solution for 40-60 seconds. Alternatively, the acid etching solution can be a mixture of HF + HNO3 or HF + additives and deionized water.

[0022] Step 4: Rinse the acid-etched silicon wafer with overflow water for 120 seconds.

[0023] Step 5: Further etch the poly layer of the non-mask area of ​​the silicon wafer using an alkaline etching solution, including both sides of the silicon wafer and the front of the winding. The alkaline etching solution is a mixture of NaOH and deionized water or NaOH, additives, and deionized water, with a NaOH volume fraction of 5%~10%, a temperature of 70~80℃, and an alkaline etching time of 90s~300s. Other alkaline solutions, such as KOH solution, can also be used.

[0024] Step 6: Perform subsequent processing on the silicon wafer after alkaline etching. The process includes: The silicon wafer after acid etching is cleaned once using overflow water; then, it is cleaned again using an alkaline mixture to remove the patterned mask layer; a second cleaning is performed using overflow water; the wafer is then cleaned using a hydrofluoric acid solution; a third cleaning is performed using overflow water; the wafer is then slowly pulled up to pre-dehydrate its surface; and finally, the pre-dehydrated wafer is dried. Wherein: The three washing cycles each lasted 120 seconds; the alkaline solution was a mixture of NaOH, H2O2, and deionized water, with a NaOH:H2O2 volume ratio of 1:4; the subsequent alkaline wash was performed at 70°C for 90 seconds; the hydrofluoric acid solution had a HF:water volume ratio of 1:4.8; the HF acid wash was performed at 25°C for 280 seconds; the deionized water was slowly lifted at a speed of 3 mm / s; the pre-dehydration temperature was 48-50°C; and the drying temperature was 95°C for 600 seconds.

[0025] The second preparation method of the present invention includes the following steps: Step 1: Apply a patterned mask to the metal electrode area on the back side of the poly-coated silicon wafer. The poly-coated silicon wafer is either a PE-poly-coated or LP-poly-coated silicon wafer.

[0026] Step 2: The PSG layer and poly layer in the non-mask area of ​​the silicon wafer are etched using an acid etching mixture to thin or remove the poly layer in the non-metallic electrode area. The acid etching mixture is a mixture of hydrofluoric acid and deionized water. The volume fraction of HF in the acid etching mixture is 6%, and the silicon wafer is immersed in the acid etching mixture for 60-100 seconds at room temperature. The acid etching mixture can also be a mixture of HF + HNO3 or HF + additives and deionized water.

[0027] Step 3: Rinse the acid-etched silicon wafer with overflow water for 120 seconds; Step 4: Further etch the poly layer of the non-mask area of ​​the silicon wafer using an alkaline etching mixture: the alkaline etching mixture is a mixture of NaOH + deionized water or NaOH + additive + deionized water, with a NaOH volume fraction of 5%~10%, a temperature of 70~80℃, and an alkaline etching time of 90s~300s. Other alkaline solutions, such as KOH solution, can also be used.

[0028] Step 5: Perform subsequent processing on the silicon wafer after acid etching. The process includes: The silicon wafer after acid etching is cleaned once using overflow water; then, it is cleaned again using an alkaline mixture to remove the patterned mask layer; a second cleaning is performed using overflow water; the wafer is then cleaned using a hydrofluoric acid solution; a third cleaning is performed using overflow water; the wafer is then slowly pulled up to pre-dehydrate its surface; and finally, the pre-dehydrated wafer is dried. Wherein: The three washing cycles each lasted 120 seconds; the alkaline solution was a mixture of NaOH, H2O2, and deionized water, with a NaOH:H2O2 volume ratio of 1:4; the subsequent alkaline wash was performed at 70°C for 90 seconds; the hydrofluoric acid solution had a HF:water volume ratio of 1:4.8; the HF acid wash was performed at 25°C for 280 seconds; the deionized water was slowly lifted at a speed of 3 mm / s; the pre-dehydration temperature was 48-50°C; and the drying temperature was 95°C for 600 seconds.

[0029] If only an acid etching solution is used to etch the poly layer, it is indeed possible to etch the PSG layer + poly layer on the back of the silicon wafer by controlling the concentration, time and temperature of the solution. However, this acid etching solution can also easily etch the BSG on the front side and destroy the textured surface of the bottom layer on the front side.

[0030] Because silicon dioxide (the PSG on the back of the silicon wafer is phosphorus-doped silicon dioxide, and the BSG on the front is boron-doped silicon dioxide) reacts with hydrofluoric acid to produce soluble hexafluorosilicic acid (H2SiF6) and water. The thickness of the BSG (borosilicate glass) layer prepared in the front-end of the production line fluctuates greatly. However, when the thickness is too low, HF will first etch away the BSG layer. The texturing process damages the silicon surface by oxidizing it with nitric acid (HNO3) (which generates nitrous acid (HNO2)), forming a very thin layer of silicon dioxide (SiO2). Hydrofluoric acid will then quickly dissolve the silicon dioxide formed in the previous step, generating soluble hexafluorosilicic acid (H2SiF6), thus re-exposing the fresh silicon surface, which will affect battery performance.

[0031] This invention adds an alkaline etching process after appropriate acid etching, and uses a low-concentration alkaline etching solution for further etching. That is, after acid etching of the PSG layer, alkaline etching is performed to further etch the poly layer. The etching rate is controlled by adjusting the temperature, time, concentration of the alkaline solution, and additives, thus controlling the depth and width of the alkaline etching. Furthermore, since the reaction between this alkaline etching solution and silicon dioxide is extremely slow at both room temperature and high temperature (70-80°C), it is negligible. Therefore, when alkaline etching the poly layer in the non-gateway areas on the back side, the front BSG layer and the underlying textured surface are not damaged. This is beneficial for mass production on the production line and improves the efficiency and yield of cell fabrication.

[0032] In the N-TopCon battery manufacturing process, the "PE-poly post-processing" refers to a semi-finished product that has undergone the following processes: The process involves texturing the silicon wafer, boron diffusion on the front side, removal of BSG from the front side, polishing the back side, PECVD-poly (deposition of a tunneling oxide layer and a doped amorphous silicon layer on the back side), and annealing and crystallization. After completing this step, the "PE-poly" silicon wafer is obtained. Then, the subsequent process of removing PSG and RCA is performed.

[0033] The term "LE-poly post-processing" refers to the semi-finished product after undergoing the following process: After completing the following steps—silicon wafer texturing, front-side boron diffusion, removal of front-side BSG and back-side polishing, LPCVD-poly (back-side tunneling oxidation + intrinsic polysilicon deposition), and back-side phosphorus diffusion—the "LP-poly post-" silicon wafer is obtained. Then, the subsequent processes of removing PSG and RCA are performed.

[0034] The present invention will be further described below through specific embodiments.

[0035] Example 1 Using the first fabrication method, the silicon wafer after PE-poly processing undergoes PSG removal, patterning masking, acid etching, water washing, alkaline positive etching, and subsequent processing steps, such as... Figure 1 The process flow shown is as follows.

[0036] 1. PSG Removal: The PE-poly silicon wafer is fed into a chain-type PSG removal device. A mixed solution of HF and deionized water at a volume ratio of 1:4.8 is used, and the wafer is treated at 25°C for 100-120 seconds to remove the PSG layer (phosphosilicate glass) deposited on both sides and the front side of the silicon wafer. The BSG layer (borosilicate glass) on the front side is retained as a mask layer for subsequent protection. The degree of PSG removal is checked by observing the dehydration of the silicon wafer surface; complete dehydration indicates that the PSG has been completely removed.

[0037] 2. Patterned Mask: The PSG (Power Seal) of the metal electrode area on the back side of the silicon wafer after PSG removal is patterned using a mask. This involves spraying mask material onto the back of the silicon wafer using a spray printing method to form a mask pattern. The printed grid lines have a height of 15-18µm and a width of 100-120µm. Mask materials mainly include one or more of the following: paraffin wax, ink, resin, or adhesive film.

[0038] 3. Acid Etching: The silicon wafer with the patterned mask is subjected to acid etching. An acid etching solution of HF + deionized water is used, wherein the HF volume fraction is 1%. At room temperature, the silicon wafer is immersed in the acid etching solution for 40-60 seconds. By suppressing the reaction rate at low temperature, the PSG layer and poly layer exposed in the non-patterned mask area are removed, including the PSG layers on both sides of the silicon wafer and those extending to the front of the silicon wafer, or the PSG layer and part of the poly layer, to achieve a controllable poly layer etching depth. The acid etching solution can also be a mixture of HF + HNO3 or HF + additives and deionized water.

[0039] 4. After acid etching, rinse the silicon wafer with overflow water for 120 seconds to remove impurities and residual acid solution from the surface of the silicon wafer and ensure that the surface of the silicon wafer is clean.

[0040] 5. Alkaline etching of the poly layer in the non-mask area of ​​the silicon wafer using an alkaline etching mixture: The alkaline etching solution is a mixture of NaOH and deionized water or NaOH, additives, and deionized water, with a NaOH volume fraction of 5%–10%, a temperature of 70–80°C, and an alkaline etching time of 90–300 seconds. Alkaline etching is performed on the non-mask poly areas on the back and sides of the silicon wafer. By controlling the temperature, time, concentration of the alkaline solution, and additives in the alkaline etching process, the etching rate can be controlled, allowing for precise control of the etching depth and width. This effectively reduces parasitic light absorption in the non-electrode areas on the back side, improving the photoelectric conversion efficiency and yield of the solar cell.

[0041] 6. First rinse: Use overflow water to rinse for 120 seconds to remove impurities and residual acid solution from the silicon wafer surface, ensuring the silicon wafer surface is clean.

[0042] 7. Post-alkaline wash: A mixed solution of NaOH + H2O2 + deionized water is mainly used. The volume ratio of NaOH to H2O2 is 1:4. The temperature is 70℃ and the process time is 90s. This wash cleans the silicon wafer after acid etching, neutralizes the residual acid etching solution on the silicon wafer, removes the porous silicon generated by the acid etching reaction, and removes the patterned mask layer.

[0043] 8. Secondary water rinse: Use overflow water to rinse for 120 seconds to remove impurities and residual alkaline solution from the silicon wafer surface, ensuring the silicon wafer surface is clean.

[0044] 9. HF Wash: A final HF wash is performed to remove the front BSG and back PSG. The HF:water ratio is 1:4.8, the washing temperature is 25℃, and the washing time is 280 seconds.

[0045] 10. Three-stage water rinse: Rinse with overflow water for 120 seconds to remove impurities and residual acid solution from the silicon wafer surface, ensuring the silicon wafer surface is clean. 11. Slow lifting: Deionized water (lifting speed 3mm / s, working temperature 48-50℃) is used to pre-dehydrate the surface of the monocrystalline silicon wafer to avoid watermarks during drying.

[0046] 12. Drying: Dry the cleaned silicon wafers at 95℃ for 600 seconds.

[0047] Example 2 Using the first fabrication method, the silicon wafer after LP-poly processing undergoes PSG removal, patterning masking, acid etching, water washing, alkaline etching, and subsequent steps, such as... Figure 2 The process flow shown is as follows: The processing method for the silicon wafer after LP-poly etching—PSG removal, patterning masking, acid etching, water washing, alkaline etching, and subsequent processes—is basically the same as the process in Example 1. The difference is that a poly layer is also deposited on the BSG on the front side of the silicon wafer after LP-poly etching. Therefore, during the acid etching process after patterning masking, in addition to removing the PSG layer or PSG layer and part of the poly layer exposed in the non-patterned mask area on the back side of the silicon wafer, as well as the PSG layer or PSG layer and poly layer on both sides of the silicon wafer that wrap around to the front side of the silicon wafer, the poly layer covering the BSG on the front side of the silicon wafer must also be removed to achieve a controllable poly layer etching depth. The processing of the silicon wafer after acid etching is the same as in Example 1.

[0048] The first fabrication method requires first removing the PSG deposited on both sides and the front of the polysilicon wafer. The process involves patterning a mask, acid etching, water washing, alkaline etching, and subsequent treatment. This fabrication method is suitable for manufacturers' existing equipment and processes. It allows the continued use of the "chain-type PSG removal" equipment in the current Topcon conventional process to remove the PSG layers deposited on both sides and the front of the polysilicon wafer. Only the patterning mask equipment and the necessary acid etching tanks need to be added to achieve the fabrication method of this invention. Production line modification is convenient, saving time and costs.

[0049] The second preparation method provided by this invention is used below to achieve thinning of the poly layer in photovoltaic cells.

[0050] Example 3 The second fabrication method involves patterning the silicon wafer after PE-poly etching, followed by acid etching and subsequent processing steps, such as... Figure 3 The process flow shown is as follows.

[0051] 1. Patterned Mask: A patterned mask is applied to the PSG (Power Photocell) on the metal electrode area of ​​the back side of the silicon wafer after PE-polymerization. This involves spraying mask material onto the back of the silicon wafer using a spray printing method to form a mask pattern. The printed grid lines have a height of 15-18µm and a width of 100-120µm. Mask materials mainly include one or more of the following: paraffin wax, ink, resin, or adhesive film.

[0052] 2. Acid Etching: The silicon wafer with the patterned mask is subjected to acid etching. A mixture of HF and deionized water is used, with HF comprising 6% by volume. At room temperature, the silicon wafer is immersed in the acid etching solution for 60-100 seconds. By suppressing the reaction rate at low temperature, the exposed PSG layer or PSG layer and part of the poly layer in the non-patterned mask area is removed, including the PSG layer or PSG layer and part of the poly layer on both sides of the silicon wafer and extending to the front side of the silicon wafer, in order to achieve a controllable poly layer etching depth. The acid etching mixture can also be a mixture of HF + HNO3 or HF + additives and deionized water.

[0053] 3. After acid etching, rinse the silicon wafer with overflow water for 120 seconds to remove impurities and residual acid solution from the surface of the silicon wafer and ensure that the surface of the silicon wafer is clean.

[0054] 4. Alkaline etching of the poly layer in the non-mask area of ​​the silicon wafer using an alkaline etching mixture: The alkaline etching solution is a mixture of NaOH and deionized water or NaOH, additives, and deionized water, with a NaOH volume fraction of 5%–10%, a temperature of 70–80°C, and an alkaline etching time of 90–300 seconds. Alkaline etching is performed on the non-mask poly areas on the back and sides of the silicon wafer. By controlling the temperature, time, concentration of the alkaline solution, and additives in the alkaline etching process, the etching rate can be controlled, allowing for precise control of the etching depth and width. This effectively reduces parasitic light absorption in the non-electrode areas on the back side, improving the photoelectric conversion efficiency and yield of the solar cell.

[0055] 5. First rinse: Use overflow water to rinse for 120 seconds to remove impurities and residual acid solution from the silicon wafer surface, ensuring the silicon wafer surface is clean.

[0056] 6. Post-alkaline washing: mainly using a mixed solution of NaOH + H2O2 + deionized water, with a volume ratio of NaOH:H2O2 of 1:4, a temperature of 70℃, and a process time of 90s, to clean the silicon wafer after the previous acid etching, neutralize the solution residue left on the silicon wafer by acid etching, remove the porous silicon generated by the acid etching reaction, and remove the patterned mask layer at the same time.

[0057] 7. Secondary water rinse: Use overflow water to rinse for 120 seconds to remove impurities and residual alkaline solution from the silicon wafer surface, ensuring the silicon wafer surface is clean.

[0058] 8. HF Wash: A final HF wash is performed to remove the front-side BSG and back-side PSG. Among these steps... HF:water = 1:4.8, cleaning temperature 25℃, cleaning time 280 seconds.

[0059] 9. Three-stage water rinse: Rinse with overflow water for 120 seconds to remove impurities and residual acid solution from the silicon wafer surface, ensuring the silicon wafer surface is clean. 10. Slow lifting: Deionized water (lifting speed 3mm / s, working temperature 48-50℃) is used to pre-dehydrate the surface of the monocrystalline silicon wafer to avoid watermarks during drying.

[0060] 11. Drying: Dry the cleaned silicon wafers. The temperature is 95℃ and the time is 600 seconds.

[0061] Example 4 The second fabrication method involves patterning the silicon wafer after LP-poly etching, followed by acid etching and subsequent processing steps, such as... Figure 4 The process flow shown is as follows: The processing method for the silicon wafer after LP-poly etching—patterning masking, acid etching, water washing, alkaline etching, and subsequent processes—is basically the same as the process in Example 3. The difference is that a poly layer is also deposited on the front side of the silicon wafer in addition to the BSG layer. Therefore, during the acid etching process after patterning masking, in addition to removing the PSG layer or PSG layer and poly layer exposed in the non-patterned mask area of ​​the silicon wafer, as well as the PSG layer or PSG layer and poly layer on both sides of the silicon wafer and those extending to the front side, the poly layer covering the BSG on the front side of the silicon wafer must also be removed to achieve a controllable poly layer etching depth. The processing of the silicon wafer after acid etching is the same as in Example 3.

[0062] The second fabrication scheme, considering process optimization, integrates the first scheme's process of first removing the PSG layers on both sides and the front of the silicon wafer using a chain-type device, and then removing the PSG and poly layers in non-patterned mask areas via subsequent acid etching. This involves directly applying a patterned mask to the back of the silicon wafer after POLY etching, followed by a single step of acid etching to remove the PSG and poly layers. This eliminates the need for the existing "chain-type PSG removal equipment," saving process steps and offering better results at lower costs and higher efficiency. However, it requires additional equipment for removing the patterned mask and a tank for acid etching, enabling the etching of the poly layers in the non-gateline areas on the back.

[0063] The above description is merely a specific embodiment of the present invention. It should be noted that any modifications, equivalent substitutions, and variations made within the spirit and framework of the present invention should be included within the protection scope of the present invention.

Claims

1. A process for thinning the poly layer of a photovoltaic cell using a combinatorial chemical method, comprising the following steps: Step 1: Pattern the metal electrode area on the back side of the polysilicon wafer using a mask; Step 2: Use an acid etching mixture to etch the PSG layer in the non-mask area of ​​the silicon wafer to remove the PSG layer or PSG layer and part of the poly layer in the non-mask area. Step 3: Rinse the silicon wafer after acid etching with overflow water; Step 4: Alkaline etching is performed on the poly layer of the non-mask area of ​​the silicon wafer using an alkaline etching mixture; Step 5: Perform subsequent processing on the silicon wafer after alkaline etching.

2. The process method as described in claim 1, characterized in that, The poly-coated silicon wafer is either a PE-poly-coated silicon wafer or an LP-poly-coated silicon wafer.

3. The process method as described in claim 1, characterized in that, The acid etching mixture is a mixture of HF, HF and HNO3 or HF and an additive, and deionized water.

4. The process method as described in claim 1, characterized in that, In step 2, the volume fraction of HF in the acid etching mixture is 6%, and the silicon wafer is immersed in the acid etching mixture at room temperature for 60-100 seconds.

5. The process method as described in claim 1, characterized in that, The alkaline etching solution is a mixture of NaOH and deionized water or NaOH, additives, and deionized water, wherein the volume fraction of NaOH is 5% to 10%, the alkaline etching temperature is 70 to 80°C, and the alkaline etching time is 90 to 300 seconds.

6. The process method as described in claim 1, characterized in that, In step 1, the PSG layer that was coated on both sides and the front side of the silicon wafer after Poly was removed is first applied, and then the patterned mask is applied.

7. The process method as described in claim 6, characterized in that, The PSG layer was first removed using an HF solution with a volume ratio of HF to deionized water of 1:4.8, and the treatment was carried out at 25°C for 100-120 seconds.

8. The process method as described in claim 6, characterized in that, In step 2, the volume fraction of HF in the acid etching mixture is 1%, and the silicon wafer is immersed in the acid etching mixture at room temperature for 40-60 seconds.

9. The process method as described in claim 1, characterized in that, The subsequent processing in step 5 includes the following procedures: The silicon wafer after acid etching is cleaned once using overflow water; the silicon wafer is then cleaned with an alkaline mixture to remove the patterned mask layer; the silicon wafer is cleaned a second time using overflow water; the silicon wafer is cleaned with hydrofluoric acid solution; the silicon wafer is cleaned a third time using overflow water; and the silicon wafer is slowly pulled up to pre-dehydrate its surface. The pre-dehydrated silicon wafers are then dried.

10. The process method as described in claim 9, characterized in that, The cleaning time for each step is 120 seconds; the alkaline solution is a mixture of NaOH, H2O2, and deionized water, with a NaOH:H2O2 volume ratio of 1:4; the subsequent alkaline washing temperature is 70°C and the time is 90 seconds; the hydrofluoric acid solution has a HF:water volume ratio of 1:4.8; the HF acid washing temperature is 25°C and the time is 280 seconds; the deionized water is slowly lifted at a speed of 3 mm / s; the pre-dehydration temperature is 48-50°C; and the drying temperature is 95°C and the time is 600 seconds.

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