Back contact gate all-around field effect transistor structure with thicker gate below lowest channel than between channels

Abstract

A gate all around field effect transistor (FET) structure and a method for manufacturing the gate all around field effect transistor (FET) structure are disclosed. In one aspect, a gate-all-around FET structure includes a gate structure (244a-244e) disposed between a first vertical source / drain (S / D) structure (208b) and a second vertical S / D structure (208c), the gate structure including a channel structure including a plurality of vertically stacked horizontal channels, the plurality of vertically stacked horizontal channels connect the first vertical S / D structure (208b) to the second vertical S / D structure (208c) in a first horizontal direction by a vertical metal gate structure (244a-244e) that at least partially surrounds the plurality of vertically stacked horizontal channels. A first thickness of the vertical metal gate structure (244e) below a bottom channel of the plurality of vertically stacked horizontal channels is greater than a second thickness of the vertical metal gate structure (244b, 244c, 244d) between adjacent channels of the plurality of vertically stacked horizontal channels. The gate is back contacted by an interlayer dielectric (238) under the vertical metal gate structure (244a-244e) using a contact structure (222).

Description

Cross-reference to related applications

[0001] This patent application claims the benefit of U.S. Patent Application No. 18 / 824,706, filed September 4, 2024, entitled “GATE-ALL-AROUND FIELD EFFECTTRANSISTOR STRUCTURES,” which is a continuation-in-part of U.S. Patent Application Serial No. 18 / 469,496, filed September 18, 2023, entitled “GATE-ALL-AROUND FIELDEFFECT TRANSISTOR STRUCTURES,” which has been assigned to the assignee of this application and is expressly incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates generally to semiconductor wafer processes, and more particularly to a gate-all-around (GAA) field-effect transistor (FET) structure and a method for manufacturing the gate-all-around (GAA) field-effect transistor (FET) structure. Background Technology

[0003] Integrated circuit (IC) technology has made significant strides in improving computing power through the miniaturization of electrical components. IC devices can be implemented as IC chips, which have a set of circuits integrated on them, including multiple active and passive components (e.g., transistors, diodes, capacitors, inductors, and / or resistors) and several layers of contacts and interconnects above the active and passive components. In some aspects, the contacts and interconnects of an IC device are formed on the active and passive components on the front side of the IC device. As the size of the IC device and the components formed on it become smaller, the available area for forming the contacts and interconnects also becomes smaller. Therefore, the routing complexity and / or parasitic resistance and capacitance of the contacts and interconnects may increase, and thus the manufacturing cost or performance of the IC device may be negatively affected. Summary of the Invention

[0004] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0005] In one aspect, a field-effect transistor (FET) structure includes: a gate structure disposed between a first vertical source / drain (S / D) structure and a second vertical S / D structure, the gate structure including a channel structure including a plurality of vertically stacked horizontal channels, the plurality of vertically stacked horizontal channels connecting the first vertical S / D structure to the second vertical S / D structure in a first horizontal direction via a vertical metal gate structure at least partially surrounding the plurality of vertically stacked horizontal channels; and a back-side interlayer dielectric (ILD) layer disposed below the vertical metal gate structure and separated from a portion of the vertical metal gate structure by a shallow trench isolation (STI) layer, wherein a first thickness of the vertical metal gate structure below the bottom channel in the plurality of vertically stacked horizontal channels is greater than a second thickness of the vertical metal gate structure between adjacent channels in the plurality of vertically stacked horizontal channels.

[0006] In one aspect, a method for manufacturing a FET structure includes: providing a gate structure disposed between a first vertical S / D structure and a second vertical S / D structure, the gate structure including a channel structure including a plurality of vertically stacked horizontal channels, the plurality of vertically stacked horizontal channels connecting the first vertical S / D structure to the second vertical S / D structure in a first horizontal direction via a vertical metal gate structure at least partially surrounding the plurality of vertically stacked horizontal channels; and providing a back-side ILD layer disposed below the vertical metal gate structure and separated from a portion of the vertical metal gate structure via an STI layer, wherein a first thickness of the vertical metal gate structure below the bottom channel of the plurality of vertically stacked horizontal channels is greater than a second thickness of the vertical metal gate structure between adjacent channels of the plurality of vertically stacked horizontal channels.

[0007] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0008] A more complete understanding of the various aspects of this disclosure and its many accompanying advantages will be readily available when considered in conjunction with the following detailed description taken in conjunction with the accompanying drawings, wherein similar reference numerals denote similar parts, and the drawings are given for illustrative purposes only and do not constitute any limitation on this disclosure.

[0009] Figure 1A This is a top view of a portion of the conventional semiconductor structure of an integrated circuit (IC) device without a back-side power supply or signal routing.

[0010] Figure 1B This is an example of... Figure 1AA schematic diagram of the circuit generated by the illustrated semiconductor structure.

[0011] Figure 2A and Figure 2B This is a top view of a portion of the semiconductor structure of an IC device according to various aspects of this disclosure.

[0012] Figures 2C to 2H It is a cross-sectional view of the semiconductor structure of an IC device according to various aspects of this disclosure.

[0013] Figures 3A to 3D This is a cross section illustrating steps in the process of manufacturing a back-side contact above an active gate (BSCOAG) and / or a back-side gate contact (BSGC) according to various aspects of this disclosure.

[0014] Figure 4 This is a flowchart of an example process associated with the manufacture of BSCOAG and / or BSGC according to various aspects of this disclosure.

[0015] Figure 5 Mobile devices according to some examples of this disclosure are illustrated.

[0016] Figure 6 Various electronic devices that can be integrated with any of the aforementioned integrated devices or semiconductor devices are illustrated according to various examples of this disclosure.

[0017] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0018] A field-effect transistor (FET) structure and a method for manufacturing the FET structure are disclosed. In some aspects, the FET structure includes a gate structure disposed between a first vertical source / drain (S / D) structure and a second vertical S / D structure. The gate structure includes a channel structure comprising a plurality of vertically stacked horizontal channels, the plurality of vertically stacked horizontal channels horizontally connecting the first vertical S / D structure to the second vertical S / D structure via a vertical metal gate structure at least partially surrounding the horizontal channels. The FET structure also includes a back-side interlayer dielectric (ILD) layer disposed beneath the vertical metal gate structure and separated from a portion of the vertical metal gate structure by a shallow trench isolation (STI) layer, wherein a first thickness T1 of the vertical metal gate structure beneath the bottom channel of the plurality of vertically stacked horizontal channels is greater than a second thickness T2 of the vertical metal gate structure between adjacent channels of the plurality of vertically stacked horizontal channels. In some aspects, the active portion of the gate structure (i.e., containing the channel structure and the vertical metal gate structure) is in direct contact with the back-side ILD layer, and the passive portion of the gate structure (i.e., not containing the channel structure and the vertical metal gate structure) is separated from the back-side ILD through the STI layer. In some aspects, the back-side contact structure is electrically coupled to the vertical metal gate structure through the back-side ILD layer, the STI layer, and the high-k dielectric at the bottom of the gate structure (in this case, it is called a "back-side gate contact" (BSGC)), or electrically coupled to the vertical metal gate structure through the back-side ILD layer and the high-k dielectric at the bottom of the gate structure (in this case, it is called a "back-side gate contact above the active gate" (BSCOAG)). In some aspects, the BSCOAG structure is used as a gate isolation low to electrically isolate the circuit from adjacent circuits. For example, the gate of the pFET is connected to VDD, and the gate of the nFET is connected to VSS, forcing both transistors to be in the off state.

[0019] Various aspects of this disclosure are provided in the following description and accompanying drawings of various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. Additionally, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0020] Various aspects generally relate to integrated circuit devices and methods of manufacturing such integrated circuit devices. Some aspects more specifically relate to integrated circuit devices having back-side gate contacts above an active gate and back-side gate contacts isolated by shallow trenches. These contacts are suitable for a full-around-gate structure and are compatible with back-side power distribution networks.

[0021] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. Back-side gate contacts constructed using a unique manufacturing process allow back-side connections to field-effect transistor (FET) gates via the gate active region or via shallow trench isolation (STI), including gate all-around (GAA) topologies. The former is referred to herein as a back-side contact above the active gate (BSCOAG), and the latter as a back-side gate contact (BSGC). Both gate contact structures provide back-side access to standard cells for signal routing. In contrast, conventional standard cell designs have back-side connections used only for power wiring and not for signal routing. The use of back-side signal routing allows for a reduction in standard cell size and parasitic resistance and capacitance, thereby providing improved standard cell performance as well as area reduction / cell compactness.

[0022] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as superior to or better than other aspects. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0023] Those skilled in the art will understand that any of a variety of different techniques and methods can be used to represent the information and signals described below. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the following description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, depending in part on the specific application, in part on the desired design, in part on the corresponding technology, and so on.

[0024] Furthermore, many aspects are described according to a sequence of actions to be performed by elements of, for example, a computing device. It will be appreciated that the various actions described herein can be performed by specific circuitry (e.g., an application-specific integrated circuit (ASIC)), by program instructions executed by one or more processors, or by a combination of both. Additionally, the sequence of actions described herein can be considered to be entirely embodied in any form of non-transitory computer-readable storage medium storing a corresponding set of computer instructions that, when executed, will cause or command the associated processor of the device to perform the functionality described herein. Therefore, various aspects of this disclosure can be embodied in a variety of different forms, all of which are contemplated within the scope of the claimed subject matter. Furthermore, for each aspect described herein, any corresponding form of any such aspect may be described herein as, for example, "logic configured to perform the described actions."

[0025] Figure 1A This is a top view of a portion of the semiconductor structure 100 of a conventional integrated circuit (IC) device without a back-side power supply or signal routing. In some respects, Figure 1A Some components of the semiconductor structure 100 are shown for illustrative purposes only, and Figure 1A The components shown in the diagram may be positioned above and / or below that are not in the [specific location]. Figure 1A Other elements shown in the diagram.

[0026] like Figure 1A As shown, the semiconductor structure 100 includes gate stacks 102, 104, and 106 spaced apart along a first direction (e.g., the x-direction) and having lengths along a second direction (e.g., the y-direction). The semiconductor structure 100 also includes a source / drain (S / D) structure 122 between gate stacks 102 and 104, an S / D structure 124 between gate stacks 102 and 106, an S / D structure 126 between gate stacks 102 and 104, and an S / D structure 128 between gate stacks 102 and 106. S / D structures 122 and 126 are separated from each other in the second direction (e.g., the y-direction), and S / D structures 124 and 128 are also separated from each other in the second direction (e.g., the y-direction).

[0027] The portion of gate stack 102 adjacent to S / D structures 122 and 124 can be configured as a first gate structure, and a first channel structure can be formed through the first gate structure in a first direction. S / D structures 122 and 124 can be electrically coupled to the first channel structure. Additionally, the portion of gate stack 102 adjacent to S / D structures 126 and 128 can be configured as a second gate structure, and a second channel structure can be formed through the second gate structure in a first direction. S / D structures 126 and 128 can be electrically coupled to the second channel structure. In some aspects, S / D structures 122 and 124 may have a first doping type, and S / D structures 126 and 128 may have a second doping type different from the first doping type.

[0028] In some aspects, the first gate structure, the first channel structure, S / D structure 122, and S / D structure 124 may be configured as a first type of first transistor; and the second gate structure, the second channel structure, S / D structure 126, and S / D structure 128 may be configured as a second type of second transistor. In some aspects, gate stacks 104 and 106 may be configured as dummy gates, which will be biased to electrically isolate S / D structures 122, 124, 126, and 128 from adjacent S / D structures (not shown).

[0029] like Figure 1AAs shown, the semiconductor structure 100 includes a contact 132 electrically coupled to the S / D structure 122, a contact 134 electrically coupled to the S / D structures 124 and 128, and a contact 136 electrically coupled to the S / D structure 126. The semiconductor structure 100 includes a first conductive structure 142, a second conductive structure 144, a third conductive structure 146, and a fourth conductive structure 148. The semiconductor structure 100 further includes a contact 152 electrically coupling the contact 132 to the first conductive structure 142, a contact 154 electrically coupling the contact 136 to the second conductive structure 144, a contact 156 electrically coupling the gate stack 102 to the third conductive structure 146, and a contact 158 ​​electrically coupling the contact 134 to the fourth conductive structure 148.

[0030] Figure 1B This is a schematic diagram illustrating an exemplary circuit generated by the semiconductor structure 100. In some aspects, Figure 1A A portion of the semiconductor structure 100 shown forms an inverter and can be used as a standard cell for manufacturing inverters in IC devices. In some aspects, the first conductive structure 142 may be a first power line configured to carry a first power supply voltage (e.g., VDD), and the second conductive structure 144 may be a second power line configured to carry a second power supply voltage (e.g., VSS or ground). In some aspects, the third conductive structure 146 may be a signal line configured to carry gate voltages for controlling the first gate structure of the first transistor and the second gate structure of the second transistor, such as the IN pin of the inverter. In some aspects, the fourth conductive structure 148 may be a signal line configured to carry S / D voltages at the S / D structure 124 of the first transistor and the S / D structure 128 of the second transistor, such as the OUT pin of the inverter.

[0031] Figure 2A and Figure 2B This is a top view of a portion of the semiconductor structure 200 of an IC device according to various aspects of this disclosure, with key elements located in their respective vertical regions. Specifically, Figure 2A The component shown can be in the vertical direction (e.g., the z-direction corresponding to the direction away from the drawing plane). Figure 2B The element shown is above the element. In some respects, Figure 2A and Figure 2B Some components of the semiconductor structure 200 are shown for illustrative purposes only, and Figure 2A and Figure 2B The components shown in the diagram may be positioned above and / or below that are not in the [specific location]. Figure 2A and Figure 2B Other elements shown in the diagram.

[0032] Figure 2A and Figure 2BThe diagram shows portions of two standard cells (cell 202 and cell 204) placed side-by-side. Each cell has multiple gate structures 206, a first set of S / D structures 208, and a second set of S / D structures 210. In some respects, the S / D structures are epitaxial layers. For ease of description, the gate structures 206 are labeled G1, G2, G3, G4, and G5. The first set of S / D structures 208 is further divided into S / D 208a, S / D 208b, S / D 208c, and S / D 208d. The second set of S / D structures 210 is further divided into S / D 210a, S / D 210b, S / D 210c, and S / D 210d. Although five gate structures are shown, it should be understood that a non-specific number of gate structures may exist in a cell or FET structure.

[0033] Figure 2A The diagram shows a front gate contact 212 positioned above and connected to the active portion of gate G1. The front gate contact above the active portion of the gate may be referred to herein as a "front contact above the active gate" (FSCOAG).

[0034] Figure 2A Also shown is a front gate contact 214 located above the non-active portion of the gate G2 and connected to the gate. The front gate contact above the non-active portion of the gate may be referred to herein as a "front gate contact" (FSGC).

[0035] Figure 2A The front S / D contact 216 connected to S / D 208b is also shown. Figure 2A A front S / D contact 218 connected to S / D 210d is also shown. The front S / D contact may be referred to herein as the "front S / D contact" (FSDC).

[0036] exist Figure 2A and Figure 2B In the example shown, portion 220 of gate G3 has been removed, effectively dividing the gate into a first portion G3 above S / D structure 208 and a second portion G3' above S / D structure 210. As will be explained in more detail below, G3 and G3' can be connected to a power source to shut down the corresponding active portion of the gate, which allows the separate gates to electrically isolate cell 202 from cell 204.

[0037] Please note that the general term “Front Side Contact” (FSC) can be used to refer to all types of front side contacts, and can also be used to refer to specific types such as FSCOAG, FSGC, or FSDC, depending on the context.

[0038] Figure 2B The diagram shows that the back-side gate contact 222 is placed above the active portion of G3 and connected to G3. Figure 2B Also shown is a back-side gate contact 224 above the active portion of G3' and connected to G3'. The back-side gate contact above the active portion of the gate may be referred to as a "back-side contact above the active gate" (BSCOAG).

[0039] Figure 2B Also shown is a back-side gate contact 226 located below the non-active portion of G4 and connected to G4. The back-side contact above the non-active portion of the gate may be referred to herein as a "back-side gate contact" (BSGC).

[0040] Figure 2B Also shown is the back-side S / D contact 228 connected to S / D 210a. Figure 2B Also shown is a back-side S / D contact 230 connected to S / D 208d. The back-side contact to the S / D area may be referred to herein as a "back-side S / D contact" (BSDC).

[0041] Please note that the general term "back-side contact" (BSC) can be used to refer to all types of back-side contacts, and can also refer to specific types such as BSCOAG, BSGC, or BSDC, depending on the context. It should be understood that any type of back-side contact can be used for signal routing, power routing, gate isolation, other purposes, or combinations thereof.

[0042] Figure 2B The back-side metal structure 232 connecting BSCOAG 222 and BSDC 230 is also shown. Figure 2B A back-side metal structure 234 connecting the BSCOAG224 and BSDC 228 is also shown. The back-side metal structure can be used for power supply, local routing, or both. For example, in some aspects, back-side metal structure 232 carries VDD and back-side metal structure 234 carries VSS.

[0043] Figure 2C This is a cross-sectional view of semiconductor structure 200 along the cutting line AA. Figure 2C Cross-sections of cells 202 and 204 are shown, as are cross-sections of gates G1-G5 and S / D structure 208.

[0044] Figure 2CAn epitaxial (EPI) termination layer 236 is also shown, located below the S / D structure 208 and surrounding the bottom portion of each gate stack. The EPI termination layer 236 is situated in the S / D region to prevent EPI growth from the substrate and serves as an etch stop layer for BSDC (but not BSGC). The EPI termination layer 236 also serves as an isolation layer between the BSCOAG structure and the S / D structure to prevent short circuits between the BSCOAG structure and the S / D structure. Example materials used for the EPI termination layer 236 include, but are not limited to, SiON, SiCON, SiN, or combinations thereof. In some aspects, the lower surface of the EPI termination layer 236 may be at approximately the same level as the lower surface of the gate structure of the gate stack.

[0045] Figure 2C Also shown is a back-side interlayer dielectric (BS-ILD) layer 238 that separates the EPI termination layer 236 from the back-side metal structure 232. Figure 2C The front interlayer dielectric (FS-ILD) layer 240 covering the S / D structure 208 and the gates G1-G5 is also shown. Figure 2C FSCOAG 212, which connects to the top of gate G1 through FS-ILD layer 240, is also shown. Figure 2C It is also shown that FSDC 216 is connected to the top of S / D 208b through FS-ILD layer 240. Figure 2C Also shown is BSCOAG 222, which is connected to the bottom of gate G3 through BS-ILD layer 238. Figure 2C Also shown is the BSDC 230, which connects to the bottom of the S / D 208d through the BS-ILD layer 238. Figure 2C In the example shown, BSCOAG 222 and BSDC 230 are connected to the back metal structure 232.

[0046] exist Figure 2C In the magnified area 242, details of a portion of the gate stack are shown. Figure 2CIn the example shown, each gate stack includes five gate portions, each gate portion including a corresponding gate electrode (e.g., gate electrodes 244a-244e) and a corresponding gate dielectric structure (e.g., gate dielectric structures 246a-246e). In this disclosure, all gate electrodes in the gate stack may be collectively referred to as gate electrode structure 244. In some aspects, the top gate portion of the gate stack may include gate spacers 248a on the sidewalls of gate dielectric structure 246a. In some aspects, the gate portions of the gate stack other than the top gate portion may include internal spacers (e.g., internal spacers 248b-248e) on the sidewalls of the corresponding gate dielectric structures (e.g., gate dielectric structures 246b-246e). Enlarged region 242 also shows the locations of channels 250a-250d through which charge carriers travel horizontally from left to right or right to left in the figure.

[0047] like Figure 2C As shown, the first thickness T1 of the gate electrode below the bottom channel 250d is greater than the second thickness T2 of the gate electrode between adjacent channels 250a-250d. Therefore, the inner gate electrodes 244b-244d have a second thickness T2, and the bottom gate electrode 244e has a first thickness T1 greater than T2. ​​The larger thickness T1 provides good margin for the etching step that creates the back-side gate contact. Specifically, the additional thickness provides greater process margin during the etching step that allows for the use of the bottom gate electrode 244e through the BSCOAG 222 of the BS-ILD layer 238. In some aspects, the thickness of T1 is twice that of T2. In some aspects, the thickness of T1 is more than twice that of T2. In some aspects, T1 is thicker than T2, but less than twice the thickness of T2. In some aspects, T1 is 1.3-2.0 times thicker than T2. ​​In some aspects, the third thickness T3 of the gate electrode above the top channel 250a is greater than the second thickness T2. The larger thickness T3 also provides good margin for the etching steps that produce the front gate contacts.

[0048] exist Figure 2C In the illustrated embodiments, the gate stack is a gate-all-around (GAA) design that surrounds one or more channels, such as channel 250a, channel 250b, channel 250c, etc., but the BSGC disclosed herein is also applicable to FinFET and other FET designs. The BSCOAG disclosed herein will not be applicable to FinFET because there is no gate material accessible to BSCOAG beneath the FinFET channels.

[0049] Therefore, in Figure 2CIn the illustrated embodiment, the gate stacks G1-G5 include a gate structure disposed between a first vertical S / D structure and a second vertical S / D structure. The gate structure includes a channel structure comprising a plurality of vertically stacked horizontal channels. The plurality of vertically stacked horizontal channels horizontally connect the first vertical S / D structure to the second vertical S / D structure via a vertical metal gate structure that at least partially surrounds the plurality of vertically stacked horizontal channels. The first thickness T1 of the metal gate electrode below the bottom channel in the plurality of vertically stacked horizontal channels is greater than the second thickness T2 of the metal gate electrode between adjacent channels in the plurality of vertically stacked horizontal channels.

[0050] Figure 2D This is a cross-sectional view of semiconductor structure 200 along the cutting line BB. Figure 2D The cross-sections of gates G1-G5 are shown, where there are no side-wing S / D structures and no channels (i.e., not above the active region), and where the gate stack is separated by FS-ILD 240. Figure 2D As shown, the gate stack is separated from the BS-ILD layer 238 by the shallow trench isolation (STI) layer 248. Figure 2D As shown, the back-side intermetallic dielectric (BS-IMD) layer 252 is disposed below the BS-ILD layer 238.

[0051] Figure 2D FSGC 214, which contacts G2 through FS-ILD layer 240, is also shown. Figure 2D Also shown is BSGC 226, which contacts a portion of the bottom surface of the gate stack of gate G4 through STI layer 248 and BS-ILD layer 238.

[0052] Figure 2E This is a cross-sectional view of semiconductor structure 200 along the cutting line CC. Figure 2E The cross section of section 220, showing gates G3 and G3' and the gate stack being removed to create two portions G3 and G3', is shown. Figure 2E Channels 250a-250d, gate dielectric structure 246, and gate electrode structure 244 are also shown. (See diagram for reference.) Figure 2E As shown, the gate stack is separated from the BS-ILD layer 238 by the STI layer 248. BSCOAG 224 is connected to the back metal structure 234 through the BS-ILD layer 238, and BSCOAG 222 is connected to the back metal structure 232 through the BS-ILD layer 238. The back metal structures are isolated from each other by the BS-IMD layer 252. Figure 2EAn example of "gate isolation low" is shown, where the gates are separated such that one portion is above the pFET and the other portion is above the nFET, and where the gate of the pFET is connected to VDD and the gate of the nFET is connected to VSS, turning them both off. For example, if gate G3 is the gate of the pFET and gate G3' is the gate of the nFET, and if back metal structure 232 carries VDD and back metal structure 234 carries VSS, then gates G3 and G3' generate a gate isolation low, which isolates the circuitry of cell 202 from the circuitry of cell 204.

[0053] Figure 2F This is a top view of a variant of the semiconductor structure 200 of an IC device with power rails aligned to the boundary according to various aspects of this disclosure. Specifically, Figure 2F The element shown illustrates that it can be located in the vertical direction. Figure 2A The component shown is below the component shown. Unless otherwise stated, Figure 2F The components shown are Figure 2B Elements with the same number are identical, and therefore their descriptions will not be repeated here. Figure 2F In the example shown, the back-side metal structures 232 and 234 that provide power to the back-side gate contacts 222 and 224, respectively, are boundary aligned, meaning that they extend along the edges of cells 202 and 204 in the X direction, are separated in the Y direction, and have a row spacing equal to the height of cells 202 and 204. This allows each back-side metal structure 232 and 234 to also be used by a standard cell adjacent to cells 202 and 204 in the Y direction.

[0054] Figure 2G yes Figure 2F The diagram shows a cross-sectional view of the semiconductor structure along the dicing line DD. Figure 2G Cross-sections of cells 202 and 204 are shown, as are cross-sections of gates G1-G5 and the S / D structure 208. Unless otherwise stated, Figure 2G The components shown are Figure 2C Elements with the same number are identical, and therefore their descriptions will not be repeated here. Figure 2G In the example shown, the back metal structure 232 is boundary aligned, and its position ensures that FSCOAG 212 and FSDC 216 are not present at the cut line location, and therefore in Figure 2G Not shown in the image.

[0055] Figure 2H yes Figure 2F The diagram shows a cross-sectional view of the semiconductor structure along the dicing line EE. Unless otherwise specified, Figure 2H The components shown are Figure 2EThe elements with the same number are identical, and therefore their description will not be repeated here. It can be seen that in Figure 2H In the middle, BSCOAG 222 and 224 are positioned closer to the edge of the standard cell in the Y direction to contact the back metal structures 232 and 234, which are aligned with the boundary, respectively.

[0056] Figures 3A to 3D This is a cross-section illustrating steps in the process of manufacturing BSCOAG according to various aspects of this disclosure. For example... Figure 3A As shown, the process begins with a semiconductor structure 200, which includes a gate stack (e.g., gate G3) having channels connecting a first S / D structure 208b and a second S / D structure 208c within an epitaxial layer 209, which itself is disposed within an FS-ILD layer 240. An EPI termination layer 236 separates the epitaxial layer 209 from the BS-ILD layer 238. Figures 3A to 3D In the example shown, the gate stack includes a GAA structure, but the same principle can be applied to finFET or other structures.

[0057] Figure 3A The results after applying the resist layer 300 and the patterning process, which can be referred to herein as the BSCOAG / BSGC lithography step, are illustrated.

[0058] Figure 3B The result is illustrated after the first etch process, which etches through the BS-ILD layer 238 but terminates at the high-K gate dielectric structure 246e.

[0059] Figure 3C The result is illustrated after a second etching process that etches through the high-K gate dielectric structure 246e but terminates at the gate electrode 244e.

[0060] Figure 3D The results are illustrated after removing the resist layer 300, metallizing BSCOAG 222 (or BSGC), and planarization steps such as chemical / mechanical polishing. The materials for BSCOAG and BSGC may include, but are not limited to, tungsten, cobalt, molybdenum, and ruthenium.

[0061] Figure 4 This is a flowchart of an example process 400 associated with the fabrication of a GAA FET transistor structure according to various aspects of this disclosure.

[0062] like Figure 4As shown, at block 410, process 400 may include providing a gate structure disposed between a first vertical S / D structure and a second vertical S / D structure. The gate structure includes a channel structure and a vertical metal gate structure. The channel structure includes a plurality of vertically stacked horizontal channels that horizontally connect the first vertical S / D structure to the second vertical S / D structure via the vertical metal gate structure that at least partially surrounds the plurality of vertically stacked horizontal channels.

[0063] In some respects, at least one of the first vertical S / D structure and the second vertical S / D structure includes an EPI layer.

[0064] In some respects, the vertical metal gate structure includes a high-k dielectric layer that at least partially surrounds the work function metal layer.

[0065] In some respects, the channel structure is contained within a first portion of the vertical metal gate structure and not within a second portion of the vertical metal gate structure.

[0066] In some respects, the second part of the vertical metal gate structure is separated from the back-side ILD structure by an STI layer.

[0067] like Figure 4 As further shown, at block 420, process 400 may include providing a back-side ILD layer disposed below the vertical metal gate structure, wherein a first thickness T1 of the vertical metal gate structure below the bottom channel of the plurality of vertically stacked horizontal channels is greater than a second thickness T2 of the vertical metal gate structure between adjacent channels of the plurality of vertically stacked horizontal channels.

[0068] In some aspects, process 400 may further include providing a back-side contact structure electrically coupled to the vertical metal gate structure through the back-side ILD layer or through the back-side ILD layer and STI layer.

[0069] In some respects, the back-side contact structure is electrically coupled to a back-side metallization structure disposed beneath the back-side ILD layer.

[0070] In some aspects, the FET structure is a component of a standard cell having a left cell boundary and a right cell boundary separated from each other in a first horizontal direction, and a top cell boundary and a bottom cell boundary separated from each other in a second horizontal direction, wherein providing the back-side metallization structure includes providing a pair of conductors that extend from the left cell boundary to the right cell boundary in the first horizontal direction and are separated from each other in the second horizontal direction. The first horizontal direction may be orthogonal to the second horizontal direction.

[0071] In some aspects, providing the pair of conductors includes providing the pair of conductors in the second horizontal direction between the top cell boundary and the bottom cell boundary.

[0072] In some aspects, providing the pair of conductors includes providing a first conductor in the pair that crosses the top cell boundary and a second conductor in the pair that crosses the bottom cell boundary.

[0073] In some aspects, the back-side contact structure includes a back-side gate isolation low, for example, to connect a portion of the vertical metal gate structure to VDD or VSS.

[0074] In some aspects, process 400 may further include providing an S / D via through the back side ILD layer to the first vertical S / D structure.

[0075] In some aspects, process 400 may further include providing a front-side ILD layer that at least partially surrounds the gate structure.

[0076] In some aspects, process 400 may further include providing an S / D via through the front ILD layer to connect to the first vertical S / D structure.

[0077] Process 400 may include additional embodiments, such as any single embodiment or any combination of embodiments of one or more other processes described above and / or in conjunction with those described elsewhere herein. Although Figure 4 An example block diagram of process 400 is shown, but in some specific implementations, process 400 may include... Figure 4 The boxes depicted in the process 400 may be fewer, different, or arranged differently than additional boxes, fewer, different, or different from other boxes. Alternatively, two or more boxes in the process 400 may be executed in parallel.

[0078] Figure 5 A mobile device 500 according to various aspects of this disclosure is illustrated. In some aspects, the mobile device 500 may be implemented by including one or more IC devices manufactured based on the examples described in this disclosure.

[0079] In some aspects, the mobile device 500 can be configured as a wireless communication device. As shown, the mobile device 500 includes a processor 502. The processor 502 is communicatively coupled to a memory 504 via a link, which can be a die-to-die or chip-to-chip link. The mobile device 500 also includes a display 506 and a display controller 508, wherein the display controller 508 is coupled to the processor 502 and the display 506. The mobile device 500 may include an input device 510 (e.g., a physical or virtual keyboard), a power supply 512 (e.g., a battery), a speaker 514, a microphone 516, and a wireless antenna 518. In some aspects, the power supply 512 may directly or indirectly provide the power supply voltage for some or all of the components of the mobile device 500.

[0080] In some respects, Figure 5 It may include a decoder / decoder (codec) 520 (e.g., an audio and / or voice codec) coupled to the processor 502; a speaker 514 and a microphone 516 coupled to the codec 520; and a wireless circuit 522 (which may include a modem, RF circuitry, filters, etc.) coupled to the wireless antenna 518 and coupled to the processor 502.

[0081] In some aspects, one or more of the processor 502, display controller 508, memory 504, codec 520, and wireless circuit 522 may include one or more IC devices, the one or more IC devices including semiconductor structures manufactured according to the examples described in this disclosure.

[0082] It should be noted that, although Figure 5 Mobile device 500 is described, but similar architectures can be used to implement devices including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed-location data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices.

[0083] Figure 6 Examples of various electronic devices that may integrate any of the following: the aforementioned devices, semiconductor devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, stacked package (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, as described herein, mobile phone device 602, laptop computer device 604, fixed-location terminal device 606, wearable device 608, or motor vehicle 610 may include semiconductor device 600 (e.g., semiconductor structure 200). Figure 6The devices 602, 604, 606, and 608 illustrated herein, as well as vehicle 610, are merely exemplary. Other devices or apparatuses may also feature semiconductor device 600, including but not limited to a group of devices comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0084] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various aspects of this disclosure may include fewer features than those in the individual example clauses disclosed. Therefore, the following clauses should be regarded accordingly as incorporated into the description, where each clause may serve as a separate example. Although each dependent clause may refer in the clause to a specific combination with one of the other clauses, the aspect of that dependent clause is not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects of a dependent clause with the subject matter of any other dependent or independent clause, or combinations of any feature with other dependent and independent clauses. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of a clause may be included in any other independent clause, even if that clause does not directly depend on the independent clause.

[0085] Specific implementation examples are described in the following numbered clauses.

[0086] Clause 1. A field-effect transistor (FET) structure, the FET structure comprising: a gate structure disposed between a first vertical source / drain (S / D) structure and a second vertical S / D structure, the gate structure including a channel structure and a vertical metal gate structure, the channel structure including a plurality of vertically stacked horizontal channels, the plurality of vertically stacked horizontal channels connecting the first vertical S / D structure to the second vertical S / D structure in a first horizontal direction through the vertical metal gate structure at least partially surrounding the plurality of vertically stacked horizontal channels; and a back-side interlayer dielectric (ILD) layer disposed below the vertical metal gate structure, wherein a first thickness of the vertical metal gate structure below the bottom channel of the plurality of vertically stacked horizontal channels is greater than a second thickness of the vertical metal gate structure between adjacent channels of the plurality of vertically stacked horizontal channels.

[0087] Clause 2. The FET structure according to Clause 1, wherein the third thickness of the vertical metal gate structure above the top channel of the plurality of vertically stacked horizontal channels is greater than the second thickness of the vertical metal gate structure between adjacent channels of the plurality of vertically stacked horizontal channels.

[0088] Clause 3. The FET structure according to any one of Clauses 1 to 2, the FET structure further comprising a back-side contact structure electrically coupled to the vertical metal gate structure through the back-side ILD layer or through the back-side ILD layer and the shallow trench isolation (STI) layer.

[0089] Clause 4. The FET structure according to Clause 3, wherein the back-side contact structure is electrically coupled to a back-side metallization structure disposed beneath the back-side ILD layer.

[0090] Clause 5. The FET structure according to Clause 4, wherein the FET structure is an assembly of a standard cell having a left cell boundary and a right cell boundary separated from each other in a first horizontal direction, and having a top cell boundary and a bottom cell boundary separated from each other in a second horizontal direction, and wherein the back-side metallization structure includes a pair of conductors extending from the left cell boundary to the right cell boundary in the first horizontal direction and separated from each other in the second horizontal direction.

[0091] Clause 6. The FET structure according to Clause 5, wherein the pair of conductors are located between the top cell boundary and the bottom cell boundary in the second horizontal direction.

[0092] Clause 7. The FET structure according to Clause 5, wherein the first conductor of the pair of conductors crosses the top cell boundary and the second conductor of the pair of conductors crosses the bottom cell boundary.

[0093] Clause 8. The FET structure according to any one of Clauses 3 to 7, wherein the back-side contact structure includes a back-side gate isolation low.

[0094] Clause 9. The FET structure according to any one of Clauses 1 to 8, the FET structure further comprising a back-side S / D via through the back-side ILD layer connected to the first vertical S / D structure.

[0095] Clause 10. A method for manufacturing a field-effect transistor (FET) structure, the method comprising: providing a gate structure disposed between a first vertical source / drain (S / D) structure and a second vertical S / D structure, the gate structure including a channel structure and a vertical metal gate structure, the channel structure including a plurality of vertically stacked horizontal channels, the plurality of vertically stacked horizontal channels connecting the first vertical S / D structure to the second vertical S / D structure in a first horizontal direction through the vertical metal gate structure at least partially surrounding the plurality of vertically stacked horizontal channels; and providing a back-side interlayer dielectric (ILD) layer disposed below the vertical metal gate structure, wherein a first thickness of the vertical metal gate structure below a bottom channel in the plurality of vertically stacked horizontal channels is greater than a second thickness of the vertical metal gate structure between adjacent channels in the plurality of vertically stacked horizontal channels.

[0096] Clause 11. The method according to Clause 10, wherein the third thickness of the vertical metal gate structure above the top channel of the plurality of vertically stacked horizontal channels is greater than the second thickness of the vertical metal gate structure between adjacent channels of the plurality of vertically stacked horizontal channels.

[0097] Clause 12. The method according to any one of Clauses 10 to 11, the method further comprising providing a back-side contact structure electrically coupled to the vertical metal gate structure through the back-side ILD layer or through the back-side ILD layer and the shallow trench isolation (STI) layer.

[0098] Clause 13. The method according to Clause 12, wherein the back-side contact structure is electrically coupled to a back-side metallization structure disposed beneath the back-side ILD layer.

[0099] Clause 14. The method according to Clause 13, wherein the FET structure is a component of a standard cell having a left cell boundary and a right cell boundary separated from each other in a first horizontal direction, and having a top cell boundary and a bottom cell boundary separated from each other in a second horizontal direction, and wherein providing the back-side metallization structure includes providing a pair of conductors that extend from the left cell boundary to the right cell boundary in the first horizontal direction and are separated from each other in the second horizontal direction.

[0100] Clause 15. The method according to Clause 14, wherein providing the pair of conductors includes providing the pair of conductors in the second horizontal direction between the top cell boundary and the bottom cell boundary.

[0101] Clause 16. The method according to Clause 14, wherein providing the pair of conductors includes providing a first conductor of the pair of conductors that crosses the top cell boundary and providing a second conductor of the pair of conductors that crosses the bottom cell boundary.

[0102] Clause 17. The method according to any one of Clauses 12 to 16, wherein the back-side contact structure includes a back-side gate isolation low.

[0103] Clause 18. The method according to any one of Clauses 12 to 17, wherein providing the back-side contact structure electrically coupled to the vertical metal gate structure through the back-side ILD layer or through the back-side ILD layer and the STI layer comprises: etching the back-side ILD layer to expose a dielectric layer of the vertical metal gate structure below the bottom channel in a plurality of vertically stacked horizontal channels; etching the dielectric layer to expose a gate electrode of the vertical metal gate structure below the bottom channel in a plurality of vertically stacked horizontal channels; and performing a metallization process to produce the back-side contact structure electrically coupled to the vertical metal gate structure below the bottom channel in a plurality of vertically stacked horizontal channels.

[0104] Clause 19. The method according to any one of Clauses 10 to 18, the method further comprising providing a back-side S / D via through the back-side ILD layer to the first vertical S / D structure.

[0105] Clause 20. The method according to any one of Clauses 14 to 16, wherein the first horizontal direction is orthogonal to the second horizontal direction.

[0106] Clause 21. The FET structure according to any one of Clauses 5 to 7, wherein the first horizontal direction is orthogonal to the second horizontal direction.

[0107] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0108] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0109] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0110] The methods, sequences, and / or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. Example storage media are coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0111] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0112] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. Furthermore, the functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Moreover, although elements of this disclosure may be described or claimed in the singular, the plural form may also be considered unless expressly stated as limited to the singular.

Claims

1. A field-effect transistor (FET) structure, the field-effect transistor (FET) structure comprising: A gate structure disposed between a first vertical source / drain (S / D) structure and a second vertical S / D structure, the gate structure including a channel structure and a vertical metal gate structure, the channel structure including a plurality of vertically stacked horizontal channels, the plurality of vertically stacked horizontal channels connecting the first vertical S / D structure to the second vertical S / D structure in a first horizontal direction through the vertical metal gate structure surrounding the plurality of vertically stacked horizontal channels at least partially. and A back-side interlayer dielectric (ILD) layer is disposed beneath the vertical metal gate structure. The first thickness of the vertical metal gate structure below the bottom channel in the plurality of vertically stacked horizontal channels is greater than the second thickness of the vertical metal gate structure between adjacent channels in the plurality of vertically stacked horizontal channels.

2. The FET structure of claim 1, wherein the third thickness of the vertical metal gate structure above the top channel of the plurality of vertically stacked horizontal channels is greater than the second thickness of the vertical metal gate structure between adjacent channels of the plurality of vertically stacked horizontal channels.

3. The FET structure according to claim 1, wherein the FET structure further comprises a back-side contact structure electrically coupled to the vertical metal gate structure through the back-side ILD layer or through the back-side ILD layer and the shallow trench isolation (STI) layer.

4. The FET structure according to claim 3, wherein the back-side contact structure is electrically coupled to a back-side metallization structure disposed below the back-side ILD layer.

5. The FET structure of claim 4, wherein the FET structure is a component of a standard cell having a left cell boundary and a right cell boundary separated from each other in a first horizontal direction, and having a top cell boundary and a bottom cell boundary separated from each other in a second horizontal direction, and wherein the back-side metallization structure includes a pair of conductors extending from the left cell boundary to the right cell boundary in the first horizontal direction and separated from each other in the second horizontal direction.

6. The FET structure of claim 5, wherein the pair of conductors are located between the top cell boundary and the bottom cell boundary in the second horizontal direction.

7. The FET structure of claim 5, wherein the first conductor of the pair of conductors crosses the top cell boundary, and the second conductor of the pair of conductors crosses the bottom cell boundary.

8. The FET structure of claim 5, wherein the first horizontal direction is orthogonal to the second horizontal direction.

9. The FET structure of claim 3, wherein the back-side contact structure includes a back-side gate isolation low.

10. The FET structure of claim 1, further comprising a back-side S / D via through the back-side ILD layer and connected to the first vertical S / D structure.

11. A method for manufacturing a field-effect transistor (FET) structure, the method comprising: A gate structure is provided, the gate structure being disposed between a first vertical source / drain (S / D) structure and a second vertical S / D structure, the gate structure including a channel structure and a vertical metal gate structure, the channel structure including a plurality of vertically stacked horizontal channels, the plurality of vertically stacked horizontal channels connecting the first vertical S / D structure to the second vertical S / D structure in a first horizontal direction through the vertical metal gate structure at least partially surrounding the plurality of vertically stacked horizontal channels; and A back-side interlayer dielectric (ILD) layer is provided, the back-side interlayer dielectric (ILD) layer being disposed beneath the vertical metal gate structure. The first thickness of the vertical metal gate structure below the bottom channel in the plurality of vertically stacked horizontal channels is greater than the second thickness of the vertical metal gate structure between adjacent channels in the plurality of vertically stacked horizontal channels.

12. The method of claim 11, wherein the third thickness of the vertical metal gate structure above the top channel of the plurality of vertically stacked horizontal channels is greater than the second thickness of the vertical metal gate structure between adjacent channels of the plurality of vertically stacked horizontal channels.

13. The method of claim 11, further comprising providing a back-side contact structure electrically coupled to the vertical metal gate structure through the back-side ILD layer or through the back-side ILD layer and the shallow trench isolation (STI) layer.

14. The method of claim 13, wherein the back-side contact structure is electrically coupled to a back-side metallization structure disposed beneath the back-side ILD layer.

15. The method of claim 14, wherein the FET structure is a component of a standard cell having a left cell boundary and a right cell boundary separated from each other in a first horizontal direction, and a top cell boundary and a bottom cell boundary separated from each other in a second horizontal direction, and wherein providing the back-side metallization structure includes providing a pair of conductors that extend from the left cell boundary to the right cell boundary in the first horizontal direction and are separated from each other in the second horizontal direction.

16. The method of claim 15, wherein providing the pair of conductors comprises providing the pair of conductors in the second horizontal direction between the top cell boundary and the bottom cell boundary.

17. The method of claim 15, wherein providing the pair of conductors comprises providing a first conductor of the pair of conductors across the top cell boundary and providing a second conductor of the pair of conductors across the bottom cell boundary.

18. The method of claim 13, wherein the back-side contact structure includes a back-side gate isolation low.

19. The method of claim 13, wherein providing the back-side contact structure electrically coupled to the vertical metal gate structure through the back-side ILD layer or through the back-side ILD layer and the STI layer comprises: Etch the back-side ILD layer to expose the dielectric layer of the vertical metal gate structure beneath the bottom channel in the plurality of vertically stacked horizontal channels; Etch the dielectric layer to expose the gate electrode of the vertical metal gate structure beneath the bottom channel in the plurality of vertically stacked horizontal channels; as well as A metallization process is performed to produce a back-side contact structure electrically coupled to the vertical metal gate structure below the bottom channel in the plurality of vertically stacked horizontal channels.

20. The method of claim 11, the method further comprising providing a back-side S / D via through the back-side ILD layer to the first vertical S / D structure.

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