Gate grounding using trench grounding scheme in backside power architecture

Abstract

A gate ground (GTD) cell utilizing a backside power delivery scheme is disclosed in which metal lines that deliver power are disposed on the backside of a wafer. Thus, an ultra-low height standard cell may be implemented. And relatively high area miniaturization can be realized. In addition, performance and power gain may be maximized.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor devices, and more specifically, but not exclusively, to novel structures and fabrication techniques for using trench grounding (TDD) schemes to construct gate grounding (GTD) in back-side power architectures. Background Technology

[0002] Integrated circuit (IC) technology has made significant strides in improving computing power through the miniaturization of active components. In IC technology, a cell can be viewed as a circuit that provides logic functions such as AND, NOT, OR, etc. Gate-grounded (GTD) enables electrical diffusion interruption and avoids the need for physical diffusion interruption. Conventional GTD schemes typically implement front-side power designs, where the metal lines are on the front side of the wafer. Unfortunately, this usually requires wider power rails and larger / taller logic cells.

[0003] Accordingly, there is a need for systems, apparatuses, and methods to overcome the shortcomings of conventional equipment, including the methods, systems, and apparatuses provided herein. Summary of the Invention

[0004] The following is a simplified overview relating to one or more aspects and / or examples associated with the various apparatuses and methods disclosed herein. Thus, this overview should not be considered an exhaustive overview relating to all aspects and / or examples considered, nor should it be considered to identify key or decisive elements relating to all aspects and / or examples considered, or to depict the scope relating to any particular aspect and / or example. Accordingly, the sole purpose of the following overview is to present, in a simplified form, certain concepts relating to one or more aspects and / or examples of the apparatuses and methods disclosed herein before the detailed descriptions presented below.

[0005] An exemplary gate-grounded (GTD) cell is disclosed. The cell may include a first edge gate and a second edge gate extending in a first direction. The first edge gate and the second edge gate may define the boundary of the GTD cell. The cell may also include a channel band extending from the first edge gate to the second edge gate in a second direction different from the first direction. The channel band may be formed at least partially within the first edge gate and the second edge gate. The cell may also include a back-side power (BSP) rail extending in the second direction. The BSP rail may be formed below the first edge gate and the second edge gate and below the channel band. The cell may also include a BSP trench extending in the second direction. The BSP trench may be formed on the BSP rail. The BSP trench may be conductive and electrically coupled to the BSP rail and to the first edge gate and the second edge gate. A first edge portion of the channel band within the first edge gate may be configured to prevent the formation of a first channel in the first edge portion when a turn-off voltage is applied to the first edge gate. The second edge portion of the channel band within the second edge gate can be configured to prevent the formation of a second channel in the second edge portion when the turn-off voltage is applied to the second edge gate. The BSP rail can be configured to apply the turn-off voltage to the first edge gate and the second edge gate through the BSP trench.

[0006] A method for manufacturing a gate-grounded (GTD) cell is disclosed. The method may include forming a first edge gate and a second edge gate extending in a first direction. The first edge gate and the second edge gate may define the boundary of the GTD cell. The method may further include forming a channel strip extending from the first edge gate to the second edge gate in a second direction different from the first direction. The channel strip may be formed at least partially within the first edge gate and the second edge gate. The method may further include forming a back-side power (BSP) rail extending in the second direction. The BSP rail may be formed below the first edge gate and the second edge gate and below the channel strip. The method may further include forming a BSP trench extending in the second direction. The BSP trench may be formed on the BSP rail. The BSP trench may be conductive and electrically coupled to the BSP rail and to the first edge gate and the second edge gate. A first edge portion of the channel strip within the first edge gate may be configured to prevent the formation of a first channel in the first edge portion when a turn-off voltage is applied to the first edge gate. The second edge portion of the channel band within the second edge gate can be configured to prevent the formation of a second channel in the second edge portion when the turn-off voltage is applied to the second edge gate. The BSP rail can be configured to apply the turn-off voltage to the first edge gate and the second edge gate through the BSP trench.

[0007] Other features and advantages associated with the various apparatuses and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. Attached Figure Description

[0008] When considered in conjunction with the accompanying drawings, a more complete understanding of the various aspects of this disclosure and its many advantages therefrom will become better understood by referring to the following detailed description, which is presented for illustrative purposes only and does not constitute any limitation on this disclosure.

[0009] Figure 1 A conventional gate grounding unit is illustrated.

[0010] Figure 2 An example of a gate grounding unit according to one or more aspects of this disclosure is illustrated.

[0011] Figures 3A to 3D Examples of one or more aspects of this disclosure are illustrated. Figure 2 The cross-section of the gate grounding unit.

[0012] Figures 4A to 11B Examples of various stages of manufacturing a gate ground cell according to one or more aspects of this disclosure are illustrated.

[0013] Figures 12 to 14 A flowchart illustrating an example method for manufacturing a gate ground cell according to one or more aspects of this disclosure is provided.

[0014] Figure 15 Various electronic devices that can utilize one or more aspects of this disclosure are illustrated.

[0015] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. As is customary, the features depicted in the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily enlarged or reduced for clarity. As is customary, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular apparatus or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0016] Various aspects of this disclosure are illustrated in the following description and related figures with respect to specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of this teaching. Furthermore, well-known elements of the illustrative embodiments herein will not be described in detail or will be omitted to avoid obscuring the relevant details of the teachings in this disclosure.

[0017] In some of the described example implementations, instances are identified where various parts of the component structures and operations are available from known conventional techniques and are subsequently arranged according to one or more exemplary embodiments. In such instances, internal details of the parts of known conventional component structures and / or operations may be omitted to help avoid potential confusion with the concepts illustrated in the exemplary embodiments disclosed herein.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the term “comprising,” as used herein, specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0019] As noted above, a cell can be viewed as a circuit providing logic functions such as AND, NOT, and OR. Gate connection (GTD) enables electrical diffusion interruption and avoids the need for physical diffusion interruption. Conventional GTD schemes typically implement front-side power designs, where the metal lines are on the front side of the wafer.

[0020] Figure 1 A standard cell utilizing a conventional GTD scheme is illustrated. As shown, cell 100 includes a first edge gate 110A and a second edge gate 110B extending vertically, and an inner gate 120 also extending vertically. The inner gate 120 is located between the first edge gate 110A and the second edge gate 110B. The conventional cell 100 also includes power rails 140 and channel strips 150 (shown as dashed boxes) extending horizontally. The channel strips 150 are located between the power rails 140. The power rails 140 are electrically coupled to the edge gates 110A and 110B via a ground via 160. A gate notch 130 illustrates an area where portions of the gate (e.g., portions of the first edge gate 110A and the second edge gate 110B and / or the inner gate 120) can be cut or otherwise removed.

[0021] exist Figure 1In this embodiment, the upper and lower boundaries of cell 100 are defined by the upper and lower sides of the first edge gate 110A and the second edge gate 110B. Additionally, the left and right boundaries of the cell are defined by the first edge gate 110A and the second edge gate 110B. That is, in one aspect, it can be said that the first edge gate 110A and the second edge gate 110B at least partially define the boundaries of cell 100. Cell 100 should be isolated from other cells, such as adjacent cells. In the GTD scheme, electrical isolation is achieved by applying a gate turn-off voltage (or more simply, a "turn-off" voltage) to the first edge gate 110A and the second edge gate 110B. When the turn-off voltage is applied to the first edge gate 110A and the second edge gate 110B, no conductive channel is formed in the channel band below the first edge gate 110A and the second edge gate 110B. Therefore, electrical isolation can be achieved even if the channel band 150 itself is physically continuous outside the boundaries of cell 100. In other words, it is not necessary to physically interrupt the channel band 150. Therefore, in this configuration, it is assumed that the power rail delivers the turn-off voltage. This "electrical diffusion interruption" is desirable because it reduces parameter variations compared to units with "physical diffusion interruption".

[0022] In cell 100 employing a conventional GTD (Getting Things Done) scheme, the metal lines are on the front side of the wafer. Figure 1 In this context, it means that power rail 140 is "above" the first edge gate 110A and the second edge gate 110B. As technology miniaturizes, cells become shorter. Unfortunately, implementing GTD using typical "front-side power" becomes more difficult. Generally, wider power rails and larger or taller logic cells are required, which is undesirable.

[0023] To address these and other issues of conventional GTD cells, a trench configuration (i.e., the Trench Grounding (TDD) method) is proposed to utilize back-side power. Using this method, cell miniaturization (e.g., smaller cells) can be achieved while still utilizing GTD. Significant technical advantages exist in implementing GTD using the proposed TDD method. These include (not necessarily exhaustive): • Achieve ultra-low height standard units; • Achieve greater area miniaturization; and • Maximize performance and power gain.

[0024] Figure 2 Examples of gate-grounded (GTD) cells according to one or more aspects of this disclosure are illustrated. Specifically, Figure 2The diagram shows a top view of a unit 200 embodying an example design. Unit 200 may include a first edge gate 210A and a second edge gate 210B (also commonly referred to as one or more edge gates 210). The first edge gate 210A and the second edge gate 210B may extend in a first direction (e.g., a vertical direction). An inner gate 120 extending in the first direction may be between the first edge gate 210A and the second edge gate 210B. The edge gates 210A, 210B and / or the inner gate 220 may be formed of a metal (e.g., copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), ruthenium (Ru), titanium aluminide (TiAl), titanium nitride (TiN), etc.). Although only one inner gate 220 is illustrated, any number of inner gates 220 may be present between the edge gates 210A, 210B. Gate cutout 230 illustrates a region in which portions of the gate (e.g., portions of the first edge gate 210A and the second edge gate 210B and / or the inner gate 220) can be cut or otherwise removed.

[0025] Cell 200 may also include one or more channel bands 250 extending in a second direction (e.g., a horizontal direction) different from the first direction. In one aspect, the first and second directions may be orthogonal (or substantially orthogonal) to each other. The channel bands 250 may be formed of silicon (Si) or other semiconductor materials such as silicon germanium (SiGe), gallium arsenide (GaAs), etc. The channel bands 250 may be formed at least partially within the first edge gate 210A and the second edge gate 210B and / or the inner gate 220. Cell 200 may be a fin field-effect transistor (FinFET) cell. That is, the channel bands 250 may be the fins of a FinFET device. Alternatively, cell 200 may be a gate all-around (GAA) cell. That is, the channel bands 250 may be nanosheets of a GAA device.

[0026] Unit 200 may also include one or more back-side power (BSP) rails 240 extending in a second (e.g., horizontal) direction. The BSP rails 240 may be positioned below the channel band 250. The BSP rails 240 may be formed of a metal (e.g., Cu, Co, Mo, W, Ru, TiAl, TiN, etc.).

[0027] Unit 200 may also include one or more BSP trenches 260 extending in a second (e.g., horizontal) direction. In one aspect, each BSP trench 260 may be formed on a corresponding BSP rail 240. The BSP trenches 260 may be conductive. For example, the BSP trenches 260 may be formed of a metal such as Cu, Co, Mo, W, Ru, TiAl, TiN, etc. The BSP trenches 260 may be electrically coupled to the BSP rails 240 (e.g., a first edge gate 210A and a second edge gate 210B). However, the inner gate 220 does not need to be electrically coupled to the BSP rails. The inner gate 220 may be configured to be electrically coupled to one or more signal lines instead of power lines.

[0028] Cell 200 may also include one or more trench contacts 270. The trench contacts 270 can electrically couple the BSP trench 260 to the source / drain (S / D) of cell 200.

[0029] exist Figure 2 In this configuration, the first edge gate 210A and the second edge gate 210B may define the boundaries of cell 200 in one direction (e.g., left and right boundaries), and the BSP trench 260 may define boundaries in an orthogonal direction (e.g., top and bottom boundaries). In one aspect, the BSP rail 240 may be configured to apply a turn-off voltage (e.g., one of Vss and Vdd) to the first edge gate 210A and the second edge gate 210B through the BSP trench 260. Therefore, cell 200 may be isolated from other cells (including adjacent cells immediately adjacent to cell 200).

[0030] Figure 3A Example of the edge of unit 200 Figure 2 The cross-section of the X1-X1 cut line is shown. As seen in the figure, cell 200 along this cross-section may include a BSP rail 240, an oxide (or dielectric) 325 located on the BSP rail 240, and a first gate 210A and a second gate 210B located on the oxide 325. In one aspect, the oxide 325 may be used as shallow trench isolation (STI). A BSP trench 260 may be formed on the BSP rail 240. Recall that the BSP trench 260 may electrically couple the BSP rail 240 to the first edge gate 210A and / or the second edge gate 210B. In one aspect, the BSP trench 260 may be in direct contact with the BSP rail 240. Alternatively or otherwise, the BSP trench 260 may be in direct contact with the first gate 210A and / or the second gate 210B.

[0031] The trench contact 270 may be formed on the BSP trench 260. On one hand, the trench contact 270 and the BSP trench 260 may be formed of the same material (e.g., any or more of Cu, Co, Mo, W, Ru, TiAl, TiN, etc.). In fact, on the other hand, the trench contact 270 and the BSP trench 260 may be integrally formed.

[0032] Figure 3B Example of the edge of unit 200 Figure 2 The cross-section of the X2-X2 dicing line is shown. As illustrated, cell 200 may include a back-side dielectric 335 along this cross-section. A first edge gate 210A, a second edge gate 210B, and an inner gate 220 may be on the back-side dielectric. A gate hard mask 355 may be on the first edge gate 210A, the second edge gate 210B, and the inner gate 220. One or more channel strips 250 may be formed over the back-side dielectric 335. In one aspect, the channel strip 250 may be a strip of a nanosheet wafer. At least one channel strip 250 may be formed such that any one or more of the first edge gate 210A, the second edge gate 210B, and / or the inner gate 220 at least partially surrounds the channel strip. That is, at least one channel strip 250 may be at least partially surrounded by the first edge gate 210A, the second edge gate 210B, and / or the inner gate 220.

[0033] For ease of reference, a portion of the channel strip 250 within the first edge gate 210A may be referred to as a first edge portion. Additionally, a channel that may be formed in the first edge portion may be referred to as a first channel. Similarly, a portion of the channel strip 250 within the second edge gate 210B may be referred to as a second edge portion, and a channel that may be formed in the second edge portion may be referred to as a second channel.

[0034] To recap, BSP rail 240 is configured to apply a turn-off voltage to the first edge gate 210A and the second edge gate 210B via BSP trench 260. Therefore, it can be said that the first edge portion of channel band 250 is configured to prevent the formation of a first channel in the first edge portion when a turn-off voltage is applied to the first edge gate 210A. Similarly, it can be said that the second edge portion of channel band 250 is configured to prevent the formation of a second channel in the second edge portion when a turn-off voltage is applied to the second edge gate 210B.

[0035] A source / drain (S / D) 345 may be formed in the channel band 250 between each of the first edge gate 210A and the second edge gate 210B and the inner gate 220. The S / D 345 may be epitaxial. For ease of reference, the S / D 345 between the first edge gate 210A and the inner gate 220 may be referred to as the first S / D 345, and the S / D 345 between the second edge gate 210B and the inner gate 220 may be referred to as the second S / D 345. Note that the channel band 250 may be electrically contacted with the first S / D and the second S / D 345.

[0036] Trench contacts 270 may be formed on the S / D 345. For ease of reference, the trench contact 270 on the first S / D 345 may be referred to as the first trench contact 270, and the trench contact 270 on the second S / D 345 may be referred to as the second trench contact 270. The first trench contact 270 may be electrically coupled to the first S / D 345. For example, the first trench contact 270 may be in direct contact with the first S / D 345. Alternatively or otherwise, the second trench contact 270 may be electrically coupled to the second S / D 345. For example, the second trench contact 270 may be in direct contact with the second S / D 345. A spacer 365 may be formed between the gate (e.g., the first edge gate 210A and the second edge gate 210B, the inner gate 220) and the trench contact 270. Additionally, an inner spacer 369 may be formed between the gate (e.g., the first edge gate 210A and the second edge gate 210B, the inner gate 220) and the S / D 345. An epitaxial block 371 may be formed between the first S / D and the second S / D 345 and the back-side dielectric 335.

[0037] On one hand, one of the first groove contact and the second groove contact 270 may be electrically coupled to the BSP rail 240, for example, through the BSP groove 260, while the other is not electrically coupled to the BSP rail 240. For example, the electrically coupled groove contact 270 may be in direct contact with the BSP groove 260.

[0038] As indicated above, when the first edge gate 210A and the second edge gate 210B are grounded by applying a turn-off voltage, the GTD (Getting Things Done) properties of cell 200 electrically isolate cell 200. This is true even if the channel strip 250 physically extends beyond the cell boundary. For example, the channel strip 250 may extend to the left beyond the first edge gate 210A (not shown) and / or may extend to the right beyond the second edge gate 210B (not shown). If the channel strip 250 extends to the left beyond the first edge gate 210A, it can be said that the first edge portion electrically isolates the first inner portion from the first outer portion, wherein the first inner portion is defined as a portion of the channel strip 250 on the side of the first edge portion within cell 200, and the first outer portion is defined as a portion of the channel strip 250 on the side of the first edge portion outside cell 200. If the channel band 250 extends to the right beyond the second edge gate 210B, it can be said that the second edge portion electrically isolates the second inner portion from the second outer portion, wherein the second inner portion is defined as a part of the channel band 250 on the side of the second edge portion within the cell 200, and the second outer portion is defined as a part of the channel band 250 on the side of the second edge portion outside the cell 200.

[0039] While the first edge gate 210A and the second edge gate 210B receive only a turn-off voltage (e.g., one of Vss and Vdd), the inner gate 220 may receive either a turn-off voltage or a turn-on voltage (e.g., the other of Vss and Vdd). For ease of reference, a portion of the channel band 250 within the inner gate 220 may be referred to as an inner portion. Additionally, a channel that may be formed in the inner portion may be referred to as an inner channel. When a turn-on voltage is applied to the inner gate 220, an inner channel is formed that can electrically couple the first S / D and the second S / D 345. Conversely, when a turn-off voltage is applied to the inner gate 220, the formation of the inner channel is prevented.

[0040] Figure 3C Example of the edge of unit 200 Figure 2 The cross-section of the Y1-Y1 cut line is shown. As can be seen, a BSP rail 240 and a back-side dielectric 335 may be provided. A BSP trench 260 and a trench contact 270 may be provided on the BSP rail 240, and an oxide 325 (e.g., used as an STI) may be provided on the BSP rail 240 and the back-side dielectric 335. A channel strip 250 may be formed within a gate 210 (e.g., a first gate 210A and / or a second gate 210B).

[0041] Edge gates 210 (e.g., first edge gate 210A, second edge gate 210B) may be formed on oxide 325 and on back-side dielectric 335. Channel bands 250 may be at least partially vertically aligned with a portion of the back-side dielectric 335 that contacts the gate 210. When translated to the first edge gate 210A, Figure 3C The channel band 250 shown may correspond to the first edge portion. Alternatively or otherwise, when translated to the second edge gate 210B, Figure 3C The channel strip 250 shown may correspond to the first edge portion.

[0042] It should be noted that the BSP trench 260 can directly contact both the BSP rail 240 and the edge gate 210. Figure 3C (and Figure 3A The example clearly illustrates gate grounding (GTD) using back-side power (e.g., BSP rail 240) via trench grounding (TDD). This differs from the conventional GTD cell 100, which illustrates a front-side power GTD scheme.

[0043] Figure 3D Example of the edge of unit 200 Figure 2 The cross-section of the Y2-Y2 cut line. As shown, a BSP rail 240 and a back-side dielectric 335 may be provided. A BSP trench 260 and a trench contact 270 may be on the BSP rail 240. An oxide 325 may be on the BSP rail 240 and the back-side dielectric 335. An interlayer dielectric (ILD) 327 may be on the oxide 325. An epitaxial block 371 and an S / D 345 may also be formed (in this order) above the back-side dielectric 335.

[0044] Figures 4A to 11B Examples of the various stages of manufacturing a GTD unit (such as GTD unit 200) are shown. Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A Examples are shown along Figure 2 The formation of the tangent X1-X1 cross section is related to each stage, and Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B Examples are shown along Figure 2The formation of the tangent X2-X2 cross section relates to various stages. From these examples, the processing steps for manufacturing cell 200 are determined to be relatively straightforward. For ease of reference, the X1-X1 cross section may also be referred to as the "first region" of the GTD cell, and the X2-X2 cross section may also be referred to as the "second region" of the GTD cell. Note that the first region and the second region may be parallel to each other.

[0045] Figure 4A and Figure 4B This illustrates a stage where a substrate 412 (e.g., a carrier) can be provided. Along the X1-X1 cross-section ( Figure 4A Oxide 325 can be provided on substrate 412. Along the X2-X2 cross section ( Figure 4B Alternating dummy layers 417 (e.g., SiGe layers) and channel bands 250 may be provided on substrate 412. In one aspect, substrate 412, dummy layers 417, and channel bands 250 may be part of a nanosheet wafer. In another aspect, Figure 4A and Figure 4B This can be illustrated after the defined diffusion region (OD).

[0046] Figure 5A and Figure 5B An example is shown on oxide 325 ( Figure 5A ) and (for example, on the channel band 250 of a nanosheet wafer) Figure 5B The stage of forming dummy gates (first dummy edge gate 510A, second dummy edge gate 510B, and internal dummy gate 520).

[0047] Figure 6A and Figure 6B An example is shown where spacers 365 can be formed on the side of a dummy gate (first dummy edge gate 510A, second dummy edge gate 510B, and inner dummy gate 520).

[0048] Figure 7A and Figure 7B An example is illustrated of the stages in which an S / D 345 can be formed along an X2-X2 cross section. For example, an S / D 345 can be formed between a first dummy edge gate 510A and an inner dummy gate 520, and another S / D 345 can be formed between a second dummy edge gate 510B and an inner dummy gate 520. For example, a groove can be formed in a nanosheet wafer between the first edge gate 210A and the second edge gate 210B and the inner gate 220. The groove can expose a substrate 412. An epitaxial block 371 can be formed on the exposed portion of the substrate 412. Then, an S / D 345 can be formed on the epitaxial block 371. Internal spacers 369 can also be formed on the sides of the S / D 345 and the epitaxial block 371. A channel band 250 can be electrically contacted with the S / D 345.

[0049] Figure 8A and Figure 8B The stage of releasing dummy gates (first dummy edge gate 510A, second dummy edge gate 510B, and inner dummy gate 520) is illustrated. At their locations, the gates of the cell (first edge gate 210A, second edge gate 210B, and inner gate 220) can be formed. Additionally, a gate hard mask 355 can be formed on the gates (first edge gate 210A, second edge gate 210B, and inner gate 220) along an X2-X2 cross-section. Furthermore, an ILD 327 can be deposited, for example, to package an S / D 345. For example, after depositing the ILD 327, the first dummy gate 510A, second dummy gate 510B, and inner dummy gate 520 can be released. Metal deposition can then be performed to form gates 210A, 210B, and 220, and then the gate hard mask 355 can be formed, for example, by forming a self-aligned contact (SAC).

[0050] Figure 9A and Figure 9B The stage of performing a gate dicing along the X1-X1 cross section to remove the internal gate 220 is illustrated. More ILD 327 backfill space is available.

[0051] Figure 10A and Figure 10B The stage of removing spacer 365 and ILD 327 along X1-X1 is illustrated. The space left by the removal can then be filled with a trench material (e.g., Cu, Co, Mo, W, Ru, TiAl, TiN, etc.) to form BSP trench 260, and trench contact 270 can be formed. The upper surfaces of gate hard mask 355, spacer 365, and trench contact 270 can be made coplanar, for example, by polishing.

[0052] Figure 11A and Figure 11B An example of a removable substrate 412 is shown. A back-side metallization process can then be performed to provide a BSP rail 240. A back-side dielectric 335 may also be provided.

[0053] Figure 12 A flowchart illustrating an example method 1200 for manufacturing a GTD cell (such as cell 200) according to one or more aspects of this disclosure is provided. In block 1210, a first edge gate 210A and a second edge gate 210B may be formed. The first edge gate 210A and the second edge gate 210B may extend in a first direction and may at least partially define the boundary of the GTD cell 200.

[0054] In block 1220, a channel band 250 may be formed extending in a second direction from the first edge gate 210A to the second edge gate 210B. The second direction may differ from the first direction. The channel band 250 may be formed at least partially within the first edge gate 210A and the second edge gate 210B. A first edge portion of the channel band 250 within the first edge gate 210A may be configured to prevent the formation of a first channel in that first edge portion when a turn-off voltage is applied to the first edge gate 210A. A second edge portion of the channel band 250 within the second edge gate 210B may be configured to prevent the formation of a second channel in that second edge portion when a turn-off voltage is applied to the second edge gate 210B.

[0055] In block 1230, a back-side power (BSP) rail 240 extending in a second direction may be formed. The BSP rail 240 may be formed below the first edge gate 210A and the second edge gate 210B and below the channel band 250.

[0056] In block 1240, a BSP trench 260 extending in a second direction may be formed. The BSP trench 260 may be formed on BSP rail 240. The BSP trench 260 may be conductive and electrically coupled to the BSP rail 240 and to the first edge gate 210A and the second edge gate 210B. The BSP rail 240 may be configured to apply a turn-off voltage to the first edge gate 210A and the second edge gate 210B through the BSP trench 260.

[0057] Figure 13 A flowchart of an example method 1300 for manufacturing a GTD unit (such as unit 200) according to one or more aspects of this disclosure. In one aspect, method 1300 can be considered as a more detailed version of method 1200 for manufacturing a GTD unit.

[0058] Block 1310 may be similar to block 1210. That is, a first edge gate 210A and a second edge gate 210B may be formed in block 1310. The first edge gate 210A and the second edge gate 210B may extend in a first direction and may at least partially define the boundary of the GTD cell 200.

[0059] Block 1320 may be similar to block 1220. That is, in block 1320, a channel band 250 extending from the first edge gate 210A to the second edge gate 210B in a second direction may be formed. The second direction may be different from the first direction. The channel band 250 may be formed at least partially within the first edge gate 210A and the second edge gate 210B. The first edge portion of the channel band 250 within the first edge gate 210A may be configured to prevent the formation of a first channel in the first edge portion when a turn-off voltage is applied to the first edge gate 210A. The second edge portion of the channel band 250 within the second edge gate 210B may be configured to prevent the formation of a second channel in the second edge portion when a turn-off voltage is applied to the second edge gate 210B.

[0060] Block 1330 may be similar to block 1230. That is, in block 1330, a back-side power (BSP) rail 240 extending in the second direction may be formed. The BSP rail 240 may be formed below the first edge gate 210A and the second edge gate 210B and below the channel band 250.

[0061] Block 1340 may be similar to block 1240. That is, a BSP trench 260 extending in the second direction may be formed in block 1340. The BSP trench 260 may be formed on the BSP rail 240. The BSP trench 260 may be conductive and electrically coupled to the BSP rail 240 and to the first edge gate 210A and the second edge gate 210B. The BSP rail 240 may be configured to apply a turn-off voltage to the first edge gate 210A and the second edge gate 210B through the BSP trench 260.

[0062] In block 1350, an inner gate 220 extending in a first direction may be formed. The inner gate may be between a first edge gate 210A and a second edge gate 210B. A channel band 250 may be at least partially within the inner gate 220. The inner portion of the channel band 250 within the inner gate 220 may be configured to form an internal channel in the inner portion when an on-state voltage is applied to the inner gate 220, and may be configured to prevent the formation of an internal channel in the inner portion when an off-state voltage is applied to the inner gate 220.

[0063] In block 1360, a first source / drain (S / D) 345 may be formed in channel band 250 between the first edge gate 210A and the inner gate 220. In block 1370, a second S / D 345 may be formed in channel band 250 between the second edge gate 210B and the inner gate 220. When an on-state voltage is applied to the inner gate 220, the inner channel may electrically couple the first S / D and the second S / D 345.

[0064] In block 1380, a first trench contact 270 electrically coupled to the first S / D 345 may be formed on the first S / D 345. In block 1390, a second trench contact 270 electrically coupled to the second S / D 345 may be formed on the second S / D 345.

[0065] Figure 14 Example specific embodiments of frames 1210-1240 and 1310-1340 are illustrated. In frame 1410, a substrate 412 may be provided. An oxide 325 may be formed or otherwise provided on the substrate 412 in a first region (e.g., an X1-X1 cross section) of the GTD unit 200. A channel strip 250 may be provided or formed on the substrate in a second region (e.g., an X2-X2 cross section) of the GTD unit 200. For example, a nanosheet wafer may be provided in the second region. In one aspect, frame 1410 may correspond to Figure 4A and Figure 4B The illustrated stages.

[0066] In block 1420, a first dummy edge gate 510A, a second dummy edge gate 510B, and an internal dummy gate 520 may be formed on oxide 325 and channel band 250. In one aspect, block 1420 may correspond to... Figure 5A and Figure 5B The illustrated stages.

[0067] In block 1430, spacers 365 may be formed on the sides of the first dummy edge gate 510A and the second dummy edge gate 510B, as well as on the sides of the inner dummy gate 520. In one aspect, block 1430 may correspond to... Figure 6A and Figure 6B The illustrated stages.

[0068] In block 1440, an S / D 345 may be formed in the channel band 250 in the second region between the first dummy edge gate 510A and the inner dummy gate 520, and between the second dummy edge gate 510B and the inner dummy gate 520. In one aspect, block 1440 may correspond to... Figure 7A and Figure 7B The illustrated stages.

[0069] In block 1450, the first dummy edge gate 510A, the second dummy edge gate 510B, and the internal dummy gate 520 can be released.

[0070] In block 1452, a first edge gate 210A, a second edge gate 210B, and an inner gate 220 may be formed to replace the released first dummy edge gate 510A, the released second dummy edge gate 510B, and the released inner dummy gate 520, respectively.

[0071] In block 1454, a gate hard mask 355 may be formed in the second region on the first edge gate 210A, the second edge gate 210B, and the inner gate 220. In one aspect, blocks 1450, 1452, and 1454 may correspond to... Figure 8A and Figure 8B The illustrated stages.

[0072] In block 1460, a gate dicing can be performed in a first region. The gate dicing removes the inner gate 220, spacer 365, and oxide 325 to expose the substrate 412 between the first edge gate 210A and the second edge gate 210B. In one aspect, block 1460 may correspond to... Figure 9A , Figure 9B , Figure 10A and Figure 10B The illustrated stages.

[0073] In frame 1470, trench material can be deposited to form BSP trench 260 and trench contact 270. The trench material (e.g., Cu, Co, Mo, W, Ru, TiAl, TiN, etc.) can be conductive. In one aspect, frame 1470 can correspond to... Figure 10A and Figure 10B The illustrated stages.

[0074] In block 1480, the BSP rail 240 can be provided by removing the substrate 412 and subsequently performing back-side metallization. In one aspect, block 1480 may correspond to... Figure 11A and Figure 11B The illustrated stages.

[0075] about Figures 12 to 14 The following should be noted regarding the indicated flow: Unless otherwise indicated, the flow of the boxes does not necessarily restrict the order in which they can be executed. Otherwise, the boxes may be executed in any logical order.

[0076] Figure 15 Various electronic devices 1500 that can be integrated with any of the aforementioned GAA devices according to various aspects of this disclosure are illustrated. For example, mobile phone device 1502, laptop computer device 1504 and fixed location terminal device 1506 may each generally be considered as user equipment (UE) and may include one or more units (e.g., unit 200) as described herein. Figure 15The illustrated devices 1502, 1504, and 1506 are merely exemplary. Other electronic devices may also include die packages, including but not limited to a group of devices (e.g., electronic devices) that include: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units (such as instrument reading devices), communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0077] The devices and functionalities disclosed above can be designed and configured in computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer-readable medium. Some or all of these files can be provided to a manufacturing process provider that manufactures the device based on such files. The resulting product may include semiconductor wafers, which are subsequently diced into semiconductor dies and packaged into glass antenna devices. These glass antenna devices can then be used in the devices described herein.

[0078] Specific implementation examples are described in the following numbered clauses:

[0079] Clause 1: A gate-grounded (GTD) cell comprising: a first edge gate and a second edge gate extending in a first direction, the first edge gate and the second edge gate defining a boundary of the GTD cell; a channel band extending from the first edge gate to the second edge gate in a second direction different from the first direction, the channel band being formed at least partially within the first edge gate and the second edge gate; a back-side power (BSP) rail extending in the second direction, the BSP rail being formed below the first edge gate and the second edge gate and below the channel band; and a BSP trench extending in the second direction, the BSP... SP trenches are formed on the BSP rails, the BSP trenches being conductive and electrically coupled to the BSP rails and to the first edge gate and the second edge gate, wherein a first edge portion of the channel band within the first edge gate is configured to prevent the formation of a first channel in the first edge portion when a turn-off voltage is applied to the first edge gate, wherein a second edge portion of the channel band within the second edge gate is configured to prevent the formation of a second channel in the second edge portion when the turn-off voltage is applied to the second edge gate, and wherein the BSP rails are configured to apply the turn-off voltage to the first edge gate and the second edge gate through the BSP trenches.

[0080] Clause 2: The GTD unit as described in Clause 1, wherein the first direction and the second direction are orthogonal to each other.

[0081] Clause 3: A GTD cell according to any one of Clauses 1 to 2, wherein the BSP trench is in direct contact with the BSP rail, the first edge gate, the second edge gate, or any combination thereof.

[0082] Clause 4: A GTD cell according to any one of Clauses 1 to 3, wherein the first edge gate at least partially surrounds the first edge portion, or wherein the second edge gate at least partially surrounds the second edge portion, or both.

[0083] Clause 5: A GTD unit according to any one of Clauses 1 to 4, wherein when the turn-off voltage is applied, the first edge portion electrically isolates the first inner portion from the first outer portion, or the second edge portion electrically isolates the second inner portion from the second outer portion, the first inner portion and the first outer portion being portions of the channel strip on the sides of the first edge portion respectively inside and outside the GTD unit, and the second inner portion and the second outer portion being portions of the channel strip on the sides of the second edge portion respectively inside and outside the GTD unit.

[0084] Clause 6: The GTD unit according to any one of Clauses 1 to 5 further includes: an internal gate extending in the first direction, the internal gate being between the first edge gate and the second edge gate, wherein the channel band is at least partially within the internal gate, and wherein an internal portion of the channel band within the internal gate is configured to form an internal channel in the internal portion when an on-state voltage is applied to the internal gate, and is configured to prevent the formation of the internal channel in the internal portion when the off-state voltage is applied to the internal gate.

[0085] Clause 7: The GTD cell as described in Clause 6, wherein the internal gate is not electrically coupled to the BSP rail.

[0086] Clause 8: The GTD cell according to any one of Clauses 6 to 7 further comprises: a first source / drain (S / D) formed over a back-side dielectric between the first edge gate and the inner gate, the channel band being electrically contacted with the first S / D; and a second S / D formed between the second edge gate and the inner gate, the channel band being electrically contacted with the second S / D, wherein when the on-state voltage is applied to the inner gate, the inner channel electrically couples the first S / D to the second S / D.

[0087] Clause 9: The GTD unit according to Clause 8 further includes: a first trench contact formed on and electrically coupled to the first S / D; and a second trench contact formed on and electrically coupled to the second S / D.

[0088] Clause 10: The GTD unit according to Clause 9, wherein one of the first trench contact and the second trench contact is electrically coupled to the BSP rail, and the other of the first trench contact and the second trench contact is not electrically coupled to the BSP rail.

[0089] Clause 11: The GTD unit according to Clause 10, wherein one of the first trench contact and the second trench contact is in direct contact with the BSP trench.

[0090] Clause 12: The GTD unit according to any one of Clauses 9 to 11, wherein the BSP trench, the first trench contact and the second trench contact are formed of the same material.

[0091] Clause 13: The GTD unit according to any one of Clauses 1 to 12, wherein the BSP trench is formed of any one or more of copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), ruthenium (Ru), titanium aluminide (TiAl), and titanium nitride (TiN).

[0092] Clause 14: A GTD cell according to any one of Clauses 1 to 13, wherein the cell is a fin field-effect transistor (FinFET) cell or a gate all around (GAA) cell.

[0093] Clause 15: A GTD unit according to any one of Clauses 1 to 14, wherein the GTD unit is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, Internet of Things (IoT) devices, laptop computers, servers, and devices in motor vehicles.

[0094] Clause 16: A method of manufacturing a gate-grounded (GTD) cell, the method comprising: forming a first edge gate and a second edge gate extending in a first direction, the first edge gate and the second edge gate defining a boundary of the GTD cell; forming a channel band extending from the first edge gate to the second edge gate in a second direction different from the first direction, the channel band being formed at least partially within the first edge gate and the second edge gate; forming a back-side power (BSP) rail extending in the second direction, the BSP rail being formed below the first edge gate and the second edge gate and below the channel band; and forming a BSP trench extending in the second direction. The BSP trench is formed on the BSP rail, the BSP trench is conductive and electrically coupled to the BSP rail and to the first edge gate and the second edge gate, wherein a first edge portion of the channel band within the first edge gate is configured to prevent the formation of a first channel in the first edge portion when a turn-off voltage is applied to the first edge gate, wherein a second edge portion of the channel band within the second edge gate is configured to prevent the formation of a second channel in the second edge portion when the turn-off voltage is applied to the second edge gate, and wherein the BSP rail is configured to apply the turn-off voltage to the first edge gate and the second edge gate through the BSP trench.

[0095] Clause 17: The method described in Clause 16, wherein the first direction and the second direction are orthogonal to each other.

[0096] Clause 18: The method according to any one of Clauses 16 to 17, wherein the BSP trench is in direct contact with the BSP rail, the first edge gate, the second edge gate, or any combination thereof.

[0097] Clause 19: The method according to any one of Clauses 16 to 18, wherein the first edge gate at least partially surrounds the first edge portion, or wherein the second edge gate at least partially surrounds the second edge portion, or both.

[0098] Clause 20: The method according to any one of Clauses 16 to 19, wherein when the turn-off voltage is applied, the first edge portion electrically isolates the first inner portion from the first outer portion, or the second edge portion electrically isolates the second inner portion from the second outer portion, the first inner portion and the first outer portion being portions of the channel strip on the sides of the first edge portion respectively inside and outside the GTD unit, and the second inner portion and the second outer portion being portions of the channel strip on the sides of the second edge portion respectively inside and outside the GTD unit.

[0099] Clause 21: The method according to any one of Clauses 16 to 20, the method further comprising: forming an internal gate extending in the first direction, the internal gate being between the first edge gate and the second edge gate, wherein the channel band is at least partially within the internal gate, and wherein an internal portion of the channel band within the internal gate is configured to form an internal channel in the internal portion when an on-state voltage is applied to the internal gate, and is configured to prevent the formation of the internal channel in the internal portion when the off-state voltage is applied to the internal gate.

[0100] Clause 22: The method according to Clause 21, wherein the internal gate is not electrically coupled to the BSP rail.

[0101] Clause 23: The method according to any one of Clauses 21 to 22, the method further comprising: forming a first source / drain (S / D) over a back-side dielectric between a first edge gate and an inner gate, the channel strip being electrically contacted with the first S / D; and forming a second S / D between a second edge gate and an inner gate, the channel strip being electrically contacted with the second S / D, wherein when the on-state voltage is applied to the inner gate, the inner channel electrically couples the first S / D to the second S / D.

[0102] Clause 24: The method according to Clause 23 further comprises: forming a first trench contact electrically coupled to the first S / D on the first S / D; and forming a second trench contact electrically coupled to the second S / D on the second S / D.

[0103] Clause 25: The method according to Clause 24, wherein one of the first groove contact and the second groove contact is electrically coupled to the BSP rail, and the other of the first groove contact and the second groove contact is not electrically coupled to the BSP rail.

[0104] Clause 26: The method according to Clause 25, wherein one of the first groove contact and the second groove contact is in direct contact with the BSP groove.

[0105] Clause 27: The method according to any one of Clauses 24 to 26, wherein the BSP trench, the first trench contact and the second trench contact are formed of the same material.

[0106] Clause 28: The method according to any one of Clauses 16 to 27, wherein the BSP trench is formed from any one or more of copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), ruthenium (Ru), titanium aluminide (TiAl), and titanium nitride (TiN).

[0107] Clause 29: The method according to any one of Clauses 16 to 28, wherein the cell is a fin field-effect transistor (FinFET) cell or a gate all around (GAA) cell.

[0108] Clause 30: The method according to any one of Clauses 16 to 29, wherein forming the first edge gate and the second edge gate, forming the channel strip, forming the back-side power (BSP) rail, and forming the BSP trench comprises: providing a substrate, providing an oxide on the substrate in a first region of the GTD cell, and providing the channel strip on the substrate in a second region of the GTD cell; forming a first dummy edge gate, a second dummy edge gate, and an inner dummy gate on the oxide and the channel strip; forming spacers on the sidewalls of the first dummy edge gate and the second dummy edge gate and on the sidewalls of the inner dummy gate; forming a source / drain (S / D) in the second region between the first dummy edge gate and the inner dummy gate and between the second dummy edge gate and the inner dummy gate, wherein the trench The track makes electrical contact with the first S / D and the second S / D; releases the first dummy edge gate and the second dummy edge gate and the inner dummy gate; forms the first edge gate and the second edge gate and the inner gate to replace the released first dummy edge gate and the released second dummy edge gate and the released inner dummy gate, respectively; forms a gate hard mask on the first edge gate and the second edge gate and the inner gate in the second region; performs a gate dicing in the first region, the gate dicing removing the inner gate, the spacer and the oxide to expose the substrate between the first edge gate and the second edge gate; deposits trench material to form the BSP trench and the trench contact, the trench material being conductive; and provides the BSP track by removing the substrate and subsequently performing back-side metallization.

[0109] As used herein, the terms “user equipment” (or “UE”), “user device,” “user terminal,” “client device,” “communication device,” “wireless device,” “wireless communication device,” “handheld device,” “mobile device,” “mobile terminal,” “mobile station,” “phone,” “access terminal,” “subscriber device,” “subscriber terminal,” “subscriber station,” “terminal,” and variations thereof may interchangeably refer to any suitable mobile or stationary device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, onboard equipment in motor vehicles, and / or other types of portable electronic devices that are typically carried by an individual and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device capable of receiving wireless communication and / or navigation signals (such as via short-range wireless, infrared, wired, or other connections), regardless of whether satellite signal reception, auxiliary data reception, and / or positioning-related processing occur at that device or at that other device. Furthermore, these terms are intended to encompass all devices, including wireless and wired communication devices capable of communicating with the core network via a radio access network (RAN), through which the UE can connect to external networks such as the Internet and other UEs. Of course, other mechanisms for connecting to the core network and / or the Internet are also possible for the UE, such as via a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.). The UE can be implemented using any of several types of devices, including but not limited to printed circuit (PC) cards, compact flash memory devices, external or internal modems, wireless or wired telephones, smartphones, tablet devices, tracking devices, asset tags, etc. The communication link through which the UE can transmit signals to the RAN is called an uplink channel (e.g., reverse traffic channel, reverse control channel, access channel, etc.). The communication link through which the RAN can transmit signals to the UE is called a downlink or forward link channel (e.g., paging channel, control channel, broadcast channel, forward traffic channel, etc.). As used herein, the term “Traffic Channel (TCH)” can refer to either the uplink / reverse traffic channel or the downlink / forward traffic channel.

[0110] Wireless communication between electronic devices can be based on different technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, and Bluetooth.® (BT), Bluetooth ® Low Energy (BLE), IEEE 802.11 (Wi-Fi) ® Bluetooth is compatible with IEEE 802.15.4 (Zigbee / Thread) and other protocols that can be used in wireless or data communication networks. ® Low power (also known as Bluetooth) ® LE, BLE and Bluetooth ® (Smart) is made of Bluetooth ® Bluetooth is a wireless personal area network (BLAN) technology designed and marketed by the Bluetooth Technology Alliance, aiming to provide significantly reduced power consumption and cost while maintaining similar communication range. BLE was merged into the main Bluetooth network in 2010. ® The standard uses Bluetooth. ® Core specification version 4.0 and in Bluetooth ® Updated in version 5.

[0111] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" is not to be construed as superior to other examples. Similarly, the term "example" does not imply that all examples include the features, advantages, or modes of operation discussed. Furthermore, specific features and / or structures may be combined with one or more other features and / or structures. Additionally, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0112] It should be noted that the terms “connection,” “coupling,” or any variation thereof mean any direct or indirect connection or coupling between elements, and may cover the presence of an intermediate element between two elements through which the two elements are “connected” or “coupled” together, unless the connection is explicitly disclosed as a direct connection.

[0113] The use of designations such as "first," "second," etc., to refer to elements in this document does not limit the number and / or order of those elements. Rather, these designations are used as a convenient way to distinguish two or more elements and / or instances of elements. Moreover, unless otherwise stated, a collection of elements may include one or more elements.

[0114] Those skilled in the art will recognize that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0115] Nothing described or illustrated in this application is intended to bring any component, action, feature, benefit, advantage, or equivalent to the public, whether or not such component, action, feature, benefit, advantage, or equivalent is stated in the claims.

[0116] In the detailed description above, it can be seen that different features are grouped together in the various examples. This manner of disclosure should not be construed as reflecting an intention that the claimed examples have more features than those explicitly mentioned in the corresponding claims. Rather, this disclosure may include all features of fewer than the individual examples disclosed. Therefore, the appended claims should be considered as incorporated into this description, wherein each claim may be a separate example in itself. Although each claim may be a separate example in itself, it should be noted that while dependent claims in the claims may refer to a specific combination with one or more claims, other examples may also cover or include combinations of the subject matter of said dependent claim with any other dependent claim or any feature with other dependent and independent claims. Such combinations are presented herein unless explicitly stated that a particular combination is not intended to be used. Furthermore, it is intended that features of a claim may be included in any other independent claim, even if said claim is not directly dependent on that independent claim.

[0117] Furthermore, it should be noted that the methods, systems, and apparatuses disclosed in this description or claims may be implemented by devices including components for performing corresponding actions and / or functions of the disclosed methods.

[0118] Furthermore, in some examples, a single action can be subdivided into one or more sub-actions, or contain one or more sub-actions. Such sub-actions can be included in the disclosure of a single action or can be part of the disclosure of a single action.

[0119] Although the foregoing disclosure has shown illustrative examples of this disclosure, it should be noted that various changes and modifications may be made without departing from the scope of this disclosure as defined by the appended claims. The functions and / or actions in the method claims of the examples of this disclosure described herein do not necessarily have to be performed in any particular order. Furthermore, well-known elements will not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. Moreover, although elements of this disclosure may be described or claimed in the singular, the plural form may also be considered unless expressly stated as limited to the singular.

Claims

1. A gate-grounded (GTD) unit, the gate-grounded (GTD) unit comprising: A first edge gate and a second edge gate extending in a first direction, the first edge gate and the second edge gate defining the boundary of the GTD cell; A channel band extending from the first edge gate to the second edge gate in a second direction different from the first direction, the channel band being formed at least partially within the first edge gate and the second edge gate; A back-side power (BSP) rail extending in the second direction, the BSP rail being formed below the first edge gate and the second edge gate and below the channel band; and A BSP trench extending in the second direction, the BSP trench being formed on the BSP rail, the BSP trench being conductive and electrically coupled to the BSP rail and to the first edge gate and the second edge gate. The first edge portion of the channel band within the first edge gate is configured to prevent the formation of a first channel in the first edge portion when a turn-off voltage is applied to the first edge gate. The second edge portion of the channel band within the second edge gate is configured to prevent the formation of a second channel in the second edge portion when the turn-off voltage is applied to the second edge gate. The BSP rail is configured to apply the turn-off voltage to the first edge gate and the second edge gate through the BSP trench.

2. The GTD unit according to claim 1, wherein the first direction and the second direction are orthogonal to each other.

3. The GTD cell of claim 1, wherein the BSP trench is in direct contact with the BSP rail, the first edge gate, the second edge gate, or any combination thereof.

4. The GTD unit according to claim 1, Wherein the first edge gate at least partially surrounds the first edge portion, or Wherein the second edge gate at least partially surrounds the second edge portion, or Both.

5. The GTD unit of claim 1, wherein when the turn-off voltage is applied, the first edge portion electrically isolates the first internal portion from the first external portion, or the second edge portion electrically isolates the second internal portion from the second external portion. The first inner portion and the first outer portion are the portions of the channel strip on the sides of the first edge portion, respectively, inside and outside the GTD unit. The second inner portion and the second outer portion are portions of the channel strip on the sides of the second edge portion, respectively, inside and outside the GTD unit.

6. The GTD unit according to claim 1, wherein the GTD unit further comprises: An internal gate extending in the first direction, the internal gate being located between the first edge gate and the second edge gate. The channel band is at least partially within the inner gate, and The inner portion of the channel band within the inner gate is configured to form an internal channel in the inner portion when an on-state voltage is applied to the inner gate, and is configured to prevent the formation of the internal channel in the inner portion when the off-state voltage is applied to the inner gate.

7. The GTD cell of claim 6, wherein the internal gate is not electrically coupled to the BSP rail.

8. The GTD unit according to claim 6, wherein the GTD unit further comprises: A first source / drain (S / D) is formed above the back-side dielectric between the first edge gate and the inner gate, and the channel band is electrically contacted with the first S / D. and A second S / D is formed between the second edge gate and the inner gate, and the channel band is electrically contacted with the second S / D. When the on-state voltage is applied to the internal gate, the internal channel electrically couples the first S / D to the second S / D.

9. The GTD unit according to claim 8, further comprising: A first grooved contact is formed on and electrically coupled to the first S / D; and A second grooved contact is formed on and electrically coupled to the second S / D.

10. The GTD unit of claim 9, wherein one of the first groove contact and the second groove contact is electrically coupled to the BSP rail, and the other of the first groove contact and the second groove contact is not electrically coupled to the BSP rail.

11. The GTD unit of claim 10, wherein one of the first groove contact and the second groove contact is in direct contact with the BSP groove.

12. The GTD unit of claim 9, wherein the BSP trench, the first trench contact, and the second trench contact are formed of the same material.

13. The GTD unit according to claim 1, wherein the BSP trench is formed from any or more of copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), ruthenium (Ru), titanium aluminide (TiAl), and titanium nitride (TiN).

14. The GTD cell of claim 1, wherein the cell is a fin field-effect transistor (FinFET) cell or a gate all around (GAA) cell.

15. The GTD unit of claim 1, wherein the GTD unit is incorporated into an apparatus selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, Internet of Things (IoT) devices, laptop computers, servers, and devices in motor vehicles.

16. A method of manufacturing a gate-grounded (GTD) cell, the method comprising: A first edge gate and a second edge gate extending in a first direction are formed, the first edge gate and the second edge gate defining the boundary of the GTD cell; A channel band is formed in a second direction different from the first direction, extending from the first edge gate to the second edge gate, the channel band being formed at least partially within the first edge gate and the second edge gate; A back-side power (BSP) rail extending in the second direction is formed below the first edge gate and the second edge gate and below the channel band; as well as A BSP trench extending in the second direction is formed on the BSP rail. The BSP trench is conductive and electrically coupled to the BSP rail and to the first edge gate and the second edge gate. The first edge portion of the channel band within the first edge gate is configured to prevent the formation of a first channel in the first edge portion when a turn-off voltage is applied to the first edge gate. The second edge portion of the channel band within the second edge gate is configured to prevent the formation of a second channel in the second edge portion when the turn-off voltage is applied to the second edge gate. The BSP rail is configured to apply the turn-off voltage to the first edge gate and the second edge gate through the BSP trench.

17. The method of claim 16, wherein the first direction and the second direction are orthogonal to each other.

18. The method of claim 16, wherein the BSP trench is in direct contact with the BSP rail, the first edge gate, the second edge gate, or any combination thereof.

19. The method according to claim 16, Wherein the first edge gate at least partially surrounds the first edge portion, or Wherein the second edge gate at least partially surrounds the second edge portion, or Both.

20. The method of claim 16, wherein when the turn-off voltage is applied, the first edge portion electrically isolates the first inner portion from the first outer portion, or the second edge portion electrically isolates the second inner portion from the second outer portion. The first inner portion and the first outer portion are the portions of the channel strip on the sides of the first edge portion, respectively, inside and outside the GTD unit. The second inner portion and the second outer portion are portions of the channel strip on the sides of the second edge portion, respectively, inside and outside the GTD unit.

21. The method according to claim 16, further comprising: An internal gate is formed extending in the first direction, the internal gate being located between the first edge gate and the second edge gate. The channel band is at least partially within the inner gate, and The inner portion of the channel band within the inner gate is configured to form an internal channel in the inner portion when an on-state voltage is applied to the inner gate, and is configured to prevent the formation of the internal channel in the inner portion when the off-state voltage is applied to the inner gate.

22. The method of claim 21, wherein the internal gate is not electrically coupled to the BSP rail.

23. The method of claim 21, further comprising: A first source / drain (S / D) is formed above the back-side dielectric between the first edge gate and the inner gate, and the channel band is electrically contacted with the first S / D. as well as A second S / D is formed between the second edge gate and the inner gate, and the channel band is electrically contacted with the second S / D. When the on-state voltage is applied to the internal gate, the internal channel electrically couples the first S / D to the second S / D. When the on-state voltage is applied to the internal gate, the internal channel electrically couples the first S / D to the second S / D.

24. The method of claim 23, further comprising: A first groove contact element electrically coupled to the first S / D is formed on the first S / D; as well as A second groove contact is formed on the second S / D that is electrically coupled to the second S / D.

25. The method of claim 24, wherein one of the first grooved contact and the second grooved contact is electrically coupled to the BSP rail, and the other of the first grooved contact and the second grooved contact is not electrically coupled to the BSP rail.

26. The method of claim 25, wherein one of the first groove contact and the second groove contact is in direct contact with the BSP groove.

27. The method of claim 24, wherein the BSP trench, the first trench contact, and the second trench contact are formed of the same material.

28. The method of claim 16, wherein the BSP trench is formed from any or more of copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), ruthenium (Ru), titanium aluminide (TiAl), and titanium nitride (TiN).

29. The method of claim 16, wherein the unit is a fin field-effect transistor (FinFET) unit or a gate all around (GAA) unit.

30. The method of claim 16, wherein forming the first edge gate and the second edge gate, forming the channel strip, forming the back-side power (BSP) rail, and forming the BSP trench comprises: A substrate is provided, on which an oxide is provided in a first region of the GTD cell, and on which the channel band is provided in a second region of the GTD cell; A first dummy edge gate, a second dummy edge gate, and an internal dummy gate are formed on the oxide and on the channel band; Spacers are formed on the sides of the first dummy edge gate and the second dummy edge gate, as well as on the sides of the inner dummy gate; A source / drain (S / D) is formed in the second region between the first dummy edge gate and the inner dummy gate, and between the second dummy edge gate and the inner dummy gate, and the channel band is electrically contacted with the first S / D and the second S / D; Release the first dummy edge gate, the second dummy edge gate, and the internal dummy gate; The first edge gate, the second edge gate, and the inner gate are formed to replace the released first dummy edge gate, the released second dummy edge gate, and the released inner dummy gate, respectively; A gate hard mask is formed in the second region on the first edge gate, the second edge gate, and the inner gate; A gate dicing is performed in the first region to remove the inner gate, the spacer, and the oxide to expose the substrate between the first edge gate and the second edge gate; Depositing trench material to form the BSP trench and the trench contact, wherein the trench material is conductive; as well as The BSP rail is provided by removing the substrate and subsequently performing back-side metallization.

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