Gate grounding using trench grounding scheme in backside power architecture
By using the trench grounding (TDD) method in the back-side power architecture, the scaling difficulties in conventional GTD schemes are solved, achieving greater area scaling and performance gains, and making it suitable for gate grounding designs in integrated circuits.
CN121866867APending Publication Date: 2026-04-14QUALCOMM INC
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Patent Information
- Application Number
- CN202480057352.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-18
- Filing Date
- 2024-08-22
- Publication Date
- 2026-04-14
AI Technical Summary
Technical Problem
Conventional gate-grounded (GTD) schemes require wider power rails and larger/taller logic cells in integrated circuits, making miniaturization difficult and hindering the achievement of ultra-low height standard cells and high area miniaturization.
Method used
The trench grounding (TDD) method is used to achieve gate grounding by forming conductive back-side power (BSP) rails and trenches in the back-side power architecture. The BSP trenches are used to apply the turn-off voltage to the edge gate, preventing channel formation and achieving electrical isolation.
Benefits of technology
It achieves greater area reduction and performance gain, reduces parameter variations, avoids the need for physical diffusion interruptions, and supports smaller cell designs.
✦ Generated by Eureka AI based on patent content.
Abstract
A gate ground (GTD) cell utilizing a backside power delivery scheme is disclosed in which metal lines that deliver power are disposed on the backside of a wafer. Thus, an ultra-low height standard cell may be implemented. And relatively high area miniaturization can be realized. In addition, performance and power gain may be maximized.
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