Dynamic power management and dynamic voltage and frequency regulation method for AI intelligent calculation system power consumption

Abstract

The invention relates to an AI intelligent calculation system power consumption dynamic power management and dynamic voltage and frequency regulation method, and belongs to the technical field of artificial intelligence. According to the AI intelligent computing system, an intelligent hybrid heterogeneous computing architecture of CPU + NPU + FPGA is adopted, computing power improvement of the low-power-consumption miniaturized intelligent computing system can be achieved, and the requirement for high computing power of an AI data processing function is met. The real-time state of the system is judged through a software algorithm, dynamic voltage and frequency regulation is performed on the CPU while dynamic power management of the intelligent computing system is realized, the problems of poor endurance and high energy consumption of an embedded unmanned intelligent platform in a severe environment can be solved, longer endurance of unmanned intelligent equipment in the severe environment can be ensured, and the service life of the unmanned intelligent equipment is prolonged. And the unmanned equipment is enabled to avoid infrared tracking.

Description

Technical Field

[0001] This invention belongs to the field of artificial intelligence technology, specifically relating to a method for dynamic power management and dynamic voltage and frequency regulation of an AI intelligent computing system. Background Technology

[0002] With the development of artificial intelligence technology, and given the urgent need for powerful intelligent computing capabilities and diverse application scenarios of unmanned aerial vehicles (UAVs), power consumption has increasingly become a hot topic of concern, rising to a level of importance equal to performance and cost. The unique characteristics of artificial intelligence pose new challenges to embedded technology. Deep neural networks have high demands on computing power and resources, inevitably leading to increased system power consumption. UAVs typically rely on batteries for operation in harsh environments; therefore, research into low-power control technologies is needed to extend their operating time and meet the intelligent computing application scenarios of UAVs.

[0003] Embedded CPUs are currently offered by several domestic manufacturers, including the Loongson 2K series, Phytium E-series, Rockchip RK series, and Ingenic M-series. After considering factors such as computing power-to-power ratio and environmental adaptability, Rockchip and Ingenic's consumer-grade products were excluded. The Phytium E-series, based on the ARM architecture, has a relatively rich open-source software ecosystem, facilitating the deployment of intelligent development frameworks and the portability of other software. The Phytium E2000Q supports 64-bit / 32-bit instructions, is compatible with the ARM V8 virtualization system, and supports KVM and Xen virtual machines; it supports single-precision and double-precision floating-point operations; it integrates two FTC664 cores with a frequency of 1.8GHz and two FTC310 cores with a frequency of 1.5GHz; it is configured with a 6-lane PCIe 3.0 interface, 2 CAN interfaces, 1 SPI interface, and 1 DP 1.4 interface, as well as an external debugging interface; it integrates a 72-bit DDR4 controller; the Phytium E2000Q is chosen not only for its strong versatility but also for its low power consumption.

[0004] In the domestic intelligent computing field, computing architectures can be categorized into various heterogeneous accelerated computing methods, such as CPU+GPU, CPU+NPU, and CPU+FPGA. Each accelerated computing method has its own applicable scope. To maximize the utilization of the computing resources of embedded intelligent computing systems, improve resource utilization efficiency, and enhance the performance and reliability of intelligent computing, it is necessary to consider combining various heterogeneous computing methods, focusing on solving the problem of integrating multiple heterogeneous computing devices into intelligent computing.

[0005] Problems with existing technologies include: 1. Existing methods, by selecting only low-power devices, do not significantly reduce power consumption; 2. The embedded intelligent platform has poor battery life in harsh environments, and the overall power consumption of the device is too high. It cannot save energy, and the high power consumption results in poor ability to avoid infrared detection. 3. The imbalance between computing performance and energy consumption of embedded artificial intelligence in unmanned aerial vehicle (UAV) mobile platforms results in low energy efficiency and weak versatility of individual embedded heterogeneous intelligent computing modules. Summary of the Invention

[0006] (a) Technical problems to be solved The technical problem to be solved by this invention is to provide a method for dynamically adjusting the voltage and frequency of the system CPU by implementing dynamic power management of the AI ​​intelligent computing system, so as to solve the problems of poor battery life and high energy consumption of embedded unmanned intelligent platforms in harsh environments.

[0007] (II) Technical Solution To address the aforementioned technical problems, this invention provides a method for dynamic power management and dynamic voltage and frequency regulation in an AI intelligent computing system, which is implemented through the following design: The hardware circuit of the AI ​​intelligent computing system is designed based on Phytium Tenlong E2000Q. The hardware circuit includes NPU, FPGA, BMC, PCIe expansion bridge, isolated power supply module, memory, and firmware BIOS. The AI ​​intelligent computing system is powered by an external aviation plug interface. The power supply is converted into the working power of the AI ​​intelligent computing system through an isolated power module, and then the working power is converted into the working power of the onboard chips; the onboard chips include NPU and FPGA. The CPU of the AI ​​intelligent computing system, Phytium Tenlong E2000Q, is connected to the FPGA via the PCIe bus. The out-of-band part of the FPGA controls the power-on, reset, and clock enable of the AI ​​intelligent computing system, as well as the power control and clock enable of the NPU. The CPU is connected to two AI intelligent modules in the AI ​​intelligent computing system through the PCIe expansion bridge. The power supply and clock of the AI ​​intelligent modules are designed separately, and the power supply, clock and reset of the AI ​​intelligent modules are controlled by the FPGA. The BMC monitors the health information of the AI ​​intelligent computing system, collecting real-time data on the system's operating voltages, temperatures, and input current, and calculating the total power consumption. The BMC and CPU communicate via serial port, transmitting the data collected by the BMC to the CPU in real time. This data serves as the basis for the CPU's dynamic voltage adjustment.

[0008] (III) Beneficial Effects The AI ​​intelligent computing system in this invention adopts an intelligent hybrid heterogeneous computing architecture of "CPU+NPU+FPGA", which can improve the computing power of a low-power miniaturized intelligent computing system and meet the high computing power requirements of AI data processing functions. This invention uses software algorithms to determine the real-time status of the system, achieving dynamic power management of the intelligent computing system while dynamically adjusting the voltage and frequency of the CPU. This solves the problems of poor battery life and high energy consumption of embedded unmanned intelligent platforms in harsh environments, ensuring longer battery life for unmanned intelligent devices under harsh conditions and enabling them to evade infrared tracking. Attached Figure Description

[0009] Figure 1 This is a design block diagram of the CPU motherboard solution designed in this invention; Figure 2 This is a block diagram of the power supply scheme designed in this invention; Figure 3 This is a flowchart of the dynamic power management and dynamic voltage and frequency regulation method of the present invention. Detailed Implementation

[0010] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0011] This invention provides a method for dynamic power management based on an AI intelligent computing system, thereby enabling dynamic voltage and frequency regulation of the system CPU. The AI ​​intelligent computing system in this invention adopts an intelligent hybrid heterogeneous computing architecture of "CPU+NPU+FPGA," which can improve the computing power of a low-power, miniaturized intelligent computing system and meet the high computing power requirements of AI data processing functions. Effectively utilizing the computing power of this hybrid heterogeneous computing architecture is a challenge, requiring the operating system to allocate and schedule hybrid heterogeneous computing resources during runtime through a hybrid heterogeneous computing resource scheduling framework.

[0012] By using software algorithms to determine the real-time status of the system, this invention enables dynamic power management of the intelligent computing system while simultaneously dynamically adjusting the CPU's voltage and frequency. While existing low-power power management technologies have been researched, their application is still immature. This invention, by implementing dynamic CPU voltage and frequency adjustment, can minimize the overall system power consumption, thus addressing the problems of poor battery life and high energy consumption in embedded unmanned intelligent platforms operating in harsh environments.

[0013] Low-power control technology is particularly important when unmanned intelligent devices operate in harsh environments. It is essential to ensure both the smooth execution of tasks and sufficient power supply. By using dynamic power management technology and dynamic voltage and frequency regulation of the CPU to minimize system power consumption, unmanned intelligent devices can be guaranteed to have a longer battery life in harsh environments. At the same time, reducing power consumption can help unmanned devices avoid infrared tracking.

[0014] Simply using low-power components to reduce the overall power consumption of an unmanned intelligent device platform is ineffective and offers limited savings. However, by combining hardware design with software algorithms to dynamically manage the system's power supply, power consumption can be effectively adjusted. As the computing power demands of unmanned intelligent platforms increase, system power consumption also rises significantly. Dynamic power management can dynamically control the shutdown of idle AI modules, reducing unnecessary power loss while preserving essential system functions. Furthermore, dynamic voltage and frequency regulation of the CPU, based on dynamic power management technology, can also reduce CPU power consumption. Combining these two techniques to maximally reduce overall system power consumption can effectively address issues such as low system efficiency due to the imbalance between energy consumption and performance when unmanned intelligent devices perform tasks in harsh environments, as well as the low energy efficiency and limited versatility of systems using only a single embedded heterogeneous intelligent computing module.

[0015] To address the aforementioned technical problems, this invention provides a method for implementing dynamic power management and dynamic voltage and frequency regulation based on an AI intelligent computing system, comprising the following steps: 1) Design the hardware circuit of the AI ​​intelligent computing system based on Phytium E2000Q, including NPU, FPGA, BMC, PCIe expansion bridge, isolated power supply module, LPDDR4 memory chip, mSATA hard drive, firmware BIOS; 2) The AI ​​intelligent computing system is powered by an external aviation plug interface. The power supply is converted into the working power of the AI ​​intelligent computing system through an isolated power module, and then converted into the working power of the onboard chips through a DC-DC converter. The onboard chips include NPU and FPGA. 3) The CPU of the AI ​​intelligent computing system is connected to the FPGA (Field Programmable Gate Array) via the PCIe bus. The out-of-band part of the FPGA (IOB control unit) controls the power-on, reset, clock enable of the AI ​​intelligent computing system, and the power control, clock enable, and module reset of the NPU. The CPU is connected to two AI intelligent modules in the AI ​​intelligent computing system via the PCIe expansion bridge. The power supply and clock of each AI intelligent module are designed independently. The FPGA controls the power supply, clock, and reset of the AI ​​intelligent modules. Through the working status monitoring unit of the AI ​​intelligent modules, when the AI ​​intelligent computing system is in low-power mode, a scheduling algorithm can be used to shut down one of the AI ​​intelligent modules, which can minimize the system power consumption. (The working status monitoring unit of the AI ​​intelligent modules monitors whether the AI ​​intelligent modules are currently in working state. Combined with the software algorithm, it determines whether the AI ​​intelligent computing system has entered low-power mode. According to the predetermined dynamic power adjustment strategy, one of the AI ​​intelligent modules is shut down, which can minimize the system power consumption.)

[0016] 4) The BMC monitors the health information of the AI ​​intelligent computing system, collects the operating voltage and temperature of the AI ​​intelligent computing system and the system input current in real time, and calculates the overall power consumption of the system; the BMC and the CPU transmit data through a serial port, and transmit the data collected by the BMC to the CPU in real time. The data collected by the BMC is used as the basis for the CPU to dynamically adjust the voltage. 5) The CPU and CPU core power controller are connected via the IIC bus, which can dynamically adjust and control the output of the CPU core power supply; it supports dynamic voltage and frequency adjustment of the CPU. The system can determine whether the system is in an idle state based on task requirements and reduce the CPU frequency and core voltage, thereby reducing CPU power consumption. In step 1), the hardware circuit of the processing board based on Phytium Tenglong E2000Q is designed, and all domestic low-power components are selected.

[0017] In step 2), the system uses a 24V power supply via an aviation plug interface, which is converted into a 12V system operating power supply through an isolation power module, and then converted into the operating power supply of each onboard chip through a DC-DC converter.

[0018] In step 3), the system uses the out-of-band portion of the FPGA to control the power supply, clock, and reset of each branch circuit to ensure normal system operation. When the system does not need to process a large amount of AI data, it will automatically enter a low-power mode. The FPGA receives the interrupt signal from the system, calls the algorithm control strategy, and disconnects the power supply and clock of a designated AI module, ensuring that another AI module can still operate normally. This achieves dynamic power management of the AI ​​modules and minimizes system power consumption.

[0019] In step 4), the BMC collects the system's input voltage and current in real time and calculates the current total system power consumption, determining that the current power consumption is lower than the total power consumption threshold during normal system startup. The CPU determines that the system has entered low-power mode based on the power consumption comparison result. In low-power mode, the system still maintains its intelligent computing capabilities; when the system receives simple tasks, individual AI modules continue to operate normally. If the system is not processing any data, its power consumption remains at its lowest level. If the BMC collects a current power consumption value that is consistently lower than the minimum power consumption preset value, it determines that the system is not executing any tasks and is in an idle state.

[0020] In step 5), the CPU core power supply circuit is implemented using a DrMOS chip driven by a digital power control system. The register values ​​of the CPU core power controller can be adjusted via the IIC interface to achieve controllable CPU core power supply. When the system enters low-power mode and the collected system power consumption value is consistently lower than the preset power consumption value, the system is determined to be in an idle state. An automatic adjustment algorithm is invoked, and the system automatically reduces the CPU frequency to the minimum while adaptively adjusting the core power supply to the minimum operating power corresponding to that frequency. This achieves dynamic voltage and frequency regulation of the CPU, reducing CPU power consumption. When the system has task requirements, the automatic adjustment algorithm is invoked to adjust the CPU frequency to the maximum operating frequency, while adaptively adjusting the CPU core power supply to the maximum operating voltage to ensure normal system operation.

[0021] This invention proposes a method for dynamic power management and dynamic voltage and frequency regulation in AI intelligent computing systems. The overall design scheme block diagram is shown below. Figure 1 As shown. This system is based on the Phytium E2000Q processor board hardware circuit design, including NPU, FPGA, BMC, PCIe bridge, power module, LPDDR4 memory chips, etc. To improve the system's versatility, this system also provides multiple interfaces such as network, DP display, USB, RS232, RS485, CAN, and CXP for easy application expansion. To achieve low power consumption, domestically produced low-power components were used during component selection, ensuring functional requirements were met.

[0022] The AI ​​intelligent computing system is powered by an external 18V~36V aviation plug interface. It uses a 1 / 16 brick isolation power supply to convert the power supply to the system's working power of 12V, and then uses a DC-DC converter to convert the power supply to the working power of each circuit chip. The CPU is connected to the FPGA via the PCIe bus, and the system first powers on the FPGA. After the FPGA is working normally, its out-of-band GPIO interface controls the CPU's power-on, clock enable, and reset, as well as the NPU's power-on, clock enable, and reset. The two NPUs use independent power supplies and clocks, and can be controlled separately to complete the initialization process.

[0023] After the system powers on, the CPU begins its startup process. The CPU first loads the BIOS into memory and then transfers control to the BIOS, which then begins running. The BIOS initializes the serial ports, memory, PCIe devices, network cards, graphics cards, USB ports, etc. After initialization, the BIOS bootloader from the boot device and loads it into memory. Once the bootloader is loaded, the BIOS transfers control to it and jumps to its entry point to begin execution. The bootloader is responsible for loading the operating system, initializing it, configuring the operating system kernel, and initializing hardware devices, thus completing the entire system startup. At this point, all system functional modules are operating stably.

[0024] After the 12V power supply converted by the isolated power supply module stabilizes, the 12V power supply is converted by DC-DC to power the P3V3_BMC. The BMC serves as a system health information monitoring circuit, and its ADC pin is designed to collect the operating voltage of each circuit in the system, the system temperature, and the system input voltage and current in real time, and calculate the total power consumption of the system.

[0025] The BMC uses a zero-drift, bidirectional current sensing amplifier, powered by a single 2.7V to 30V power supply. It can sense the voltage drop across the resistor under common-mode voltages from -0.2V to 30V. The sampling resistor is 5mΩ and connected in series at the power input. The negative power supply GND voltage drives the REF terminal of the current sensing chip to detect the positive current. The voltage (OUT) at the detection output terminal increases linearly with the current under test. The system input current corresponding to the sampling voltage can be calculated by formula (1).

[0026] (1) System current acquisition and calculation Where: Vout — sampled output voltage R1 / R3 — Sampling magnification factor, here the magnification factor is 50. Iload — Sampled current, i.e., system output current Ishunt – Uses a resistor, specifically a 5mΩ resistor. REF—Sampling reference voltage, connected to GND here. The BMC and CPU communicate via the UART bus. The BMC transmits the collected system data to the CPU in real time, and the CPU parses the message data transmitted by the BMC. Users can access the system terminal and read the collected relevant information through system commands. The collected power consumption value provides a reference for system status prediction.

[0027] The CPU connects to two AI modules via a PCIe 2.0 x4 bus through a PCIe expansion bridge. The PCIe expansion bridge uses PCIe non-transparent bridge-based data transmission technology to enable data interaction between the master CPU and the slave devices. Master-slave data communication is dynamically configured via software switching. The AI ​​module supports typical neural network algorithms such as YOLO, MobileNET, and ResNet, with an intelligent computing power of ≥64 TOPS@INT8. Using two AI modules increases computing power but also increases system power consumption. Therefore, an algorithm needs to be developed to maintain low power consumption while meeting computing power requirements. This can be achieved by shutting down one AI module via software algorithm, thus minimizing system power consumption.

[0028] After the system powers on, the status monitoring unit first records the current system voltage (denoted as Vcur) and current current (denoted as Icur) collected by the BMC, and calculates the current power consumption (denoted as Pcur). If the system has no tasks assigned for a long time, the power consumption comparison unit is called through an algorithm to compare whether the current power consumption is less than the preset power consumption (denoted as Ppreset).

[0029] The system initiates an adaptive timeout policy. The principle behind this policy is that after a system task request is completed, it does not immediately switch to a low-power state but waits for a specified period. During this time, the system remains in operating mode: if a new task request arrives during this period, it continues to serve; if no new task request arrives after this period, the device switches to low-power mode. This waiting period is called the timeout policy threshold (denoted as Tmin). The threshold of the adaptive timeout policy changes dynamically with system operation. The threshold Tmin is adjusted in real-time based on changes in system load, and the change in threshold depends on changes in task requests and the benefits of the previously set threshold.

[0030] The system starts the counting and statistics unit. If a new task request arrives within Tmin time, the system will not switch the working mode. If the system times out and Pcur < Ppreset, the system will be put into low power mode, the dynamic power management unit will be enabled, and the power supply and clock of one NPU module will be turned off.

[0031] Power supply design block diagram as follows Figure 2As shown, the CPU core power controller design adopts a combination of a Chipown digital power controller (model BPD92028A) and a DrMOS (model BPD80370E). The CPU core power controller controls the CPU core power supply through PWM output. The enable pin of the CPU core power controller is controlled by the FPGA. After the FPGA starts normally, it enables the digital power controller to ensure that the CPU core power supply is powered on first. The CPU's MIO8_A and MIO8_B pins are configured as IIC interfaces and connected to the IIC interface of the CPU core power controller. The CPU core power controller program is burned with a specified output voltage of 0.8V before device mounting. The CPU can write to the CPU core power controller through the IIC interface to change the value of the CPU core power controller register, thereby realizing the CPU's adjustment of its own operating power output.

[0032] The CPU has 2 small cores and 2 large cores. When the system is in low power mode, the CPU adjusts the 4 cores to maintain the highest operating frequency. The maximum operating frequency of the small cores is 1.5GHz and the maximum operating frequency of the large cores is 1.8GHz. Users can check the current core frequency operating status through system commands.

[0033] The implementation process of the dynamic power management and dynamic voltage and frequency regulation method of the present invention is as follows: Figure 3 As shown. When the system is in low-power mode, if it still does not receive any task assignments, the system will remain in an idle state. The BMC collects system load and related power signals in real time and calculates and saves the frequency of system power consumption changes. The operating system predicts the performance required by the system in the next time period based on the current load changes.

[0034] When the system has no tasks assigned and the system power consumption remains unchanged for a long time, the CPU power management unit will be invoked to adjust the CPU to a low-power state. That is, the CPU operating frequency will be reduced to the minimum through software-invoked algorithms. Users can enter the system root terminal through the external test serial port to check that the minimum frequency of the small core of the CPU is maintained at 0.1875GHz and the minimum frequency of the large core is maintained at 0.225GHz, indicating that the CPU frequency reduction is complete.

[0035] While reducing the CPU clock speed, it is also necessary to adjust the CPU core power supply voltage. This involves querying the CPU frequency and corresponding voltage mapping table. When the CPU clock speed is reduced to its lowest level, the corresponding core power supply voltage is also at its minimum operating voltage. The voltage control unit writes the value to the register of the CPU core power supply controller to change the power output. The user can access the system root terminal through an external test serial port and use system commands to check if the core power supply voltage collected by the BMC is 0.72V. By comparing the collected current core power supply voltage with the preset voltage value, it can be determined whether the CPU has entered a low-power state.

[0036] When a system has a task to process, the CPU frequency adaptively adjusts to the maximum operating frequency. The CPU calls the power management system to increase the CPU core power supply to the typical operating voltage corresponding to the maximum frequency. The CPU automatically switches to the working state, thus realizing the dynamic frequency and voltage regulation of the CPU.

[0037] This invention is based on an unmanned embedded AI intelligent computing platform. Through software algorithms combined with hardware design, it achieves dynamic power management of the AI ​​module and dynamic voltage and frequency regulation of the CPU. In special environments, these two methods can dynamically manage system energy consumption to prevent excessive energy consumption due to high power consumption. The hardware platform built according to the above scheme has been experimentally verified, and the results show that this method can effectively save energy and reduce system power consumption.

[0038] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for AI intelligent computing system power consumption dynamic power management and dynamic voltage and frequency scaling, characterized in that, This method is implemented through the following design: The hardware circuit of the AI ​​intelligent computing system is designed based on Phytium Tenlong E2000Q. The hardware circuit includes NPU, FPGA, BMC, PCIe expansion bridge, isolated power supply module, memory, and firmware BIOS. The AI ​​intelligent computing system is powered by an external aviation plug interface. The power supply is converted into the working power of the AI ​​intelligent computing system through an isolated power module, and then the working power is converted into the working power of the onboard chips; the onboard chips include NPU and FPGA. The CPU of the AI ​​intelligent computing system, Phytium Tenlong E2000Q, is connected to the FPGA via the PCIe bus. The out-of-band part of the FPGA controls the power-on, reset, and clock enable of the AI ​​intelligent computing system, as well as the power control and clock enable of the NPU. The CPU is connected to two AI intelligent modules in the AI ​​intelligent computing system through the PCIe expansion bridge. The power supply and clock of the AI ​​intelligent modules are designed separately, and the power supply, clock and reset of the AI ​​intelligent modules are controlled by the FPGA. The BMC monitors the health information of the AI ​​intelligent computing system, collecting real-time data on the system's operating voltages, temperatures, and input current, and calculating the total power consumption. The BMC and CPU communicate via serial port, transmitting the data collected by the BMC to the CPU in real time. This data serves as the basis for the CPU's dynamic voltage adjustment.

2. The method of claim 1, wherein, When the system does not need to process AI data, it will automatically enter a low-power mode. The FPGA receives the interrupt signal, calls the algorithm control strategy, and disconnects the power supply and clock of a designated AI module to ensure that another AI module can operate normally, thus realizing dynamic power management of the AI ​​module.

3. The method of claim 1, wherein, The BMC collects the system's input voltage and input current in real time, calculates the current total power consumption of the system, and determines whether the current power consumption is lower than the total power consumption threshold when the system starts normally. The CPU determines whether the system has entered low-power mode based on the power consumption comparison results. At this time, the power supply and clock of one NPU are turned off. In low-power mode, the system's single AI intelligent module still works normally. When the system is not processing any data, the system power consumption remains at the minimum preset value. If the total system power consumption collected by the BMC is always less than the minimum preset value, it is determined that the system is not executing any tasks and is in an idle state.

4. The method of claim 1, wherein, The CPU adjusts the register values ​​of the CPU core power controller via the IIC interface to achieve controllable CPU core power. When the system enters low-power mode and the total system power consumption collected by the BMC is consistently less than the minimum preset value, it is determined that the system is in idle state. The automatic adjustment algorithm is invoked to automatically reduce the CPU frequency to the minimum, while the CPU core power is adaptively adjusted to the minimum operating power corresponding to that frequency, achieving dynamic voltage and frequency regulation of the CPU. When the system has task requirements, the automatic adjustment algorithm is invoked to adjust the CPU frequency to the maximum operating frequency, while the CPU core power is adaptively adjusted to the maximum operating voltage to ensure normal system operation.

5. The method of claim 1, wherein, After the system powers on, the CPU starts up. The CPU first loads the BIOS into memory and then hands control over to the BIOS, which then begins running. The BIOS initializes the serial ports, memory, PCIe devices, network cards, graphics cards, and USB ports. After initialization, the BIOS bootloader from the boot device and loads it into memory. Once the bootloader is loaded into memory, the BIOS hands control over to the bootloader and jumps to the bootloader's entry point to begin execution. The bootloader is responsible for booting and loading the operating system, initializing the operating system, configuring the operating system kernel, and initializing hardware devices, thus completing the entire system startup process.

6. The method of claim 1, wherein, The system has an adaptive timeout strategy. The design principle of the adaptive timeout strategy is that after the system completes a task request, it does not immediately switch to a low-power state, but waits for a period of time. During this period, the system is maintained in the operating mode: if a new task request arrives during this period, the system continues to provide services; if no new task request arrives after this period, the system switches to low-power mode. This waiting period is called the threshold Tmin of the timeout strategy, and the threshold of the adaptive timeout strategy changes dynamically with the operation of the system.

7. The method of claim 1, wherein, The CPU core power controller controls the CPU core power supply through PWM output. The enable pin of the CPU core power controller is controlled by the FPGA. After the FPGA starts normally, it enables the CPU core power controller to ensure that the CPU core power supply is powered on first. Two pins of the CPU are configured as IIC interfaces and connected to the IIC interface of the CPU core power controller. The program for the CPU core power controller has been burned into the program for specifying the output voltage. The CPU writes to the CPU core power controller through the IIC interface to change the value of the register of the CPU core power controller, thereby realizing the CPU regulating its own operating power output.

8. The method of claim 1, wherein, When the system has a task to process, it will adaptively adjust the CPU frequency to the maximum operating frequency and increase the CPU core power supply to the operating voltage corresponding to the maximum frequency. The CPU will automatically switch to the working state, realizing dynamic frequency and voltage adjustment of the CPU.

9. The method of claim 1, wherein, This method is applied in intelligent computing.

10. A system for implementing the method as described in any one of claims 1 to 8.

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