Terminal group memory sharing management system

Abstract

The invention relates to the technical field of memory management, in particular to a terminal group memory sharing management system which comprises a computing power intensity identification module, a quota granularity control module, an intention priority module, an access arbitration sorting module and a cold region recognition and recovery module. According to the method, the performance level is formed by performing quantitative mapping on the task processing efficiency and the execution delay of the terminal in the specific time window, the quota upper limit is calculated according to the performance level and the system load, the page block granularity parameter is set, the memory page resource configuration of each terminal is dynamically adjusted, and the pre-behavior vector is constructed in combination with the historical access behavior. Extracting a plurality of data items reflecting the access intention to generate a priority control quantity, sorting the access requests in a descending manner, executing memory page access according to mapping parameters, identifying an access cold area according to an access period offset, and executing address remapping; and the resource dynamic adaptation capability is guaranteed, the access sorting precision is improved, and the invalid occupation and conflict rate is reduced.

Description

Technical Field

[0001] This invention relates to the field of memory management technology, and in particular to a terminal group memory sharing management system. Background Technology

[0002] Memory management technology involves the effective allocation, management, and optimization of memory resources in computer systems. Its core components include memory allocation, memory reclamation, memory sharing, and memory protection. The purpose of memory management is to ensure that computer systems can efficiently utilize limited memory resources and prevent problems such as memory leaks and overflows, thereby improving system stability and performance. Memory management typically relies on the operating system's memory management module, which manages the scheduling of physical and virtual memory through the operating system kernel. Furthermore, with the widespread adoption of multi-core processors and distributed systems, the application of memory sharing technology has gradually become a key technology for improving resource utilization and accelerating data processing.

[0003] Traditional terminal group memory sharing management systems refer to management systems that share memory resources among multiple terminal devices. These systems typically coordinate memory access and usage by each terminal device using a centralized or distributed approach, ensuring efficient and stable sharing of memory resources. Traditional memory sharing management systems usually employ static allocation and round-robin methods to allocate and manage shared memory. In scenarios where multiple terminal devices process in parallel, this can lead to wasted memory resources or conflicts, thus affecting overall system performance. To ensure the efficiency and reliability of memory sharing, traditional systems require complex synchronization mechanisms and conflict resolution methods, and place high demands on the communication and coordination capabilities between terminal devices. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a terminal group memory sharing management system.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a terminal group memory sharing management system, the system comprising: The computing power intensity identification module collects the number of tasks completed by the terminal per unit time and the instruction delay value, maps the number of tasks completed per unit time and the instruction delay value to a preset processing threshold range, and generates a computing power level range identification. The intent priority module extracts the mapped memory page block size based on the computing power level range identifier, calculates the quotient of the computing power level range identifier and the load weight ratio, and if the quotient is within the preset allowable expansion range, determines the quota upper limit adjustment coefficient and generates memory page block granularity configuration parameters. The quota granularity control module monitors access requests initiated by terminals, extracts shared page access interval, coverage difference, byte span change and lock failure number, combines shared page access interval, coverage difference, byte span change and lock failure number to construct memory access pre-behavior vector, calculates the weighted memory access pre-behavior vector and generates priority control quantity; The arbitration sorting module is accessed to sort access requests in descending order according to the priority control quantity. The memory page block granularity configuration parameters are called to map physical addresses, the number of accesses per unit time is recorded, and a shared page access frequency linked list is established.

[0006] As a further aspect of the present invention, the computing power level range identifier includes a performance level mapping code, a computing power threshold range boundary, and a heterogeneous terminal capability label; the memory page block granularity configuration parameters include a physical page frame size setting value, a maximum allowed mapping range, and a granularity dynamic scaling factor; the priority control quantity includes a comprehensive score for access urgency, an arbitration queue sorting index, and a resource preemption weight threshold; and the shared page access frequency linked list includes a memory page physical address node, a unit time access counter, and a heat statistics timestamp.

[0007] As a further aspect of the present invention, the computing power intensity identification module includes: The performance data aggregation submodule collects the number of tasks completed per unit time and the instruction latency value for each terminal within a preset time window, calculates the reciprocal of the average instruction execution latency value, obtains the instruction response frequency factor, performs a weighted multiplication operation on the number of tasks completed per unit time and the instruction response frequency factor to obtain the instantaneous value of instruction throughput performance, calls the pre-stored terminal hardware baseline parameters to perform a division operation on the instantaneous value of instruction throughput performance to complete the numerical normalization process, and smooths the normalized values ​​of multiple consecutive sampling points through a moving average algorithm to generate a normalized evaluation value of terminal performance. The threshold interval matching submodule calls the terminal performance normalization evaluation value, traverses the preset processing threshold intervals stored in the configuration unit, extracts the lower boundary value and upper boundary value corresponding to each interval in turn, executes the value comparison logic, and determines whether the terminal performance normalization evaluation value is greater than or equal to the lower boundary value and less than the upper boundary value. When the judgment condition is met, the current interval position is locked, the computing power level definition metadata associated with the interval is read, and the interval sequence number and computing power level definition metadata are concatenated and formatted to assemble the fields to establish a computing power level mapping index key. The identifier encoding generation submodule retrieves the corresponding level feature code from the computing power level definition table based on the computing power level mapping index key, extracts the device type identification code and memory bus bandwidth parameters of the current terminal, converts the computing power level mapping index key into the corresponding binary feature vector, combines the level feature code, device type identification code and binary feature vector into a data frame according to the preset displacement rules, performs cyclic redundancy check calculation on the combined data frame to add integrity check bits, and generates a computing power level range identifier.

[0008] As a further aspect of the present invention, the process of setting the processing threshold interval specifically involves: statistically analyzing the sample set of normalized evaluation values ​​of terminal performance reported by all active terminals within a historical operating cycle; using box plot analysis to remove outliers from the sample set; arranging the cleaned sample data in ascending order; calculating the cumulative distribution function of the sample sequence; extracting multiple key quantile values ​​corresponding to the cumulative distribution function curve at equal intervals based on the preset number of computing power grading granularities; establishing adjacent quantile values ​​as the lower and upper limits of the interval, and constructing multiple continuous and non-overlapping numerical ranges as the processing threshold interval.

[0009] As a further aspect of the present invention, the quota granularity control module includes: The baseline page block extraction submodule retrieves the kernel's preset memory mapping specification table based on the computing power level interval identifier, matches the physical page frame segmentation standard corresponding to the performance level to which the identifier belongs, obtains the baseline size of the mapped page block, extracts the computing power intensity feature field from the computing power level interval identifier, calls the base conversion instruction to convert the feature field into a double-precision floating-point computing power level quantization value, and stores the size and value into a temporary register. The expansion coefficient determination submodule monitors the task scheduling queue depth and the number of active processing units on the bus in real time, calculates the ratio of the two to obtain the current load weight ratio, performs a division operation between the computing power level quantification value and the current load weight ratio to obtain the load adaptability quotient, compares the load adaptability quotient with the boundary value of the preset allowable expansion range, and if it is determined that the load adaptability quotient falls within the range, calls the preset segmented mapping function to calculate the corresponding gain value and generates the quota upper limit adjustment coefficient. The parameter encapsulation generation submodule performs a weighted multiplication operation based on the mapped page block base size and quota upper limit adjustment coefficient to calculate the dynamic mapping granularity value. It then calls a preset memory address alignment verification algorithm to perform a binary bitmasking operation on the dynamic mapping granularity value, extracts the maximum transfer unit limit value of the memory controller, and combines and encapsulates the aligned granularity value with the limit value to generate memory page block granularity configuration parameters.

[0010] As a further aspect of the present invention, the intent priority module includes: The behavior measurement and organization submodule monitors the access requests initiated by each terminal, records the timestamps of the most recent shared page requests, calculates the interval value, compares the coverage of the target page address range to obtain the difference, and counts the number of the most recent page frame locking failures, generating a raw measurement set of memory access behavior. The pre-access behavior mapping submodule parses the original metric set of memory access behavior, extracts the byte span change value of the most recent multiple access requests, maps the interval value to the time dimension, maps the difference and the byte span change value of the most recent multiple access requests to the spatial dimension, and combines the number of the most recent page frame locking failures to establish a memory access pre-access behavior vector. The priority calculation submodule deconstructs the memory access pre-action vector to obtain multi-dimensional components, and detects in real time the queuing depth of the current bus arbitration queue, the historical cache hit rate of the target memory page, and the remaining bus bandwidth to calculate and obtain the priority control value.

[0011] As a further aspect of the present invention, the access arbitration sorting module includes: The request sorting queue submodule, based on the value of the priority control quantity, traverses the backlog of access requests in the current buffer, binds the handle of each request to the corresponding priority value as a tuple object, sorts the tuple objects in descending order, and reassembles the request handle queue according to the sorted order to generate an ordered access request sequence. The address mapping execution submodule calls the memory page block granularity configuration parameters to obtain the physical page frame segmentation size and alignment mask, extracts the virtual target address from the ordered access request sequence in sequence, performs bit shifting operations to separate the page number and the page offset, maps the virtual page number to the corresponding physical base address according to the segmentation size, and writes read / write permission bits and existence bits to the mapping table to generate a physical page frame mapping index. The frequency statistics linking module locks the corresponding memory region based on the physical page frame mapping index, starts the hardware performance monitoring unit to collect the read and write instruction trigger signals within a unit of time after mapping, counts the cumulative access operation count for each index entry, dynamically allocates memory space for each accessed page frame, creates a statistics node, writes the physical base address and cumulative access operation count into the node data field, connects all nodes using pointers, and establishes a shared page access frequency linked list.

[0012] As a further aspect of the present invention, the system further includes: The cold zone identification and recycling module traverses the shared page access frequency linked list, calculates the average access period of the sliding time window, and calculates the absolute value of the difference between the average access period and the historical average as the offset. If the offset exceeds the offset judgment threshold and there is no rebound, a remapping pointer is obtained. The remapping pointer includes the target reclaimed area address, space reuse status flag, and read / write permission reset bit.

[0013] As a further aspect of the present invention, the cold zone identification and recycling module includes: The access average statistics submodule traverses the shared page access frequency linked list, accesses each node in turn and extracts the stored access timestamp sequence, sets the time span parameter of the sliding window, extracts the most recent continuous access record falling into the current window on the time axis, calculates the time difference between two adjacent access events, performs an arithmetic average operation on the extracted time difference, and generates the access period sliding average. The heat decay determination submodule calls the access cycle moving average, reads the corresponding historical average data from the database, performs subtraction and takes the absolute value to obtain the access heat offset, compares the offset with the preset offset determination threshold, calculates the change gradient of the access cycle moving average in the continuous cycle, confirms that there is no rebound trend, and if the determination condition is met, locks the corresponding memory page physical page frame number and generates the cold zone determination index address. The mapping pointer injection submodule addresses the corresponding page table entry based on the cold zone determination index address, requests the target storage space for data migration, obtains the target reclamation area address, generates a space reuse status flag to identify page availability and a read / write permission reset bit to block illegal writing, performs bit concatenation operation on the three data items and writes them into the reserved field of the page table entry, completes the address redirection, and generates a remapping pointer.

[0014] As a further aspect of the present invention, the method for setting the offset judgment threshold is as follows: retrieve the distribution data of the historical mean within a preset long period, calculate the standard deviation of the distribution data to quantify the dispersion of historical access fluctuations, and use it as the basic fluctuation tolerance; collect the current global free memory page frame ratio in real time, construct a dynamic adjustment coefficient that is positively correlated with the free memory page frame ratio, and perform a multiplication operation between the basic fluctuation tolerance and the dynamic adjustment coefficient to obtain the offset judgment threshold.

[0015] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In this invention, a performance level is formed by quantifying and mapping the task processing efficiency and execution latency of a terminal within a specific time window. Based on the performance level and system load, the quota limit is calculated and page block granularity parameters are set. The memory page resource configuration of each terminal is dynamically adjusted. A pre-behavioral vector is constructed by combining historical access behavior. Multiple data items reflecting access intentions are extracted to generate priority control quantities. Access requests are sorted in descending order and memory page access is performed according to the mapping parameters. The access frequency is recorded in real time and an access list is formed. Access cold zones are identified based on the access cycle offset and address remapping is performed. This improves access sorting accuracy and reduces invalid occupation and conflict rates while ensuring dynamic resource adaptation capabilities. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a system flowchart of the present invention; Figure 2 This is a schematic diagram of the system framework of the present invention; Figure 3 This is a flowchart of the computing power intensity identification module of the present invention; Figure 4 This is a flowchart of the quota granularity control module of the present invention; Figure 5 This is a flowchart of the intent priority module of the present invention; Figure 6 This is a flowchart of the process for accessing the arbitration sorting module in this invention; Figure 7 This is a flowchart of the cold zone identification and recycling module of the present invention. Detailed Implementation

[0018] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0019] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0020] In the embodiments of this invention, the terms "image" and "picture" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, their intended meanings are consistent. Similarly, the terms "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, their intended meanings are consistent.

[0021] In this embodiment of the invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When the difference is not emphasized, the meaning they express is the same.

[0022] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0023] Please see Figure 1 A terminal group memory sharing management system, the system includes a computing power intensity identification module, a quota granularity control module, an intent priority module, an access arbitration and sorting module, and a cold zone identification and reclamation module; The computing power intensity identification module collects the number of tasks completed per unit time and the average instruction execution latency of each terminal within a preset time window, maps the number of tasks completed per unit time and the average instruction execution latency to a preset processing threshold range, determines the performance level of each terminal, and generates a computing power level range identifier. The quota granularity control module extracts the corresponding mapped memory page block size based on the computing power level range identifier, calculates the quotient of the ratio of the computing power level range identifier to the current system load weight, and if the quotient is within the preset allowable expansion range, determines the quota upper limit adjustment coefficient for each terminal and generates memory page block granularity configuration parameters. The intent priority module monitors access requests initiated by each terminal, extracts the time interval between the three most recent shared page accesses, the difference in target page address range coverage, the byte span change between the two most recent access requests, and the number of page frame locking failures, and combines them to construct a memory access pre-behavior vector. The module then performs weighted summation and standardization calculations on the values ​​in the memory access pre-behavior vector to generate a priority control quantity. Access the arbitration sorting module, sort the access requests in descending order according to the value of the priority control quantity, call the memory page block granularity configuration parameters to perform physical address mapping, record the number of memory page access operations per unit time after mapping, and establish a shared page access frequency linked list. The cold zone identification and recycling module traverses the shared page access frequency linked list, calculates the average access cycle within the sliding time window, and calculates the absolute value of the difference between the average access cycle and the historical average as the offset. If the offset exceeds the preset offset judgment threshold and there is no rebound within the continuous cycle, a remapping pointer is inserted at the corresponding memory page address. The computing power level range identifier includes performance level mapping code, computing power threshold range boundary and heterogeneous terminal capability label; memory page block granularity configuration parameters include physical page frame size setting value, maximum allowed mapping range and granularity dynamic scaling factor; priority control quantities include access urgency comprehensive score, arbitration queue sorting index and resource preemption weight threshold; shared page access frequency linked list includes memory page physical address node, unit time access counter and heat statistics timestamp; remapping pointer includes target reclamation area address, space reuse status flag and read / write permission reset bit.

[0024] Please see Figure 2 and Figure 3 The computing power intensity identification module includes: The performance data aggregation submodule collects the number of tasks completed per unit time and the instruction latency value for each terminal within a preset time window, calculates the reciprocal of the average instruction execution latency value, obtains the instruction response frequency factor, performs a weighted multiplication operation on the number of tasks completed per unit time and the instruction response frequency factor to obtain the instantaneous value of instruction throughput performance, calls the pre-stored terminal hardware benchmark parameters to perform a division operation on the instantaneous value of instruction throughput performance to complete the numerical normalization process, and smooths the normalized values ​​of multiple consecutive sampling points through a moving average algorithm to eliminate numerical jitter caused by sudden computing power fluctuations and generate a normalized evaluation value of terminal performance. The system kernel's task scheduling counter interface is invoked to set a preset time window of 100 milliseconds for a specific terminal device (e.g., an image rendering node equipped with an eight-core processor). Within this window, the number of valid task blocks submitted to the instruction pipeline by the terminal is accumulated to 12. Simultaneously, the performance monitoring unit (PMU) collects the average number of clock cycles from instruction execution to retirement, measuring 5 clock cycles. Combined with a 2GHz clock frequency, the average instruction execution latency is calculated to be 2.5 nanoseconds. The reciprocal operation yields the instruction response frequency factor. The instantaneous instruction throughput performance is calculated by performing a weighted multiplication operation on the number of tasks completed per unit time (12) and the instruction response frequency factor. Retrieve the pre-stored theoretical maximum instruction throughput of this type of terminal (e.g.) Using this as the terminal hardware baseline parameter, a division operation is performed to obtain a normalized value of 0.48. This value is then stored in a first-in-first-out queue of length 5. The queue already contains values ​​from previous time steps (0.46, 0.47, 0.45, 0.49). An arithmetic mean operation is performed on all values ​​in the queue to obtain a smoothed value of 0.47. This eliminates sudden fluctuations caused by cache misses in a single sampling and generates a normalized evaluation value for terminal performance.

[0025] The threshold interval matching submodule calls the terminal performance normalization evaluation value, traverses the preset processing threshold intervals stored in the configuration unit, extracts the lower boundary value and upper boundary value corresponding to each interval in turn, executes the value comparison logic, and determines whether the terminal performance normalization evaluation value is greater than or equal to the lower boundary value and less than the upper boundary value. When the judgment condition is met, the current interval position is locked, the computing power level definition metadata associated with the interval is read, and the interval sequence number and computing power level definition metadata are concatenated and formatted to assemble the fields and establish a computing power level mapping index key. The specific process for setting the processing threshold interval is as follows: by statistically analyzing the sample set of normalized evaluation values ​​of terminal performance reported by all active terminals within the historical operating cycle, outliers in the sample set are removed using box plot analysis. The cleaned sample data is then sorted in ascending order, and the cumulative distribution function of the sample sequence is calculated. Based on the preset number of computing power grading granularities, multiple key quantile values ​​corresponding to the cumulative distribution function curve are extracted at equal intervals. The values ​​of two adjacent quantiles are established as the lower limit and upper limit of the interval, respectively, and multiple continuous and non-overlapping numerical ranges are constructed as the processing threshold interval. The system reads the preset processing threshold ranges stored in the system configuration unit, as shown in Table 1. The computing power is divided into three levels. The lower and upper boundary values ​​of each range are extracted sequentially. Numerical comparison logic is executed. First, 0.47 is compared with the upper limit of 0.30 for the low computing power range, determining that it does not belong to this range. Then, 0.47 is compared with the lower limit of 0.30 and the upper limit of 0.70 for the medium computing power range, determining... If the conditions are met, the current interval is locked as the "medium computing power interval". The computing power level definition metadata associated with this interval (e.g., level code "M-Tier") is read. The interval sequence number (e.g., "02") is concatenated and formatted with the computing power level definition metadata using ASCII code fields to establish a computing power level mapping index key. The process of setting the preset processing threshold interval is as follows: a sample set of normalized evaluation values ​​of terminal performance reported by all active terminals within the historical operating cycle of the system (e.g., the past 168 hours) is collected (a total of 100,000 sample points). The quartiles of the samples are calculated using box plot analysis, and samples with values ​​lower than the threshold are removed. and higher Outliers were identified by sorting 98,000 cleaned sample data in ascending order and calculating the cumulative distribution function (CDF) of the sample sequences. Based on the preset number of computational power grading granularities (e.g., 3 levels), key quantile values ​​corresponding to cumulative probabilities of 33.3% and 66.6% on the CDF curve were extracted at equal intervals and set to 0.30 and 0.70, respectively. Adjacent quantile values ​​were established as the lower and upper limits of the interval, respectively, thus constructing three continuous and non-overlapping numerical ranges of [0, 0.30), [0.30, 0.70], and [0.70, 1.0], which served as the processing threshold intervals.

[0026] Table 1. Configuration table of computing power threshold range; The identifier encoding generation submodule retrieves the corresponding level feature code from the computing power level definition table based on the computing power level mapping index key, extracts the device type identification code and memory bus bandwidth parameters of the current terminal, converts the computing power level mapping index key into the corresponding binary feature vector, combines the level feature code, device type identification code and binary feature vector into a data frame according to the preset displacement rules, performs cyclic redundancy check calculation on the combined data frame to add integrity check bits, and generates computing power level interval identifiers. The corresponding level feature code (e.g., hexadecimal number 0x02) is retrieved from the pre-defined hash table of computing power level. The device type identification code (e.g., the identification code of a GPU node is 0xA1) and memory bus bandwidth parameters (e.g., 64GB / s) of the current terminal are extracted by reading the terminal hardware descriptor. The string form of the computing power level mapping index key is converted into a 256-bit binary feature vector using the SHA-256 algorithm. According to the preset shift rules, 0x02 is shifted left by 56 bits and 0xA1 is shifted left by 48 bits. The first 48 bits of the binary feature vector are extracted and combined into a data frame by performing a bitwise OR operation on the three to obtain the basic identification frame. The basic identification frame is then subjected to CRC32 cyclic redundancy check calculation to generate a 32-bit check value (e.g., 0x3F2A1C9B). This check value is appended to the end of the basic identification frame to generate the computing power level range identifier.

[0027] Please see Figure 2 and Figure 4 The quota granularity control module includes: The baseline page block extraction submodule retrieves the kernel's pre-set memory mapping specification table based on the computing power level interval identifier, matches the physical page frame segmentation standard corresponding to the performance level to which the identifier belongs, obtains the baseline size of the mapped page block, extracts the computing power intensity feature field from the computing power level interval identifier, calls the base conversion instruction to convert the feature field into a double-precision floating-point computing power level quantization value, and stores the size and value into a temporary register. Based on the level feature code (0x02), the kernel's pre-built memory mapping specification table is retrieved. The table defines the physical memory page management strategy corresponding to different computing power levels. The physical page frame segmentation standard corresponding to the computing power level is matched as "big page mode (2MB)". The base size of the mapped page block is obtained as 2097152 bytes (2MB). The computing power intensity feature field hidden in the computing power level interval identifier (e.g., the value 0.64 after normalization based on the bandwidth parameter) is extracted. The number conversion instruction of the floating point unit is called to convert the feature field into a double-precision floating-point computing power level quantization value (0.64). The base size of the mapped page block and the computing power level quantization value are stored in the high-speed temporary storage register for subsequent quota calculation logic to generate size and value temporary storage data.

[0028] The expansion coefficient determination submodule monitors the task scheduling queue depth and the number of active processing units on the bus in real time, calculates the ratio of the two to obtain the current load weight ratio, performs a division operation between the computing power level quantification value and the current load weight ratio to obtain the load adaptability quotient, compares the load adaptability quotient with the boundary value of the preset allowable expansion range, and if it is determined that the load adaptability quotient falls within the range, calls the preset segmented mapping function to calculate the corresponding gain value and generates the quota upper limit adjustment coefficient. Monitor the task scheduling queue depth on the bus (e.g., the number of currently waiting tasks is 40) and the number of active processing units (e.g., the number of currently active cores is 4), calculate the ratio of the two (40 / 4 = 10) to obtain the current load weight ratio, retrieve the computing power level quantization value (0.64) from the register, and perform a division operation between the computing power level quantization value and the current load weight ratio. The load adaptability quotient is obtained and compared with the boundary value of the preset allowable expansion range (e.g., [0.05, 0.15]). If 0.064 falls within this range, it indicates that the current system load is moderate and the terminal has expansion potential. The preset segmentation mapping function (e.g., ...) is then called. Substituting 0.064 into the calculation yields the gain value. The quota limit adjustment coefficient is generated; the boundary value setting of the "allowed expansion range" refers to the system's crash threshold under full load stress test. By gradually increasing the virtual load and monitoring the memory overflow frequency, the quotient value corresponding to the overflow rate of 1% is set as the lower limit, and the value of 5% is set as the upper limit.

[0029] The parameter encapsulation generation submodule performs a weighted multiplication operation based on the base size of the mapped page block and the quota upper limit adjustment coefficient to calculate the dynamic mapping granularity value. It then calls a preset memory address alignment verification algorithm to perform a binary bitmasking operation on the dynamic mapping granularity value to verify the address boundary alignment. Finally, it extracts the maximum transfer unit limit value of the memory controller and combines and encapsulates the aligned granularity value with the limit value to generate memory page block granularity configuration parameters.

[0030] A weighted multiplication operation is performed based on the mapped page block base size (2MB) and the quota limit adjustment factor (1.64). The dynamic mapping granularity value is calculated, and the preset memory address alignment check algorithm is called. Based on the system's minimum page size (4KB), a binary bitmasking operation (AND0xFFFFF000) is performed on 3.28MB (3358720 bytes). The lower 12 bits are cleared to ensure address boundary alignment, resulting in an aligned granularity value of 3.2MB (3355443 bytes). The maximum transfer unit limit value of the memory controller (e.g., 4MB) is extracted, and the aligned granularity value and the limit value are combined and encapsulated to construct a data structure containing "granularity: 3.2MB, upper limit: 4MB", generating memory page block granularity configuration parameters.

[0031] Please see Figure 2 and Figure 5 The intent priority module includes: The behavior measurement and organization submodule monitors the access requests initiated by each terminal, records the timestamps of the most recent shared page requests, calculates the interval value, compares the coverage of the target page address range to obtain the difference, and counts the number of the most recent page frame locking failures, generating a raw measurement set of memory access behavior. Deploy probes at the entry point of the memory management unit to monitor virtual memory access requests initiated by each terminal and record the system timestamps of the four most recent shared page requests (e.g., ...). The interval values ​​between adjacent requests are calculated (5ms, 10ms, 15ms). The start and end addresses of the target page for each request are extracted, the address coverage range is calculated (e.g., each request covers 4KB), the coverage range of adjacent requests is compared to obtain the difference (if both are 4KB, the difference is 0), and the page table lock status register is queried to count the number of lock failures of the target page frame in the last second (e.g., 2 times). The above time intervals, space coverage differences and lock failure counts are packaged to generate the original metric set of memory access behavior.

[0032] The pre-access behavior mapping submodule parses the original metric set of memory access behavior, extracts the byte span change value of the most recent multiple access requests, maps the interval value to the time dimension, maps the difference and the byte span change value of the most recent multiple access requests to the spatial dimension, and combines the number of the most recent page frame locking failures to establish a memory access pre-access behavior vector. Extract the byte span of the most recent access requests (e.g., from 0x1000 to 0x5000, with a span change of 16KB). Map the interval values ​​(5ms, 10ms, 15ms) to the time dimension using an exponential weighted average algorithm to obtain the time urgency feature value. Map the address coverage difference (0) and the byte span change value of the most recent access requests (16KB) to the spatial dimension. Combine this with the number of the most recent page frame locking failures (2 times) to construct a vector structure containing three-dimensional data of [time urgency, spatial span, locking conflict], and establish a memory access pre-action vector.

[0033] The priority calculation submodule deconstructs the memory access pre-access behavior vector to obtain multi-dimensional components, and detects in real time the queuing depth of the current bus arbitration queue, the historical cache hit rate of the target memory page, and the remaining bus bandwidth, using the formula: ; Obtain priority control values ​​through computation; in, This represents the priority control quantity. This represents the number of times the page frame has most recently failed to lock, as counted by a counter. This represents the queuing depth of the bus arbitration queue, obtained by reading the arbitrator status register. This represents the normalized coefficient calculated based on the ratio of the change in byte span between the two most recent access requests to the maximum transmission unit. This represents the normalized coefficient calculated based on the ratio of the difference in target page address segment coverage to the standard page frame size. This represents the normalized coefficient calculated based on the ratio of the time interval between the three most recent shared page accesses to the system time base. This represents the historical cache hit rate of the target memory page, obtained by querying the cache controller statistics. This represents the normalized value of the system bus clock cycle obtained by collecting the real-time clock cycle and comparing it with the reference cycle. This represents the normalized value of the system's remaining bus bandwidth, obtained by monitoring the remaining bandwidth and dividing it by the maximum bus capacity.

[0034] Real-time monitoring of the current bus arbitration queue depth (e.g., 5 requests), the historical cache hit rate of the target memory page (e.g., 80%), and the remaining bus bandwidth (e.g., 30GB / s) is performed using the following formula: ; The priority control value is obtained through calculation. The calculation logic and meaning of each parameter in the formula are as follows: This represents the priority control value; the higher the value, the higher the priority in preempting the bus. This represents the number of times the page frame was last locked, as counted by a counter; it is set to 3. The queue depth of the bus arbitration queue obtained by reading the arbitrator status register is set to 12; the product of the two (36) reflects the degree of congestion in resource competition. The more severe the congestion, the more urgent it is to raise the priority to avoid starvation. The normalization factor, calculated as 0.25, represents the ratio of the byte span change (e.g., 16KB) between the two most recent access requests to the maximum transfer unit (e.g., 64KB). The normalization coefficient, calculated as the ratio of the target page address segment coverage difference (e.g., 0) to the standard page frame size, is set to 0. This reflects the spatial mutability of the access pattern; the larger the mutation, the faster the processing needs to be; the square root operation of the numerator part ( This is used to smooth out the effects of congestion factors; The normalization coefficient, calculated as 0.1, represents the ratio of the time interval between the three most recent shared page accesses (average 10ms) to the system time base (100ms). The historical cache hit rate of the target memory page, obtained by querying the cache controller statistics, is set to 0.9; the denominator ( This reflects temporal locality; the shorter the interval or the higher the hit rate (meaning the data may already be in the cache), the smaller the denominator, and the larger the overall score (Note: the logic here is that frequently accessed and highly hit hot data should receive extremely high priority to maintain the pipeline); the first part of the result is... ; The normalized value of the system bus clock cycle obtained by acquiring the real-time clock cycle (2ns) and comparing it with the reference cycle (1ns) is calculated as 2.0. The normalized value of the system's remaining bus bandwidth, obtained by monitoring the remaining bandwidth (30GB / s) and dividing it by the maximum bus capacity (100GB / s), is calculated to be 0.3; Part Two ( As a penalty, the lower the bandwidth or the slower the clock speed, the lower the priority should be to prevent bus congestion; the final calculation yields... This result indicates that the current request has extremely high access urgency, and a priority control variable is generated.

[0035] Please see Figure 2 and Figure 6 Access to the arbitration sorting module includes: The request sorting queue submodule, based on the value of the priority control quantity, traverses the backlog of access requests in the current buffer, binds the handle of each request to the corresponding priority value as a tuple object, sorts the tuple objects in descending order, and reassembles the request handle queue according to the sorted order to ensure that high-priority requests occupy the bus arbitration bit first, generating an ordered access request sequence. For example, if request A is 60.22, request B is 45.10, and request C is 55.30, iterate through the backlog of access requests in the current buffer, and bind the handle ID of each request to a tuple object with its corresponding priority value (e.g., ...).<ID_A,60.22> The tuple objects are sorted in descending order using the Quick Sort algorithm, resulting in RequestA -> Request C -> Request B. The request handle queue is then reorganized according to the sorted order to ensure that high-priority requests occupy the bus arbitration bit first, generating an ordered access request sequence.

[0036] The address mapping execution submodule calls the memory page block granularity configuration parameters to obtain the physical page frame segmentation size and alignment mask, extracts the virtual target address from the ordered access request sequence, performs bitwise operations to separate the page number and the page offset, maps the virtual page number to the corresponding physical base address according to the segmentation size, writes read / write permission bits and existence bits to the mapping table, and generates a physical page frame mapping index. Obtain the physical page frame segment size (3.2MB) and alignment mask. Extract the virtual target address (e.g., 0x7F000000) sequentially from the first position of the ordered access request sequence. Perform a right shift operation (Shift Right 21 bits) to separate the virtual page number (VPN). Based on the segment size, search for contiguous free blocks in the physical memory pool. Map the virtual page number to the corresponding physical base address (e.g., 0x20000000). Write the read / write permission bit (RW=1) and the presence bit flag (P=1) to the control bit field of the page table. Establish a virtual address to physical address translation entry and generate a physical page frame mapping index.

[0037] The frequency statistics chain building module locks the corresponding memory region based on the physical page frame mapping index, starts the hardware performance monitoring unit to collect the read and write instruction trigger signals within a unit of time after mapping, counts the cumulative access operation count for each index entry, dynamically allocates memory space for each accessed page frame, creates a statistics node, writes the physical base address and cumulative access operation count into the node data field, connects all nodes using pointers, and establishes a shared page access frequency linked list. Based on the memory region (a 3.2MB region starting from physical address 0x20000000), the access counter in the hardware performance monitoring unit (PMU) is started, and the read and write instruction trigger signals within a unit of time (e.g., 1 second) after the mapping region are collected. The cumulative access operation count corresponding to the index entry is counted as 1500 times. A structure memory space is dynamically allocated in the kernel heap area for each accessed page frame, and a statistical node is created. The physical base address (0x20000000) and the cumulative access operation count (1500) are written into the node data field. The node is connected to other existing statistical nodes in the system using a doubly linked list pointer to generate a shared page access frequency linked list.

[0038] Please see Figure 2 and Figure 7 The cold zone identification and recycling module includes: The access average statistics submodule traverses the shared page access frequency linked list, visits each node in turn and extracts the stored access timestamp sequence, sets the time span parameter of the sliding window, extracts the most recent continuous access record falling into the current window on the time axis, calculates the time difference between two adjacent access events, performs an arithmetic average operation on the extracted time difference, eliminates the numerical jitter caused by a single random access, and generates the access period sliding average. Each node is visited sequentially, and the most recent 50 timestamp sequences of visits are extracted. The time span parameter of the sliding window is set to 200ms. The most recent continuous access record (e.g., containing 20 visits) that falls within the current window is extracted on the time axis. The time difference between two adjacent access events (e.g., 10ms, 8ms, 12ms, etc.) is calculated. The arithmetic mean of the extracted 19 time differences is calculated to obtain an average interval of 10ms. This eliminates the numerical jitter caused by a single random access and generates a sliding mean of the access period.

[0039] The heat decay determination submodule calls the access cycle moving average, reads the corresponding historical average data from the database, performs subtraction and takes the absolute value to obtain the access heat offset, compares the offset with the preset offset determination threshold, calculates the change gradient of the access cycle moving average in the continuous period, confirms that there is no rebound trend, and if the determination condition is met, locks the corresponding memory page physical page frame number and generates the cold zone determination index address. The specific method for setting the offset judgment threshold is as follows: retrieve the distribution data of the historical average within a preset long period, calculate the standard deviation of the distribution data to quantify the dispersion of historical access fluctuations, and use it as the basic fluctuation tolerance. Collect the current global free memory page frame ratio in real time, construct a dynamic adjustment coefficient that is positively correlated with the free memory page frame ratio, and perform a multiplication operation between the basic fluctuation tolerance and the dynamic adjustment coefficient to obtain the offset judgment threshold. Call the access cycle moving average (10ms), read the historical average data corresponding to this memory page from the database (e.g., 5ms, indicating more frequent access in the past), perform subtraction and take the absolute value. The process involves obtaining the access frequency offset (5ms), comparing it with a preset offset threshold (e.g., 4ms), and determining if 5ms > 4ms. This indicates a significant decrease in access frequency. Further calculations are made of the first derivative (gradient of change) of the moving average of access cycles over three consecutive cycles. If the gradient value is greater than or equal to 0, it confirms no rebound trend, meets the cold zone determination criteria, locks the corresponding physical page frame number of the memory page, and generates a cold zone determination index address. The specific method for setting the "offset threshold" is as follows: Historical average distribution data within a preset long period (24 hours) is retrieved, and the standard deviation of the distribution data (e.g., 1.5ms) is calculated to quantify the dispersion of historical access fluctuations, serving as the basic fluctuation tolerance. The current global free memory page frame ratio (e.g., 10%) is collected in real-time, and a dynamic adjustment coefficient positively correlated with the free memory page frame ratio is constructed (the calculation formula is...). ,Right now The base fluctuation tolerance (1.5ms) is multiplied by the dynamic adjustment coefficient (2.0). (This is just an example; the previous example used 4ms, but if we follow this example, it would be 3ms. This shows that the threshold is dynamically calculated.) This gives us the offset determination threshold.

[0040] The mapping pointer injection submodule addresses the corresponding page table entry based on the cold zone determination index address, requests the target storage space for data migration, obtains the target reclamation area address, generates a space reuse status flag to identify page availability and a read / write permission reset bit to block illegal writing, performs bit concatenation operation on the three data items and writes them into the reserved field of the page table entry, completes the address redirection, and generates a remapped pointer.

[0041] The corresponding page table entry (PTE) is located through a multi-level page table addressing mechanism. Target storage space for data migration is requested in the disk swap partition. The target reclaimed area address (e.g., Swap Offset0x0000AB) is obtained. A space reuse status flag (Bit 0 = 0, indicating physical memory is unavailable) is generated to identify page availability, and a read / write permission reset bit (Bit 1 = 0, indicating read-only or access prohibited) is generated to block illegal writes. The target reclaimed area address, space reuse status flag, and read / write permission reset bit are concatenated. The concatenated data is written to the reserved field of the page table entry, completing the address redirection and generating a remapping pointer.

[0042] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0043] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0044] It should be understood that, in various embodiments of the present invention, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0045] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0046] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0047] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0048] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0049] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0050] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0051] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of protection of the described technical solutions.

Claims

1. A terminal group memory sharing management system characterized by comprising: The system includes: The computing power intensity identification module collects the number of tasks completed by the terminal per unit time and the instruction delay value, maps the number of tasks completed per unit time and the instruction delay value to a preset processing threshold range, and generates a computing power level range identification. The quota granularity control module extracts the mapped memory page block size based on the computing power level range identifier, calculates the quotient of the computing power level range identifier and the load weight ratio, and if the quotient is within the preset allowable expansion range, determines the quota upper limit adjustment coefficient and generates memory page block granularity configuration parameters. The intent priority module monitors access requests initiated by the terminal, extracts shared page access interval, coverage difference, byte span change and lock failure number, combines shared page access interval, coverage difference, byte span change and lock failure number to construct memory access pre-behavior vector, calculates the weighted memory access pre-behavior vector and generates priority control quantity; The arbitration sorting module is accessed to sort access requests in descending order according to the priority control quantity. The memory page block granularity configuration parameters are called to map physical addresses, the number of accesses per unit time is recorded, and a shared page access frequency linked list is established.

2. The terminal group memory sharing management system according to claim 1, wherein The computing power level range identifier includes performance level mapping code, computing power threshold range boundary and heterogeneous terminal capability label. The memory page block granularity configuration parameters include physical page frame size setting value, maximum allowed mapping range and granularity dynamic scaling factor. The priority control quantity includes access urgency comprehensive score, arbitration queue sorting index and resource preemption weight threshold. The shared page access frequency linked list includes memory page physical address node, unit time access counter and heat statistics timestamp.

3. The terminal group memory sharing management system according to claim 2, characterized in that, The computing power intensity identification module includes: The performance data aggregation submodule collects the number of tasks completed per unit time and the instruction latency value for each terminal within a preset time window, calculates the reciprocal of the average instruction execution latency value, obtains the instruction response frequency factor, performs a weighted multiplication operation on the number of tasks completed per unit time and the instruction response frequency factor to obtain the instantaneous value of instruction throughput performance, calls the pre-stored terminal hardware baseline parameters to perform a division operation on the instantaneous value of instruction throughput performance to complete the numerical normalization process, and smooths the normalized values ​​of multiple consecutive sampling points through a moving average algorithm to generate a normalized evaluation value of terminal performance. The threshold interval matching submodule calls the terminal performance normalization evaluation value, traverses the preset processing threshold intervals stored in the configuration unit, extracts the lower boundary value and upper boundary value corresponding to each interval in turn, executes the value comparison logic, and determines whether the terminal performance normalization evaluation value is greater than or equal to the lower boundary value and less than the upper boundary value. When the judgment condition is met, the current interval position is locked, the computing power level definition metadata associated with the interval is read, and the interval sequence number and computing power level definition metadata are concatenated and formatted to assemble the fields to establish a computing power level mapping index key. The identifier encoding generation submodule retrieves the corresponding level feature code from the computing power level definition table based on the computing power level mapping index key, extracts the device type identification code and memory bus bandwidth parameters of the current terminal, converts the computing power level mapping index key into the corresponding binary feature vector, combines the level feature code, device type identification code and binary feature vector into a data frame according to the preset displacement rules, performs cyclic redundancy check calculation on the combined data frame to add integrity check bits, and generates a computing power level range identifier.

4. The terminal group memory sharing management system according to claim 3, characterized in that, The specific process for setting the processing threshold interval is as follows: by statistically analyzing the sample set of normalized evaluation values ​​of terminal performance reported by all active terminals within the historical operating cycle, outliers in the sample set are removed using box plot analysis. The cleaned sample data is then sorted in ascending order, and the cumulative distribution function of the sample sequence is calculated. Based on the preset number of computing power grading granularities, multiple key quantile values ​​corresponding to the cumulative distribution function curve are extracted at equal intervals. The values ​​of two adjacent quantiles are respectively established as the lower limit and upper limit of the interval, thus constructing multiple continuous and non-overlapping numerical ranges as the processing threshold interval.

5. The terminal group memory sharing management system according to claim 4, characterized in that, The quota granularity control module includes: The baseline page block extraction submodule retrieves the kernel's preset memory mapping specification table based on the computing power level interval identifier, matches the physical page frame segmentation standard corresponding to the performance level to which the identifier belongs, obtains the baseline size of the mapped page block, extracts the computing power intensity feature field from the computing power level interval identifier, calls the base conversion instruction to convert the feature field into a double-precision floating-point computing power level quantization value, and stores the size and value into a temporary register. The expansion coefficient determination submodule monitors the task scheduling queue depth and the number of active processing units on the bus in real time, calculates the ratio of the two to obtain the current load weight ratio, performs a division operation between the computing power level quantification value and the current load weight ratio to obtain the load adaptability quotient, compares the load adaptability quotient with the boundary value of the preset allowable expansion range, and if it is determined that the load adaptability quotient falls within the range, calls the preset segmented mapping function to calculate the corresponding gain value and generates the quota upper limit adjustment coefficient. The parameter encapsulation generation submodule performs a weighted multiplication operation based on the mapped page block base size and quota upper limit adjustment coefficient to calculate the dynamic mapping granularity value. It then calls a preset memory address alignment verification algorithm to perform a binary bitmasking operation on the dynamic mapping granularity value, extracts the maximum transfer unit limit value of the memory controller, and combines and encapsulates the aligned granularity value with the limit value to generate memory page block granularity configuration parameters.

6. The terminal group memory sharing management system according to claim 5, characterized in that, The intent priority module includes: The behavior measurement and organization submodule monitors the access requests initiated by each terminal, records the timestamps of the most recent shared page requests, calculates the interval value, compares the coverage of the target page address range to obtain the difference, and counts the number of the most recent page frame locking failures, generating a raw measurement set of memory access behavior. The pre-access behavior mapping submodule parses the original metric set of memory access behavior, extracts the byte span change value of the most recent multiple access requests, maps the interval value to the time dimension, maps the difference and the byte span change value of the most recent multiple access requests to the spatial dimension, and combines the number of the most recent page frame locking failures to establish a memory access pre-access behavior vector. The priority calculation submodule deconstructs the memory access pre-action vector to obtain multi-dimensional components, and detects in real time the queuing depth of the current bus arbitration queue, the historical cache hit rate of the target memory page, and the remaining bus bandwidth to calculate and obtain the priority control value.

7. The terminal group memory sharing management system according to claim 6, characterized in that, The access arbitration sorting module includes: The request sorting queue submodule, based on the value of the priority control quantity, traverses the backlog of access requests in the current buffer, binds the handle of each request to the corresponding priority value as a tuple object, sorts the tuple objects in descending order, and reassembles the request handle queue according to the sorted order to generate an ordered access request sequence. The address mapping execution submodule calls the memory page block granularity configuration parameters to obtain the physical page frame segmentation size and alignment mask, extracts the virtual target address from the ordered access request sequence in sequence, performs bit shifting operations to separate the page number and the page offset, maps the virtual page number to the corresponding physical base address according to the segmentation size, and writes read / write permission bits and existence bits to the mapping table to generate a physical page frame mapping index. The frequency statistics linking module locks the corresponding memory region based on the physical page frame mapping index, starts the hardware performance monitoring unit to collect the read and write instruction trigger signals within a unit of time after mapping, counts the cumulative access operation count for each index entry, dynamically allocates memory space for each accessed page frame, creates a statistics node, writes the physical base address and cumulative access operation count into the node data field, connects all nodes using pointers, and establishes a shared page access frequency linked list.

8. The terminal group memory sharing management system according to claim 7, characterized in that, The system also includes: The cold zone identification and recycling module traverses the shared page access frequency linked list, calculates the average access period of the sliding time window, and calculates the absolute value of the difference between the average access period and the historical average as the offset. If the offset exceeds the offset judgment threshold and there is no rebound, a remapping pointer is obtained. The remapping pointer includes the target reclaimed area address, space reuse status flag, and read / write permission reset bit.

9. The terminal group memory sharing management system according to claim 8, characterized in that, The cold zone identification and recycling module includes: The access average statistics submodule traverses the shared page access frequency linked list, accesses each node in turn and extracts the stored access timestamp sequence, sets the time span parameter of the sliding window, extracts the most recent continuous access record falling into the current window on the time axis, calculates the time difference between two adjacent access events, performs an arithmetic average operation on the extracted time difference, and generates the access period sliding average. The heat decay determination submodule calls the access cycle moving average, reads the corresponding historical average data from the database, performs subtraction and takes the absolute value to obtain the access heat offset, compares the offset with the preset offset determination threshold, calculates the change gradient of the access cycle moving average in the continuous cycle, confirms that there is no rebound trend, and if the determination condition is met, locks the corresponding memory page physical page frame number and generates the cold zone determination index address. The mapping pointer injection submodule addresses the corresponding page table entry based on the cold zone determination index address, requests the target storage space for data migration, obtains the target reclamation area address, generates a space reuse status flag to identify page availability and a read / write permission reset bit to block illegal writing, performs bit concatenation operation on the three data items and writes them into the reserved field of the page table entry, completes the address redirection, and generates a remapping pointer.

10. The terminal group memory sharing management system according to claim 9, characterized in that, The specific method for setting the offset judgment threshold is as follows: retrieve the distribution data of the historical average within a preset long period, calculate the standard deviation of the distribution data to quantify the dispersion of historical access fluctuations, and use it as the basic fluctuation tolerance. Collect the current global free memory page frame ratio in real time, construct a dynamic adjustment coefficient that is positively correlated with the free memory page frame ratio, and perform a multiplication operation between the basic fluctuation tolerance and the dynamic adjustment coefficient to obtain the offset judgment threshold.

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