Automatic testing method based on self-learning and coverage rate evaluation

Abstract

The invention relates to the technical field of function testing, and particularly discloses an automatic testing method based on self-learning and coverage rate evaluation, comprising the following steps: S1, acquiring DUT design parameters and ATE hardware parameters; s2, judging whether the DUT is normal or not, and determining whether normalization processing is carried out or not according to a result; s3, integrating the normalized values into a unified input vector, inputting the unified input vector into a deep reinforcement learning model, and presetting a weight ratio of coverage rate related features; and S4, presetting a current fault coverage rate target, calculating a path prediction value and a time sequence prediction value, adjusting a weight ratio of corresponding features, regenerating a unified input vector, and judging whether iteration is stopped or not. According to the method, redundancy is reduced through parameter matching verification and normalization, cost is reduced, efficiency is improved, coverage rate is predicted based on a reinforcement learning model, yield and reliability are improved, and strategy self-optimization is realized through weight iteration to adapt to various DUTs; testing is promoted to be converted into intelligent driving, and long-term efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of functional testing technology, and more specifically to an automated testing method based on self-learning and coverage assessment. Background Technology

[0002] With the rapid development of the semiconductor industry, the integration and functional complexity of devices under test (DUTs) such as MCU chips are constantly increasing, placing higher demands on the accuracy, efficiency, and coverage of automated test equipment (ATE). As the core equipment for chip mass production verification and quality control, the testing performance of ATE directly determines chip yield and reliability. In high-end application fields such as automotive electronics and consumer electronics, the requirements for test coverage are particularly stringent, necessitating efficient testing strategies.

[0003] Existing ATE testing methods generally suffer from significant technical bottlenecks: First, the matching of test parameters lacks pre-verification, and the direct use of fixed test vectors for testing can easily lead to test distortion or invalidity due to incompatibility between DUT design parameters and ATE hardware parameters; second, test vector generation lacks intelligent support and fails to combine parameter characteristics for precise optimization, resulting in large redundancy and insufficient targeting, leading to low testing efficiency; third, coverage assessment and test strategy optimization are disconnected, making it impossible to dynamically adjust test parameters based on real-time predicted coverage, making it difficult to ensure comprehensive test coverage and easily overlooking potential faults.

[0004] The aforementioned shortcomings make it difficult for existing testing methods to balance testing efficiency and coverage, resulting in high testing costs and an inability to meet the testing needs of complex DUTs. Therefore, developing an ATE testing method that can achieve precise parameter matching, intelligent test vector generation, and dynamic coverage optimization, by integrating the parameter characteristics of DUTs and ATEs and introducing intelligent models to achieve self-iterative testing strategies, has become an urgent technical problem to be solved in the current semiconductor testing field. Summary of the Invention

[0005] The purpose of this invention is to provide an automated testing method based on self-learning and coverage evaluation to solve the above-mentioned technical problems.

[0006] The objective of this invention can be achieved through the following technical solutions: An automated testing method based on self-learning and coverage evaluation includes the following steps: S1: Obtain the DUT design parameters and ATE hardware parameters. The DUT design parameters include the maximum clock frequency f and the number of functional modules G. The ATE hardware parameters include the number of channels C and the sampling rate F. S2: If the maximum clock frequency f of the DUT is less than or equal to Fm and the number of functional modules of the DUT is less than or equal to C, then it is considered normal; otherwise, it is considered abnormal. If it is marked as normal, then continuous parameter normalization is performed, including the following steps: Obtain the clock frequency range [f_min, f_max] of the MCU chip, and calculate the normalized value f_norm corresponding to the maximum clock frequency = (f_now - f_min) / (f_max - f_min), where f_now represents the current clock frequency of the MCU chip; similarly, obtain the normalized value F_norm corresponding to the ATE sampling rate. S3: Integrate the obtained normalized values ​​f_norm and F_norm into a unified input vector [f_norm, F_norm]; Input a unified input vector [f_norm, F_norm] into the deep reinforcement learning model, and pre-set the weight ratio γ of the coverage-related features in the deep reinforcement learning model; S4: Preset the target fault coverage C_fault for this operation; Obtain the number of fault-sensitive paths n and the total number of fault paths N that can be triggered by the unified input vector [f_norm, F_norm], and calculate the path prediction value C_fault_pred=n / N; Obtain the time series range t and total time series range T that can be covered by the unified input vector [f_norm, F_norm], and calculate the time series prediction value C_timing_pred=t / T; If the predicted value is less than the fault coverage target C_fault, adjust the weight ratio γ of the corresponding feature in the deep reinforcement learning model to 1.5 times the original weight ratio, regenerate a unified input vector, and stop iterating when all predicted values ​​are greater than C_fault.

[0007] As a further aspect of the present invention: in step S4, a new unified input vector is generated to replace the vector with the lowest concentrated prediction value in the original unified input vector, ensuring that the overall number of unified input vectors remains unchanged.

[0008] As a further aspect of the present invention: in step S2, when the ATE test is marked as abnormal, the MCN chip is recorded as an invalid chip and is removed from subsequent operations.

[0009] As a further aspect of the present invention: in step S2, when obtaining the clock frequency range of the MCU chip, the MCU chip is powered by the rated voltage.

[0010] As a further aspect of the present invention: in step S4, the unified input vector that cannot trigger the core functional module of the DUT is recorded as an invalid vector, and the invalid vector is removed and does not participate in the iteration process.

[0011] As a further aspect of the present invention: in step S1, if there is a unified input vector that does not match the interface protocol, it is directly eliminated.

[0012] As a further aspect of the present invention: in step S3, when the weight ratio γ of the coverage-related features in the deep reinforcement learning model is preset, the value of the weight ratio γ is ensured to be greater than or equal to 50%.

[0013] As a further aspect of the present invention: when there are equal vectors in the original unified input vector, the unified input vector generated earlier is preferentially replaced.

[0014] The beneficial effects of this invention are as follows: The testing method of this invention significantly overcomes the shortcomings of traditional ATE systems, such as test redundancy, insufficient coverage, poor adaptability, and inadequate data utilization, and has multiple beneficial effects. First, by first verifying the matching between the DUT design parameters and the ATE hardware parameters, invalid tests caused by hardware incompatibility are avoided. Combined with parameter normalization processing, the adaptability of input data is improved, laying the foundation for subsequent accurate testing, effectively reducing redundant test vectors, shortening test time, and reducing test costs. Second, relying on a deep reinforcement learning model, key normalized parameters are integrated to generate input vectors. Coverage is predicted by combining fault-sensitive paths and timing ranges, ensuring test targeting, significantly improving fault coverage, reducing potential defect omissions, and significantly improving chip yield and reliability. Third, through an iterative mechanism that dynamically adjusts the model feature weight ratio, the test strategy achieves self-learning optimization, which can adapt to DUTs with different clock frequencies and the number of functional modules, solving the drawbacks of fixed traditional test processes. Fourth, construct a closed-loop mechanism for parameter acquisition, normalization, prediction, and optimization to fully explore the value of test data, promote the transformation of the testing process from experience-driven to data intelligence-driven, and improve the intelligence level and long-term testing efficiency of the ATE system. Attached Figure Description

[0015] The invention will now be further described with reference to the accompanying drawings.

[0016] Figure 1 This is a flowchart illustrating an automated testing method based on self-learning and coverage assessment according to the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Please see Figure 1As shown, this invention is an automated testing method based on self-learning and coverage evaluation, comprising the following steps: S1: Obtain the DUT design parameters and ATE hardware parameters. The DUT design parameters include the maximum clock frequency f and the number of functional modules G. The ATE hardware parameters include the number of channels C and the sampling rate F. S2: If the maximum clock frequency f of the DUT is less than or equal to Fm and the number of functional modules of the DUT is less than or equal to C, then it is considered normal; otherwise, it is considered abnormal. If it is marked as normal, then continuous parameter normalization is performed, including the following steps: Obtain the clock frequency range [f_min, f_max] of the MCU chip, and calculate the normalized value f_norm corresponding to the maximum clock frequency = (f_now - f_min) / (f_max - f_min), where f_now represents the current clock frequency of the MCU chip; similarly, obtain the normalized value F_norm corresponding to the ATE sampling rate. S3: Integrate the obtained normalized values ​​f_norm and F_norm into a unified input vector [f_norm, F_norm]; Input a unified input vector [f_norm, F_norm] into the deep reinforcement learning model, and pre-set the weight ratio γ of the coverage-related features in the deep reinforcement learning model; S4: Preset the target fault coverage C_fault for this operation; Obtain the number of fault-sensitive paths n and the total number of fault paths N that can be triggered by the unified input vector [f_norm, F_norm], and calculate the path prediction value C_fault_pred=n / N; Obtain the time series range t and total time series range T that can be covered by the unified input vector [f_norm, F_norm], and calculate the time series prediction value C_timing_pred=t / T; If the predicted value is less than the fault coverage target C_fault, adjust the weight ratio γ of the corresponding feature in the deep reinforcement learning model to 1.5 times the original weight ratio, regenerate a unified input vector, and stop iterating when all predicted values ​​are greater than C_fault.

[0019] It is important to note that obtaining the design parameters of the Device Under Test (DUT) and the hardware parameters of the Automated Test Equipment (ATE) is crucial. This step provides core data support for subsequent test strategy formulation, hardware compatibility verification, and intelligent test vector generation, serving as a prerequisite for ensuring test accuracy, safety, and efficiency. The core DUT design parameters include the maximum clock frequency *f* and the number of functional modules *G*. The maximum clock frequency *f* represents the highest clock signal frequency the DUT can withstand during normal operation, directly determining the parameter thresholds of the clock excitation signal during testing. The number of functional modules *G* reflects the scale of the core functional units within the DUT and is a key basis for planning test channel allocation and test process breakdown. Key ATE hardware parameters include the number of channels *C* and the sampling rate *F*. The number of channels *C* determines the number of DUT test pins the ATE can simultaneously connect to, directly affecting parallel testing capabilities and efficiency. The sampling rate *F* represents the ATE's acquisition accuracy and response speed of the DUT output signal and must match the DUT clock frequency to ensure signal acquisition integrity.

[0020] First, the accuracy of parameter sources is crucial. DUT design parameters should be extracted primarily from official design documents, chip datasheets, and design verification reports. If necessary, confirmation with the design team is required to avoid test plan failures due to parameter deviations. Second, ATE hardware parameters must be obtained comprehensively from equipment calibration reports, hardware configuration lists, and real-time self-test data. Simultaneously, the actual parameter values ​​under the current operating state of the equipment should be recorded to eliminate parameter drift caused by factors such as equipment aging and environmental interference. Third, for batch testing scenarios, the design parameters of the same batch of DUTs need to be sampled and verified, and the ATE hardware parameters need to be periodically checked to ensure parameter consistency and stability, avoiding the impact of individual differences or equipment fluctuations on the overall test results.

[0021] After acquiring the DUT design parameters and ATE hardware parameters, a hardware compatibility check is performed first. If the maximum clock frequency f of the DUT is less than or equal to the maximum sampling frequency threshold Fm supported by the ATE equipment, and the number of functional modules G of the DUT is less than or equal to the number of effective channels C of the ATE, then the test combination is marked as normal; otherwise, if any condition is not met, it is marked as abnormal. This check is a crucial pre-verification to ensure test feasibility, preventing problems such as test signal distortion and insufficient test channels to fully cover functional modules due to hardware performance mismatch, avoiding the initiation of invalid test processes, and thus reducing test resource waste and equipment wear. Fm is the upper limit of the stable sampling frequency determined after ATE equipment calibration. It must be accurately determined based on the equipment technical manual and recent calibration report, and the theoretical nominal value should not be used directly to prevent misjudgment due to equipment aging or changes in environmental temperature and humidity leading to a decrease in actual sampling capability.

[0022] Retrieve the official technical specifications of the same model MCU chip and extract its rated operating clock frequency range [f_min, f_max], where f_min is the minimum clock frequency for stable chip operation and f_max is the maximum operating clock frequency. Then, using the actual maximum clock frequency of the MCU chip under test as f_now, calculate the normalized clock frequency value f_norm = (f_now - f_min) / (f_max - f_min) using the normalization formula, ensuring f_norm is within the [0,1] interval, thus visually reflecting the relative level of the current chip's clock frequency within the rated range. Using the same logic to process the ATE sampling rate parameters, first determine the effective sampling rate range [F_min, F_max] of the ATE device. Extract the actual sampling rate of the ATE under the current test conditions as F_now, and calculate the normalized sampling rate value F_norm = (F_now - F_min) / (F_max - F_min). It should be noted that the parameter range extraction should be based on the official authoritative document. If there are batch differences, additional sampling verification is required to ensure the consistency of the normalization benchmark. At the same time, at least 4 decimal places should be retained during the calculation process to avoid the loss of precision affecting the subsequent model prediction effect.

[0023] After normalizing the clock frequency and sampling rate, the resulting normalized values ​​f_norm and F_norm are integrated into a unified input vector [f_norm, F_norm] in a fixed-dimensional order. The core purpose of this integration step is to achieve structured encapsulation of these two key parameters, eliminating the interference of parameter discreteness on the model input, reducing the complexity of model data processing, and making the input information more consistent with the input format requirements of deep reinforcement learning models. The unified input vector, as the core carrier connecting parameter preprocessing and model decision-making, can accurately convey the matching relationship between the current DUT clock characteristics and ATE sampling capabilities, providing core data support for the model's subsequent prediction of test coverage and generation of optimized test strategies.

[0024] The unified input vector [f_norm, F_norm] is then input into a pre-defined deep reinforcement learning model, along with a pre-defined weight γ for coverage-related features. The weight γ must be scientifically planned based on the testing objectives and chip characteristics, prioritizing features corresponding to core evaluation metrics such as fault coverage and time-series coverage. Initial values ​​can be determined by referencing historical test data and model training experience from similar chips to ensure that coverage-related features dominate model decisions. It is crucial that the dimensional order of the input vector strictly matches the input format used during model training to avoid model prediction failures due to dimensional inconsistencies. Furthermore, the initial weight γ settings must be recorded and archived to provide a benchmark for dynamic adjustments based on test results, ensuring the traceability and controllability of the model optimization process.

[0025] Set a target fault coverage rate, C_fault, for this test. This value is not fixed. For example, for chips used in high-end fields such as automotive electronics and aerospace, it is recommended to set C_fault to no less than 99%; for low-to-mid-range consumer electronics chips, it can be set between 95% and 98% depending on the cost and performance balance requirements. At the same time, the C_fault setting should allow for reasonable redundancy to avoid the actual coverage rate falling short of expectations due to objective factors such as fluctuations in the test environment and deviations in equipment accuracy. After setting, it should be included in the test plan archive as a core benchmark for subsequent coverage evaluation.

[0026] Based on the unified input vector [f_norm, F_norm] generated earlier, the feature extraction module of the deep reinforcement learning model obtains the number of fault-sensitive paths n and the total number of fault paths N corresponding to this input vector. Fault-sensitive paths refer to critical signal transmission paths prone to logical errors, timing violations, and other faults, requiring accurate identification based on timing constraints in the DUT design drawings and fault simulation reports. The total number of fault paths N covers all paths within the DUT that may experience faults. Subsequently, the path prediction value C_fault_pred = n / N is calculated using the formula. This value directly reflects the coverage capability of the test strategy corresponding to the current input vector for fault-sensitive paths.

[0027] The timing range t and total timing range T of the DUT that can be covered by the unified input vector are obtained simultaneously. The timing range coverage needs to take into account normal working timing, extreme timing and edge timing conditions. The total timing range T is determined based on parameters such as the DUT clock frequency range and the response delay of functional modules. The timing prediction value is calculated by the formula C_timing_pred=t / T to evaluate the coverage effect of the test strategy on timing-related faults.

[0028] After calculating the two predicted values, C_fault_pred and C_timing_pred are compared with the preset target C_fault. If either predicted value is less than C_fault, it indicates that the coverage of the current test strategy has not met the requirements. The weight γ of the corresponding feature in the deep reinforcement learning model must be immediately adjusted to 1.5 times the original weight. Specifically, if the path prediction value is substandard, the weights of the fault path-related features are adjusted; if the time-series prediction value is substandard, the weights of the time-series-related features are adjusted. After the weight adjustment, a unified input vector is regenerated, and the above prediction calculation process is repeated until both C_fault_pred and C_timing_pred are greater than C_fault, at which point the iteration stops. It is important to record the weight adjustment value, input vector, and prediction result for each iteration to ensure traceability of the optimization process. Furthermore, the upper limit of the weight adjustment should be controlled within 3 times the original weight to avoid over-adjustment that could lead to model convergence failure.

[0029] In another preferred embodiment of the present invention, a new unified input vector is generated to replace the vector with the lowest concentrated prediction value in the original unified input vector, so as to ensure that the overall number of unified input vectors remains unchanged.

[0030] It's worth noting that by selecting the vector with the lowest predicted value from the current input vector set and directly replacing it with a newly generated vector, the overall size of the input vector set remains constant. This replacement rule accurately eliminates invalid vectors that contribute little to coverage, avoiding a decrease in model computational efficiency due to the expansion of the vector set. Simultaneously, it selectively strengthens the proportion of high-value input features, accelerating model iteration and convergence. During the replacement process, the parameter information and predicted value data of the replaced vector must be recorded simultaneously.

[0031] In another preferred embodiment of the present invention, when the ATE test is marked as abnormal, the MCN chip is recorded as an invalid chip and is removed from subsequent operations.

[0032] Understandably, when an ATE test is marked as abnormal based on compatibility criteria, it indicates that the maximum clock frequency of the MCU chip under test exceeds the maximum sampling frequency threshold supported by the ATE equipment, or the number of functional modules exceeds the number of effective ATE channels, meaning the hardware cannot meet the basic conditions for accurate testing. In this case, the MCU chip is directly marked as an invalid chip and must be immediately removed from all subsequent testing processes, including parameter normalization, model input, and coverage prediction. This prevents invalid chips from consuming test resources and reducing test efficiency, while also preventing erroneous test data caused by hardware incompatibility from interfering with the accuracy of the overall test results.

[0033] In another preferred embodiment of the present invention, when obtaining the clock frequency range of the MCU chip, the MCU chip is powered by the rated voltage.

[0034] It is important to note that when obtaining the clock frequency range of an MCU chip, the parameter extraction process must be based on the chip's rated operating voltage. The rated voltage is a core electrical indicator that ensures the stable operation of each functional module of the MCU chip; deviations from this voltage value will cause a shift in the actual clock frequency range that the chip can withstand.

[0035] In another preferred embodiment of the present invention, the unified input vector that cannot trigger the core functional module of the DUT is recorded as an invalid vector, and the invalid vector is removed and does not participate in the iteration process.

[0036] It should be noted that an invalid vector screening step needs to be added during the unified input vector generation and iterative optimization process. If a unified input vector [f_norm, F_norm] fails to trigger the core functional modules of the DUT after model validation, i.e., it cannot drive the core modules to complete the preset basic functions, this vector will be directly marked as invalid. Invalid vectors must be removed immediately to ensure that they do not participate in any subsequent processes such as coverage prediction, weight adjustment, and iterative optimization. This effectively eliminates redundant vectors that do not contribute to the test objective, avoids invalid vectors consuming model computing resources and slowing down iteration efficiency, and prevents them from interfering with the accuracy of coverage prediction results.

[0037] In another preferred embodiment of the present invention, if there is a unified input vector that does not match the interface protocol, it is directly eliminated.

[0038] Understandably, an interface protocol matching check needs to be added to the unified input vector validity verification process. If there is a unified input vector that does not match the DUT and ATE's preset interface protocol, it should be directly determined as an invalid vector and discarded, and will not participate in the subsequent coverage prediction and model iteration process. This avoids test command transmission failures due to protocol incompatibility and ensures the stability and reliability of the test process.

[0039] In another preferred embodiment of the present invention, when the weight ratio γ of coverage-related features in the deep reinforcement learning model is preset, the value of the weight ratio γ is ensured to be greater than or equal to 50%.

[0040] It is worth noting that the goal is to ensure that coverage-related features play a dominant role in the model decision-making process, and to avoid the model output deviating from the core objective of improving test coverage due to excessive weight of other secondary features.

[0041] The specific value of γ needs to be fine-tuned according to the requirements of the test scenario. For example, in the test scenario for high reliability chips, γ can be set between 60% and 70% to further enhance the priority of coverage features. In the test of conventional consumer chips, γ can be taken as a baseline value of 50% to balance test efficiency and coverage.

[0042] In a preferred embodiment, when there are equal vectors in the original unified input vector, the unified input vector generated earlier is preferentially replaced.

[0043] It's worth noting that this setup aims to ensure the timeliness of the input vector set and the targeted nature of iterative optimization, avoiding a decrease in model learning efficiency due to the retention of outdated vectors. Specifically, a unique timestamp needs to be added to each generated uniform input vector [f_norm, F_norm] to record the vector's generation time. When duplicate vector values ​​occur, the timestamp information of each duplicate vector is retrieved, and the vector with the earliest generation time is selected as the replacement target. The newly generated optimized vector directly replaces this outdated vector, while the remaining relatively new duplicate vectors are retained.

[0044] This approach effectively reduces the interference of redundant and outdated vectors on model training, ensuring that the input vector set always drives model iteration with the latest parameter features, improving the prediction accuracy and optimization efficiency of deep reinforcement learning models for test coverage, while maintaining a constant overall number of vectors to ensure the stability of subsequent iteration processes.

[0045] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. An automated testing method based on self-learning and coverage evaluation, characterized in that, Includes the following steps: S1: Obtain the DUT design parameters and ATE hardware parameters. The DUT design parameters include the maximum clock frequency f and the number of functional modules G. The ATE hardware parameters include the number of channels C and the sampling rate F. S2: If the maximum clock frequency f of the DUT is less than or equal to Fm and the number of functional modules of the DUT is less than or equal to C, then it is considered normal; otherwise, it is considered abnormal. If it is marked as normal, then continuous parameter normalization is performed, including the following steps: Obtain the clock frequency range [f_min, f_max] of the MCU chip, and calculate the normalized value f_norm corresponding to the maximum clock frequency = (f_now - f_min) / (f_max - f_min), where f_now represents the current clock frequency of the MCU chip; similarly, obtain the normalized value F_norm corresponding to the ATE sampling rate. S3: Integrate the obtained normalized values ​​f_norm and F_norm into a unified input vector [f_norm, F_norm]; Input a unified input vector [f_norm, F_norm] into the deep reinforcement learning model, and pre-set the weight ratio γ of the coverage-related features in the deep reinforcement learning model; S4: Preset the target fault coverage C_fault for this operation; Obtain the number of fault-sensitive paths n and the total number of fault paths N that can be triggered by the unified input vector [f_norm, F_norm], and calculate the path prediction value C_fault_pred=n / N; Obtain the time series range t and total time series range T that can be covered by the unified input vector [f_norm, F_norm], and calculate the time series prediction value C_timing_pred=t / T; If the predicted value is less than the fault coverage target C_fault, adjust the weight ratio γ of the corresponding feature in the deep reinforcement learning model to 1.5 times the original weight ratio, regenerate a unified input vector, and stop iterating when all predicted values ​​are greater than C_fault.

2. The automated testing method based on self-learning and coverage evaluation according to claim 1, characterized in that, In step S4, a new unified input vector is generated to replace the vector with the lowest predicted value in the original unified input vector, ensuring that the overall number of unified input vectors remains unchanged.

3. The automated testing method based on self-learning and coverage evaluation according to claim 1, characterized in that, In step S2, when the ATE test is marked as abnormal, the MCN chip is recorded as an invalid chip and is removed from subsequent operations.

4. The automated testing method based on self-learning and coverage evaluation according to claim 1, characterized in that, In step S2, when obtaining the clock frequency range of the MCU chip, the MCU chip is powered by the rated voltage.

5. The automated testing method based on self-learning and coverage evaluation according to claim 1, characterized in that, In step S4, the unified input vector that cannot trigger the core functional module of the DUT is recorded as an invalid vector, and the invalid vector is removed and does not participate in the iteration process.

6. The automated testing method based on self-learning and coverage evaluation according to claim 1, characterized in that, In step S1, if there is a unified input vector that does not match the interface protocol, it is directly discarded.

7. The automated testing method based on self-learning and coverage evaluation according to claim 1, characterized in that, In step S3, when presetting the weight ratio γ of coverage-related features in the deep reinforcement learning model, ensure that the value of the weight ratio γ is greater than or equal to 50%.

8. The automated testing method based on self-learning and coverage evaluation according to claim 2, characterized in that, When there are equal vectors in the original unified input vector, the unified input vector generated earlier will be replaced first.

Images