Reliable data link transmission method
By introducing a data packet acknowledgment handshake mechanism into the RGMII interface data link layer, the problem of data packet loss between the FPGA and the processor is solved, reliable data packet transmission is achieved, and the communication reliability of the system is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING INST OF COMP TECH & APPL
- Filing Date
- 2025-11-21
- Publication Date
- 2026-04-17
AI Technical Summary
In the RGMII interface communication between the FPGA and the processor, data packets cannot be received in time and are forced to be dropped due to the data flow blockage on the receiving side, resulting in packet loss at the link layer and affecting system reliability.
A handshake mechanism based on packet acknowledgment (ACK) is introduced into the data link layer of the RGMII interface. By implementing a lightweight link layer acknowledgment protocol between the FPGA and the processor, reliable transmission of each data packet is ensured.
This system enables reliable data packet transmission between the FPGA and the processor, avoiding packet loss issues caused by insufficient backend processing capabilities or delays, and improving the system's communication reliability.
Smart Images
Figure CN121880245A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of data transmission technology, and specifically relates to a reliable data link transmission method. Background Technology
[0002] Currently, Gigabit Ethernet data communication between FPGAs and processors commonly uses the RGMII interface. Internally, the standard implementation converts data into Axi-Stream or similar data stream formats via the RGMII interface logic before transmitting it to subsequent data processing modules. However, this existing approach has a serious drawback: when the backend data processing module cannot receive data in time due to congestion, insufficient processing power, or external memory access delays, the Stream channel between it and the RGMII interface becomes blocked. In this situation, the RGMII interface logic, lacking sufficient buffering or an effective backpressure mechanism, is forced to discard subsequent arriving packets after the receive FIFO is full, resulting in packet loss and severely impacting system reliability. Summary of the Invention
[0003] (a) Technical problems to be solved This invention aims to solve the core technical challenge of packet loss at the link layer in FPGA-based systems using the RGMII interface for communication. This is caused by data stream congestion on the receiving side, leading to data packets being dropped and unable to be received in time. Specifically, the receiving side lacks any mechanism to notify the sending side to pause transmission, causing the sending side to continue sending subsequent data packets at its inherent rate without being aware of the congestion, resulting in unreliable communication.
[0004] (II) Technical Solution To address the aforementioned technical problems, this invention provides a reliable data link transmission method. This method achieves reliable transmission of data packets between the FPGA and the processor through various logic modules within the FPGA. The method introduces a handshake mechanism based on data packet acknowledgment in the RGMII interface data link layer that communicates with the processor, thereby enabling reliable transmission of each data packet between the FPGA and the processor.
[0005] (III) Beneficial Effects This invention fundamentally solves the packet loss problem caused by backend Stream data stream blockage by introducing a handshake mechanism based on packet acknowledgment (ACK) in the RGMII interface data link layer that communicates with the processor, thus realizing reliable transmission of each data packet between the FPGA and the processor. Attached Figure Description
[0006] Figure 1This is a block diagram illustrating the implementation principle of the present invention; Figure 2 The sending flowchart of this invention Figure 3 This is a flowchart illustrating the receiving process implemented in this invention. Detailed Implementation
[0007] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0008] This invention provides a reliable data link transmission method to achieve reliable data packet transmission between an FPGA and a processor. The principle block diagram of the implementation is shown below. Figure 1 As shown, Figure 1 The document outlines the various logic modules implemented internally by the FPGA. The FPGA includes a data transmission logic module, a packet buffer and transmission logic module, a standard RGMII tx transmission logic module, a standard RGMIIrx transmission logic module, a receive FIFO and ACK generation logic module, and a data reception logic module. Among these: The data sending logic module is responsible for forwarding the data packet tx_data to be sent to the processor to the packet buffer and sending logic module. Packet caching and sending logic module (state machine): Responsible for caching data packets tx_data, sending the cached data packets tx_data to the standard RGMII tx sending logic module, and receiving the ACK response rx_ack corresponding to the sequence number of the data packet sent this time. If rx_ack is not received after a certain period of time when the cached data packet tx_data is sent to the processor, a timeout retransmission is initiated. If rx_ack is received, the next cached data packet is sent. Standard RGMII tx transmission logic module: Converts internal FPGA data into standard RGMII format data and sends it to the RGMII physical link; Standard RGMII rx transmission logic module: converts standard RGMII format data on the RGMII physical link into data internal to the FPGA; The FIFO and ACK generation logic module is responsible for receiving data packets rx_data and ACK responses rx_ack sent by the processor. Upon receiving the data packet rx_data, it generates an ACK response tx_ack with the corresponding sequence number and sends it to the standard RGMII tx logic module, and forwards the data packet rx_data to the data receiving logic module. Upon receiving the ACK response rx_ack from the processor, it directly passes it through to the packet buffer and sending logic module. Data receiving logic module: responsible for receiving data packets rx_data sent from the processor.
[0009] The flowchart of the sending process of the present invention is as follows: Figure 2 As shown, the data transmission logic module starts sending the data packet tx_data. After the packet buffer and transmission logic module buffers the data packet tx_data, it adds a sequence number to the data packet and sends it to the standard RGMII tx transmission logic module. At this time, it waits for the ACK response (rx_ack) with the corresponding sequence number sent by the processor at the other end. If the ACK response rx_ack with the corresponding sequence number is received, the current logic is closed, and the next data packet sent by the data transmission logic module is received, and a new sequence number is added before it is sent. If it is not received, it continues to wait for the ACK response rx_ack.
[0010] The flowchart of the receiving process of the present invention is as follows: Figure 3 As shown, when the standard RGMII rx sending logic module (RGMII interface) receives a data packet rx_data or an ACK response rx_ack, the receive FIFO and ACK generation logic module buffers this data packet rx_data or ACK response rx_ack. If an ACK response rx_ack is received from the peer, the packet buffer and sending logic module is notified to close the loop of data transmission containing the sequence number of this packet. If a data packet rx_data is received, an ACK response, i.e., an ACK reply packet tx_ack, is generated and logically sent to the peer through the standard RGMIIvtx sending logic module (RGMII interface). Then, the data packet rx_data is forwarded to the data receiving logic module, ending the current receiving process. If the received data packet is neither a data packet rx_data nor an ACK response rx_ack, the data packet rx_data is discarded and the current receiving process ends.
[0011] The core innovation of this invention lies in introducing a handshake mechanism based on packet acknowledgment (ACK) in the RGMII interface data link layer that communicates with the processor. This fundamentally solves the packet loss problem caused by the blocking of the backend Stream data stream and realizes reliable transmission of each data packet between the FPGA and the processor.
[0012] Specifically, the innovations of this invention are reflected in the following aspects: 1. Innovative introduction of link-layer reliable transmission protocols The standard RGMII interface protocol only defines the frame format for the physical and data link layers, lacking an acknowledgment and retransmission mechanism for upper-layer network protocols. When the Axi-Stream between the FPGA backend processing module and the RGMII interface is blocked due to heavy traffic, the interface is forced to drop packets due to buffer exhaustion, and the processor is completely unaware of this. This invention defines and implements a lightweight, link-layer acknowledgment protocol between the RGMII interface logic on the FPGA side and the MAC controller on the processor side. This protocol stipulates that after successfully receiving and retrieving a complete data packet from its own FIFO, the processor or FPGA must send an acknowledgment signal (ACK) to the other end. This ensures that transmission reliability no longer depends on the uncontrollable backend processing speed, but is guaranteed by the link layer itself.
[0013] 2. Active flow control mechanism based on ACK response Neither the FPGA side nor the processor side is aware of the receiving buffer status at the other end during transmission; once the buffer overflows, packets are immediately lost. This invention designs a packet buffer management and transmission state machine. After sending a data packet, this state machine waits for the corresponding ACK signal from the other end. Only after receiving the ACK will the state machine remove the packet from the buffer and prepare to send the next packet. If no ACK is received within a certain time, the state machine triggers a retransmission of the data packet. This mechanism implements a proactive, acknowledgment-based flow control, ensuring that the transmission rate strictly matches the receiving processing capacity of the other end.
[0014] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A reliable data link transmission method, characterized in that, This method achieves reliable transmission of data packets between the FPGA and the processor through various logic modules within the FPGA. By introducing a handshake mechanism based on data packet acknowledgment in the RGMII interface data link layer that communicates with the processor, this method enables reliable transmission of each data packet between the FPGA and the processor.
2. The method as described in claim 1, characterized in that, This method defines and implements a link layer acknowledgment protocol between the RGMII interface logic on the FPGA side and the MAC controller on the processor side. This protocol stipulates that after the processor or FPGA successfully receives and retrieves a complete data packet from its own FIFO, it sends an acknowledgment signal to the other end, which ensures the reliability of transmission by the link layer itself.
3. The method as described in claim 1, characterized in that, The internal logic modules of the FPGA include a data transmission logic module, a packet buffer and transmission logic module, a standard RGMII tx transmission logic module, a standard RGMII rx transmission logic module, a receive FIFO and ACK generation logic module, and a data reception logic module; among which: Data sending logic module: used to forward the data packet tx_data to be sent to the processor to the packet buffer and sending logic module; Packet caching and sending logic module: responsible for caching data packets tx_data, sending the cached data packets tx_data to the standard RGMII tx sending logic module, and receiving the ACK response rx_ack corresponding to the sequence number of the data packet sent this time. If rx_ack is not received after a certain period of time when the cached data packet tx_data is sent to the processor, a timeout retransmission is initiated. If rx_ack is received, the next cached data packet is sent. Standard RGMII tx transmission logic module: Converts data into standard RGMII format data and sends it to the RGMII physical link; Standard RGMII rx transmission logic module: converts standard RGMII format data on the RGMII physical link into data internal to the FPGA; The FIFO and ACK generation logic module is responsible for receiving data packets rx_data and ACK responses rx_ack sent by the processor. Upon receiving the data packet rx_data, it generates an ACK response tx_ack with the corresponding sequence number and sends it to the standard RGMII tx logic module, and forwards the data packet rx_data to the data receiving logic module. Upon receiving the ACK response rx_ack from the processor, it directly passes it through to the packet buffer and sending logic module. Data receiving logic module: responsible for receiving data packets rx_data sent from the processor.
4. The method as described in claim 3, characterized in that, The packet caching and sending logic module is a state machine.
5. The method as described in claim 3, characterized in that, The data transmission process implemented in this method is as follows: The data transmission logic module starts sending data packets tx_data. After the packet buffer and transmission logic module buffers the data packets tx_data, it adds a sequence number to the data packets and sends them to the standard RGMII tx transmission logic module. At this time, it waits for the ACK response (rx_ack) with the corresponding sequence number sent by the processor at the other end. If the ACK response rx_ack with the corresponding sequence number is received, the current logic is closed, and the next data packet sent by the data transmission logic module is received, and a new sequence number is added before it is sent. If it is not received, it continues to wait for the ACK response rx_ack.
6. The method as described in claim 3, characterized in that, The data reception process implemented in this method is as follows: When the standard RGMII rx transmission logic module receives a data packet rx_data or an ACK response rx_ack, the receive FIFO and ACK generation logic module buffers this data packet rx_data or ACK response rx_ack. If an ACK response rx_ack is received from the peer, the packet buffer and transmission logic module is notified to close the loop of data transmission containing the sequence number of this packet. If a data packet rx_data is received, an ACK response, i.e., an ACK reply packet tx_ack, is generated and logically sent to the peer through the standard RGMII v tx transmission logic module. Then, the data packet rx_data is forwarded to the data reception logic module, ending the reception process. If the received data packet is neither a data packet rx_data nor an ACK response rx_ack, the data packet rx_data is discarded and the reception process ends.
7. The method as described in claim 3, characterized in that, After sending a data packet, the packet buffering and sending logic module waits for the corresponding ACK response from the other end. Only after receiving the ACK response will the packet buffering and sending logic module remove the data packet from the buffer and prepare to send the next data packet. If no ACK response is received within a certain period of time, the packet buffering and sending logic module will trigger the retransmission of the data packet.
8. A system for implementing the method as described in any one of claims 1 to 7.
9. An application of the method as described in any one of claims 1 to 7 in the field of data transmission technology.
10. An application of the system as described in claim 8 in the field of data transmission technology.