A digital circuit engineering simulation system

Abstract

This invention relates to the field of integrated circuit electronic design automation technology, specifically a digital circuit engineering simulation system. It includes modules for netlist reconstruction, current excitation, noise convolution, timing backfilling, and risk assessment. The system extracts parasitic impedance by analyzing the physical layout to determine independent power supply regions. Its core is to generate a voltage drop by convolving instantaneous current with impedance characteristics, nonlinearly correcting logic gate delays and backfilling them to the scheduler, while simultaneously calculating the path robustness index based on dynamic delays to generate an evaluation signal. This invention breaks down the barriers between logic simulation and physical verification, realizing a shift from discrete logic verification to physically-aware continuous waveform simulation, and can realistically reflect the impact of physical topology on circuit behavior.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit electronic design automation technology, specifically a digital circuit engineering simulation system. Background Technology

[0002] In digital circuit design and verification processes, logic simulation is typically used to ensure the logical correctness of circuit functions. However, existing traditional logic simulation schemes are generally based on ideal environment assumptions, focusing only on discrete logic flip states and failing to perceive the parasitic impedance characteristics of power distribution networks and the voltage noise caused by transient current surges. This approach of separating logical behavior from physical effects results in the simulation process failing to accurately reflect the nonlinear degradation of logic gate delays caused by voltage drop fluctuations under low-voltage processes. It also makes it difficult to accurately identify timing failure risks caused by power supply noise in the early stages of design, creating a barrier between design verification and physical verification. Therefore, how to introduce a multi-physics coupling mechanism in the simulation stage to establish a dynamic mapping between logical behavior and physical quantities, so as to accurately capture the impact of the physical environment on timing and quantitatively evaluate circuit robustness, has become an urgent technical problem to be solved. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a digital circuit engineering simulation system. Specifically, the technical solution of this invention includes:

[0004] Physically sensitive netlist reconstruction unit, transient current excitation unit, dynamic noise convolution unit, dynamic time-series backfill unit, and robust risk assessment and feedback control unit;

[0005] The physical sensitive netlist reconstruction unit is used to parse the physical layout and process library files of the preset digital circuit design, extract the parasitic impedance parameters of the power distribution network, and divide the digital circuit into independent power supply areas;

[0006] The transient current excitation unit is used to calculate the current density of an independent power supply area and generate the instantaneous total current.

[0007] The dynamic noise convolution unit is used to perform time-domain convolution of the instantaneous total current with the impedance characteristics of the power distribution network to generate the transient voltage drop value.

[0008] The dynamic timing backfill unit is used to perform nonlinear correction on the delay of logic gates based on the transient voltage drop value, generate dynamic propagation delay, and backfill the dynamic propagation delay to the simulation event scheduler.

[0009] The robustness risk assessment and feedback control unit is used to calculate the path robustness index based on dynamic transmission delay and preset clock constraints. The path robustness index is compared with the preset benchmark value to generate design robustness signal, metastable risk signal or functional timing violation signal.

[0010] Preferably, the generation process of the instantaneous total current is as follows:

[0011] The switching state of logic gates in an independent power supply region within the discrete time step of the logic simulation clock cycle is obtained, and the peak switching current weight of logic gates under a specific load is obtained from the standard cell library.

[0012] The dynamic current component is obtained by summing the product of the peak switching current weights of all logic gates in the independent power supply area and the corresponding values ​​of the switching event functions.

[0013] The static leakage current, determined by the process library parameters, current temperature, and voltage angle, is obtained. The dynamic current component is added to the static leakage current to generate the instantaneous total current.

[0014] Preferably, the process for generating the transient voltage drop value is as follows:

[0015] The parasitic parameter netlist of the power distribution network is obtained, and the frequency domain impedance is obtained by AC analysis. The inverse Laplace transform of the frequency domain impedance is then performed to obtain the transimpedance impulse response function.

[0016] The instantaneous total current and the transimpedance impulse response function are integrated within a preset convolution window time to generate the transient voltage drop value.

[0017] The convolution window time is set to a multiple of the resonant period of the power distribution network impedance.

[0018] Preferably, the dynamic transmission delay generation process is as follows:

[0019] The nominal delay in the standard timing library is obtained, along with the standard power supply voltage of the chip, and the process sensitivity coefficient and nonlinear fitting index obtained through simulation fitting of the ring oscillator.

[0020] The ratio of the transient voltage drop to the chip's standard supply voltage is calculated, and a power-law operation is performed using the process sensitivity coefficient and the nonlinear fitting exponent to generate a delay correction factor.

[0021] The dynamic transmission delay is generated by multiplying the nominal delay by the corresponding value of the delay correction factor.

[0022] Preferably, the path robustness index is generated as follows:

[0023] Obtain the clock cycle defined in the design constraint file, as well as the setup time requirement of the path end trigger under the current voltage and conversion rate, and the target safety margin threshold.

[0024] The total propagation delay of the data path is obtained by summing the dynamic transmission delays of all logic gates on the data path.

[0025] Subtract the setup time requirement from the clock cycle, and then subtract the total propagation delay of the data path to obtain the physical margin.

[0026] The path robustness index is generated by dividing the physical real margin by the target safety margin threshold.

[0027] The preferred interval comparison process is as follows:

[0028] When the path robustness index is greater than or equal to the preset first benchmark value, a design robustness signal is generated. The design robustness signal indicates that the physical margin exceeds the target buffer value expected in the design.

[0029] When the path robustness index is less than the first benchmark value and greater than or equal to the preset second benchmark value, a metastable risk signal is generated. The metastable risk signal indicates that the physical margin is positive but lower than the expected target.

[0030] When the path robustness index is less than the second baseline value, a functional timing violation signal is generated, which indicates that the physical margin is negative.

[0031] The first reference value is set to 1.0, and the second reference value is set to 0.0.

[0032] Preferably, the flip event function represents an indication value of a state transition of a logic gate at the simulation time;

[0033] If the logic gate undergoes a level transition during simulation, the toggle event function takes the value of one; if the logic gate does not undergo a level transition during simulation, the toggle event function takes the value of zero.

[0034] Preferably, the nonlinear fitting index is used to fit the short-channel effect, and the value range of the nonlinear fitting index is set between 1.0 and 2.0; the process sensitivity coefficient characterizes the sensitivity of the device speed to voltage changes.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. This system establishes a mapping relationship between logic design and physical implementation through a physically sensitive netlist reconstruction unit, analyzes the physical layout and extracts the parasitic impedance parameters of the power distribution network, and divides the circuit into independent power supply areas. At the same time, combined with a transient current excitation unit, the discrete logic gate flip states are transformed into continuous current waveforms containing physical driving capabilities. This mechanism breaks down the barrier between logic simulation and physical signature, ensuring that the simulation process can truly reflect the influence of physical topology and device static physical properties on circuit behavior.

[0037] 2. This system employs a dynamic noise convolution unit and utilizes the theory of linear time-invariant systems to perform time-domain convolution between the instantaneous total current and the transimpedance impulse response function of the power distribution network. By setting the convolution window time to a multiple of the impedance resonance period of the power distribution network, the system can fully cover the energy decay and voltage rebound process caused by inductor-capacitor oscillations, preventing calculation errors caused by window truncation, and avoiding resource waste caused by infinite integration, thereby accurately generating the transient voltage drop value.

[0038] 3. This system utilizes a dynamic timing backfill unit, abandoning the traditional fixed delay mode. By introducing the process sensitivity coefficient and nonlinear fitting index obtained through simulation fitting of a ring oscillator, the system can nonlinearly correct the nominal delay of the logic gate based on the transient voltage drop. This method quantitatively describes the sensitivity of short-channel effect and transistor saturation current to voltage changes, generating a dynamic propagation delay that conforms to the current voltage environment, thereby solving the problem of increased logic gate delay caused by voltage drop, which leads to timing failure.

[0039] 4. This system calculates the path robustness index and performs interval comparisons through a robustness risk assessment and feedback control unit, subdividing the circuit state into three levels: design robustness, metastability risk, and functional timing violation. This mechanism can not only identify substantial timing violations, but also accurately locate vulnerable paths that, although logically correct, have physical margins lower than the expected safety targets through metastability risk signals. This provides designers with precise optimization guidance, helping to eliminate potential metastability hazards in the early stages of design and improve the final mass production yield. Attached Figure Description

[0040] The present invention will be further explained below with reference to the accompanying drawings and embodiments:

[0041] Figure 1 This is a structural diagram of the system of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0043] Example 1:

[0044] Please see Figure 1 A digital circuit engineering simulation system includes a physically sensitive netlist reconstruction unit, a transient current excitation unit, a dynamic noise convolution unit, a dynamic timing backfill unit, and a robust risk assessment and feedback control unit.

[0045] The physical sensitive netlist reconstruction unit is used to parse the physical layout and process library files of the preset digital circuit design, extract the parasitic impedance parameters of the power distribution network, and divide the digital circuit into independent power supply areas;

[0046] The transient current excitation unit is used to calculate the current density of an independent power supply area and generate the instantaneous total current.

[0047] The dynamic noise convolution unit is used to perform time-domain convolution of the instantaneous total current with the impedance characteristics of the power distribution network to generate the transient voltage drop value.

[0048] The dynamic timing backfill unit is used to perform nonlinear correction on the delay of logic gates based on the transient voltage drop value, generate dynamic propagation delay, and backfill the dynamic propagation delay to the simulation event scheduler.

[0049] The robustness risk assessment and feedback control unit is used to calculate the path robustness index based on dynamic transmission delay and preset clock constraints. The path robustness index is compared with the preset benchmark value to generate design robustness signal, metastable risk signal or functional timing violation signal.

[0050] This embodiment discloses a digital circuit engineering simulation system, which aims to solve the shortcomings of traditional logic simulation in that it cannot perceive the influence of the physical environment. By introducing a multi-physics coupling mechanism, it can accurately identify the timing failure risk caused by power supply noise in the early stage of design. The system mainly includes a physical sensitive netlist reconstruction unit, a transient current excitation unit, a dynamic noise convolution unit, a dynamic timing backfill unit, and a robust risk assessment and feedback control unit.

[0051] The physically sensitive netlist reconstruction unit serves as the system's fundamental data processing interface. Its core function is to establish a mapping relationship between logical design and physical implementation. During execution, this unit reads and parses the preset physical layout data and process library files of the digital circuit design, extracting the parasitic impedance parameters of the power distribution network. These parasitic impedance parameters include resistance, capacitance, and inductance components. Based on the physical location and power supply topology, this unit divides the massive digital circuit layout into N independent power supply regions, laying the foundation for subsequent partitioning calculations.

[0052] The transient current excitation unit is used to convert discrete flip events at the logic simulation level into continuous current waveforms at the physical level. For each independent power supply area, this unit calculates the current density by combining the flip state of the logic gate with the physical driving capability, thereby generating the instantaneous total current that can reflect the real-time power consumption characteristics of the circuit.

[0053] The dynamic noise convolution unit is based on the theory of linear time-invariant systems and is used to simulate the dynamic response of a power distribution network to current surges. The unit performs time-domain convolution operation on the calculated instantaneous total current and the impedance characteristics of the power distribution network to solve for the transient voltage drop value with time lag effect and voltage rebound characteristics.

[0054] The dynamic timing backfill unit is used to construct a nonlinear mapping between voltage fluctuations and signal transmission speed. Based on the calculated transient voltage drop, the unit uses a physical model to nonlinearly correct the nominal delay of the logic gate, generates a dynamic transmission delay that conforms to the current voltage environment, and backfills the dynamic transmission delay into the simulation event scheduler, thereby dynamically changing the arrival time of the signal in the circuit.

[0055] The robustness risk assessment and feedback control unit is used to quantify and classify the timing safety of the circuit. The unit calculates the path robustness index based on the corrected dynamic propagation delay and preset clock constraints, and compares the path robustness index with the preset benchmark value. Then, based on the comparison results, it generates design robustness signals, metastability risk signals or functional timing violation signals, providing designers with precise optimization guidance.

[0056] Through the collaborative work of the above units, this system breaks down the barrier between logic simulation and physical verification, and can significantly improve the functional reliability and yield expectations of digital chips in real physical environments.

[0057] Example 2:

[0058] The generation process of the instantaneous total current is as follows:

[0059] The switching state of logic gates in an independent power supply region within the discrete time step of the logic simulation clock cycle is obtained, and the peak switching current weight of logic gates under a specific load is obtained from the standard cell library.

[0060] The dynamic current component is obtained by summing the product of the peak switching current weights of all logic gates in the independent power supply area and the corresponding values ​​of the switching event functions.

[0061] The static leakage current, determined by the process library parameters, current temperature, and voltage angle, is obtained. The dynamic current component is added to the static leakage current to generate the instantaneous total current.

[0062] The flip-event function indicates the state transition of a logic gate at the simulation time;

[0063] If the logic gate undergoes a level transition during simulation, the toggle event function takes the value of one; if the logic gate does not undergo a level transition during simulation, the toggle event function takes the value of zero.

[0064] This embodiment details the specific process by which the transient current excitation unit generates the instantaneous total current. This process aims to establish a quantitative mapping between logic behavior flipping and physical quantity current, ensuring that the current model includes both the dynamic characteristics of logic activities and the static physical properties of the device itself.

[0065] During the calculation, the system obtains the toggle state of each logic gate in the independent power supply region within the discrete time step of the logic simulation clock cycle; at the same time, the system obtains the peak toggle current weight of the logic gate under a specific load from the standard cell library, and obtains the switching activity factor from the statistical analysis results of the waveform file.

[0066] Peak switching current weighting here The peak current value is derived from the lookup table values ​​of the internal power consumption and switching power consumption of the logic gate under the current output load capacitance, as defined in the standard cell library, and then converted. This conversion process is based on the principle of charge conservation, dividing the total energy of the standard cell in a single switching event by the chip's standard supply voltage. The product of the average peak current and the simulation time step is used to obtain the equivalent average peak current weight, thus ensuring the consistency of the energy integral.

[0067] The system calculates dynamic current components using the superposition principle; specifically, the system iterates through each logic gate in the Kth independent power supply region, and weights the peak current of the i-th logic gate. The flip event function of the logic gate at the current moment. Multiply the results and sum the calculation results of all logic gates within the region to obtain the dynamic current component; among them, the toggle event function... It is a key indicator variable connecting discrete logic and continuous physics. If the i-th logic gate undergoes a level transition at simulation time t, i.e., a state transition from zero to one or from one to zero, then the toggle event function is activated. The value is set to 1; if the i-th logic gate does not undergo a level transition at simulation time t, then the toggle event function is applied. The value is set to zero; this approach ensures that the current excitation is generated only when a real logical action occurs.

[0068] The system acquires the static leakage current determined by process library parameters, current operating temperature, and voltage angle. The static leakage current characterizes the background power consumption of the circuit in the non-flipping state.

[0069] The system adds the calculated dynamic current component to the static leakage current to generate the final instantaneous total current. The mathematical expression is:

[0070] ;

[0071] in, Let be the total number of logic gates in the k-th region. This indicates a summation operation on all logic gates within the region; the statistical probability-based switching activity factor has been removed here. Because of the deterministic flip event function The instantaneous switching action of the logic gate has been accurately described based on the discrete time step, so there is no need to add an average probability factor.

[0072] By introducing a switching activity factor and weighting parameters based on a standard cell library, this embodiment can accurately capture the charge movement characteristics of the circuit at the instant of clock edge transition, providing a high-fidelity excitation source for subsequent voltage drop calculation.

[0073] Example 3:

[0074] The generation process of the transient voltage drop is as follows:

[0075] The parasitic parameter netlist of the power distribution network is obtained, and the frequency domain impedance is obtained by AC analysis. The inverse Laplace transform of the frequency domain impedance is then performed to obtain the transimpedance impulse response function.

[0076] The instantaneous total current and the transimpedance impulse response function are integrated within a preset convolution window time to generate the transient voltage drop value.

[0077] The convolution window time is set to a multiple of the resonant period of the power distribution network impedance.

[0078] Among them, the convolution window time Set to three to five times the duration of the first-order impedance resonance period of the power distribution network;

[0079] Setting it as a multiple of the low-frequency resonant period aims to ensure the integration interval. It can fully cover the inductor-capacitor oscillation process, which has the slowest energy decay in the power network, thereby preventing calculation errors in voltage drop due to window truncation.

[0080] This embodiment details the specific process by which the dynamic noise convolution unit generates the transient voltage drop value; this process utilizes the time-domain convolution method to accurately analyze the impedance response of the power distribution network to transient current;

[0081] The system acquires the parasitic parameter netlist of the power distribution network and performs AC analysis on it to obtain the frequency domain impedance. The system performs an inverse Laplace transform on the frequency domain impedance to obtain the transimpedance impulse response function in the time domain. This function describes the voltage fluctuation characteristics of a power network when subjected to a unit pulse current surge.

[0082] The system performs convolution integral operations; specifically, the system calculates the instantaneous total current obtained in the previous steps. With transimpedance impulse response function Within the preset convolution window time The integral operation is performed to generate the transient voltage drop value at time t. The calculation formula is as follows:

[0083] ;

[0084] In this embodiment, the convolution window time The time window is set to three to five times the resonant period of the power distribution network impedance. The technical motivation for setting this time window is to ensure that the integration process covers the main energy decay process of the power network, which can capture the voltage rebound noise caused by inductor-capacitor oscillations and avoid the waste of computational resources caused by infinite integration, thus achieving a balance between simulation accuracy and efficiency.

[0085] Example 4:

[0086] The process of generating dynamic transmission delay is as follows:

[0087] The nominal delay in the standard timing library is obtained, along with the standard power supply voltage of the chip, and the process sensitivity coefficient and nonlinear fitting index obtained through simulation fitting of the ring oscillator.

[0088] The ratio of the transient voltage drop to the chip's standard supply voltage is calculated, and a power-law operation is performed using the process sensitivity coefficient and the nonlinear fitting exponent to generate a delay correction factor.

[0089] The dynamic transmission delay is generated by multiplying the nominal delay by the corresponding value of the delay correction factor.

[0090] The nonlinear fitting index is used to fit the short-channel effect, and the value range of the nonlinear fitting index is set between 1.0 and 2.0; the process sensitivity coefficient characterizes the sensitivity of the device speed to voltage changes.

[0091] This embodiment details the specific process of generating dynamic transmission delay by the dynamic timing backfill unit; this process abandons the traditional fixed delay mode and uses physical formulas to map the real-time voltage drop into the delay increment of the logic gate;

[0092] The system obtains the nominal delay of logic gates at standard voltage from the standard timing library. Simultaneously obtain the chip's standard power supply voltage Furthermore, in order to construct an accurate nonlinear correction model, the system also needs to obtain the process sensitivity coefficient. and nonlinear fitting index These two parameters were obtained by performing SPICE simulations and fitting data on the ring oscillator under different voltage conditions. Specifically, the fitting process involved: based on the simulation delay of the ring oscillator under different supply voltages V... The following equations are subjected to parameter regression using the nonlinear least squares method:

[0093] ;

[0094] in, and These are the extracted process sensitivity coefficient and nonlinear fitting index, respectively; V is the actual power supply voltage variable of the ring oscillator during simulation.

[0095] Extract the optimal matching process sensitivity coefficient from it. and nonlinear fitting index This ensures that the parameter can accurately characterize the nonlinear degradation trend of device delay with voltage decrease at the current process node;

[0096] Among them, the nonlinear fitting index Used to fit the short-channel effect, its value is strictly set to be between 1.0 and 2.0; process sensitivity coefficient This characterizes the sensitivity of the speed of this type of device to voltage changes;

[0097] The system calculates the delay correction factor; specifically, the calculation method is to take the transient voltage drop value as the factor. With the chip's standard power supply voltage The ratio is calculated and combined with the process sensitivity coefficient. With nonlinear fitting index Power-law operations are performed, and their mathematical expression follows the Taylor expansion form of the Alpha-PowerLaw model.

[0098] The system will specify the delay. Multiply by the calculated delay correction factor to generate the physically corrected dynamic transmission delay. The calculation formula is as follows:

[0099] ;

[0100] This implementation can quantitatively describe the sensitivity of transistor saturation current to voltage fluctuations under low-voltage processes, effectively solving the problem of timing failure caused by increased logic gate delay due to IRDrop.

[0101] Example 5:

[0102] The process of generating the path robustness index is as follows:

[0103] Obtain the clock cycle defined in the design constraint file, as well as the setup time requirement of the path end trigger under the current voltage and conversion rate, and the target safety margin threshold.

[0104] The total propagation delay of the data path is obtained by summing the dynamic transmission delays of all logic gates on the data path.

[0105] Subtract the setup time requirement from the clock cycle, and then subtract the total propagation delay of the data path to obtain the physical margin.

[0106] The path robustness index is generated by dividing the physical real margin by the target safety margin threshold.

[0107] This embodiment details the specific process of robustness risk assessment and feedback control unit generation path robustness index; this index is a dimensionless comprehensive evaluation index used to quantify the timing safety margin of the chip in a real physical environment.

[0108] The system obtains the clock period defined in the design constraint file. Simultaneously, the setup time requirement of the path endpoint trigger under the current voltage and signal conversion rate is obtained from the technology library. In addition, the system also needs to obtain the preset target safety margin threshold. This threshold is typically set by the design team based on yield targets, such as five to ten percent of the clock cycle.

[0109] The system accumulates the dynamic propagation delays of all logic gates along the data path to obtain the total propagation delay of the data path, taking into account the effects of voltage noise, denoted as . ;

[0110] The system calculates the clock cycle. Subtract the establishment time requirement Subtract the total propagation delay of the data path. This yields the physical true margin, which represents the time difference between the arrival of the signal and the triggering of the clock edge.

[0111] This yields the physical true margin, which represents the time difference between the arrival of the signal and the triggering of the clock edge.

[0112] The system divides the physical real margin by the target safety margin threshold. Generate path robustness index The calculation formula is as follows:

[0113] ;

[0114] Through this normalization process, the index can not only reflect whether the timing meets the requirements, but also intuitively reflect the degree to which the design is close to the failure edge.

[0115] Example 6:

[0116] The interval comparison process is as follows:

[0117] When the path robustness index is greater than or equal to the preset first benchmark value, a design robustness signal is generated. The design robustness signal indicates that the physical margin exceeds the target buffer value expected in the design.

[0118] When the path robustness index is less than the first benchmark value and greater than or equal to the preset second benchmark value, a metastable risk signal is generated. The metastable risk signal indicates that the physical margin is positive but lower than the expected target.

[0119] When the path robustness index is less than the second baseline value, a functional timing violation signal is generated, which indicates that the physical margin is negative.

[0120] The first reference value is set to 1.0, and the second reference value is set to 0.0.

[0121] This embodiment details the specific logic of interval comparison and signal generation; the system calculates the path robustness index. By comparing with a preset benchmark value, the health status of the circuit path is divided into three levels;

[0122] When the path robustness index When the value is greater than or equal to a preset first reference value, a design robustness signal is generated; in this embodiment, the first reference value is set to a value of 1.0; this indicates that the physical margin has exceeded the target buffer value expected by the design, the design is in a robust state, and no additional optimization is required.

[0123] When the path robustness index When the value is less than the first reference value and greater than or equal to the preset second reference value, the system generates a metastable risk signal. In this embodiment, the second reference value is set to 0.0. This means that although the physical margin is positive, that is, the function is correct in theory, its value is lower than the expected safety target and is in a high-risk area on the edge of metastability. Targeted optimization is required to prevent failure due to process deviation.

[0124] When the path robustness index When the value is less than the second reference value, a functional timing violation signal is generated; this indicates that the physical real margin is negative, the signal cannot stabilize before the clock edge arrives, a substantial setup time violation has occurred, and it must be corrected.

[0125] This tiered evaluation mechanism helps designers identify paths that, while passing traditional static timing analysis, are extremely vulnerable in real physical environments, thereby significantly improving the final mass production yield of chips.

[0126] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A digital circuit engineering simulation system, characterized by comprising: It includes a physically sensitive netlist reconstruction unit, a transient current excitation unit, a dynamic noise convolution unit, a dynamic time-series backfill unit, and a robust risk assessment and feedback control unit; The physical sensitive netlist reconstruction unit is used to parse the physical layout and process library files of the preset digital circuit design, extract the parasitic impedance parameters of the power distribution network, and divide the digital circuit into independent power supply areas; The transient current excitation unit is used to calculate the current density of an independent power supply area and generate the instantaneous total current. The dynamic noise convolution unit is used to perform time-domain convolution of the instantaneous total current with the impedance characteristics of the power distribution network to generate the transient voltage drop value. The dynamic timing backfill unit is used to perform nonlinear correction on the delay of logic gates based on the transient voltage drop value, generate dynamic propagation delay, and backfill the dynamic propagation delay to the simulation event scheduler. The robustness risk assessment and feedback control unit is used to calculate the path robustness index based on dynamic transmission delay and preset clock constraints, compare the path robustness index with the preset benchmark value, and generate design robustness signal, metastability risk signal or functional timing violation signal. The process of generating dynamic transmission delay is as follows: The nominal delay in the standard timing library is obtained, along with the standard power supply voltage of the chip, and the process sensitivity coefficient and nonlinear fitting index obtained through simulation fitting of the ring oscillator. Transient voltage drop With the chip's standard power supply voltage The ratio is calculated and combined with the process sensitivity coefficient. With nonlinear fitting index Perform power-law operations to generate delay correction factors; nominal delay Multiply by the corresponding value of the delay correction factor to generate the dynamic transmission delay. The calculation formula is as follows: ; The nonlinear fitting index is used to fit the short-channel effect, and the value range of the nonlinear fitting index is set between 1.0 and 2.0; the process sensitivity coefficient characterizes the sensitivity of the device speed to voltage changes.

2. The digital circuit engineering simulation system according to claim 1, wherein The generation process of the instantaneous total current is as follows: The switching state of logic gates in an independent power supply region within the discrete time step of the logic simulation clock cycle is obtained, and the peak switching current weight of logic gates under a specific load is obtained from the standard cell library. The dynamic current component is obtained by summing the product of the peak switching current weights of all logic gates in the independent power supply area and the corresponding values ​​of the switching event functions. The static leakage current, determined by the process library parameters, current temperature, and voltage angle, is obtained. The dynamic current component is added to the static leakage current to generate the instantaneous total current.

3. The digital circuit engineering simulation system according to claim 1, wherein The generation process of the transient voltage drop is as follows: The parasitic parameter netlist of the power distribution network is obtained, and the frequency domain impedance is obtained by AC analysis. The inverse Laplace transform of the frequency domain impedance is then performed to obtain the transimpedance impulse response function. The instantaneous total current and the transimpedance impulse response function are integrated within a preset convolution window time to generate the transient voltage drop value. The convolution window time is set to a multiple of the resonant period of the power distribution network impedance.

4. The digital circuit engineering simulation system according to claim 1, wherein The process of generating the path robustness index is as follows: Obtain the clock cycle defined in the design constraint file, as well as the setup time requirement of the path end trigger under the current voltage and conversion rate, and the target safety margin threshold. The total propagation delay of the data path is obtained by summing the dynamic transmission delays of all logic gates on the data path. Subtract the setup time requirement from the clock cycle, and then subtract the total propagation delay of the data path to obtain the physical margin. The path robustness index is generated by dividing the physical real margin by the target safety margin threshold.

5. The digital circuit engineering simulation system according to claim 4, wherein The interval comparison process is as follows: When the path robustness index is greater than or equal to the preset first benchmark value, a design robustness signal is generated. The design robustness signal indicates that the physical margin exceeds the target buffer value expected in the design. When the path robustness index is less than the first benchmark value and greater than or equal to the preset second benchmark value, a metastable risk signal is generated. The metastable risk signal indicates that the physical margin is positive but lower than the expected target. When the path robustness index is less than the second baseline value, a functional timing violation signal is generated, which indicates that the physical margin is negative. The first reference value is set to 1.0, and the second reference value is set to 0.

0.

6. The digital circuit engineering simulation system according to claim 2, wherein The flip-event function indicates the state transition of a logic gate at the simulation time; If a logic gate undergoes a level transition during simulation, the flip-flop event function will take the value of one. If the logic gate does not undergo a level transition during simulation, the flip event function will take the value of zero.

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