Charging circuit

Abstract

The invention discloses a charging circuit, and the circuit comprises a DC source which provides a DC power supply voltage; the at least one power converter is connected with the direct-current source and converts the direct-current power supply voltage into output voltage; the at least one output port is respectively connected with the power converter and is used for charging a load; the control circuit is used for generating a switch control signal of the power converter according to a state signal of the load and the output voltage so as to adjust the output voltage, the state signal of the load represents whether the output port has the load, and the power converter comprises an output capacitor which is connected between the first end and the second end of the output port; the charging circuit comprises a bleeder circuit which provides a bleeder channel for the output capacitor. Under the conditions that simple devices are used and the cost is low, the bleeder circuit multiplexes the power converter or independently provides a bleeder channel for the output capacitor, stable output voltage is output when the output port has a load, and the output voltage is reduced to a preset value when the output port is not connected with the load.

Description

[0001] This is a divisional application. The original application number is 202010430704.8, the title is "Charging Circuit", and the application date is May 20, 2020. Technical Field

[0002] This invention relates to power supply technology, and more specifically, to a charging circuit for multi-channel fast charging. Background Technology

[0003] In portable devices such as mobile phones, e-readers, tablets, and laptops, battery capacities are increasing to ensure battery life, resulting in excessively long charging times. Fast charging technology can effectively improve charging efficiency, thus significantly reducing charging time. When the charging circuit is connected to a load, its output voltage can quickly build up, charging the load; when disconnected from the load, the output voltage can decrease to a preset value within a specified time.

[0004] Figure 1 A schematic block diagram of a charging circuit in the prior art is shown. For example... Figure 1 As shown, the charging circuit includes an input circuit 11, a first power converter 12, a second power converter 13, and a control circuit 14. The input circuit 11 includes a capacitor Cin, a transformer T1, a primary-side power switch Q, a diode D1, and an output capacitor C1. The input terminal of the input circuit 11 receives a DC input voltage Vin. The first power converter 12 includes a DC-DC converter circuit with a load switch and an output port with a bleed channel. The DC-DC converter circuit with a load switch includes two power switches Q11 and Q12, an inductor L1, a load switch S1, and a capacitor C12. The output port with a bleed channel includes a resistor R11 and an output port (not shown in the figure). The second power converter 13 is the same as the first power converter 12 and will not be described again here. The first power converter 12 and the second power converter 13 are connected in parallel across the output capacitor C1 of the input circuit 11. Taking the first power converter 12 as an example, when the control circuit 14 detects that the load Load1 is connected to the output port of the first power converter 12, the load switch S1 is turned on, and the power switch transistors Q11 and Q12 are alternately turned on to supply power to the load Load1; when the load Load1 is detected to be removed, the load switch S1 is turned off, and the output port voltage (the input voltage of the load Load1) is quickly reduced to a preset value through the resistor R11.

[0005] like Figure 1The circuit shown can achieve dual-channel fast charging, and the two voltages are independent of each other. However, a load switch and a discharge channel are required to meet the output requirements of the charging circuit. The load switch and discharge channel not only increase system losses and reduce system efficiency, but also increase system cost and size, hindering miniaturization. Summary of the Invention

[0006] In view of the above problems, the purpose of the present invention is to provide a charging circuit in which the discharge circuit reuses its power converter or provides a discharge channel separately for the output capacitor, thereby reducing the number of circuit components and reducing circuit losses.

[0007] According to one aspect of the present invention, a charging circuit is provided, comprising: a DC source providing a DC supply voltage; at least one power converter connected to the DC source to convert the DC supply voltage into an output voltage; at least one output port connected to the power converter for charging a load; a control circuit generating a switching control signal for the power converter to adjust the output voltage based on a load status signal and the output voltage, wherein the load status signal indicates whether a load is connected to the output port; wherein the power converter includes an output capacitor connected between a first terminal and a second terminal of the output port; the charging circuit further includes a discharge circuit providing a discharge path for the output capacitor.

[0008] Preferably, when no load is connected to the output port, the switch control signal controls the corresponding power converter to reduce the output voltage across the output capacitor to a preset value.

[0009] Preferably, when a load is connected to the output port, the switch control signal controls the corresponding power converter to generate a stable output voltage.

[0010] Preferably, the discharge circuit of the output capacitor reuses the power converter.

[0011] Preferably, the power converter is a BUCK circuit.

[0012] Preferably, the discharge circuit includes a first inductor, a first transistor, and a first capacitor, wherein the first transistor and the first inductor are connected to a first terminal of the DC source and a first terminal of the output port; the first capacitor is connected between the first terminal and the second terminal of the DC source; and the charge on the output capacitor flows sequentially through the first inductor, the first transistor, and the first capacitor to form a discharge circuit.

[0013] Preferably, the discharge circuit includes a first inductor and a second transistor, wherein the first inductor and the second transistor are connected in series between the first and second terminals of the output port; the charge on the output capacitor flows sequentially through the first inductor and the second transistor to form a discharge circuit.

[0014] Preferably, the power converter further includes a first transistor, a second transistor, and a first inductor, wherein the first transistor and the first inductor are connected to a first terminal of the DC source and a first terminal of the output port; the second transistor is connected between a first node between the first transistor and the first inductor and a second terminal of the output port; the control terminal of the first transistor is connected to a control circuit and receives a first switch control signal; the control terminal of the second transistor is connected to a control circuit and receives a second switch control signal.

[0015] Preferably, when a load is connected to the output port, the first switch control signal and the second switch control signal are out of phase, respectively controlling the first transistor and the second transistor to alternately turn on and off.

[0016] Preferably, when no load is connected to the output port, the first switch control signal controls the first transistor to be in a synchronous rectification or off state, and the second switch control signal controls the second transistor to be in an alternating on and off state.

[0017] Preferably, when no load is connected to the output port, the first switch control signal controls the first transistor to be in the off state, and the second switch control signal controls the second transistor to operate in the constant current region.

[0018] Preferably, when no load is connected to the output port, the first switch control signal controls the first transistor to be in the off state, and the second switch control signal controls the second transistor to be in the on state.

[0019] Preferably, the discharge circuit includes a first inductor, a first resistor, and a third transistor, wherein the first inductor, the first resistor, and the third transistor are connected in series between the first and second terminals of the output port; the charge on the output capacitor flows sequentially through the first inductor, the first resistor, and the third transistor to form a discharge circuit.

[0020] Preferably, the power converter further includes a first transistor, a second transistor, and a first inductor, wherein the first transistor and the first inductor are connected to a first terminal of the DC source and a first terminal of the output port; the second transistor is connected between a first node between the first transistor and the first inductor and a second terminal of the output port; a first resistor and a third transistor are connected in series between the first node between the first transistor and the first inductor and a second terminal of the output port; the control terminal of the first transistor is connected to a control circuit and receives a first switch control signal; the control terminal of the second transistor is connected to a control circuit and receives a second switch control signal; and the control terminal of the third transistor is connected to a control circuit and receives a third switch control signal.

[0021] Preferably, when a load is connected to the output port, the first switch control signal and the second switch control signal are out of phase, respectively controlling the first transistor and the second transistor to alternately turn on and off, and the third switch control signal controls the third transistor to turn off.

[0022] Preferably, when no load is connected to the output port, the first switch control signal controls the first transistor to be in the off state, the second switch control signal controls the second transistor to be in the off state, and the third switch control signal controls the third transistor to be in the on state.

[0023] Preferably, the discharge circuit includes a first inductor and a second resistor, wherein the first inductor and the second resistor are connected in series between the first end of the output port and the control circuit; the charge on the output capacitor flows through the first inductor and the second resistor in sequence to form a discharge circuit.

[0024] Preferably, the power converter further includes a first transistor, a second transistor, and a first inductor, wherein the first transistor and the first inductor are connected to a first terminal of the DC source and a first terminal of the output port; the second transistor is connected between a first node between the first transistor and the first inductor and a second terminal of the output port; a second resistor is connected between the first node between the first transistor and the first inductor and a control terminal of the first transistor; the control terminal of the first transistor is connected to a control circuit and receives a first switch control signal; the control terminal of the second transistor is connected to a control circuit and receives a second switch control signal.

[0025] Preferably, when no load is connected to the output port, the first switch control signal controls the first transistor to be in the off state, and the second switch control signal controls the second transistor to be in the off state.

[0026] Preferably, the power converter is a buck-boost circuit.

[0027] Preferably, the discharge circuit includes a sixth transistor, a second inductor, a fourth transistor, and a first capacitor, wherein the fourth transistor, the second inductor, and the sixth transistor are connected in series between the first terminal of the DC source and the first terminal of the output port; the first capacitor is connected between the first terminal and the second terminal of the DC source; and the charge on the output capacitor flows sequentially through the sixth transistor, the second inductor, the fourth transistor, and the first capacitor to form a discharge circuit.

[0028] Preferably, the discharge circuit includes a sixth transistor, a second inductor, and a fifth transistor, wherein the fifth transistor, the second inductor, and the sixth transistor are connected in series between the second terminal of the DC source and the first terminal of the output port; the charge on the output capacitor flows sequentially through the sixth transistor, the second inductor, and the fifth transistor to form a discharge circuit.

[0029] Preferably, the discharge circuit includes a sixth transistor and a seventh transistor, wherein the sixth transistor and the seventh transistor are connected in series between the first and second terminals of the output port; the charge on the output capacitor flows through the sixth transistor and the seventh transistor in sequence to form a discharge circuit.

[0030] Preferably, the power converter further includes a fourth to a seventh transistor and a second inductor, wherein the fourth and fifth transistors are connected in series between a first terminal and a second terminal of the DC source; the sixth and seventh transistors are connected in series between a first terminal and a second terminal of the output port; the second inductor is connected between a second node between the fourth and fifth transistors and a third node between the sixth and seventh transistors; the output capacitor is connected between the first and second terminals of the output port; the control terminal of the fourth transistor is connected to a control circuit and receives a fourth switch control signal; the control terminal of the fifth transistor is connected to a control circuit and receives a fifth switch control signal; the control terminal of the sixth transistor is connected to a control circuit and receives a sixth switch control signal; and the control terminal of the seventh transistor is connected to a control circuit and receives a seventh switch control signal.

[0031] Preferably, when a load is connected to the output port, the fourth switch control signal and the fifth switch control signal control the fourth transistor and the fifth transistor to conduct alternately, the sixth switch control signal controls the sixth transistor to be in the conducting state, and the seventh switch control signal controls the seventh transistor to be in the off state.

[0032] Preferably, when a load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the on state, the fifth switch control signal controls the fifth transistor to be in the off state, and the sixth switch control signal and the seventh switch control signal control the sixth transistor and the seventh transistor to be turned on alternately, respectively.

[0033] Preferably, when a load is connected to the output port, the fourth control signal, the fifth control signal, the sixth control signal, and the seventh control signal control the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor to conduct alternately, respectively.

[0034] Preferably, when no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in a synchronous rectification or off state, the fifth switch control signal controls the fifth transistor to alternately turn on and off, the sixth switch control signal controls the sixth transistor to be in a conducting state, and the seventh switch control signal controls the seventh transistor to be in a off state.

[0035] Preferably, when no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to operate in the constant current region, the sixth switch control signal controls the sixth transistor to operate in the constant current region, and the seventh switch control signal controls the seventh transistor to be in the off state, or operate in the variable resistance region, or operate in the constant current region, or be in the on state.

[0036] Preferably, when no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the off state or to operate in the variable resistance region or the constant current region or to be in the on state, the sixth switch control signal controls the sixth transistor to operate in the constant current region, and the seventh switch control signal controls the seventh transistor to operate in the constant current region.

[0037] Preferably, when no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the on state, the sixth switch control signal controls the sixth transistor to be in the on state, and the seventh switch control signal controls the seventh transistor to be in the off state or to operate in the variable resistance region.

[0038] Preferably, when no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the off state or to operate in the variable resistance region, the sixth switch control signal controls the sixth transistor to be in the on state, and the seventh switch control signal controls the seventh transistor to be in the on state.

[0039] Preferably, when no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the on state, the sixth switch control signal controls the sixth transistor to be in the on state, and the seventh switch control signal controls the seventh transistor to be in the on state.

[0040] Preferably, the discharge circuit includes a sixth transistor, a second inductor, a third resistor, and an eighth transistor, wherein the sixth transistor, the second inductor, the third resistor, and the eighth transistor are connected in series between the first and second terminals of the output port; the charge on the output capacitor flows sequentially through the sixth transistor, the second inductor, the third resistor, and the eighth transistor to form a discharge loop.

[0041] Preferably, the power converter further includes a fourth to a seventh transistor and a second inductor, wherein the fourth and fifth transistors are connected in series between a first terminal and a second terminal of the DC source; the sixth and seventh transistors are connected in series between a first terminal and a second terminal of the output port; the second inductor is connected between a second node between the fourth and fifth transistors and a third node between the sixth and seventh transistors; the third resistor and an eighth transistor are connected in series between the second node between the fourth and fifth transistors and the second terminal of the output port; the control terminal of the fourth transistor is connected to a control circuit and receives a fourth switch control signal; the control terminal of the fifth transistor is connected to a control circuit and receives a fifth switch control signal; the control terminal of the sixth transistor is connected to a control circuit and receives a sixth switch control signal; the control terminal of the seventh transistor is connected to a control circuit and receives a seventh switch control signal; and the control terminal of the eighth transistor is connected to a control circuit and receives an eighth switch control signal.

[0042] Preferably, when a load is connected to the output port, the fourth switch control signal and the fifth switch control signal control the fourth transistor and the fifth transistor to conduct alternately, the sixth switch control signal controls the sixth transistor to be in the conducting state, the seventh switch control signal controls the seventh transistor to be in the off state, and the eighth switch control signal controls the eighth transistor to be in the off state.

[0043] Preferably, when a load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the on state, the fifth switch control signal controls the fifth transistor to be in the off state, the sixth switch control signal and the seventh switch control signal respectively control the sixth transistor and the seventh transistor to be alternately turned on, and the eighth switch control signal controls the eighth transistor to be in the off state.

[0044] Preferably, when a load is connected to the output port, the fourth control signal, the fifth control signal, the sixth control signal and the seventh control signal control the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor to be turned on alternately, and the eighth switch control signal controls the eighth transistor to be in the off state.

[0045] Preferably, when no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the off state, the sixth switch control signal controls the sixth transistor to be in the on state, the seventh switch control signal controls the seventh transistor to be in the off state, and the eighth switch control signal controls the eighth transistor to be in the on state.

[0046] Preferably, the discharge circuit includes a sixth transistor, a second inductor, and a fourth resistor, wherein the sixth transistor, the second inductor, and the fourth resistor are connected in series between the first end of the output port and the control circuit; the charge on the output capacitor flows sequentially through the sixth transistor, the second inductor, and the fourth resistor to form a discharge loop.

[0047] Preferably, the power converter further includes a fourth to a seventh transistor and a second inductor, wherein the fourth and fifth transistors are connected in series between a first terminal and a second terminal of the DC source; the sixth and seventh transistors are connected in series between a first terminal and a second terminal of the output port; the second inductor is connected between a second node between the fourth and fifth transistors and a third node between the sixth and seventh transistors; the fourth resistor is connected between the second node and the control circuit; the control terminal of the fourth transistor is connected to the control circuit and receives a fourth switch control signal; the control terminal of the fifth transistor is connected to the control circuit and receives a fifth switch control signal; the control terminal of the sixth transistor is connected to the control circuit and receives a sixth switch control signal; and the control terminal of the seventh transistor is connected to the control circuit and receives a seventh switch control signal.

[0048] Preferably, when a load is connected to the output port, the fourth switch control signal and the fifth switch control signal control the fourth transistor and the fifth transistor to conduct alternately, the sixth switch control signal controls the sixth transistor to be in the conducting state, and the seventh switch control signal controls the seventh transistor to be in the off state.

[0049] Preferably, when a load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the on state, the fifth switch control signal controls the fifth transistor to be in the off state, and the sixth switch control signal and the seventh switch control signal control the sixth transistor and the seventh transistor to be turned on alternately, respectively.

[0050] Preferably, when a load is connected to the output port, the fourth control signal, the fifth control signal, the sixth control signal, and the seventh control signal control the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor to conduct alternately, respectively.

[0051] Preferably, when no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the off state, the sixth switch control signal controls the sixth transistor to be in the on state, and the seventh switch control signal controls the seventh transistor to be in the off state.

[0052] Preferably, the discharge circuit is connected in parallel with the output capacitor.

[0053] Preferably, the discharge circuit includes a second resistor and a third transistor, which are connected in series between the first and second terminals of the output port; the charge on the output capacitor flows through the second resistor and the third transistor in sequence to form a discharge circuit.

[0054] Preferably, the power converter further includes a first transistor, a second transistor, and a first inductor; wherein the first transistor and the first inductor are connected to a first terminal of the DC source and a first terminal of the output port; the second transistor is connected between a first node between the first transistor and the first inductor and a second terminal of the output port; a first resistor and a third transistor are connected in series between the two ends of the output capacitor; the control terminal of the first transistor is connected to a control circuit and receives a first switch control signal; the control terminal of the second transistor is connected to a control circuit and receives a second switch control signal; and the control terminal of the third transistor is connected to a control circuit and receives a third switch control signal.

[0055] Preferably, when a load is connected to the output port, the first switch control signal and the second switch control signal are out of phase, respectively controlling the first transistor and the second transistor to alternately turn on and off, and the third switch control signal controls the third transistor to turn off.

[0056] Preferably, when no load is connected to the output port, the first switch control signal controls the first transistor to be in the off state, the second switch control signal controls the second transistor to be in the off state, and the third switch control signal controls the third transistor to be in the on state.

[0057] Preferably, the discharge circuit includes a third resistor and an eighth transistor, and the charge on the output capacitor flows sequentially through the third resistor and the eighth transistor to form a discharge circuit.

[0058] Preferably, the power converter further includes a fourth to an eighth transistor and a second inductor, wherein the fourth and fifth transistors are connected in series between a first terminal and a second terminal of the DC source; the sixth and seventh transistors are connected in series between a first terminal and a second terminal of the output port; the second inductor is connected between a second node between the fourth and fifth transistors and a third node between the sixth and seventh transistors; a third resistor and the eighth transistor are connected in series between the two ends of the output capacitor; the control terminal of the fourth transistor is connected to a control circuit and receives a fourth switch control signal; the control terminal of the fifth transistor is connected to a control circuit and receives a fifth switch control signal; the control terminal of the sixth transistor is connected to a control circuit and receives a sixth switch control signal; the control terminal of the seventh transistor is connected to a control circuit and receives a seventh switch control signal; and the control terminal of the eighth transistor is connected to a control circuit and receives an eighth switch control signal.

[0059] Preferably, when a load is connected to the output port, the fourth switch control signal and the fifth switch control signal control the fourth transistor and the fifth transistor to conduct alternately, the sixth switch control signal controls the sixth transistor to be in the conducting state, the seventh switch control signal controls the seventh transistor to be in the off state, and the eighth switch control signal controls the eighth transistor to be in the off state.

[0060] Preferably, when a load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the on state, the fifth switch control signal controls the fifth transistor to be in the off state, the sixth switch control signal and the seventh switch control signal respectively control the sixth transistor and the seventh transistor to be alternately turned on, and the eighth switch control signal controls the eighth transistor to be in the off state.

[0061] Preferably, when a load is connected to the output port, the fourth control signal, the fifth control signal, the sixth control signal and the seventh control signal control the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor to be turned on alternately, and the eighth switch control signal controls the eighth transistor to be in the off state.

[0062] Preferably, when no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the off state, the sixth switch control signal controls the sixth transistor to be in the on state, the seventh switch control signal controls the seventh transistor to be in the off state, and the eighth switch control signal controls the eighth transistor to be in the on state.

[0063] According to the charging circuit of this invention, under the conditions of using simpler components and lower cost, the discharge circuit reuses the power converter or provides a discharge channel separately for the output capacitor. When a load is connected to the output port, it outputs a stable output voltage, and when no load is connected to the output port, it reduces the output voltage to a preset value, achieving the same effect as a traditional fast charging circuit (i.e., a combination of a DC-DC circuit and a load switch). This reduces the number of circuit components, lowers circuit losses, and thus improves conversion efficiency; it also reduces size and lowers cost. Attached Figure Description

[0064] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0065] Figure 1 A schematic block diagram of a charging circuit in the prior art is shown.

[0066] Figure 2 A schematic block diagram of a charging circuit according to a first embodiment of the present invention is shown.

[0067] Figure 3 A schematic block diagram of the control circuit in the charging circuit according to a first embodiment of the present invention is shown.

[0068] Figure 4 Show Figure 2 The diagram shows an exemplary operating waveform of the charging circuit.

[0069] Figure 5 A schematic block diagram of a charging circuit according to a second embodiment of the present invention is shown.

[0070] Figure 6 A schematic block diagram of the control circuit in the charging circuit according to a second embodiment of the present invention is shown.

[0071] Figure 7 A schematic block diagram of a charging circuit according to a third embodiment of the present invention is shown.

[0072] Figure 8 A schematic block diagram of a charging circuit according to a fourth embodiment of the present invention is shown.

[0073] Figure 9 A schematic block diagram of the control circuit in the charging circuit according to a fourth embodiment of the present invention is shown.

[0074] Figure 10 A schematic block diagram of a charging circuit according to a fifth embodiment of the present invention is shown.

[0075] Figure 11 A schematic block diagram of the control circuit in a charging circuit according to a fifth embodiment of the present invention is shown.

[0076] Figure 12 A schematic block diagram of a charging circuit according to a sixth embodiment of the present invention is shown.

[0077] Figure 13 A schematic block diagram of the control circuit in a charging circuit according to a sixth embodiment of the present invention is shown.

[0078] Figure 14 A schematic block diagram of a charging circuit according to a seventh embodiment of the present invention is shown.

[0079] Figure 15 A schematic block diagram of a charging circuit according to an eighth embodiment of the present invention is shown.

[0080] Figure 16 A schematic block diagram of the control circuit in the charging circuit according to the eighth embodiment of the present invention is shown. Detailed Implementation

[0081] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0082] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0083] The charging circuit provided in this embodiment of the invention includes a DC source, at least one power converter, and a control circuit to support fast charging at least one output port (e.g., a USB port). Each power converter is a DC-DC conversion circuit, and the control circuit controls the power converter to charge the load when a load is connected and to reduce the output voltage of the power converter to a preset value when no load is connected. In this embodiment of the invention, the USB port can be Type-A, Type-C, etc., and the power converter can be a boost, buck, or buck-boost circuit, etc.

[0084] In the following embodiments, one of the charging circuits will be used as an example (see details). Figure 2 , Figure 5 , Figure 7 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 15 This will be explained in more detail. In some other embodiments, the charging circuit includes at least two charging circuits.

[0085] Figure 2 A schematic block diagram of a charging circuit according to a first embodiment of the present invention is shown. Figure 2As shown, the charging circuit 20 includes a DC source 21, a power converter 22, a control circuit 23, an output port 24, and a discharge circuit.

[0086] The DC source 21 provides a DC supply voltage. In this embodiment, the DC source 21 includes a DC source unit 21a and a first capacitor C1. The DC source unit 21a converts the AC input voltage into a DC supply voltage, and the first capacitor C1 filters the DC supply voltage output by the DC source unit 21a. The DC supply voltage is, for example, 5V, but is not limited to this.

[0087] Power converter 22 is connected to the DC source 21 and converts the DC supply voltage DC into an output voltage Vo. The power converter includes an output capacitor Cout, connected between the first and second terminals of the output port 24. In this embodiment, the power converter is a buck circuit.

[0088] The control circuit 23 is connected to the load Load and the power converter 22. Based on the status signal VL of the load Load and the output voltage Vo, it generates a switching control signal for the power converter 22 to adjust the output voltage Vo. The status signal VL of the load Load indicates whether a load Load is connected to the output port 24. When a load Load is connected to the output port 24, the switching control signal controls the corresponding power converter 22 to generate a stable output voltage Vo.

[0089] The bleeder circuit provides a discharge path for the output capacitor Cout. When no load is connected to the output port 24, the output capacitor Cout reduces the output voltage Vo to a preset value through the bleeder circuit.

[0090] The charging circuit provided in this embodiment of the invention, using simpler components and lower cost, utilizes the transistors of the power converter in the discharge circuit to provide a discharge path for the output capacitor. When a load is connected to the output port, it outputs a stable output voltage; when no load is connected, it reduces the output voltage to a preset value, achieving the same effect as a traditional fast charging circuit (i.e., a combination of a DC-DC converter circuit and a load switch). This reduces the number of circuit components, lowers losses, and thus improves conversion efficiency; it also reduces size and lowers cost.

[0091] It should be understood that various power converters and control circuits that achieve a rapid reduction of the output voltage to a preset value are applicable to this embodiment, and are not limited to the power converters and control circuits described in the specification.

[0092] like Figure 2As shown, the power converter 22 includes a first transistor Q1, a second transistor Q2, a first inductor L1, and an output capacitor Cout. The first transistor Q1 and the first inductor L1 are connected in series between the first terminal of the DC source 21 and the first terminal of the output port 24. The output capacitor Cout is connected between the first terminal and the second terminal of the output port 24. The second transistor Q2 is connected between the first node A between the first transistor Q1 and the first inductor L1 and the second terminal of the output port 24. The control terminals of the first transistor Q1 and the second transistor Q2 are respectively connected to the control circuit 23. The switching control signals include a first switching control signal Vg1 and a second switching control signal Vg2. Specifically, the control terminal of the first transistor Q1 is connected to the control circuit 23 and receives the first switching control signal Vg1; the control terminal of the second transistor Q2 is connected to the control circuit 23 and receives the second switching control signal Vg2.

[0093] Output port 24 is connected to the power converter 22, and when a load Load is connected, output port 24 charges the load Load; when no load Load is connected, it discharges the load Load to reduce the output voltage Vo to a preset value. Specifically, when no load Load is connected, the discharge circuit reuses the power converter 22 to provide a discharge path for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

[0094] The discharge circuit includes a first inductor L1, a first transistor Q1, and a first capacitor C1, wherein the first capacitor C1 is connected between the first terminal and the second terminal of the DC source 21; the charge on the output capacitor Cout flows sequentially through the first inductor L1, the first transistor Q1, and the first capacitor C1 to form a discharge circuit.

[0095] Alternatively, the discharge circuit includes a first inductor L1 and a second transistor Q2, and the charge on the output capacitor Cout flows sequentially through the first inductor L1 and the second transistor Q2 to form a discharge circuit.

[0096] When no load is connected to output port 24, the first switch control signal Vg1 controls the first transistor Q1 to be in synchronous rectification or off state, and the second switch control signal Vg2 controls the second transistor Q2 to alternately turn on and off, thus disconnecting the power converter 22 from the DC source 21. When the second transistor Q2 is on, the charge on the output capacitor Cout flows sequentially through the first inductor L1 and the second transistor Q2 to form a discharge circuit, causing the output voltage Vo to decrease to a preset value. When the second transistor Q2 is off, the charge on the output capacitor Cout flows sequentially through the first inductor L1, the first transistor Q1, and the first capacitor C1 to form a discharge circuit. When the first transistor Q1 is off, the first transistor Q1 freewheels in reverse through its body diode.

[0097] In a preferred embodiment, when no load is connected to the output port 24, the first switch control signal Vg1 controls the first transistor Q1 to be in the off state, thereby disconnecting the power converter 22 from the DC source 21. The second switch control signal Vg2 controls the second transistor Q2 to operate in the constant current region. The charge on the output capacitor Cout flows sequentially through the first inductor L1 and the second transistor Q2 to form a discharge circuit, thereby reducing the output voltage Vo to a preset value.

[0098] In a preferred embodiment, when no load is connected to the output port 24, the first switch control signal Vg1 controls the first transistor Q1 to be in the off state, thereby disconnecting the power converter 22 from the DC source 21. The second switch control signal Vg2 controls the second transistor Q2 to be in the on state. The charge on the output capacitor Cout flows sequentially through the first inductor L1 and the second transistor Q2 to form a discharge circuit, thereby reducing the output voltage Vo to a preset value.

[0099] Figure 4 Show Figure 1 The diagram shows an exemplary operating waveform of the charging circuit. Figure 4As shown, at time t0, the load Load is removed, and output port 24 is not connected to the load Load. The status signal VL of the load Load changes from high to low, the first switch control signal Vg1 changes from high to low, and the first transistor Q1 is turned off. During t0-t3, the status signal VL of the load Load remains low, the first switch control signal Vg1 remains low, and the first transistor Q1 remains off. At time t0, the second switch control signal Vg2 changes from low to high, the second transistor Q2 turns on, and the output capacitor Cout discharges through the second transistor Q2, causing the current IQ2 of the second transistor Q2 to rise in the reverse direction. At time t1, the second switch control signal Vg2 changes from high to low, the second transistor Q2 turns off, and the current IQ2 of the second transistor Q2 decreases to 0. At this time, the charge on the output capacitor Cout charges the first capacitor C1 through the first inductor L1 and the first transistor Q1, and the body diode of the first transistor Q1 freewheels. At time t2, the second switch control signal Vg2 changes from low to high, and the second transistor Q2 turns on again. During time t2-t3, the second transistor Q2 periodically turns on and off until the output capacitor Cout is completely discharged. At time t3, a load Load is detected connected to output port 24. The status signal VL of the load Load changes from low to high, the second switch control signal Vg2 changes from high to low, the second transistor Q2 turns off, the first switch control signal Vg1 changes from low to high, the first transistor Q1 turns on, and the current IQ1 of the first transistor Q1 increases. The energy of the DC source 21 is transferred to the load Load via the first transistor Q1 and the first inductor L1. At time t4, the first switch control signal Vg1 changes from high to low, the second switch control signal Vg2 changes from low to high, the first transistor Q1 turns off, the second transistor Q2 turns on, the current IQ1 of the first transistor Q1 decreases to 0, and the current of the first inductor L1 freewheels through the load Load and the second transistor Q2. At time t5, the first switch control signal Vg1 goes high again, the second switch control signal Vg2 goes low, the first transistor Q1 turns on, and the second transistor Q2 turns off. During t3-t6, the first transistor Q1 and the second transistor Q2 alternately turn on. At time t6, the load Load is removed, and output port 24 is no longer connected to the load Load. The load Load status signal VL changes from high to low, the first switch control signal Vg1 changes from high to low, and the second switch control signal Vg2 changes from low to high.

[0100] Figure 3 A schematic block diagram of the control circuit in a charging circuit according to a first embodiment of the present invention is shown. Figure 3As shown, the control circuit 23 includes an operational amplifier 231, a sawtooth wave generation module 232, a comparator 233, a first logic module 234, a PWM generation module 235, a second logic module 236, a third logic module 237, and a fourth logic module 238.

[0101] Operational amplifier 231 is connected to output port 24 to obtain a sampling signal of output voltage Vo, and the sampling signal of output voltage Vo is compared with reference voltage Vref to obtain error signal Vcomp; sawtooth wave generation module 232 provides sawtooth wave signal; comparator 233 is connected to operational amplifier 231 and sawtooth wave generation module 232, and generates first PWM control signal PWM1 according to error signal Vcomp and sawtooth wave signal; first logic module 234 is connected to load Load and comparator 233, and generates first switching control signal Vg1 according to state signal VL of load Load and first PWM control signal PWM1. PWM generation module 235 provides a second PWM control signal PWM2; second logic module 236 is connected to the load Load and generates a first logic signal based on the state signal VL of the load Load; third logic module 237 is connected to the second logic module 236 and the PWM generation module 235 and generates a second logic signal based on the first logic signal and the second PWM control signal PWM2; fourth logic module 238 is connected to the first logic module 234 and the third logic module 237 and generates a second switch control signal Vg2 based on the first switch control signal Vg1 and the second logic signal.

[0102] In this embodiment, the first logic module 234 is an AND gate, the second logic module 236 is a NOT gate, the third logic module 237 is an AND gate, and the fourth logic module 238 is a NOR gate.

[0103] When a load is connected to the output port 24, the first switch control signal Vg1 and the second switch control signal Vg2 are out of phase, respectively controlling the first transistor Q1 and the second transistor Q2 to alternately turn on and off, thereby maintaining the stability of the output voltage Vo. That is, the power converter 22 generates a stable output voltage Vo to charge the load Load.

[0104] Figure 5 A schematic block diagram of a charging circuit according to a second embodiment of the present invention is shown. The charging circuit 30 includes a DC source 31, a power converter 32, a control circuit 33, an output port 34, and a discharge circuit.

[0105] Compared to the charging circuit of the first embodiment, the main difference of the charging circuit 30 according to the second embodiment is that the discharge circuit includes a first inductor L1, a first resistor R1, and a third transistor Q3. The charge on the output capacitor Cout flows sequentially through the first inductor L1, the first resistor R1, and the third transistor Q3 to form a discharge circuit. The power converter 32 includes a first transistor Q1, a second transistor Q2, a first inductor L1, and an output capacitor Cout. The first transistor Q1 and the first inductor L1 are connected in series at the first terminal of the DC source 31 and the first terminal of the output port 34. The output capacitor Cout is connected between the first terminal and the second terminal of the output port 34. The second transistor Q2 is connected between the first node A between the first transistor Q1 and the first inductor L1 and the second terminal of the output port 34. The first resistor R1 and the third transistor Q3 are connected in series between the first node A and the second terminal of the output port 34. The control terminals of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are respectively connected to the control circuit 33.

[0106] The switch control signals include a first switch control signal Vg1, a second switch control signal Vg2, and a third switch control signal Vg3. Specifically, the control terminal of the first transistor Q1 is connected to the control circuit 33 and receives the first switch control signal Vg1; the control terminal of the second transistor Q2 is connected to the control circuit 33 and receives the second switch control signal Vg2; and the control terminal of the third transistor Q3 is connected to the control circuit 33 and receives the second switch control signal Vg3.

[0107] Output port 34 is connected to the power converter 32. When a load Load is connected, output port 34 charges the load Load, and when no load Load is connected, it discharges the load Load to reduce the output voltage Vo to a preset value. When no load Load is connected, the discharge circuit reuses the power converter 32 to provide a discharge path for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

[0108] When a load Load is connected to the output port 34, the first switch control signal Vg1 and the second switch control signal Vg2 are out of phase, respectively controlling the first transistor Q1 and the second transistor Q2 to alternately turn on and off. The third switch control signal Vg3 controls the third transistor Q3 to be in the off state, thereby maintaining the stability of the output voltage Vo. That is, the power converter 32 generates a stable output voltage Vo to charge the load Load.

[0109] Specifically, when a load Load is connected to the output port 34, the first transistor Q1 is turned on, and the second transistor Q2 and the third transistor Q3 are turned off. The current of the power converter 32 flows through the first terminal of the DC source 31, through the first transistor Q1, the first inductor L1, the load Load, and finally to ground. When the second transistor Q2 is turned on, the first transistor Q1 and the third transistor Q3 are turned off. The current in the first inductor L1 cannot change abruptly. The current in the first inductor L1 flows through the load Load and the second transistor Q2, and then returns to the first inductor L1, forming a freewheeling loop.

[0110] When the load is removed from the output port 34, the first transistor Q1 and the second transistor Q2 are turned off, thereby cutting off the voltage of the preceding stage. At the same time, the third transistor Q3 is turned on, and the charge on the output capacitor Cout flows through the first inductor L1, the first resistor R1 and the third transistor Q3 in sequence to form a discharge circuit, causing the output voltage Vo to drop to the preset value.

[0111] Specifically, when no load Load is connected to the output port 34, the first switch control signal Vg1 controls the first transistor Q1 to be in the off state, the second switch control signal Vg2 controls the second transistor Q2 to be in the off state, so that the power converter 32 is disconnected from the DC source 31, and the third switch control signal Vg3 controls the third transistor Q3 to be in the on state. The charge on the output capacitor Cout flows through the first inductor L1, the first resistor R1 and the third transistor Q3 in sequence to form a discharge circuit, so as to reduce the output voltage Vo to a preset value.

[0112] Figure 6 A schematic block diagram of the control circuit in a charging circuit according to a second embodiment of the present invention is shown. Figure 6 As shown, the control circuit 33 includes an operational amplifier 331, a sawtooth wave generation module 332, a comparator 333, a first logic module 334, a fifth logic module 335, a sixth logic module 336, and a seventh logic module 337.

[0113] Operational amplifier 331 is connected to output port 34 to obtain a sampling signal of output voltage Vo. The sampling signal of output voltage Vo is compared with reference voltage Vref to obtain an error signal Vcomp. Sawtooth wave generation module 332 provides a sawtooth wave signal. Comparator 333 is connected to operational amplifier 331 and sawtooth wave generation module 332, and generates a first PWM control signal PWM1 based on the error signal Vcomp and the sawtooth wave signal. First logic module 334 is connected to load Load and comparator 333, and generates a first switch control signal Vg1 based on the state signal VL of load Load and the first PWM control signal PWM1. Fifth logic module 335 is connected to first logic module 334, and generates a fifth logic signal based on the first switch control signal Vg1. Sixth logic module 336 is connected to fifth logic module 335 and load Load, and generates a second switch control signal Vg2 based on the fifth logic signal and the state signal VL of load Load. The seventh logic module 337 is connected to the load Load and generates a third switch control signal Vg3 based on the status signal VL of the load Load.

[0114] In this embodiment, the first logic module 334 is an AND gate, the fifth logic module 335 is a NOT gate, the sixth logic module 336 is an AND gate, and the seventh logic module 337 is a NOT gate.

[0115] The remaining aspects of the charging circuit 30 according to the second embodiment are the same as those of the first embodiment, and therefore will not be described in detail.

[0116] Figure 7 A schematic block diagram of a charging circuit according to a third embodiment of the present invention is shown. The charging circuit 40 includes a DC source 41, a power converter 42, a control circuit 43, an output port 44, and a discharge circuit.

[0117] The main difference between the charging circuit of the second embodiment and the charging circuit 40 of the third embodiment is that the discharge circuit is connected in parallel with the output capacitor, and the discharge circuit includes a first resistor R1 and a third transistor Q3, which are connected in series across the output capacitor Cout. When no load Load is connected, the discharge circuit is connected in parallel with the output capacitor, providing a discharge path for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

[0118] When the load is removed from the output port 44, the first transistor Q1 and the second transistor Q2 are turned off, thereby cutting off the voltage of the preceding stage. At the same time, the third transistor Q3 is turned on, and the charge on the output capacitor Cout flows through the first resistor R1 and the third transistor Q3 in sequence to form a discharge circuit, causing the output voltage Vo to drop to the preset value.

[0119] Specifically, when no load Load is connected to the output port 44, the first switch control signal Vg1 controls the first transistor Q1 to be in the off state, the second switch control signal Vg2 controls the second transistor Q2 to be in the off state, so that the power converter 42 is disconnected from the DC source 41, and the third switch control signal Vg3 controls the third transistor Q3 to be in the on state. The charge on the output capacitor Cout flows through the first resistor R1 and the third transistor Q3 in sequence to form a discharge circuit, so as to reduce the output voltage Vo to a preset value.

[0120] The remaining aspects of the charging circuit 40 according to the third embodiment are the same as those of the second embodiment, and therefore will not be described in detail.

[0121] Figure 8 A schematic block diagram of a charging circuit according to a fourth embodiment of the present invention is shown. The charging circuit 50 includes a DC source 51, a power converter 52, a control circuit 53, an output port 54, and a discharge circuit.

[0122] The main difference between the charging circuit of the first embodiment and the charging circuit of the fourth embodiment is that the discharge circuit includes a first inductor L1 and a second resistor R2, and the charge on the output capacitor Cout flows sequentially through the first inductor L1 and the second resistor R2 to form a discharge circuit. The power converter 52 includes a first transistor Q1, a second transistor Q2, a first inductor L1, and an output capacitor Cout.

[0123] In this circuit, the first transistor Q1 and the first inductor L1 are connected in series at the first terminal of the DC source 51 and the first terminal of the output port 54. The output capacitor Cout is connected between the first terminal and the second terminal of the output port 54. The second transistor Q2 is connected between the first node A between the first transistor Q1 and the first inductor L1 and the second terminal of the output port 54. The second resistor R2 is connected between the first node A and the control terminal of the first transistor Q1. The control terminals of the first transistor Q1 and the second transistor Q2 are respectively connected to the control circuit 53.

[0124] The switch control signals include a first switch control signal Vg1 and a second switch control signal Vg2. Specifically, the control terminal of the first transistor Q1 is connected to the control circuit 53 and receives the first switch control signal Vg1; the control terminal of the second transistor Q2 is connected to the control circuit 53 and receives the second switch control signal Vg2.

[0125] Output port 54 is connected to the power converter 52. When a load Load is connected, output port 54 charges the load Load, and when no load Load is connected, it discharges the load Load to reduce the output voltage Vo to a preset value. When no load Load is connected, the discharge circuit reuses the power converter 52 to provide a discharge path for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

[0126] When a load Load is connected to the output port 54, the first switch control signal Vg1 and the second switch control signal Vg2 are out of phase, controlling the first transistor Q1 and the second transistor Q2 to alternately turn on and off, thereby maintaining the stability of the output voltage Vo. That is, the power converter 52 generates a stable output voltage Vo to charge the load Load. Specifically, when a load Load is connected to the output port 54, the first transistor Q1 is turned on and the second transistor Q2 is turned off. The current flows through the first terminal of the DC source 51, through the first transistor Q1, the first inductor L1, the load Load, and finally to ground, forming a power supply circuit. When the second transistor Q2 is turned on, the first transistor Q1 is turned off. The current in the first inductor L1 cannot change abruptly. The current in the first inductor L1 flows through the load Load and the second transistor Q2, and then returns to the first inductor L1, forming a freewheeling circuit.

[0127] When no load is connected to the output port 54, the first switch control signal Vg1 controls the first transistor Q1 to be in the off state, and the second switch control signal Vg2 controls the second transistor Q2 to be in the off state, thus disconnecting the power converter 52 from the DC source 51 and reducing the output voltage Vo of the power converter 52 to a preset value. Specifically, when the load Load is removed from the output port 54, the first transistor Q1 and the second transistor Q2 are turned off, thereby cutting off the voltage of the preceding stage. The charge on the output capacitor Cout flows sequentially through the first inductor L1 and the second resistor R2 to form a discharge circuit, causing the output voltage Vo to drop to the preset value.

[0128] Figure 9 A schematic block diagram of the control circuit in a charging circuit according to a fourth embodiment of the present invention is shown. Figure 9 As shown, the control circuit 43 includes an operational amplifier 531, a sawtooth wave generation module 532, a comparator 533, a first logic module 534, a fifth logic module 535, and a sixth logic module 536.

[0129] Operational amplifier 531 is connected to output port 54 to obtain a sampling signal of output voltage Vo. The sampling signal of output voltage Vo is compared with reference voltage Vref to obtain an error signal Vcomp. Sawtooth wave generation module 532 provides a sawtooth wave signal. Comparator 533 is connected to operational amplifier 531 and sawtooth wave generation module 532, and generates a first PWM control signal PWM1 based on the error signal Vcomp and the sawtooth wave signal. First logic module 534 is connected to load Load and comparator 533, and generates a first switch control signal Vg1 based on the state signal VL of load Load and the first PWM control signal PWM1. Fifth logic module 535 is connected to first logic module 534, and generates a fifth logic signal based on the first switch control signal Vg1. Sixth logic module 536 is connected to fifth logic module 535 and load Load, and generates a second switch control signal Vg2 based on the fifth logic signal and the state signal VL of load Load.

[0130] In this embodiment, the first logic module 534 is an AND gate, the fifth logic module 535 is a NOT gate, and the sixth logic module 536 is an AND gate.

[0131] The remaining aspects of the charging circuit 50 according to the fourth embodiment are the same as those of the first embodiment, and therefore will not be described in detail.

[0132] Figure 10 A schematic block diagram of a charging circuit according to a fifth embodiment of the present invention is shown. The charging circuit 60 includes a DC source 61, a power converter 62, a control circuit 63, an output port 64, and a discharge circuit.

[0133] Compared to the charging circuit of the first embodiment, the main difference of the charging circuit 60 according to the fifth embodiment is that the discharge circuit includes a sixth transistor Q6, a second inductor L2, a fourth transistor Q4, and a first capacitor C1; the charge on the output capacitor Cout flows sequentially through the sixth transistor Q6, the second inductor L2, the fourth transistor Q4, and the first capacitor C1 to form a discharge circuit. Alternatively, the discharge circuit includes a sixth transistor Q6, a second inductor L2, and a fifth transistor Q5, and the charge on the output capacitor Cout flows sequentially through the sixth transistor Q6, the second inductor L2, and the fifth transistor Q5 to form a discharge circuit. Alternatively, the discharge circuit includes a sixth transistor Q6 and a seventh transistor Q7, and the charge on the output capacitor Cout flows sequentially through the sixth transistor Q6 and the seventh transistor Q7 to form a discharge circuit. The power converter 62 includes the fourth to seventh transistors (Q4-Q7), the second inductor L2, and the output capacitor Cout. In this embodiment, the power converter is a buck-boost circuit.

[0134] In this configuration, the fourth transistor Q4 and the fifth transistor Q5 are connected in series between the first and second terminals of the DC source 61; the sixth transistor Q6 and the seventh transistor Q7 are connected in series between the first and second terminals of the output port 64; the second inductor L2 is connected between the second node B between the fourth transistor Q4 and the fifth transistor Q5 and the third node C between the sixth transistor Q6 and the seventh transistor Q7; and the output capacitor Cout is connected between the first and second terminals of the output port 64. The control terminals of the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are respectively connected to the control circuit 63.

[0135] The switch control signals include a fourth switch control signal Vg4, a fifth switch control signal Vg5, a sixth switch control signal Vg6, and a seventh switch control signal Vg7. The control terminal of the fourth transistor Q4 is connected to the control circuit 63 and receives the fourth switch control signal Vg4; the control terminal of the fifth transistor Q5 is connected to the control circuit 63 and receives the fifth switch control signal Vg5; the control terminal of the sixth transistor Q6 is connected to the control circuit 63 and receives the sixth switch control signal Vg6; and the control terminal of the seventh transistor Q7 is connected to the control circuit 63 and receives the seventh switch control signal Vg7.

[0136] Output port 64 is connected to the power converter 62, and when a load (Load) is connected to output port 64, the load is charged. Specifically, when a load (Load) is connected to output port 64, the fourth to seventh transistors (Q4-Q7) are controlled by the control circuit 63 to make the power converter 62 operate in buck mode, boost mode, and buck-boost mode. Specifically, when the power converter 62 operates in buck mode, the fourth switch control signal Vg4 and the fifth switch control signal Vg5 control the fourth transistor Q4 and the fifth transistor Q5 to conduct alternately, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in the conducting state, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in the off state. When the power converter 62 operates in boost mode, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in the conducting state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in the off state, and the sixth switch control signal Vg6 and the seventh switch control signal Vg7 control the sixth transistor Q6 and the seventh transistor Q7 to conduct alternately. When the power converter 62 operates in buck-boost mode, the fourth control signal Vg4, the fifth control signal Vg5, the sixth control signal Vg6 and the seventh control signal Vg7 control the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 to be turned on alternately.

[0137] Discharging reduces the output voltage Vo to a preset value when no load is connected. When no load is connected, the discharge circuit reuses the transistor of the power converter 62 to provide a discharge path for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

[0138] Specifically, when no load Load is connected to the output port 64, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in a synchronous rectification or off state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to alternately turn on and off, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in a conducting state, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in a off state. When the fifth transistor Q5 is on, the charge on the output capacitor Cout flows sequentially through the sixth transistor Q6, the second inductor L2, and the fifth transistor Q5 to form a discharge circuit; when the fifth transistor Q5 is off, the charge on the output capacitor Cout flows sequentially through the sixth transistor Q6, the second inductor L2, the fourth transistor Q4, and the first capacitor C1 to form a discharge circuit, causing the output voltage Vo to decrease to a preset value. When the fourth transistor Q4 is off, the fourth transistor Q4 freewheels in reverse through its body diode.

[0139] In a preferred embodiment, when no load Load is connected to the output port 64, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in the off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to operate in the constant current region, and the fifth switch control signal Vg5 controls the fifth transistor Q5 to operate in the constant current region; the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in the off state, or operate in the variable resistance region, or operate in the constant current region, or be in the on state. The charge on the output capacitor Cout flows sequentially through the sixth transistor Q6, the second inductor L2, and the fifth transistor Q5 to form a discharge circuit, causing the output voltage Vo to decrease to a preset value.

[0140] In a preferred embodiment, when no load Load is connected to the output port 64, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in the off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to operate in the constant current region, the fifth switch control signal Vg5 controls the fifth transistor Q5 to operate in the off state, the variable resistance region, the constant current region, or the on state, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to operate in the constant current region. The charge on the output capacitor Cout flows sequentially through the sixth transistor Q6 and the seventh transistor Q7 to form a discharge circuit, causing the output voltage Vo to decrease to a preset value.

[0141] In a preferred embodiment, when no load Load is connected to the output port 64, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in the off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in the on state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in the on state, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in the off state or to operate in the variable resistance region. The charge on the output capacitor Cout flows sequentially through the sixth transistor Q6, the second inductor L2, and the fifth transistor Q5 to form a discharge circuit, causing the output voltage Vo to decrease to a preset value.

[0142] In a preferred embodiment, when no load Load is connected to the output port 64, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in the off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in the on state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in the on state, off state, or operating in the variable resistance region, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in the on state. The charge on the output capacitor Cout flows sequentially through the sixth transistor Q6 and the seventh transistor Q7 to form a discharge circuit, causing the output voltage Vo to decrease to a preset value.

[0143] Figure 11 A schematic block diagram of the control circuit in a charging circuit according to a fifth embodiment of the present invention is shown. Figure 11 As shown, the control circuit 63 includes an operational amplifier 631, a sawtooth wave generation module 632, a comparator 633, a first logic module 634, a PWM generation module 635, a second logic module 636, a third logic module 637, a fourth logic module 638, and a seventh logic module 639.

[0144] Operational amplifier 631 is connected to output port 64 to obtain a sampling signal of output voltage Vo, and compares the sampling signal of output voltage Vo with reference voltage Vref to generate an error signal Vcomp; sawtooth wave generation module 632 provides a sawtooth wave signal; comparator 633 is connected to operational amplifier 631 and sawtooth wave generation module 632, and generates a first PWM control signal PWM1 based on the error signal Vcomp and the sawtooth wave signal; seventh logic module 639 is connected to load Load, and generates a fifth switch control signal Vg5 based on the state signal VL of load Load. First logic module 634 is connected to load Load and comparator 633, and generates a seventh switch control signal Vg7 based on the state signal VL of load Load and the first PWM control signal PWM1. PWM generation module 635 provides a second PWM control signal PWM2; a second logic module 636 is connected to the load Load and generates a first logic signal based on the load Load's state signal VL; a third logic module 637 is connected to the second logic module 636 and the PWM generation module 635 and generates a second logic signal based on the first logic signal and the second PWM control signal PWM2; a fourth logic module 638 is connected to the first logic module 634 and the third logic module 637 and generates a sixth switch control signal Vg6 based on the first switch control signal Vg1 and the second logic signal. The fourth switch control signal Vg6 is consistent with the load Load's state signal VL.

[0145] In this embodiment, the first logic module 634 is an AND gate, the second logic module 636 is a NOT gate, the third logic module 637 is an AND gate, the fourth logic module 638 is a NOR gate, and the seventh logic module 639 is a NOT gate.

[0146] The remaining aspects of the charging circuit 60 according to the fifth embodiment are the same as those of the first embodiment, and therefore will not be described in detail.

[0147] Figure 12 A schematic block diagram of a charging circuit according to a sixth embodiment of the present invention is shown. The charging circuit 70 includes a DC source 71, a power converter 72, a control circuit 73, an output port 74, and a discharge circuit.

[0148] Compared to the charging circuit of the fifth embodiment, the main difference of the charging circuit 70 according to the fifth embodiment is that the discharge circuit includes a sixth transistor Q6, a second inductor L2, a third resistor R3, and an eighth transistor Q8, wherein the sixth transistor Q6, the second inductor L2, the third resistor R3, and the eighth transistor Q8 are connected in series between the first and second terminals of the output port; the charge on the output capacitor flows sequentially through the sixth transistor Q6, the second inductor L2, the third resistor R3, and the eighth transistor Q8 to form a discharge circuit. The power converter 72 includes the fourth to seventh transistors (Q4-Q7), the second inductor L2, and the output capacitor Cout.

[0149] In this circuit, the fourth transistor Q4 and the fifth transistor Q5 are connected in series between the first and second terminals of the DC source 71; the sixth transistor Q6 and the seventh transistor Q7 are connected in series between the first and second terminals of the output port 74; the second inductor L2 is connected between the second node B between the fourth transistor Q4 and the fifth transistor Q5 and the third node C between the sixth transistor Q6 and the seventh transistor Q7; the output capacitor Cout is connected between the first and second terminals of the output port 74. The third resistor R3 and the eighth transistor Q8 are connected in series between the second node B and the second terminal of the output port 74. The control terminals of the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 are respectively connected to the control circuit 73.

[0150] The switch control signals include a fourth switch control signal Vg4, a fifth switch control signal Vg5, a sixth switch control signal Vg6, a seventh switch control signal Vg7, and an eighth switch control signal Vg8. The control terminal of the fourth transistor Q4 is connected to the control circuit 73 and receives the fourth switch control signal Vg4; the control terminal of the fifth transistor Q5 is connected to the control circuit 73 and receives the fifth switch control signal Vg5; the control terminal of the sixth transistor Q6 is connected to the control circuit 73 and receives the sixth switch control signal Vg6; the control terminal of the seventh transistor Q7 is connected to the control circuit 73 and receives the seventh switch control signal Vg7; and the control terminal of the eighth transistor Q8 is connected to the control circuit 73 and receives the eighth switch control signal Vg8.

[0151] Output port 74 is connected to the power converter 72, and output port 74 charges the load Load when the load Load is connected, and discharges the load Load to reduce the output voltage Vo to a preset value when the load Load is not connected. Specifically, when the load Load is not connected, the discharge circuit reuses the power converter 72 to provide a discharge path for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

[0152] When a load (Load) is connected to the output port 74, the four transistors Q4-Q7 of the power converter 72 operate in the same state as in the fifth embodiment, and will not be described again here. The eighth transistor Q8 is in the off state under the control of the control circuit 73.

[0153] When the load Load is removed from the output port 74, under the control of the control circuit 73, the fourth transistor Q4, the fifth transistor Q5 and the seventh transistor Q7 are turned off, and the sixth transistor Q6 and the eighth transistor Q8 are turned on. The output capacitor Cout, together with the sixth transistor Q6, the third resistor R3 and the eighth transistor Q8, forms a discharge circuit to release the charge on the output capacitor Cout, so that the output voltage Vo drops to the preset value.

[0154] Specifically, when no load is connected to the output port 74, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in the off state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in the off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in the on state, the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in the off state, and the eighth switch control signal Vg8 controls the eighth transistor Q8 to be in the on state.

[0155] Figure 13 A schematic block diagram of the control circuit in a charging circuit according to a sixth embodiment of the present invention is shown. Figure 13 As shown, the control circuit 73 includes an operational amplifier 731, a sawtooth wave generation module 732, a comparator 733, a first logic module 734, a fifth logic module 735, a sixth logic module 736, a seventh logic module 737, and a low-level generation module 738.

[0156] Operational amplifier 731 is connected to output port 74 to obtain a sampling signal of output voltage Vo, and compares the sampling signal of output voltage Vo with reference voltage Vref to generate an error signal Vcomp; sawtooth wave generation module 732 provides a sawtooth wave signal; comparator 733 is connected to operational amplifier 731 and sawtooth wave generation module 732, and generates a first PWM control signal PWM1 based on the error signal Vcomp and the sawtooth wave signal; first logic module 734 is connected to load Load and comparator 733, and generates a seventh switch control signal Vg7 based on the state signal VL of load Load and the first PWM control signal PWM1; fifth logic module 735 is connected to first logic module 734, and generates a fifth logic signal based on the seventh switch control signal Vg7; sixth logic module 736 is connected to fifth logic module 735 and load Load, and generates a sixth switch control signal Vg6 based on the fifth logic signal and the state signal VL of load Load. The seventh logic module 737 is connected to the load Load and generates an eighth switch control signal Vg8 based on the load Load's status signal VL. The fourth switch control signal Vg4 is consistent with the load Load's status signal VL. The low-level generation module 738 generates a fifth switch control signal Vg5, which is always at a low level.

[0157] In this embodiment, the first logic module 734 is an AND gate, the fifth logic module 735 is a NOT gate, the sixth logic module 736 is an AND gate, and the seventh logic module 737 is a NOT gate.

[0158] The remaining aspects of the charging circuit 70 according to the sixth embodiment are the same as those of the fifth embodiment, and therefore will not be described in detail.

[0159] Figure 14 A schematic block diagram of a charging circuit according to a seventh embodiment of the present invention is shown. The charging circuit 80 includes a DC source 81, a power converter 82, a control circuit 83, an output port 84, and a discharge circuit.

[0160] The main difference between the charging circuit of the sixth embodiment and the charging circuit of the seventh embodiment is that the discharge circuit of the output capacitor Cout includes a third resistor R3 and an eighth transistor Q8, which are connected in series across the output capacitor Cout. When no load Load is connected, the discharge circuit is connected in parallel with the output capacitor Cout, providing a discharge path for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

[0161] When the load is removed from the output port 84, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 are turned off, thereby cutting off the voltage of the preceding stage. At the same time, the eighth transistor Q8 is turned on, and the charge on the output capacitor Cout flows through the third resistor R3 and the eighth transistor Q8 in sequence to form a discharge circuit, causing the output voltage Vo to drop to the preset value.

[0162] Specifically, when no load Load is connected to the output port 84, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in the off state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in the off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in the off state, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in the off state, thereby disconnecting the power converter 82 from the DC source 81. The eighth switch control signal Vg8 controls the eighth transistor Q8 to be in the on state, and the charge on the output capacitor Cout flows through the third resistor R3 and the eighth transistor Q8 in sequence to form a discharge circuit, so as to reduce the output voltage Vo to a preset value.

[0163] The remaining aspects of the charging circuit 80 according to the seventh embodiment are the same as those of the sixth embodiment, and therefore will not be described in detail.

[0164] Figure 15 A schematic block diagram of a charging circuit according to an eighth embodiment of the present invention is shown. The charging circuit 90 includes a DC source 91, a power converter 92, a control circuit 93, an output port 94, and a discharge circuit.

[0165] The main difference between the charging circuit of the fifth embodiment and the charging circuit of the seventh embodiment is that the discharge circuit includes a sixth transistor Q6, a second inductor L2, and a fourth resistor R4. The sixth transistor Q6, the second inductor L2, and the fourth resistor R4 are connected in series between the first terminal of the output port and the control circuit. The charge on the output capacitor flows sequentially through the sixth transistor Q6, the second inductor L2, and the fourth resistor R4 to form a discharge circuit. The power converter 92 includes fourth to seventh transistors (Q4-Q7), a second inductor L2, and an output capacitor Cout.

[0166] In this circuit, the fourth transistor Q4 and the fifth transistor Q5 are connected in series between the first and second terminals of the DC source 51; the sixth transistor Q6 and the seventh transistor Q7 are connected in series between the first and second terminals of the output port 94; the second inductor L2 is connected between the second node B between the fourth transistor Q4 and the fifth transistor Q5 and the third node C between the sixth transistor Q6 and the seventh transistor Q7; the output capacitor Cout is connected between the first and second terminals of the output port 94. The fourth resistor R4 is connected between the control terminal of the fourth transistor Q4 and the second node B. The control terminals of the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are respectively connected to the control circuit 93.

[0167] The switch control signals include a fourth switch control signal Vg4, a fifth switch control signal Vg5, a sixth switch control signal Vg6, and a seventh switch control signal Vg7. The control terminal of the fourth transistor Q4 is connected to the control circuit 93 and receives the fourth switch control signal Vg4; the control terminal of the fifth transistor Q5 is connected to the control circuit 93 and receives the fifth switch control signal Vg5; the control terminal of the sixth transistor Q6 is connected to the control circuit 93 and receives the sixth switch control signal Vg6; and the control terminal of the seventh transistor Q7 is connected to the control circuit 93 and receives the seventh switch control signal Vg7.

[0168] Output port 94 is connected to the power converter 92, and output port 94 charges the load Load when the load Load is connected, and discharges the load Load to reduce the output voltage Vo to a preset value when the load Load is not connected. Specifically, when the load Load is not connected, the discharge circuit reuses the power converter 92 to provide a discharge path for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

[0169] When a load (Load) is connected to output port 94, the four transistors Q4-Q7 of the power converter 92 operate in the same state as in the fifth embodiment, and will not be described again here. When the load (Load) is removed from output port 94, under the control of the control circuit 93, the fourth transistor Q4, the fifth transistor Q5, and the seventh transistor Q7 are turned off, and the sixth transistor Q6 is turned on. The output capacitor Cout, together with the sixth transistor Q6, the second inductor L2, and the fourth resistor R4, forms a discharge circuit, releasing the charge on the output capacitor Cout, causing the output voltage Vo to drop to a preset value.

[0170] When no load Load is connected to the output port 94, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in the off state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in the off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in the on state, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in the off state. The charge on the output capacitor Cout is released through the fourth resistor R4, reducing the output voltage Vo to a preset value.

[0171] Figure 16 A schematic block diagram of the control circuit in a charging circuit according to an eighth embodiment of the present invention is shown. Figure 16 As shown, the system includes an operational amplifier 931, a sawtooth wave generation module 932, a comparator 933, a first logic module 934, a fifth logic module 935, a sixth logic module 936, and a low-level generation module 938.

[0172] Operational amplifier 931 is connected to output port 94 to obtain a sampling signal of output voltage Vo, and compares the sampling signal of output voltage Vo with reference voltage Vref to generate an error signal Vcomp. Sawtooth wave generation module 932 provides a sawtooth wave signal. Comparator 933 is connected to operational amplifier 931 and sawtooth wave generation module 932, and generates a first PWM control signal PWM1 based on the error signal Vcomp and the sawtooth wave signal. First logic module 934 is connected to load Load and comparator 933, and generates a seventh switch control signal Vg7 based on the state signal VL of load Load and the first PWM control signal PWM1. Fifth logic module 935 is connected to first logic module 934, and generates a fifth logic signal based on the seventh switch control signal Vg7. Sixth logic module 936 is connected to fifth logic module 935 and load Load, and generates a sixth switch control signal Vg6 based on the fifth logic signal and the state signal VL of load Load. The fourth switch control signal Vg4 is consistent with the state signal VL of load Load. The low-level generation module 938 generates a fifth switch control signal Vg5, which is always at a low level.

[0173] In this embodiment, the first logic module 934 is an AND gate, the fifth logic module 935 is a NOT gate, and the sixth logic module 936 is an AND gate.

[0174] The remaining aspects of the charging circuit 90 according to the seventh embodiment are the same as those of the fifth embodiment, and therefore will not be described in detail.

[0175] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A charging circuit, comprising: DC power source, providing DC power supply voltage; At least one power converter is connected to the DC source to convert the DC supply voltage into an output voltage; At least one output port is connected to the power converter to charge the load; The control circuit generates a switching control signal for the power converter based on the load status signal and the output voltage to adjust the output voltage. The load status signal indicates whether the output port is connected to a load. The control circuit controls the power converter to charge the load when a load is connected and to reduce the output voltage of the power converter to a preset value when no load is connected. The power converter includes an output capacitor, which is connected between the first and second terminals of the output port. The charging circuit also includes a discharge circuit, which reuses the power converter. When no load is connected to the output port, the discharge circuit provides a discharge path for the output capacitor. The switch control signal controls the corresponding power converter and discharge circuit to reduce the output voltage across the output capacitor to a preset value. The power converter is a BUCK circuit, including a first transistor, a second transistor, and a first inductor. The first transistor and the first inductor are connected to the first end of the DC source and the first end of the output port. The charge on the output capacitor flows through the first inductor, the first transistor, and the first capacitor in sequence to form a discharge circuit, or the charge on the output capacitor flows through the first inductor and the second transistor in sequence to form a discharge circuit. Alternatively, the power converter is a buck-boost circuit, including a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a second inductor. The fourth and fifth transistors are connected in series between the first and second terminals of the DC source, and the sixth and seventh transistors are connected in series between the first and second terminals of the output port. The charge on the output capacitor flows sequentially through the sixth transistor, the second inductor, the fourth transistor, and the first capacitor to form a discharge circuit; or, the charge on the output capacitor flows sequentially through the sixth transistor, the second inductor, and the fifth transistor to form a discharge circuit; or, the charge on the output capacitor flows sequentially through the sixth transistor and the seventh transistor to form a discharge circuit.

2. The charging circuit according to claim 1, wherein when a load is connected to the output port, the switch control signal controls the corresponding power converter to generate a stable output voltage.

3. The charging circuit of claim 1, wherein, The power converter is a BUCK circuit, and the discharge circuit includes the first inductor, the first transistor, and the first capacitor. The first capacitor is connected between the first and second terminals of the DC source.

4. The charging circuit according to claim 1, wherein, The power converter is a BUCK circuit, and the discharge circuit includes the first inductor and the second transistor. The first inductor and the second transistor are connected in series between the first and second ends of the output port.

5. The charging circuit according to claim 3 or 4, wherein, The first transistor and the first inductor of the BUCK circuit are connected to the first terminal of the DC source and the first terminal of the output port. The second transistor is connected between the first node between the first transistor and the first inductor and the second end of the output port; The control terminal of the first transistor is connected to the control circuit and receives the first switch control signal. The control terminal of the second transistor is connected to the control circuit and receives the second switch control signal.

6. The charging circuit according to claim 5, wherein, When a load is connected to the output port, the first switch control signal and the second switch control signal are out of phase, respectively controlling the first transistor and the second transistor to alternately turn on and off.

7. The charging circuit according to claim 5, wherein, When no load is connected to the output port, the first switch control signal controls the first transistor to be in synchronous rectification or off state, and the second switch control signal controls the second transistor to be in alternating on and off state.

8. The charging circuit according to claim 5, wherein, When no load is connected to the output port, the first switch control signal controls the first transistor to be in the off state, and the second switch control signal controls the second transistor to operate in the constant current region.

9. The charging circuit according to claim 5, wherein, When no load is connected to the output port, the first switch control signal controls the first transistor to be in the off state, and the second switch control signal controls the second transistor to be in the on state.

10. The charging circuit according to claim 1, wherein, The power converter is a step-up / step-down circuit, and the bleeder circuit includes the sixth transistor, the second inductor, the fourth transistor, and the first capacitor. The fourth transistor, the second inductor, and the sixth transistor are connected in series between the first end of the DC source and the first end of the output port. The first capacitor is connected between the first and second terminals of the DC source.

11. The charging circuit according to claim 1, wherein, The power converter is a buck-boost circuit, and the bleeder circuit includes the sixth transistor, the second inductor, and the fifth transistor. The fifth transistor, the second inductor, and the sixth transistor are connected in series between the second terminal of the DC source and the first terminal of the output port.

12. The charging circuit according to claim 1, wherein, The power converter is a buck-boost circuit, and the bleeder circuit includes the sixth transistor and the seventh transistor. The sixth transistor and the seventh transistor are connected in series between the first and second ends of the output port.

13. The charging circuit according to any one of claims 10-12, wherein, The second inductor of the buck-boost circuit is connected between the second node between the fourth and fifth transistors and the third node between the sixth and seventh transistors; The output capacitor is connected between the first and second terminals of the output port. The control terminal of the fourth transistor is connected to the control circuit and receives the control signal of the fourth switch; The control terminal of the fifth transistor is connected to the control circuit and receives the control signal from the fifth switch. The control terminal of the sixth transistor is connected to the control circuit and receives the control signal from the sixth switch. The control terminal of the seventh transistor is connected to the control circuit and receives the control signal from the seventh switch.

14. The charging circuit according to claim 13, wherein, When a load is connected to the output port, the fourth and fifth switch control signals control the fourth and fifth transistors to conduct alternately, respectively. The sixth switch control signal controls the sixth transistor to be in the conducting state, and the seventh switch control signal controls the seventh transistor to be in the off state.

15. The charging circuit according to claim 13, wherein, When a load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the on state, the fifth switch control signal controls the fifth transistor to be in the off state, and the sixth and seventh switch control signals control the sixth and seventh transistors to be turned on alternately, respectively.

16. The charging circuit according to claim 13, wherein, When a load is connected to the output port, the fourth, fifth, sixth, and seventh control signals control the fourth, fifth, sixth, and seventh transistors to conduct alternately, respectively.

17. The charging circuit according to claim 13, wherein, When no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in synchronous rectification or off state, the fifth switch control signal controls the fifth transistor to alternately turn on and off, the sixth switch control signal controls the sixth transistor to be in the on state, and the seventh switch control signal controls the seventh transistor to be in the off state.

18. The charging circuit according to claim 13, wherein, When no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to operate in the constant current region, the sixth switch control signal controls the sixth transistor to operate in the constant current region, and the seventh switch control signal controls the seventh transistor to be in the off state, or operate in the variable resistance region, or operate in the constant current region, or be in the on state.

19. The charging circuit according to claim 13, wherein, When no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the off state or to operate in the variable resistance region or the constant current region or to be in the on state, the sixth switch control signal controls the sixth transistor to operate in the constant current region, and the seventh switch control signal controls the seventh transistor to operate in the constant current region.

20. The charging circuit according to claim 13, wherein, When no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the on state, the sixth switch control signal controls the sixth transistor to be in the on state, and the seventh switch control signal controls the seventh transistor to be in the off state or to operate in the variable resistance region.

21. The charging circuit according to claim 13, wherein, When no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the off state or to operate in the variable resistance region, the sixth switch control signal controls the sixth transistor to be in the on state, and the seventh switch control signal controls the seventh transistor to be in the on state.

22. The charging circuit according to claim 13, wherein, When no load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in the off state, the fifth switch control signal controls the fifth transistor to be in the on state, the sixth switch control signal controls the sixth transistor to be in the on state, and the seventh switch control signal controls the seventh transistor to be in the on state.

23. The charging circuit according to claim 1, wherein, The discharge circuit is connected in parallel with the output capacitor.

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