Multi-phase clock generation circuit
By introducing clock edge detection, delay counting, and frequency division units into the multi-phase clock generation circuit, a set clock signal that meets the design requirements can be directly generated, solving the problem of repeated delay adjustments in the prior art, improving the accuracy of the clock signal, and simplifying the design process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- IPGOAL MICROELECTRONICS (SICHUAN) CO LTD
- Filing Date
- 2025-12-19
- Publication Date
- 2026-04-17
AI Technical Summary
Existing multi-phase clock generation circuits require repeated delay adjustments during the design process to ensure clock phase balance, which increases the design difficulty and number of adjustments, and makes it difficult to achieve high-precision phase output.
By employing a clock edge detection unit, a delay counting unit, and a frequency divider unit, the first and second clock signals with set frequencies are used. The delay counting unit directly counts the signals based on the phase selection signal and divides the signals by the frequency divider unit to generate a set clock signal that matches the design requirements, thus avoiding repeated adjustments.
It improves the accuracy of multi-phase clock signals, simplifies the design process, directly generates the set clock signal that meets the design requirements in one go, and reduces power consumption.
Smart Images
Figure CN121887157A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and more specifically to a multi-phase clock generation circuit. Background Technology
[0003] Multiphase clocks refer to multiple clock signals with the same frequency but different phases in a system. Timing optimization is achieved by controlling the phase difference, and they can be used to solve timing problems in high-speed digital systems or cross-module systems. Data processing using multiphase clocks has led to their widespread application in high-speed serial buses, ADC chips, and other fields.
[0004] Typically, a multi-phase clock generation circuit consists of a delay circuit and a selection circuit. In the delay circuit, the inputs are a low-frequency clock clk1 and a high-frequency clock clk2, where the frequency of the high-frequency clock clk2 is an integer multiple (e.g., n times) of the frequency of the low-frequency clock clk1. The delay circuit is composed of n flip-flops connected in series. The high-frequency clock clk2 is input to the clock control terminal of each flip-flop to control the triggering time of each flip-flop. The low-frequency clock clk1 is input to the data input terminal of the first flip-flop, and the input terminals of subsequent flip-flops are connected to the output terminals of the previous flip-flop. The output terminals of each flip-flop are connected to the selection circuit, thus forming the multi-phase clock (clkp1, clkp2…clkpn) input of the selection circuit.
[0005] In the multi-phase clock generation circuit, the delay circuit delays the low-frequency clock clk1 by 1-n units of time, using the period T of the high-frequency clock clk2 as the unit, thus generating multiple phase clocks (clkp1, clkp2, ..., clkpn). Finally, the selection circuit selects one of the clocks that matches the phase selection signal based on the input phase as the final clock clk3 output. This output clock clk3 has the desired phase difference from the original low-frequency clock clk1. During this process, it is necessary to ensure that the delays (the delay between each flip-flop output and the selection circuit) generated on their transmission paths are consistent for each clock (clkp1, clkp2, ..., clkpn). This ensures that the phase difference between each clock (clkp1, clkp2, ..., clkpn) is fixed, and the desired phase output clock clk3 can be obtained through the selection circuit.
[0006] In the multi-phase clock generation circuit described above, the original low-frequency clock clk1 is successively delayed to generate multiple clocks (clkp1, clkp2, ..., clkpn) with different phases. Then, the clock clk3 that matches the required phase is selected for output. The most critical aspect of this process is ensuring consistent delays across the multiple clocks (clkp1, clkp2, ..., clkpn). This means that the unit delays and routing delays of the multiple clocks (clkp1, clkp2, ..., clkpn) on the transmission channel need to be as balanced as possible. The more clocks there are (the larger the value of n), the more difficult it becomes to achieve phase balance across all clocks, requiring repeated adjustments to the circuit to meet the requirements. Furthermore, in digital circuit design, these delays must be implemented using backend placement and routing tools. Analysis of the netlist and timing files provided by the backend is necessary to determine if the delays between the multi-phase clocks meet the requirements. If not, the results must be fed back to the backend designers to correct the timing and then re-analyze. This necessitates repeated operations to obtain the desired phase clock, increasing the difficulty of backend design and the number of design iterations.
[0007] Therefore, it is necessary to provide an improved multi-phase clock generation circuit that simplifies design and requires no adjustments to overcome the above-mentioned shortcomings. Summary of the Invention
[0009] The purpose of this invention is to provide a multi-phase clock generation circuit. The multi-phase clock generation circuit of this invention has a simple structure, generates the required phase clock at once, and does not require repeated adjustment of the generated clock phase, thereby improving the accuracy of the clock phase.
[0010] To achieve the above objectives, the present invention provides a multi-phase clock generation circuit, comprising a clock edge detection unit, a delay counting unit, and a frequency divider unit. A first clock and a second clock with preset frequencies are respectively input to the clock edge detection unit, wherein the frequency of the second clock is greater than the frequency of the first clock. The clock edge detection unit samples the edge of the first clock through the second clock. When the clock edge detection unit detects the edge of the first clock, the first enable signal output by the clock edge detection unit becomes valid, and the first enable signal is output to the delay counting unit to enable the delay counting unit. An external phase selection signal is input to the delay counting unit. After receiving the valid first enable signal, the delay counting unit starts counting the edges of the second clock signal. When the count reaches the phase selection signal, the second enable signal output by the delay counting unit becomes valid, and the second enable signal is output to the frequency divider unit to enable the frequency divider unit. After receiving the valid second enable signal, the frequency divider unit divides the second clock according to a preset division number to output a preset clock signal. The phase selection signal is the phase of the preset clock signal.
[0011] Preferably, the frequency of the first clock is the same as the frequency of the set clock signal, and the frequency of the second clock is an integer multiple of the frequency of the first clock.
[0012] Preferably, the value of the phase selection signal is greater than 1 and less than the division number of the frequency division unit.
[0013] Preferably, the clock edge detection unit samples the rising edge of the first clock.
[0014] Preferably, the division number of the frequency division unit is the ratio of the second clock frequency to the first clock frequency.
[0015] Preferably, the delay counting unit counts the rising edge of the second clock.
[0016] Preferably, when the number of counts is the same as that of the phase selection signal, the delay counting unit saves the counting result and outputs a second enable signal.
[0017] Compared with the prior art, the multi-phase clock generation circuit of the present invention has a delay counting unit. The specific number of delay counts of the delay counting unit is determined by the phase selection signal. Therefore, the rising edge of the second enable signal output by the delay counting unit is the phase of the set clock signal. Then, the second clock is divided by the frequency division unit to obtain a third clock signal with the same frequency as the first clock signal. The phase of the obtained third clock signal is the rising edge of the second enable signal, and its frequency is the same as the first clock signal, which is the set clock signal required by the design. Therefore, the multi-phase clock generation circuit of the present invention can directly generate the set clock signal in one go according to the design requirements. There is no problem of multi-phase clock balance, no need to repeatedly adjust the delay, making it simpler to implement and the accuracy of the obtained set clock signal is also higher.
[0018] The invention will become clearer from the following description, taken in conjunction with the accompanying drawings, which are used to explain embodiments of the invention. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the structure of a multi-phase clock generation circuit in the prior art.
[0021] Figure 2 This is a block diagram of the multi-phase clock generation circuit of the present invention. Detailed Implementation
[0023] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which similar element reference numerals represent similar elements. As described above, the present invention provides a multi-phase clock generation circuit. The multi-phase clock generation circuit of the present invention has a simple structure, generates the required phase clock at once, and does not require repeated adjustment of the phase of the set clock signal, thereby improving the accuracy of the phase of the set clock signal.
[0024] Please refer to Figure 2 , Figure 2 This is a block diagram of the multi-phase clock generation circuit of the present invention. Figure 2As shown, the multi-phase clock generation circuit of the present invention includes a clock edge detection unit, a delay counting unit, and a frequency division unit. A first clock clk1 and a second clock clk2 with set frequencies are respectively input to the clock edge detection unit, and the second clock clk2 is also respectively input to the delay counting unit and the frequency division unit. In the present invention, the frequency of the second clock clk2 is greater than the frequency of the first clock clk1, that is, the second clock clk2 is a high-frequency clock, the first clock clk1 is a low-frequency clock, and the frequency of the second clock clk2 is an integer multiple of the frequency of the first clock clk1. The frequency of the first clock clk1 is the same as the frequency of the set clock signal, which also makes the frequency of the second clock clk2 an integer multiple of the frequency of the set clock signal. The frequency ratio dv1 of the second clock clk2 and the first clock clk1 (or the set clock signal) is an integer, and the frequency ratio dv1 is input to the frequency division unit before the circuit starts working to provide the frequency division base for the frequency division unit. The clock edge detection unit samples the edge of the first clock clk1 via the second clock clk2. When the clock edge detection unit detects the edge of the first clock clk1, it makes its output first enable signal cn1 valid (set to 1) and outputs it to the delay counting unit to start counting. Specifically, in this invention, the clock edge detection unit samples the rising edge of the first clock clk1, so that the clock edge detection unit sets the first enable signal cn1 to 1 (high level) when the rising edge of the first clock clk1 arrives, and the first enable signal cn1 will remain set to 1 until a reset signal (externally input) is received. In this invention, the edge detection unit is used to detect the rising edge of the first clock clk1, mainly to provide a starting reference point for the subsequent delay counting unit. To ensure that the starting reference point of each subsequent signal is consistent and that timing disorder does not occur; in addition, in the scheme of the present invention, the rising edge of the first clock clk1 is sampled as the effective condition of the first enable signal cn1, but in practical applications, the falling edge of the first clock clk1 can also achieve the same effect, and the rising edge is just a more commonly used method.An external one-phase selection signal sel is input to the delay counting unit. After receiving a valid first enable signal cn1, the delay counting unit starts counting the edges of the second clock signal clk2. When the count reaches the phase selection signal sel, the delay counting unit outputs a valid second enable signal cn2 (i.e., sets the second enable signal cn2 to 1), and outputs the second enable signal cn2 to the frequency division unit; wherein, the phase selection signal sel is set according to the set phase of the clock signal, and the value of the phase selection signal sel is greater than 1 and less than the division ratio dv1, that is, 1 < sel < dv1. After the phase requirement of the set clock signal is determined (the phase selection signal sel is determined), the multiple relationship between the second clock clk2 and the first clock clk1 also needs to be set according to the phase selection signal sel. Therefore, in the actual application process, the phase selection signal sel can be set to different values according to different requirements of the set clock phase, while selecting the frequency of the first clock clk1 that is the same as the set clock frequency, and then setting the appropriate multiple relationship between the second clock clk2 and the first clock clk1, so as to obtain the set clock signal with the required phase; correspondingly, the delay counting unit counts the rising edge of the second clock clk2 according to the phase selection signal sel, that is, counts the number of clock cycles of the second clock clk2. When the count reaches the value of the phase selection signal sel, the counting stops, so that the counting result is the phase of the set clock signal; at the same time, the counting result is also saved. By saving the counting result, the counting result remains unchanged, that is, the delay counting unit stops counting, which can reduce the extra power consumption caused by signal flipping to reduce the power consumption of the entire circuit. When the count of the rising edge of the second clock clk2 by the delay counting unit reaches the phase selection signal sel, the delay counting unit sets the second enable signal cn2 output by it to 1 to make it valid, and outputs the valid second enable signal cn2 to the frequency division unit to enable the frequency division unit. After receiving the valid second enable signal cn2, the frequency division unit divides the second clock clk2 according to the set division ratio dv1; the phase of the set clock signal has been obtained through the counting of the delay counting unit, and after obtaining the phase of the set clock signal, a valid second enable signal cn2 is output to make the frequency division unit start working according to the timing (phase) given by the delay counting unit. The frequency division unit divides the second clock clk2 according to the input division ratio dv1 to obtain a third clock clk3, and the frequency of the third clock clk3 is the same as that of the first clock clk1, and the phase is the phase selection signal sel, that is, the phase of the set clock signal. Therefore, the obtained third clock clk3 is the set clock signal that meets the phase and frequency design requirements.
[0025] Below, please refer to the following: Figure 2 The working process of the multi-phase clock generation circuit of the present invention is described below: Before the circuit starts working, a suitable first clock clk1 and a second clock clk2 are selected according to the phase and frequency of the designed clock signal. It is required that the frequency of the first clock clk1 is the same as the frequency of the set clock signal, and the frequency of the second clock clk2 is an integer multiple of the first clock clk1 and the multiple must be greater than the phase selection signal sel. The ratio of the frequencies of the second clock clk2 and the first clock clk1, i.e., the division number dv1, is input to the frequency division unit, and the phase selection signal sel, which reflects the phase of the set clock signal, is input to the delay counting unit so that the delay counting unit can count according to the phase selection signal sel. When the circuit starts working, both the first clock clk1 and the second clock clk2 are input to the clock edge detection unit. Simultaneously, the second clock clk2 is also input to the delay counting unit and the frequency divider unit. In the clock edge detection unit, the rising edge of the first clock clk1 is sampled using the second clock clk2. Therefore, when the rising edge of the first clock clk1 arrives, the clock edge detection unit obtains this rising edge through the second clock clk2 and sets its output first enable signal cn1 to 1 to make it valid. Then, it outputs the valid first enable signal cn1 to the delay counting unit to enable the delay counting. The delay counter unit begins counting; that is, when the rising edge of the first clock clk1 arrives, the first enable signal cnl is set to 1, and the delay counter unit starts counting. After the delay counter is enabled by the valid first enable signal cn1, it begins counting the rising edge of the second clock clk2, that is, it counts once within one clock cycle of the second clock clk2. When the count value reaches the selected phase signal sel, the counting stops, the current count result is saved, and the previously output second enable signal cn2 is set to 1 to make it valid. Then, the valid second enable signal cn2 is output to the frequency divider unit to enable the frequency divider unit. After the frequency divider unit is enabled by the valid second enable signal cn2, it divides the second clock clk2 according to the division number dv1, thereby outputting the third clock clk3. The frequency of the third clock clk is the same as that of the first clock clk1, and the phase is the phase required by the design. Therefore, the third clock clk3 is the clock that meets the design requirements.
[0026] In summary, the multi-phase clock generation circuit of the present invention, due to the inclusion of the delay counting unit, and the specific number of delay counts by the delay counting unit being determined by the phase selection signal sel, outputs through the delay counting unit... The rising edge of the second enable signal cn2 is the phase of the set clock signal. The second clock clk2 is then divided by the frequency divider dv1 to obtain a third clock signal clk3 with the same frequency as the first clock signal clk1. The phase of the third clock clk3 is the rising edge of the second enable signal cn2, and its frequency is the same as the first clock signal clk1, which is the set clock signal required by the design. Therefore, the multi-phase clock generation circuit of the present invention can directly generate the set clock signal in one go according to the design requirements. There is no problem of multi-phase clock balance, no need to repeatedly adjust the delay, making it simpler to implement and the accuracy of the obtained set clock signal is also higher.
[0027] The present invention has been described above in conjunction with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations made in accordance with the essence of the present invention.
Claims
1. A multi-phase clock generation circuit, characterized in that, The system includes a clock edge detection unit, a delay counting unit, and a frequency divider unit. A first clock and a second clock with pre-set frequencies are input to the clock edge detection unit, where the frequency of the second clock is greater than that of the first clock. The clock edge detection unit samples the edge of the first clock using the second clock. When the clock edge detection unit detects the edge of the first clock, a first enable signal is output from the clock edge detection unit and is then output to the delay counting unit to activate it. An external phase selection signal is input to the delay counting unit. Upon receiving the valid first enable signal, the delay counting unit begins counting the edges of the second clock signal. When the count reaches the phase selection signal, a second enable signal is output from the delay counting unit and is then output to the frequency divider unit to activate it. Upon receiving the valid second enable signal, the frequency divider unit divides the second clock according to a set division number to output a set clock signal. The phase selection signal represents the phase of the set clock signal.
2. The multi-phase clock generation circuit as described in claim 1, characterized in that, The frequency of the first clock is the same as the frequency of the set clock signal, and the frequency of the second clock is an integer multiple of the frequency of the first clock.
3. The multi-phase clock generation circuit as described in claim 2, characterized in that, The value of the phase selection signal is greater than 1 and less than the division number of the frequency division unit.
4. The multi-phase clock generation circuit as described in claim 3, characterized in that, The clock edge detection unit samples the rising edge of the first clock.
5. The multi-phase clock generation circuit as described in claim 3, characterized in that, The division ratio of the frequency divider unit is the ratio of the second clock frequency to the first clock frequency.
6. The multi-phase clock generation circuit as described in claim 3, characterized in that, The delay counting unit counts the rising edge of the second clock.
7. The multi-phase clock generation circuit as described in claim 3, characterized in that, When the number of counts is the same as the phase selection signal, the delay counting unit saves the counting result and outputs a valid second enable signal.