Successive approximation type analog-to-digital converter with multiple bits per cycle in double input range

Abstract

The invention discloses an each-cycle multi-bit successive approximation type analog-to-digital converter in a double input range, which relates to the field of analog-to-digital conversion, and comprises a DAC (Digital-to-Analog Converter) capacitor array, a comparator group, an SAR (Synthetic Aperture Radar) logic unit and a calibration reset logic unit, the SAR is stored and fed back to a lower polar plate switch of the DAC capacitor array to realize SAR quantization; and the calibration reset logic unit is used for calibrating the comparator group, enabling the input of the upper polar plate of the DAC capacitor array to be completely reset, and realizing the expansion of a double input range by controlling the pull-down and rise of the voltage of the upper polar plate in the DAC capacitor array. By optimizing the structure of the comparator and adding a reset stage, the analog-to-digital converter can realize a double input range only through one additional comparison and reset operation, and the problems that the input range is limited and the power consumption, the power, the speed and the precision are difficult to consider at the same time in the prior art are solved.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital conversion technology, and more specifically to a multi-bit successive approximation analog-to-digital converter with twice the input range per cycle. Background Technology

[0002] With the continuous expansion and iteration of advanced CMOS technology, successive approximation register analog-to-digital converters (SAR ADCs) have been widely and deeply applied in many fields such as consumer electronics, industrial control, and medical equipment due to their excellent balance between power consumption, area, and accuracy.

[0003] The sampling speed of a SAR ADC is primarily determined by the comparator's decision time, the settling time of the capacitive digital-to-analog converter (CDAC), and the logic delay. Reducing the number of conversion steps is one solution to improve the sampling speed of a SAR ADC. Multi-bit / cycle SAR ADCs convert more than one bit in a single comparison cycle, thus achieving the same bit resolution with fewer comparisons and accelerating the conversion rate. To achieve this, multiple DACs and comparators are required. Traditional multi-bit / cycle SAR ADCs mitigate the increased input load by introducing a reference DAC, which generates a reference voltage and operates separately from the main signal DAC.

[0004] To further improve the power efficiency of SAR ADCs, various digital-to-analog converter switching schemes and noise cancellation techniques have been proposed. Research has also found that extending the ADC's equivalent input range is another option. From one perspective, under the same supply voltage and signal-to-noise ratio (SNR) requirements, the absolute noise constraint of the circuit is effectively relaxed with a larger input signal. From another perspective, for the required input signal range, the supply voltage can be reduced to achieve the same SNR, thereby reducing the ADC's power consumption and improving power efficiency. This is typically proportional to VDD, which is also convenient for applications with limited supply voltage.

[0005] However, although the industry has proposed many technologies for SAR ADCs, such as the capacitor array and switching logic circuit of the successive approximation ADC disclosed in the document with publication number CN113014263A, which adopts a structure of 3 comparators, the existing technology represented by this document is still limited to ±Vref (Vref is the reference high voltage), which makes it difficult to meet the needs of large signal input scenarios.

[0006] Therefore, it is necessary to propose a new technology that takes into account improving the input range, reducing power consumption, improving power efficiency, and improving quantization speed and accuracy. Summary of the Invention

[0007] This invention addresses the shortcomings and defects of the existing technology by proposing a multi-bit successive approximation analog-to-digital converter (ADC) with twice the input range per cycle. Existing technologies require increasing the number of comparisons to achieve higher accuracy, which is limited by comparator noise. This invention optimizes the comparator structure and adds a reset phase, enabling the ADC to achieve twice the input range with only one additional comparison and reset operation. This not only effectively relaxes the requirements for system noise while maintaining the same accuracy, but also improves one-bit accuracy with almost no sacrifice in other performance aspects. Simultaneously, it improves quantization speed and power efficiency, thus solving the core problems of limited input range, power consumption, power, speed, and accuracy in existing technologies.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A multi-bit successive approximation analog-to-digital converter with twice the input range per cycle includes a digital logic module, a DAC capacitor array, and a comparator group; wherein, The DAC capacitor array includes two sets of differential M-bit binary switched capacitors, where M also represents the number of SAR quantization bits. Each set of differential capacitors includes two upper plates. The upper plates of each set of differential capacitors are connected to the input signal Vin or the reset common-mode voltage Vcm through parallel sampling circuits and reset switches. The lower plates of each set of differential capacitors are connected to the reference high voltage Vref and the reference low voltage GND through a switch array, respectively. The comparator group includes two two-input comparators and two four-input comparators. Each comparator is controlled by a corresponding clock. The positive and negative inputs of the two two-input comparators are respectively connected to the upper plates of two sets of differential capacitors to compare the sign of the voltage on the upper plates of the two sets of differential capacitors. The positive and negative inputs of the two four-input comparators are simultaneously connected to the upper plates of the two sets of differential capacitors to compare the relative magnitude of the voltage difference on the upper plates of the two sets of differential capacitors. The digital logic module includes a SAR logic unit and a calibration and reset logic unit. The SAR logic unit is used to obtain an M-bit SAR quantization code based on the comparison result of the comparator group, store it, and feed it back to the lower plate switch of the DAC capacitor array to realize SAR quantization. The calibration and reset logic unit is used to calibrate the comparator group, and after calibration, to control the sampling circuit to disconnect and the reset switch to turn on, so that all the upper plate inputs of the DAC capacitor array are reset, and to expand the input signal range by twice by controlling the pull-down and rise of the upper plate voltage in each group of differential capacitors.

[0009] The reset common-mode voltage Vcm is half the voltage value of the reference high voltage Vref.

[0010] The sampling process of the DAC capacitor array is as follows: During the conduction of the sampling circuit, when the input signal is at a high level, both groups of differential capacitors sample the differential input signal, and the upper plate voltages of both groups of differential capacitors are Vinp and Vinn. The positive terminal of the lower plate of one group of differential capacitors is connected to the reference high voltage Vref, and the negative terminal is connected to the reference low voltage GND. The positive terminal of the lower plate of the other group of differential capacitors is connected to the reference low voltage GND, and the negative terminal is connected to the reference high voltage Vref.

[0011] The reset process of the DAC capacitor array is as follows: Control the upper plates of both groups of differential capacitors to be disconnected, and reset the lower plate voltages to the reset common-mode voltage Vcm. Based on the charge conservation theorem, in each group of differential capacitors, the voltage of one upper plate is pulled down by a magnitude of Vcm, and the voltage of the other upper plate is lifted by a magnitude of Vcm, so that the upper plates obtain the voltage values of Vinp–Vcm and Vinn+Vcm. Correspondingly, the differential output voltage of the upper plates in the first group of differential capacitors is (Vinp-Vinn)–Vref, and the differential output voltage of the upper plates in the second group of differential capacitors is (Vinp-Vinn)+Vref, which shifts the input signal up and down by a voltage magnitude of Vref, thereby achieving an expansion of twice the input range of the input signal.

[0012] The comparison logic of the two-input comparator in the reset stage is as follows: After sampling is completed, the two two-input comparators obtain the MSB value of the positive and negative of the input signal by comparing the upper plate voltages Vinp and Vinn. If Vinp>Vinn, then MSB = 1, indicating that the first group of differential capacitors is the signal DAC, and the second group of differential capacitors is the reference level DAC. Subsequently, successive approximation quantization processing is performed on the differential output voltage (Vinp-Vinn)–Vref obtained from the first group of differential capacitors. If Vinp<Vinn, then MSB = 0, indicating that the first group of differential capacitors is the reference level DAC, and the second group of differential capacitors is the signal DAC. Subsequently, successive approximation quantization processing is performed on the differential output voltage (Vinp-Vinn)+Vref obtained from the second group of differential capacitors.

[0013] The sampling circuit includes an isolation tube and a sampling tube connected in sequence between the input signal Vin and the upper plate. When the sampling tube needs to be disconnected, the gate voltage of the sampling tube is the reference low voltage GND, and the gate voltage of the isolation tube is the reference high voltage Vref. The maximum voltage of the sampling tube is only 1*Vref. When the sampling tube needs to be conductive, the gate voltages of both the sampling tube and the isolation tube are Vref+VIN.

[0014] The calibration and reset logic unit calibrating the comparator group means that the calibration and reset logic unit feeds back the output result of the comparator group to the inside of the comparator group to achieve foreground calibration of its offset voltage.

[0015] The upper plate of each differential capacitor group is formed by connecting the upper plates of each capacitor, and they are at the same potential.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention optimizes the comparator structure and adds a reset stage mechanism, enabling the analog-to-digital converter to achieve twice the input range with only one additional comparison and reset operation. This not only effectively relaxes the requirements for system noise at the same accuracy, but also improves one bit accuracy with almost no sacrifice of other performance, while improving quantization speed and power efficiency. This solves the core problems of limited input range, power consumption, power, speed and accuracy in the prior art.

[0017] 2. This invention employs upper-level board sampling, resulting in lower switching power consumption. Through multiple comparators and a reference-level DAC, and using 2-bit / cycle comparison technology, the quantization rate is improved. Compared to traditional multi-bit-per-cycle analog-to-digital converters, this invention achieves twice the input range through a single reset operation during the sampling phase. With almost no increase in hardware resources, it effectively improves the input range of the analog-to-digital converter, thereby increasing the signal-to-noise ratio (SNR).

[0018] 3. This invention uses front-end calibration, which calibrates the offset voltage of multiple comparators to near 0 before the analog-to-digital converter starts working. Compared with other multi-comparator architectures, this significantly reduces the corresponding harmonics without affecting the operating speed of the analog-to-digital converter. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the circuit structure of the present invention; Figure 2 This is a schematic diagram of the voltage of the DAC capacitor array during the sampling and reset phases. Figure 3 This is a schematic diagram of the sampling circuit of the present invention; Figure 4 A voltage example diagram of the 2-bit / cycle quantization process with double the input range of the present invention; Figure 5 A diagram showing the correspondence between MSB values, comparator group outputs, and 2-bit codewords; Figure 6 This is a timing diagram for the present invention. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0021] like Figure 1As shown, this invention provides a multi-bit successive approximation analog-to-digital converter (ADC) with twice the input range per cycle. The multi-bit per cycle refers to 2 bits per cycle. It includes a digital logic module, a DAC capacitor array, and a comparator group; wherein... The DAC capacitor array includes two sets of differential M-bit binary switched capacitors, named CDAC1 and CDAC2 respectively. Each set of differential capacitors includes two upper plates, each formed by connecting the upper plates of all capacitors at the same potential, meaning all capacitors share the same upper plate. The upper plates in the first set of differential capacitors are named CDAC1P and CDAC1N, and the upper plates in the second set of differential capacitors are named CDAC2P and CDAC2N. The aforementioned M also represents the SAR quantization bit depth. The M capacitors are numbered C0, C1, ..., CM-1 in ascending order of weight. The upper plate of each differential capacitor group (CDAC1P, CDAC1N, CDAC2P, CDAC2N) is connected to the input signal Vin or the reset common-mode voltage Vcm through a parallel sampling circuit S and a reset switch (R1, R2). The lower plate of each differential capacitor group is connected to the reference high voltage Vref and the reference low voltage GND through a switch array, respectively. The voltage value of the reset common-mode voltage Vcm is half the voltage value of the reference high voltage Vref.

[0022] The comparator group includes two two-input comparators and two four-input comparators, named CMP1, CMP21, CMP22, and CMP3, respectively. Each comparator is controlled by a corresponding clock CLKC1, CLKC21, CLKC22, and CLKC3, and is used to compare the relative magnitudes of the voltages on the upper plates of the DAC capacitor array. The connection method of each comparator is as follows: Figure 1 As shown, the positive and negative inputs of two two-input comparators are connected to the upper plates of two sets of differential capacitors, respectively, to compare the sign of the voltage on the upper plates of the two sets of differential capacitors. Specifically, the positive and negative inputs (1P, 1N) of one two-input comparator CMP21 are connected to the upper plates CDAC1P and CDAC1N of the first set of differential capacitors, respectively, to compare the sign of CDAC1P-CDAC1N. The positive and negative inputs (2P, 2N) of the other two-input comparator CMP22 are connected to the upper plates CDAC2P and CDAC2N of the second set of differential capacitors, respectively, to compare the sign of CDAC2P-CDAC2N. The positive and negative inputs (1P, 1N, 2P, 2N) of two four-input comparators are simultaneously connected to the upper plates of the two sets of differential capacitors, to compare the relative magnitude of the voltage difference (CDAC1P-CDAC1N) and ±(CDAC2P-CDAC2N) on the upper plates of the two sets of differential capacitors.

[0023] The digital logic module ( Figure 1The LOGIC & Calibration component includes a SAR logic unit and a calibration and reset logic unit. The SAR logic unit is used to obtain an M-bit SAR quantization code based on the comparison results of the comparator group, store it, and feed it back to the lower plate switch of the DAC capacitor array to realize SAR quantization. The calibration and reset logic unit is used to calibrate the comparator group, and after calibration, to control the sampling circuit to disconnect and the reset switch to turn on, so that all the upper plate inputs of the DAC capacitor array are reset. It also expands the input signal range by twice by controlling the pull-down and rise of the upper plate voltage in each group of differential capacitors.

[0024] The calibration and reset logic unit calibrates the comparator group by feeding back the output of the comparator group to the comparator group itself, thereby achieving front-end calibration of its offset voltage.

[0025] The multi-bit successive approximation analog-to-digital converter provided by this invention performs a total reset before operation begins, grounding all inputs. The result of this reset is then fed back to the comparator group for calibration. Normal operation then commences. Before normal operation, the input range is doubled by sampling followed by a reset. The specific control logic is as follows: First, a sampling operation is performed using a successive approximation analog-to-digital converter. This sampling operation is implemented by a DAC capacitor array. Specifically, during the conduction of the sampling circuit S, when the input signal is high, both sets of differential capacitors CDAC1 and CDAC2 sample the differential input signal. Figure 2 As shown in (a), the upper plate voltages of the two sets of differential capacitors are Vinp and Vinn; the positive terminal of the lower plate of one set of differential capacitors CDAC1 is connected to the reference high voltage Vref, and the negative terminal is connected to the reference low voltage GND; the positive terminal of the lower plate of the other set of differential capacitors CDAC2 is connected to the reference low voltage GND, and the negative terminal is connected to the reference high voltage Vref.

[0026] Next, a reset operation is performed on the DAC capacitor array. The specific reset process is as follows: Figure 2As shown in (b), the upper plates of the two groups of differential capacitors are disconnected (the sampling circuit S is disconnected), and the lower plate voltages are reset to the reset common-mode voltage Vcm. At this time, based on the law of conservation of charge, in each group of differential capacitors, the voltage of one upper plate is pulled down by a magnitude of Vcm, and the voltage of the other upper plate is raised by a magnitude of Vcm, so that the upper plates obtain voltage values of Vinp–Vcm and Vinn+Vcm. That is, the upper plates of the first group of differential capacitors CDAC1 can obtain voltage values of Vinp–Vcm and Vinn+Vcm, and the upper plates of the second group of differential capacitors CDAC2 can obtain voltage values of Vinn+Vcm and Vinp–Vcm. Correspondingly, the differential output voltage of the upper plates in the first group of differential capacitors is (Vinp-Vinn)–Vref, and the differential output voltage of the upper plates in the second group of differential capacitors is (Vinp-Vinn)+Vref. This can shift the input signal up and down by a voltage magnitude of Vref, thereby achieving an expansion of twice the input range of the input signal.

[0027] Meanwhile, the comparison logic of the two-input comparator in the reset stage is as follows: after sampling is completed, the positive and negative input voltages of the two two-input comparators CMP21 and CMP22 are both Vinp and Vinn at this time. A first comparison is made at this time. By comparing the upper plate voltages Vinp and Vinn, the MSB value of the positive and negative of the input signal is obtained. If Vinp>Vinn, then MSB=1, indicating that the first group of differential capacitors CDAC1 is the signal DAC, and the second group of differential capacitors is the reference level DAC. Subsequently, successive approximation quantization processing is performed on the differential output voltage (Vinp-Vinn)–Vref obtained by the first group of differential capacitors, and the second group of differential capacitors CDAC2 is used to generate different reference levels at corresponding times. Similarly, if Vinp<Vinn, then MSB=0, indicating that the first group of differential capacitors is the reference level DAC, and the second group of differential capacitors is the signal DAC. Subsequently, successive approximation quantization processing is performed on the differential output voltage (Vinp-Vinn)+Vref obtained by the second group of differential capacitors, and the second group of differential capacitors CDAC1 is used to generate different reference levels at corresponding times. Through the foregoing processing, the selection of the signal DAC and the reference level DAC can be achieved.

[0028] Assume that the quantization process of a traditional multi-bit / cycle successive approximation analog-to-digital converter can quantize voltages within the range of [+Vref, -Vref], that is, within the power supply voltage range. Then, after the reset operation proposed by the present invention, voltages within the range of [+2Vref, -2Vref] can be quantized, that is, an expansion of twice the input range is achieved.

[0029] It is important to note that when the input signal amplitude is 2*Vref, the sampling circuit should be designed to withstand high voltage to prevent the MOSFET from breaking down when the input signal is high. This high-voltage-resistant sampling circuit includes an isolation transistor and a sampling transistor connected in sequence between the input signal Vin and the upper plate, such as... Figure 3 As shown in (a), when the sampling transistor needs to be disconnected, the gate voltage of the sampling transistor is the reference low voltage GND, and the gate voltage of the isolation transistor is the reference high voltage Vref. For the sampling transistor, it can be seen that its maximum voltage is only 1*Vref. Figure 3 As shown in (b), when the sampling tube needs to be turned on, the gate voltages of both the sampling tube and the isolation tube are Vref+VIN (achieved using a bootstrap circuit). The sampling tube has a relatively stable VGS voltage, and the on-resistance remains constant, which better ensures the sampling accuracy of the sampling circuit.

[0030] like Figure 4 As shown, this invention exemplifies a 4-bit 2-bit / cycle quantization process based on this double input quantization range technology. The input range is [+2Vref, -2Vref], with Vin assumed to be positive and MSB=1. The second set of differential capacitors CDAC2 is selected as the signal DAC, and the voltage in the range of Vin-Vref∈[+Vref, -Vref] can be processed subsequently, and the last four bits of codeword "0110" are output.

[0031] After selecting the reference level DAC, reset it: connect the upper plate of the differential capacitor of the reference level DAC to the common-mode level Vcm for reset, that is... Figure 1 The R1 or R2 signal is set to 1 to turn on the switch, preparing for the generation of the reference level. In each cycle of the subsequent successive approximation quantization conversion, the lower plate is connected to Vref or GND through the switch array to generate the corresponding reference level Vcm±1 / 4*Vref, Vcm±1 / 8*Vref, ..., Vcm±1 / 2*LSB.

[0032] Next, successive approximation quantization is performed: the clock CLKC controls the comparator group and SAR logic unit to quantize the input signal 2 bits / cycle. Each cycle, two bits of codeword are fed back to the signal DAC based on the outputs of the four comparators. After SAR quantization, the upper plate of the DAC capacitor array generates a residual voltage Vres. Unlike existing 2-bit / cycle successive approximation analog-to-digital converters using three comparators, this invention has an additional 2-input comparator connected to the upper plate of the reference-level DAC. After determining the MSB value, the corresponding CLKC2 clock can be set to 0, thus this comparator does not operate and does not consume additional power. Another difference is that the MSB value, along with the outputs of the other three comparators, affects the selection of the two-bit codeword for this cycle, as shown in the diagram. Figure 5 As shown.

[0033] Finally, the codeword output is as follows: the two-bit codeword obtained in each cycle based on the output results of the two comparators is stored in a register and saved by the digital logic module to restore the input signal.

[0034] The overall work sequence is as follows Figure 6 As shown, after sampling, the CDAC is reset, the MSB value is determined, the reference level is then reset and a corresponding reference level is generated, and successive approximation quantization is performed.

[0035] It is important to note that mismatch offset between multiple comparators can have a significant impact on performance. Therefore, a corresponding calibration and reset logic unit is required to reset all inputs of the two sets of differential capacitors to the common-mode voltage Vcm before the circuit starts working, and to perform front-end calibration to resolve the accuracy loss caused by comparator offset due to mismatch.

[0036] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent features unless otherwise specified. All features or steps in all methods or processes disclosed may be combined in any way, except for mutually exclusive features and / or steps.

Claims

1. A multi-bit successive approximation analog-to-digital converter with twice the input range per cycle, characterized in that: It includes a digital logic module, a DAC capacitor array, and a comparator group; among which, The DAC capacitor array includes two sets of differential M-bit binary switched capacitors, where M also represents the number of SAR quantization bits. Each set of differential capacitors includes two upper plates. The upper plates of each set of differential capacitors are connected to the input signal Vin or the reset common-mode voltage Vcm through parallel sampling circuits and reset switches. The lower plates of each set of differential capacitors are connected to the reference high voltage Vref and the reference low voltage GND through a switch array, respectively. The comparator group includes two two-input comparators and two four-input comparators. Each comparator is controlled by a corresponding clock. The positive and negative inputs of the two two-input comparators are respectively connected to the upper plates of two sets of differential capacitors to compare the sign of the voltage on the upper plates of the two sets of differential capacitors. The positive and negative inputs of the two four-input comparators are simultaneously connected to the upper plates of the two sets of differential capacitors to compare the relative magnitude of the voltage difference on the upper plates of the two sets of differential capacitors. The digital logic module includes a SAR logic unit and a calibration and reset logic unit. The SAR logic unit is used to obtain an M-bit SAR quantization code based on the comparison result of the comparator group, store it, and feed it back to the lower plate switch of the DAC capacitor array to realize SAR quantization. The calibration and reset logic unit is used to calibrate the comparator group, and after calibration, to control the sampling circuit to disconnect and the reset switch to turn on, so that all the upper plate inputs of the DAC capacitor array are reset, and to expand the input signal range by twice by controlling the pull-down and rise of the upper plate voltage in each group of differential capacitors.

2. The per-cycle multi-bit successive approximation analog-to-digital converter with twice the input range according to claim 1, characterized in that: The reset common-mode voltage Vcm is half the voltage value of the reference high voltage Vref.

3. A multi-bit successive approximation analog-to-digital converter with twice the input range per cycle, as described in claim 1 or 2, characterized in that: The sampling process of the DAC capacitor array is as follows: During the conduction of the sampling circuit, when the input signal is high, both sets of differential capacitors sample the differential input signal. The voltages of the upper plates of both sets of differential capacitors are Vinp and Vinn. The positive terminal of the lower plate of one set of differential capacitors is connected to the reference high voltage Vref, and the negative terminal is connected to the reference low voltage GND. The positive terminal of the lower plate of the other set of differential capacitors is connected to the reference low voltage GND, and the negative terminal is connected to the reference high voltage Vref.

4. The per-cycle multi-bit successive approximation analog-to-digital converter with twice the input range according to claim 3, characterized in that: The reset process of the DAC capacitor array is as follows: the upper plates of both sets of differential capacitors are disconnected, and the voltage of the lower plate is reset to the reset common-mode voltage Vcm. Based on the law of charge conservation, in each set of differential capacitors, the voltage of one upper plate is pulled down by a value of Vcm, and the voltage of the other upper plate is raised by a value of Vcm, so that the upper plate obtains the voltage values ​​Vinp–Vcm and Vinn+Vcm. Correspondingly, the differential output voltage of the upper plate in the first set of differential capacitors is (Vinp-Vinn)–Vref, and the differential output voltage of the upper plate in the second set of differential capacitors is (Vinp-Vinn)+Vref, so that the input signal is shifted up and down by a voltage value of Vref, thereby realizing a doubling of the input signal range.

5. A multi-bit successive approximation analog-to-digital converter with twice the input range per cycle according to claim 4, characterized in that: The comparison logic of the two-input comparator in the reset stage is as follows: after sampling is completed, the two two-input comparators obtain the MSB value of the input signal's positive and negative by comparing the upper plate voltages Vinp and Vinn. If Vinp > Vinn, then MSB = 1, indicating that the first group of differential capacitors is the signal DAC and the second group of differential capacitors is the reference level DAC. Subsequently, successive approximation quantization processing is performed on the differential output voltage (Vinp - Vinn) – Vref obtained from the first group of differential capacitors. If Vinp < Vinn, then MSB = 0, indicating that the first group of differential capacitors is the reference level DAC and the second group of differential capacitors is the signal DAC. Subsequently, successive approximation quantization processing is performed on the differential output voltage (Vinp - Vinn) + Vref obtained from the second group of differential capacitors.

6. The per-cycle multi-bit successive approximation analog-to-digital converter with twice the input range according to claim 1, characterized in that: The sampling circuit includes an isolation tube and a sampling tube connected in sequence between the input signal Vin and the upper plate. When the sampling tube needs to be disconnected, the gate voltage of the sampling tube is the reference low voltage GND, and the gate voltage of the isolation tube is the reference high voltage Vref. The maximum voltage of the sampling tube is only 1*Vref. When the sampling tube needs to be turned on, the gate voltages of both the sampling tube and the isolation tube are Vref + VIN.

7. The per-cycle multi-bit successive approximation analog-to-digital converter with twice the input range according to claim 1, characterized in that: The calibration and reset logic unit calibrating the comparator group means that the calibration and reset logic unit feeds back the output result of the comparator group to the inside of the comparator group to achieve foreground calibration of its offset voltage.

8. A multi-bit successive approximation analog-to-digital converter with twice the input range per cycle according to claim 1, characterized in that: The upper plates in each group of differential capacitors are connected together to form the same potential.

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