Systems and methods for determining and signaling low density partity check (LDPC) coding parameters

Abstract

The present disclosure is directed to systems and methods for determining and signaling low density parity check (LDPC) coding parameters. In some embodiments, a system may include a transmitter and one or more processors. The one or more processors may identify bits indicating whether a codeword size is selected from a first set of codeword sizes or a second set of codeword sizes. The one or more processors may select a set of codeword sizes from one of the first set of codeword sizes or the second set of codeword sizes based at least on the bits. The one or more processors may determine the codeword size from the selected set of codeword sizes based at least on a number of available bits. The one or more processors may: encode, via a low density parity check (LDPC) encoder, payload data using an LDPC code to generate encoded data including a codeword having the codeword size; and transmitting, via the transmitter, a frame including the bits and the encoded data.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit and priority of each of the parties to U.S. Provisional Patent Application No. 63 / 708,051, filed October 16, 2024, which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] This disclosure generally relates to systems and methods for improving the coding process and / or determining low-density parity-check (LDPC) coding parameters (e.g., LDPC codeword length, number of LDPC codewords) and for signaling information indicating said parameters. Background Technology

[0004] Error correction codes enable the reliable exchange of information data between a transmitter communication system and a receiver communication system. The transmitter communication system encodes the information data to obtain codewords. A codeword is encoded information data. The transmitter communication system transmits the codeword to the receiver communication system. Due to noise in the communication channel, the transmission received by the receiver communication system may differ from the transmitted codeword. Encoding the information data allows the receiver communication system, with an appropriate decoding process, to recover the information data from the received transmission despite the noise. For example, the transmitter communication system transmits a codeword containing payload data and a parity bit to the receiver communication system. The parity bit allows the receiver communication system to verify whether the received transmission is a valid codeword, and if the received transmission is not a valid codeword, to correct errors in the transmission. In one method, the transmitter communication system may determine encoding parameters, such as the LDPC codeword length, and encode the payload data using said encoding parameters. Summary of the Invention

[0005] In one aspect, this disclosure relates to a system comprising: a transmitter; and one or more processors configured to: identify bits indicating whether a codeword size is selected from a first set of codeword sizes or a second set of codeword sizes; select a set of codeword sizes from either the first set of codeword sizes or the second set of codeword sizes based at least on the bits; determine the codeword size from the selected set of codeword sizes based at least on the number of available bits; encode payload data using LDPC codes via a low-density parity-check (LDPC) encoder to generate encoded data containing codewords having the codeword size; and transmit a frame containing the bits and the encoded data via the transmitter.

[0006] In another aspect, this disclosure relates to a system comprising: a transmitter; and one or more processors configured to: identify bits indicating whether the codeword size is selected from a first set of codeword sizes or a second set of codeword sizes; determine the number of codewords based at least on the bits and the number of available bits; encode payload data using LDPC codes via a low-density parity-check (LDPC) encoder to generate encoded data using the number of codewords; and transmit a frame containing the bits and the encoded data via the transmitter.

[0007] In another aspect, this disclosure relates to a method comprising: identifying, by one or more processors, bits indicating whether a codeword size is selected from a first set of codeword sizes or a second set of codeword sizes; selecting, by the one or more processors, a set of codeword sizes from either the first set of codeword sizes or the second set of codeword sizes based at least on the bits; determining, by the one or more processors, the codeword size from the selected set of codeword sizes based at least on the number of available bits; encoding payload data by the one or more processors using LDPC codes via a low-density parity-check (LDPC) encoder to generate encoded data containing codewords having the codeword size; and transmitting, by the one or more processors, a frame containing the bits and the encoded data via the transmitter. Attached Figure Description

[0008] The various objects, aspects, features, and advantages of this disclosure will become more apparent and better understood through reference to the detailed description taken in conjunction with the accompanying drawings, in which similar reference characters consistently identify corresponding elements. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0009] Figure 1 It is a diagram depicting an exemplary communication environment having a communication system according to one or more embodiments.

[0010] Figure 2 This is a schematic block diagram of a computing system according to an embodiment.

[0011] Figure 3 It is a diagram depicting an exemplary rate matching system according to one or more embodiments.

[0012] Figure 4A , Figure 4B and Figure 4C It is a diagram depicting exemplary rate matching schemes that respectively include shortening, truncating, and repeating according to one or more embodiments.

[0013] Figure 5It is a diagram depicting an exemplary physical layer protocol data unit (PPDU) format comprising bits (e.g., 3888 bits) indicating a particular codeword length, according to one or more embodiments.

[0014] Figure 6A and Figure 6B It is a diagram depicting an exemplary PPDU format comprising bits (e.g., 3888 bits) indicating a particular codeword length according to one or more embodiments.

[0015] Figure 7 It is a flowchart illustrating the process of encoding data using bits (e.g., 3888 bits) indicating a specific codeword length according to one or more embodiments.

[0016] Figure 8 It is a flowchart illustrating the process of encoding data using bits (e.g., 3888 bits) indicating a specific codeword length according to one or more embodiments.

[0017] Details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first feature communicating with or communicatively coupled to a second feature may include embodiments in which the first feature directly communicates with or is directly coupled to the second feature, and may also include embodiments in which an additional feature may be inserted between the first and second features such that the first feature indirectly communicates with or is indirectly coupled to the second feature. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and is not inherently indicative of a relationship between the various embodiments and / or configurations discussed.

[0019] In one aspect, the parity check matrix defines a set of equations that any valid codeword must satisfy. The parity check matrix can be used to encode low-density parity check (“LDPC”) codes, described by Richardson and Urbanke in IEEE Transactions on Information Theory, Vol. 47, No. 2 (February 2001). Generally, many wireless and wired communication systems use LDPC as a forward error correction coding scheme. The term “error correction” refers to techniques used to detect and correct errors that occur during data transmission over a network, or any techniques used to detect and correct errors or alterations in digital data.

[0020] In one aspect, wireless communication standards (e.g., IEEE 802.11n) define LDPC physical layer protocol data unit (PPDU) encoding procedures to map an integer number of data bytes to an integer number of orthogonal frequency division multiplexing (OFDM) symbols, and to an integer number of LDPC codewords. In error correction codes, such as LDPC codes, rate matching techniques can be applied to adjust the code rate to match specific communication requirements. For example, the IEEE 802.11n standard defines the shortening, truncation, and / or repetition patterns of each codeword as rate matching techniques. The explicit payload length signaling defined in standards (e.g., IEEE 802.11n) is replaced by an implicit scheme in IEEE 802.11ac, for example, rounding the payload up to the next forward error correction (FEC) before symbol boundary using FEC pre-padding. This implicit scheme of 802.11ac is extended in IEEE 802.11ax and IEEE 802.11be with a factor "short symbol padding". The 'a' factor value refers to the duration of packet spread (PE) at different FEC front-fill boundaries. For example, an 'a' factor value of 1 indicates a 4 µs or ¼-length symbol, while an 'a' factor value of 4 indicates a 16 µs or 1-length symbol. Short symbols refer to symbols created by reducing the number of subcarriers within a symbol (e.g., OFDM symbols), resulting in shorter symbol durations. For multi-user (MU)-MIMO (Multiple-Input Multiple-Output) and Orthogonal Frequency Division Multiple Access (OFDMA), the payload length can be normalized to a common transmission length using two passes across all users.

[0021] In one aspect, the PPDU encoding process can define the payload length N. pld and the number of available bits N avbits As shown below:

[0022] …………… (Equation 1),

[0023] …………… (Equation 2),

[0024] Where length is the number of octets in the payload; N CBPS It is the number of code bits written per (OFDM) symbol; if space-time block write code (STBC) is used, then U STBC 1 if the value is true, 0 otherwise; and R is the bit rate. N bits are available. avbits It refers to the minimum number of bits in the modulation symbols that the payload can fit.

[0025] In one area, Ultra-High Reliability (UHR) is a new research group within the IEEE 802.11 working group. Its aim is to study PHY (Physical Layer) and MAC (Media Access Control) technologies that can enhance the reliability of WLAN (Wireless Local Area Network) connectivity. The IEEE 802.11bn (UHR) standard is introducing longer LDPC codes (e.g., codes with a block length of 3888 bits). According to amendments in IEEE 802.11, following predefined PPDU coding parameter specifications, the exact codeword size can be determined based on the payload size. The latest revision, IEEE 802.11bn, specifies codeword sizes of 648, 1296, and 1944. To accommodate LDPC codes with larger codeword lengths (e.g., block lengths of 3888 bits), updates to the predefined PPDU coding parameter specifications may be necessary.

[0026] To address these issues, embodiments of this disclosure relate to a technique for providing / supporting / utilizing LDPC signaling with a codeword length of 2 × 1944 bits and PPDU encoding parameters, according to certain aspects. A codeword refers to the output where the encoder's raw data is encoded, a symbol sequence representing encoded data, or encoded data containing the original information and additional redundant bits added for error detection and correction. For flexibility, in some embodiments, signaling bits may be introduced to indicate the use of a 3888-block-length LDPC code in the transmitter. A transmitter in a wireless or wireless network refers to a device or component (software, firmware, hardware, processor, circuitry) capable of transmitting data via an antenna or via a physical transmission medium (e.g., cable, optics, radio waves, microwaves, infrared, optical transmission). In some embodiments, this signaling information may be delivered to a receiver to ensure accurate decoding of the transmitted packets. According to STBC signaling bits m STBC The existing naming convention can be used with the new signaling bit field m. 2xLDPC , making m 2xLDPC =1 indicates that the PPDU encoding process includes LDPC code of length 3888 blocks. In some implementations, the name of the signaling bit field is not limited to m. 2xLDPC For example, signaling bits may be referred to as indicator bits, longer_ldpc, ldpc_2x, 2xLDPC, or 2x1944. In some implementations, the PPDU encoding process may follow the steps outlined in the following tables (e.g., Table 1, Table 2, Table 3, or Table 4).

[0027] In some implementations, the UHR's PPDU may contain signaling bits m 2xLDPCAs part of the UHR-SIG field. For example, a UHR multi-user (MU) PPDU can be used to transmit to one or more users and is not a response to a trigger frame. The term "frame" refers to a data unit used to organize and manage data transmission over a communication network, containing all the information necessary for communication (e.g., source address, destination address, payload, control fields, etc.), or any data packet containing all the information necessary for communication between devices. In some implementations, signaling bits m are included. 2xLDPC The UHR-SIG field can exist in the UHR MU PPDU.

[0028] In some implementations, UHR-triggered (TB) PPDUs can be used for transmissions in response to trigger frames from the AP. In some implementations, the UHR-SIG field is absent in the UHR TB PPDU, and the duration of the UHR-STF (Short Training Field) field is twice the duration of the UHR-STF field in the UHR MU PPDU. In some implementations, UHR variant user information fields can be defined for all trigger frame variants except for Neighbor Discovery Protocol (NDP) Feedback Reporting Polling (NFRP) trigger frames and MU-RTS (Request to Send) TXS (Transmission Opportunity Sharing) trigger frames. In some implementations, the user information field in the TB PPDU may have signaling bits m. 2xLDPC In some implementations, the signaling bit m 2xLDPC It can be bit 26 of the user information field in the TB PPDU.

[0029] In some implementations, in Table 1 below (as option 1), the symbol m 2xLDPC Indicates signaling bit m 2xLDPC , where m 2xLDPC =1 indicates a 3888-bit LDPC codeword size (or length), which is 2 x (the codeword length of a basic 1944-bit LDPC codeword). In some implementations, m 2xLDPC =1 can indicate other LDPC codeword lengths, such as 2x (the codeword length of the basic LDPC code), etc. In some implementations, the signaling bit m 2xLDPC =0 indicates that the codeword size will follow a pre-UHR LDPC scheme, such as 648, 1296, or 1944 bits. In some implementations, the mapping outlined in Table 1 is followed, based on the PPDU payload size (or length) N. pld The number of available bits N avbits m 2xLDPC Alternatively, the coderate R can be selected or determined, specifying a particular codeword size (or length) L. LDPCIn some implementations, the mapping outlined in Table 1 is followed, based on the PPDU payload size (or length) N. pld The number of available bits N avbits m 2xLDPC Alternatively, the code rate R can determine or select a specific number N of codewords. CW .

[0030]

[0031] Table 1. Calculated LDPC codeword size (length) L LDPC and the number of codewords N CW (Option 1)

[0032] In some implementations, in Table 2 below (as option 1a), the symbol m 2xLDPC Indicates signaling bit m 2xLDPC , where m 2xLDPC =1 indicates the size (or length) of a 3888-bit LDPC codeword, which is 2 x (the codeword length of a basic 1944-bit LDPC codeword). In some implementations, m 2xLDPC =1 can indicate other LDPC codeword lengths, such as 2x (the codeword length of the basic LDPC code), etc. In some implementations, the signaling bit m 2xLDPC =0 indicates that the codeword size follows a pre-UHR LDPC scheme, such as 648, 1296, or 1944 bits. In some implementations, the mapping outlined in Table 2 is followed, based on the PPDU payload size (or length) N. pld The number of available bits N avbits m 2xLDPC Alternatively, the coderate R can be selected or determined, specifying a particular codeword size (or length) L. LDPC In some implementations, the mapping outlined in Table 2 is followed, based on the PPDU payload size (or length) N. pld The number of available bits N avbits or m 2xLDPC The number N of specific codewords can be determined or selected. CW .

[0033]

[0034] Table 2. Calculated LDPC codeword size (length) L LDPC and the number of codewords N CW (Option 1a)

[0035] In some implementations, as shown in Table 3 below (as option 2), the symbol m 2xLDPC Indicates signaling bit m 2xLDPC , where m 2xLDPC=1 indicates that the LDPC codeword size is one of 648, 1296, 1944, or 3888 bits. In some implementations, the signaling bit m 2xLDPC =0 indicates that the codeword size follows a pre-UHR LDPC scheme, such as 648, 1296, or 1944 bits. In some implementations, the signaling bits m 2xLDPC =0 indicates that the LDPC codeword size is one of 648, 1296, or 1944 bits. In some implementations, following the mapping outlined in Table 3, it can be based on the PPDU payload size (or length) N. pld The number of available bits N avbits m 2xLDPC Alternatively, the code rate R can be used to select or determine a specific codeword size (or length) L. LDPC In some implementations, following the mapping outlined in Table 3, the mapping can be based on the PPDU payload size (or length) N. pld The number of available bits N avbits m 2xLDPC The code rate R determines or selects a specific number N of codewords. CW .

[0036]

[0037] Table 3. Calculated LDPC codeword size (length) L LDPC and the number of codewords N CW (Option 2)

[0038] In some implementations, in Table 4 below (as option 2a), the symbol m 2xLDPC Indicates signaling bit m 2xLDPC , where m 2xLDPC =1 indicates that the LDPC codeword size is one of 648, 1296, 1944, or 3888 bits. In some implementations, the signaling bit m 2xLDPC =0 indicates that the codeword size follows a pre-UHR LDPC scheme, such as 648, 1296, or 1944 bits. In some implementations, the signaling bits m 2xLDPC =0 indicates that the LDPC codeword size is from one of a set of 648, 1296, or 1944 bits. In some implementations, following the mapping outlined in Table 2, it can be based on the PPDU payload size (or length) N. pld The number of available bits N avbits m 2xLDPC Alternatively, the code rate R can be used to select or determine a specific codeword size (or length) L. LDPC In some implementations, following the mapping outlined in Table 4, the mapping can be based on the PPDU payload size (or length) N. pldThe number of available bits N avbits or m 2xLDPC To determine or select a specific number N of codewords CW .

[0039]

[0040] Table 4. Calculated LDPC codeword size (length) L LDPC and the number of codewords N CW (Option 2a)

[0041] In some implementations, the system (e.g., a communication system for transmitting or receiving data) may use an indicator bit m 2xLDPC To select a 3888-bit codeword, signal the PPDU to be encoded using 3888-bit LDPC code, as outlined in Options 1 (Table 1) and 2 (Table 2). In some implementations, the system may use indicator bits m 2xLDPC Using signals to represent a 3888-bit codeword size is possible, but other codeword sizes such as 648, 1296, or 1944 bits are also possible, as outlined in Option 2 (Table 3) and Option 2a (Table 4).

[0042] In some implementations, the system can decrypt or determine the exact codeword length based on a table (e.g., Table 1, Table 2, Table 3, or Table 4). For example, the system (e.g., the transmitter) can set the indicator bit m after deciding or determining whether to encode the PPDU using LDPC with a 3888-bit codeword. 2xLDPCIn some implementations, the system may decide whether to include a 3888-bit codeword size within a set of possible codeword sizes. In some implementations, the system may make a decision based on at least the following: (1) payload length; (2) modulation size; (3) bandwidth; (4) FFT (Fast Fourier Transform) size; (5) resource unit (RU); (6) data rate; (7) latency requirement; (8) percentage (or number) of truncated bits; (9) ratio of truncated bits to shortened bits; (10) number of spatial streams (NSS); (11) modulation and coding scheme (MCS); or (12) a metric selected according to (1)-(11). Data rate refers to bits per second (bps), kilobits per second (Kbps), megabits per second (Mbps), gigabits per second (Gbps), or any value representing the speed at which data is transmitted from one device to another. Modulation and coding scheme (MCS) refers to a combination of modulation and coding rates and other parameters, or any measure that determines the data rate and robustness of a wireless link. Modulation size refers to the modulation order (e.g., the modulation order in QAM (Quadrature Amplitude Modulation)), or the number of different symbols that can be used to represent data in a modulation scheme. Bandwidth refers to data bandwidth, network bandwidth, digital bandwidth, the maximum data transmission rate across a given path, or the maximum rate at which data can be transmitted over a network connection in a given amount of time. Resource unit (RU) refers to a bandwidth unit used in Orthogonal Frequency Division Multiple Access (OFDMA), or a group of subcarriers or tones within a given frequency bandwidth.

[0043] In some implementations, latency requirements can be a metric based on the application's latency requirements. For example, data transmission in some latency-sensitive applications may be limited to a 3888-bit codeword size. In some implementations, the percentage of truncated bits (or the truncated bit fraction) can be the percentage of bits (e.g., parity bits) that may be truncated (removed) during the LDPC rate matching process. In some implementations, the percentage of truncated bits may vary depending on at least one of the payload length, code rate, and / or modulation and coding scheme (MCS). A higher percentage of truncated bits may result in more severe performance degradation. In some implementations, the system may: (1) place, determine, set, or use a truncating threshold (e.g., a threshold for the number of truncated bits or a threshold percentage) for a given MCS, bandwidth, and RU; (2) compare the percentage (or number) of truncated bits with the truncating threshold; and (3) determine, based on the comparison, whether a 3888-bit codeword size should be included in a set of possible codeword sizes. For example, in response to determining that the percentage of truncated bits is greater than a truncation threshold, the system may decide not to include a 3888-bit codeword size in a set of possible codeword sizes. In some implementations, the truncation threshold is a fixed value.

[0044] In some implementations, the system can dynamically change the truncation threshold. In some implementations, when deciding whether to include a larger codeword size (e.g., a 3888-bit codeword size) within a set of possible codeword sizes, the system can consider the PPDU encoding process, which includes codeword bit shortening, truncation, and repetition. Parity bit truncation can lead to a degraded encoding performance. In some implementations, the system can estimate the relative write performance of 1944-bit and 3888-bit codes for a given scenario based on the number (or percentage) of truncated parity bits. In some implementations, the system can search, select, or identify a parity truncation threshold for 3888-bit codes (with a specific code rate) for which there is no write performance degradation compared to 1944-bit codes (with the same code rate). In some implementations, in response to determining that the number (or percentage) of truncated parity bits is less than an identified threshold, the system can use 3888-bit codes for such scenarios. In some implementations, in response to determining that the number (or percentage) of truncated parity bits exceeds an identified threshold, the system can use a second metric to determine which codeword length to use.

[0045] The embodiments in this disclosure have at least the following advantages and benefits.

[0046] First, the embodiments in this disclosure provide useful techniques for LDPC signaling utilizing a codeword length of 2 × 1944 bits and PPDU encoding parameters. In some embodiments, the system (e.g., a transmitter) can use signaling bits to flexibly indicate the use of 3888-block-length LDPC codes. For example, the signaling bits may indicate the use of 3888-block-length LDPC codes, or include 3888-block-length LDPC codes within a set of possible codeword sizes. In some embodiments, this signaling information may be conveyed to the receiver to ensure accurate decoding of transmitted packets.

[0047] Secondly, the embodiments in this disclosure provide a useful technique for finding, selecting, or identifying a parity truncation threshold for a 3888-bit LDPC code (with a specific code rate), for which there is no degradation in coding performance compared to a 1944-bit LDPC code (with the same code rate). In this way, the system can use a 3888-bit LDPC code when there is no degradation in coding performance compared to a 1944-bit LDPC code.

[0048] refer to Figure 1The diagram illustrates an exemplary communication environment 100 including communication systems (or communication devices) 105, 108 according to one or more embodiments. In one embodiment, communication system 105 includes a baseband circuit system 110 and a transmitter circuit system 120, and communication system 108 includes a baseband circuit system 150 and a receiver circuit system 140. In one aspect, communication system 105 is considered a transmitter communication system, and communication system 108 is considered a receiver communication system. These components operate together to exchange data (e.g., messages or frames) over a wireless medium. In one or more embodiments, these components are embodied as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof. In some embodiments, communication systems 105, 108 include more than Figure 1 The components shown may be more, fewer, or different. For example, each of communication systems 105, 108 includes a transceiver circuitry to allow bidirectional communication between or with other communication systems. In some embodiments, each of communication systems 105, 108 may have similar... Figure 2 The configuration of the computing system 2000 shown in the figure.

[0049] The baseband circuitry 110 of the communication system 105 is a circuitry system that generates baseband data 115 for transmission. The baseband data 115 contains information data (e.g., signals) at a baseband frequency for transmission. In one method, the baseband circuitry 110 includes an encoder 130 that encodes the data and generates or outputs parity bits. In one aspect, the baseband circuitry 110 (or encoder 130) obtains a generator matrix or a parity matrix, or uses a previously generated generator matrix or a previously generated parity matrix, and encodes the information data by applying the information data to the generator matrix or parity matrix to obtain codewords. In some embodiments, the baseband circuitry 110 stores one or more generator matrices or one or more parity matrices conforming to any IEEE 802.11 standard for WLAN communication. The baseband circuitry 110 retrieves the stored generator matrix or the stored parity matrix in response to detecting information data to be transmitted or in response to receiving an instruction to encode the information data. In one method, baseband circuitry 110 generates parity bits based on a portion of a generator matrix or using a parity matrix, and appends the parity bits to information bits to form a codeword. Baseband circuitry 110 generates baseband data 115 containing the codeword of communication system 108, and provides baseband data 115 to transmitter circuitry 120.

[0050] The transmitter circuitry 120 of the communication system 105 includes or corresponds to a circuitry that receives baseband data 115 from the baseband circuitry 110 and transmits a wireless signal 125 based on the baseband data 115. In one configuration, the transmitter circuitry 120 is coupled between the baseband circuitry 110 and an antenna (not shown). In this configuration, the transmitter circuitry 120 up-converts the baseband data 115 from the baseband circuitry 110 to a carrier signal to generate a wireless signal 125 at an RF frequency (e.g., 10 MHz to 60 GHz) and transmits the wireless signal 125 through the antenna.

[0051] The receiver circuitry 140 of communication system 108 is a circuitry that receives radio signal 125 from communication system 105 and obtains baseband data 145 from the received radio signal 125. In one configuration, receiver circuitry 140 is coupled between baseband circuitry 150 and an antenna (not shown). In this configuration, receiver circuitry 140 receives radio signal 125 through the antenna and down-converts radio signal 125 to an RF frequency according to a carrier signal to obtain baseband data 145 from radio signal 125. Receiver circuitry 140 then provides the baseband data 145 to baseband circuitry 150.

[0052] The baseband circuitry system 150 of the communication system 108 includes or corresponds to a circuitry system that receives baseband data 145 from the receiver circuitry system 140 and obtains information data from the received baseband data 145. In one embodiment, the baseband circuitry system 150 includes a decoder 160 that extracts information and parity bits from the baseband data 145. The decoder 160 decodes the baseband data 145 to obtain information data generated by the baseband circuitry system 110 of the communication system 105.

[0053] In some embodiments, each of the baseband circuit system 110 (including encoder 130), transmitter circuit system 120, receiver circuit system 140, and baseband circuit system 150 (including decoder 160) may be one or more processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof.

[0054] Figure 2This is a schematic block diagram of a computing system according to an embodiment. The illustrated exemplary computing system 2000 includes one or more processors 2010 that communicate directly or indirectly with memory 2060 via a communication system 2040 (e.g., a bus), at least one network interface controller 2030 having a network interface port for connecting to a network (not shown), and other components, such as input / output (“I / O”) components 2050. Generally, the processor 2010 executes instructions (or computer programs) received from memory. The illustrated processor 2010 is incorporated into or connected to cache memory 2020. In some cases, instructions are read from memory 2060 into cache memory 2020 and executed by processor 2010 from cache memory 2020. The computing system 2000 may not necessarily include... Figure 2 All of these components shown in the document, and may contain Figure 2 Other components not shown in the image.

[0055] More specifically, processor 2010 can be any logic circuit system that processes instructions (e.g., instructions fetched from memory 2060 or cache 2020). In many embodiments, processor 2010 is a microprocessor unit or a dedicated processor. Computing device 2050 can be based on any processor or set of processors capable of operating as described herein. Processor 2010 can be a single-core or multi-core processor. Processor 2010 can be multiple different processors.

[0056] Memory 2060 can be any device suitable for storing computer-readable data. Memory 2060 can be a device with fixed storage or a device for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), non-volatile memory, media and memory devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic disks, magneto-optical disks, and optical disks (e.g., CD ROM, DVD-ROM, or Blu-ray® optical disks). Computing system 2000 can have any number of memory devices 2060.

[0057] Generally, cache memory 2020 is a form of computer memory placed close to processor 2010 for fast read speeds. In some implementations, cache memory 2020 is part of processor 2010 or on the same chip as processor 2010. In some implementations, there are multiple levels of cache 2020, such as L2 and L3 cache layers.

[0058] Network interface controller 2030 manages data exchange via a network interface (sometimes referred to as a network interface port). Network interface controller 2030 handles the physical and data link layers of the OSI model for network communication. In some embodiments, some tasks of the network interface controller are handled by one or more processors 2010. In some embodiments, network interface controller 2030 is part of processor 2010. In some embodiments, computing system 2000 has multiple network interfaces controlled by a single controller 2030. In some embodiments, computing system 2000 has multiple network interface controllers 2030. In some embodiments, each network interface is a connection point of a physical network link (e.g., a Cat-5 Ethernet link). In some embodiments, network interface controller 2030 supports wireless network connectivity, and the interface port is a wireless (e.g., radio) receiver or transmitter (e.g., for the IEEE 802.11 protocol, Near Field Communication "NFC", Bluetooth, ANT, or any other wireless protocol). In some embodiments, network interface controller 2030 implements one or more network protocols, such as Ethernet. Generally, computing device 2050 exchanges data with other computing devices via a network interface through a physical or wireless link. The network interface can be directly linked to another device or linked to another device via an intermediate device, such as a network device that connects computing device 2000 to a data network, such as the Internet, like a hub, bridge, switch, or router.

[0059] The computing system 2000 may include one or more input or output (“I / O”) devices, or provide interfaces to said one or more input or output devices. Input devices include, but are not limited to, keyboards, microphones, touchscreens, foot pedals, sensors, MIDI devices, and pointing devices such as mice or trackballs. Output devices include, but are not limited to, video displays, speakers, Braille-refreshing terminals, lights, MIDI devices, and 2-D or 3-D printers.

[0060] Other components may include I / O interfaces, external serial device ports, and any additional coprocessors. For example, computing system 2000 may include interfaces (e.g., a Universal Serial Bus (USB) interface) for connecting input devices, output devices, or additional memory devices (e.g., portable flash drives or external media drives). In some embodiments, computing device 2000 includes additional devices such as coprocessors; for example, a mathematical coprocessor can assist processor 2010 in performing high-precision or complex calculations.

[0061] Component 2090 may be configured to connect to external media, display 2070, input device 2080, or any other component or combination thereof in computing system 2000. Display 2070 may be a liquid crystal display (LCD), organic light-emitting diode (OLED) display, flat panel display, solid-state display, cathode ray tube (CRT) display, projector, printer, or other display device now known or hereafter developed for outputting defined information. Display 2070 may serve as an interface for a user to view the functions of processor 2010, or specifically as an interface to software stored in memory 2060.

[0062] Input device 2080 can be configured to allow a user to interact with any component of computing system 2000. Input device 2080 can be a plurality of keypads, keyboards, cursor control devices such as a mouse or joystick. Alternatively, input device 2080 can be a remote control, a touchscreen display (which can be a combination of display 2070 and input device 2080), or any other device operable to interact with computing system 2000, such as any device operable to act as an interface between the user and computing system 2000.

[0063] Figure 3 This is a diagram depicting an exemplary rate matching system 300 according to one or more embodiments. The rate matching system 300 may include a rate matching (RM) controller 310, an LDPC encoder 330, a bit shortener including a first-stage (S1) bit shortener 320-1 and a second-stage (S2) bit shortener 320-2, a parity truncation 340, and / or a bit repeater 350. The term "encoder" refers to any means or component (e.g., software, firmware, hardware, circuitry, or a combination thereof) that performs error correction using error correction codes (ECC) containing LDPC codes, or any means or component (e.g., software, firmware, hardware, circuitry, or a combination thereof) that converts raw data into a write-coded format (e.g., a codeword containing the raw data and additional data for error correction). The S1 bit shortener 320-1 can perform bit shortening by adding shortened bits (e.g., zeros) before encoding, and the S2 bit shortener 320-2 can perform bit shortening removal by removing shortened bits (e.g., zeros) after encoding. The rate matching system 300 may be included in an encoder (e.g., encoder 130) or a baseband circuit system (e.g., baseband circuit system 110). The rate matching system 300 may be implemented as one or more processors, an ASIC, an FPGA, or any combination thereof. The RM controller 310 can receive / acquire / identify / calculate N. pld m 2xLDPC At least one of them, and calculate / obtain the number N of available bits. avbits (For example, using Equation 2), the number of codewords N CWor LDPC codeword length L LDPC (For example, depending on the different implementation, at least one of Tables 1, 2, 3, or 4 may be used.) The RM controller can then calculate N. avbits N CW or L LDPC (As encoder parameters) are provided to the LDPC encoder 330, enabling the LDPC encoder 330 to encode the data according to the encoder parameters.

[0064] In some implementations, the rate matching system 300 may include a bit selector 360, which may be implemented as one or more processors, ASICs, FPGAs, or any combination thereof. After determining whether to encode the PPDU using a 3888-bit codeword LDPC, the bit selector 360 may set (and output) the indicator bit m. 2xLDPC For example, in response to determining that the PPDU will be encoded using a 3888-bit codeword LDPC, the bit selector 360 can select the indicator bit m 2xLDPC Set to 1; otherwise, bit selector 360 can set the indicator bit m 2xLDPC Set to 0. Bit selector 360 can determine whether to include a 3888-bit codeword size in a set of possible codeword sizes. For example, in response to determining that a 3888-bit codeword size is included in a set of possible codeword sizes (for encoding), bit selector 360 can set the indicator bit m. 2xLDPC Set to 1; otherwise, bit selector 360 can set the indicator bit m 2xLDPC Set to 0. The bit selector 360 may make decisions based on at least the following: (1) payload length; (2) modulation size; (3) bandwidth; (4) FFT size; (5) resource unit (RU); (6) data rate; (7) latency requirement; (8) percentage (or number) of truncated bits; (9) ratio of truncated bits to shortened bits; (10) number of space streams (NSS); (11) modulation and coding scheme (MCS); or (12) the metric selected according to (1)-(11).

[0065] In some implementations, bit selector 360 may: (1) place, determine, set, or use a truncation threshold (e.g., a threshold for the number of truncated bits or a threshold for the percentage of truncated bits) for a given MCS, bandwidth, and RU; (2) compare the percentage (or number) of truncated bits with the truncation threshold; and (3) determine, based on the comparison result, whether to include a 3888-bit codeword size in a set of possible codeword sizes. For example, in response to determining that the percentage of truncated bits is greater than the truncation threshold, bit selector 360 may determine not to include a 3888-bit codeword size in a set of possible codeword sizes. In some implementations, the truncation threshold is a fixed value.

[0066] In some implementations, bit selector 360 can dynamically change the truncation threshold. In some implementations, when deciding whether to include a larger codeword size (e.g., a 3888-bit codeword size) within a set of possible codeword sizes, bit selector 360 can consider a PPDU encoding process that includes codeword bit shortening, truncation, and repetition. Parity bit truncation can lead to a degraded coding performance. In some implementations, bit selector 360 can estimate the relative write performance of 1944-bit and 3888-bit codes for a given scenario based on the number (or percentage) of truncated parity bits. In some implementations, bit selector 360 can discover, select, or identify a threshold for parity truncation of 3888-bit codes (with a specific code rate) for which there is no degraded coding performance compared to 1944-bit codes (with the same code rate). In some implementations, in response to determining that the number (or percentage) of truncated parity bits is less than an identified threshold, bit selector 360 may use a 3888-bit code for such scenarios. In some implementations, in response to determining that the number (or percentage) of truncated parity bits exceeds an identified threshold, bit selector 360 may use a second metric to determine which codeword length to use.

[0067] In some implementations, the RM controller 310 may include a parameter selector 370. Following the mappings outlined in Tables 1, 2, 3, or 4, the parameter selector 370 may be based on the PPDU payload size (or length) N. pld The number of available bits N avbits m 2xLDPC Or the code rate R, depending on the different implementation schemes to select or determine the specific codeword size (or length) L. LDPC Following the mappings outlined in Tables 1, 2, 3, or 4, parameter selector 370 can be based on PPDU payload size (or length) N. pld The number of available bits N avbits m 2xLDPC Or the code rate R, which depends on the specific number N of codewords determined or selected based on the different implementation schemes. CW .

[0068] refer to Figure 3 The RM controller 310 can be based on N calculated as above. avbits N CW and / or L LDPC To control at least one of the following: S1 bit shortener 320-1, S2 bit shortener 320-2, parity truncation unit 340, or bit repeater 350. For example, the RM controller 310 can be based on the number of shortened bits N calculated using the following Equation 3. shrtThe value is used to control the S1 bit shortener 320-1 and / or the S2 bit shortener 320-2 using one or more control signals (e.g., short_control 311, short_control 312).

[0069] …………… (Equation 3),

[0070] The shortened bits can be evenly distributed across all codewords, where the first rem(N) shrt , N CW The codeword is shortened by one bit. Here, r = rem(a, b) yields the remainder when a is divided by b, where a is the dividend and b is the divisor.

[0071] The RM controller 310 can be based on the number N of truncated bits calculated using Equation 4 below. punc The value is used to control the parity cutoff 340 using control signals (e.g., punc_control 314).

[0072] …………… (Equation 4).

[0073] The RM controller 310 can be based on the number N of repeated bits calculated using Equation 5. rep The value is used to control the bit repeater 350 using control signals (e.g., rep_control 315).

[0074] …………… (Equation 5),

[0075] The repeated bits are evenly distributed across all codewords, with the first rem(N) being the most frequent bit. rep , N CW The codeword also has one repeated bit.

[0076] Figure 4A , Figure 4B and Figure 4C Figures 400, 440, and 480 depict exemplary rate matching schemes that respectively include shortening, truncating, and repetition according to one or more embodiments. Reference Figure 4A Bit shorteners (e.g., S1 bit shortener 320-1 and S2 bit shortener 320-2) can zero-padded data bits (e.g., zero-padded bits or "shortened bits" 401) before encoding to match the number of systematic bits (e.g., systematic bits 402) per codeword, and discard the shortened bits 401 after encoding. In this way, bit shorteners can reduce the effective code rate and improve write code gain.

[0077] refer to Figure 4BA parity truncation (e.g., parity truncation 340) can discard some parity bits (e.g., "truncated bits" 441) after encoding. In this way, parity truncation 340 can increase the effective code rate and degrade the write gain. Reference Figure 4C A bit repeater (e.g., bit repeater 350) can copy some bits from the beginning of the codeword (e.g., "repeated bits" 481). In this way, bit repeater 350 can improve write code gain.

[0078] In some implementations, the system (e.g., transmitter communication system 105) can transmit signaling bit field m 2xLDPC The data is transmitted or delivered to a receiver to ensure accurate decoding of the transmitted packets. For example, system 105 may transmit a frame (e.g., a PPDU) 190, which includes a signaling bit field m in the frame preamble 192. 2xLDPC . Figure 5 This is a diagram depicting an exemplary PPDU format 500 containing bits (e.g., 3888 bits) indicating a specific codeword length. For example, PPDU 500 may be a UHR multi-user (MU) PPDU for transmission to one or more users and is not a response to a trigger frame. PPDU format 500 may include fields for a preamble, data 511, and packet extension (PE) 512. The preamble may include L-STF (non-HT (high throughput) short training field) 501, L-LTF (non-HT long training field) 502, L-SIG (non-HT signal) 503, RL-SIG (repetitive non-HT signal) 504, U-SIG (general signal) 505, UHR-SIG (UHR signal) 506, UHR-STF (UHR non-HT long training field) 507, and / or UHR-LTF (UHR non-HT regular training field) 510-1 to UHR-LTF 510-k. The PPDU500 may contain signaling bits m. 2xLDPC As part of UHR-SIG field 506, it contains signaling bit m. 2xLDPC The UHR-SIG field 506 can exist in UHR MU PPDU 500.

[0079] Figure 6A and Figure 6B This is a diagram depicting an exemplary PPDU format 600, 650 according to one or more embodiments, comprising bits (e.g., 3888 bits) indicating a specific codeword length. Reference Figure 6AA UHR-trigger (TB) based PPDU 600 can be used as a response to a trigger frame from an AP. The PPDU format 600 may include fields for a preamble, data 611, and packet extension (PE) 612. The preamble may include L-STF 601, L-LTF 602, L-SIG 603, RL-SIG 604, U-SIG 605, UHR-STF 606, and / or UHR-LTF 610-1 to UHR-LTF 610-m. In the UHR TB PPDU 600, the UHR-SIG field may be absent, and in the UHR MU PPDU 500, the duration of the UHR-STF field 606 (e.g., 8 μs) may be twice the duration of the UHR-STF field 507 (e.g., 4 μs).

[0080] refer to Figure 6B The UHR variant user information field can be defined for all trigger frame variants except for Neighbor Discovery Protocol (NDP) Feedback Report Polling (NFRP) trigger frames and MU-RTS (Request to Send) TXS (Transmission Opportunity Sharing) trigger frames. The user information field in the UHR TB PPDU can have signaling bits m 2xLDPC .like Figure 6B As shown, the user information field 650 in UHR TB PPDU600 may include AID12 651, RU assignment 652, UL FEC write code type 653, UL UHR-MCS 654, m 2xLDPC Subfields of 655, SS allocation, 656, UL target received power, 657, PS160, 658, and / or trigger-related user information 659. For example... Figure 6B As shown in the figure, signaling bit m 2xLDPC 655 can be bit 26 of the user information field 650 in UHR TB PPDU 600.

[0081] Figure 7 This is a flowchart illustrating a process 700 of encoding data using bits (e.g., 3888 bits) indicating a specific codeword length according to one or more embodiments. In some embodiments, process 700 is performed by one or more processors of a device (e.g., encoder 130 or processor 2010 of communication system 105). In other embodiments, process 700 is performed by other entities (e.g., a computing system other than system 105). In some embodiments, process 700 includes... Figure 7 The steps shown in the document may be more, fewer, or different than those in the document.

[0082] At step 702, one or more processors (e.g., RM controller 310, bit selector 360, parameter selector 370) can identify whether the indicator codeword size is selected from a first set of codeword sizes (e.g., a set of (648, 1296, 1944) bits) or from a second set of codeword sizes (e.g., a set of (648, 1296, 1944, 3888) bits) in bits (e.g., m in UHR-SIG 506). 2xLDPC position, m 2xLDPC (655).

[0083] In some implementations, one or more processors may be configured to identify truncated bits (e.g., during encoding performed by LDPC encoder 330) during the encoding process. Figure 4B The percentage of truncated bits shown in the diagram. One or more processors may be configured to determine that the percentage of truncated bits is greater than a threshold. One or more processors may be configured to... 2xLDPC The bit is set to a first value (e.g., 0) to indicate that the codeword size is selected from the first set of codeword sizes.

[0084] In some implementations, one or more processors may be configured to determine bits (e.g., m) using at least one of the following: payload data length, modulation and coding scheme (MCS), modulation size, bandwidth, resource units, data rate, application latency requirements, percentage of truncated bits, or truncation-to-shortening ratio. 2xLDPC The value of (bit).

[0085] In some implementations, the first set of codeword sizes (e.g., a set of (648, 1296, 1944) bits) may contain a first value (e.g., 1944). The second set of codeword sizes (e.g., a set of (648, 1296, 1944, 3888) bits) may contain a second value that is twice the size of the first value (e.g., 3888). In some implementations, the first set may be a subset of the second set.

[0086] In some implementations, the first codeword size may contain 1944 bits. The first codeword size may contain 648, 1296, or 1944 bits. The second codeword size may contain 3888 bits.

[0087] At step 704, one or more processors may select a set of codeword sizes from either a first set of codeword sizes or a second set of codeword sizes, at least based on the bits. For example, the parameter selector may be based on m 2xLDPC The value of the bit is used to select a group (648, 1296, 1944, 3888) bits.

[0088] At step 706, one or more processors may be based at least on the number of available bits (e.g., N available bits). avbits The number of bits is used to determine the codeword size (or length) L from a selected set of codeword sizes (e.g., a set of (648, 1296, 1944, 3888) bits). LDPC In some implementations, one or more processors may be configured based on the length of the payload data (e.g., PPDU payload size (or length) N). pld The number of available bits can be calculated (e.g., using Equation 2) for error correction. Payload data refers to: (1) user data or messages without any headers, metadata, or other protocol overhead; (2) the actual message or information intended to be transmitted over the network; or (3) the core content of a data packet that the sender wants to deliver to the receiver. For example, Table 1 can be used, based on N... avbits and m 2xLDPC The size of the codeword is determined by the number of bits (e.g., 3888 bits).

[0089] At step 708, one or more processors may encode the payload data using LDPC codes via a low-density parity-check (LDPC) encoder (e.g., LDPC encoder 330) to generate a result containing a codeword size (e.g., codeword size (or length) L). LDPC The encoded data of the codeword.

[0090] At step 710, one or more processors may transmit a frame (e.g., frame 190) containing bits (e.g., bits in preamble 192) and encoded data via a transmitter (e.g., transmitter circuitry 120).

[0091] Figure 8 This is a flowchart illustrating a process 800 of encoding data using bits indicating a specific codeword length (e.g., 3888 bits) according to one or more embodiments. In some embodiments, process 800 is performed by one or more processors of a device (e.g., encoder 130 or processor 2010 of communication system 105). In other embodiments, process 800 is performed by other entities (e.g., a computing system other than system 105). In some embodiments, process 800 includes... Figure 8 The steps shown in the document may be more, fewer, or different than those in the document.

[0092] At step 802, one or more processors (e.g., RM controller 310, bit selector 360, parameter selector 370) can identify whether the indicator codeword size is selected from a first set of codeword sizes (e.g., a set of (648, 1296, 1944) bits) or from a second set of codeword sizes (e.g., a set of (648, 1296, 1944, 3888) bits) in bits (e.g., m in UHR-SIG 506). 2xLDPC position, m 2xLDPC (655).

[0093] In some implementations, one or more processors may be configured to identify truncated bits (e.g., during encoding performed by LDPC encoder 330) during the encoding process. Figure 4B The percentage of truncated bits shown in the diagram. One or more processors may be configured to determine that the percentage of truncated bits is greater than a threshold. One or more processors may be configured to... 2xLDPC The bit is set to a first value (e.g., 0) to indicate that the codeword size is selected from the first set of codeword sizes.

[0094] In some implementations, the first set of codeword sizes (e.g., a set of (648, 1296, 1944) bits) may contain a first value (e.g., 1944). The second set of codeword sizes (e.g., a set of (648, 1296, 1944, 3888) bits) may contain a second value that is twice the size of the first value (e.g., 3888). In some implementations, the first set may be a subset of the second set.

[0095] In some implementations, the first codeword size may contain 1944 bits. The first codeword size may contain 648, 1296, or 1944 bits. The second codeword size may contain 3888 bits.

[0096] At step 804, one or more processors may be based at least on bits (e.g., m). 2xLDPC (bits) and the number of available bits (e.g., N available bits) avbits The number of codewords is determined by the number of (e.g., codeword N). CW (The number of bits). In some implementations, the number of bits, the number of available bits, and the code rate of the LDPC code can be used to determine the number of codewords. For example, Table 1 can be used, based on N... avbits N pld Bitrate R and m 2xLDPC The number N is determined by the number of codewords. CW .

[0097] At step 806, one or more processors may encode the payload data using LDPC codes via a low-density parity-check (LDPC) encoder (e.g., LDPC encoder 330) to use a number of codewords (e.g., the number of codewords N). CW This is used to generate encoded data.

[0098] At step 808, one or more processors may transmit a frame (e.g., frame 190) containing bits (e.g., bits in preamble 192) and encoded data via a transmitter (e.g., transmitter circuitry 120).

[0099] A reference to “or” can be interpreted as inclusive, such that any term described using “or” can refer to any one, more than one, or all of the terms described. A reference to at least one of a consecutive list of terms can be interpreted as inclusive “or”, indicating any one, more than one, or all of the terms described. For example, a reference to “at least one of 'A' and 'B'” can include only 'A', only 'B', or both 'A' and 'B'. Such references used in conjunction with “include” or other open-ended terms can include additional terms.

[0100] It should be noted that certain paragraphs of this disclosure may use terms such as “first” and “second” in connection with subgroups of transmission space streams, probe frames, responses, and devices to identify or distinguish them from one another. These terms are not intended to associate entities (e.g., first device and second device) merely temporally or sequentially, although in some cases such relationships may exist. These terms also do not limit the number of possible entities (e.g., STA, AP, beamformer, and / or beamformee) that may operate in the system or environment. It should be understood that the system described above may provide multiple components of any or each of those components, and these components may be provided on a standalone machine, or, in some embodiments, on multiple machines in a distributed system. Furthermore, the position of bit fields may be varied, and multiple bit words may be used. Additionally, the system and methods described above may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture, such as floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or magnetic tapes. The program can be implemented using any programming language such as LISP, PERL, C, C++, C#, or any bytecode language such as JAVA. The software program or executable instructions can be stored as object code on or within one or more artifacts.

[0101] While the foregoing written description of the methods and systems enables those skilled in the art to make and use embodiments thereof, those skilled in the art will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples described herein. Therefore, the methods and systems herein should not be limited to the embodiments, methods, and examples described above, but rather to all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. A system comprising: Transmitter; and One or more processors, configured as follows: The bit indicating whether the codeword size is selected from the first group of codeword sizes or the second group of codeword sizes; At least based on the bit, a codeword size is selected from either the first set of codeword sizes or the second set of codeword sizes; The codeword size is determined from the selected set of codeword sizes based at least on the number of available bits; The payload data is encoded using LDPC codes via a low-density parity-check LDPC encoder to generate encoded data containing codewords of the stated codeword size; and A frame containing the bits and the encoded data is transmitted via the transmitter.

2. The system according to claim 1, wherein The size of the first group of codewords includes the first value, and The second group of codewords contains a second value that is twice the size of the first value.

3. The system according to claim 2, wherein The first group is a subgroup of the second group.

4. The system of claim 2, wherein the one or more processors are configured to: Identify the percentage of truncated bits during the encoding process performed via LDPC encoding; It is determined that the percentage of truncated bits is greater than the threshold; and The bit is set to a first value to indicate that the codeword size is selected from the first set of codeword sizes.

5. The system according to claim 1, wherein The first group of codeword sizes includes codeword sizes of 648, 1296, or 1944 bits, and The second group of codeword sizes contains 3888 bits of codeword size.

6. The system of claim 1, wherein the one or more processors are configured to: The value of the bit is determined using at least one of the following: the length of the payload data, the modulation and coding scheme (MCS), the modulation size, the bandwidth, the resource unit, the data rate, the application's latency requirements, the percentage of truncated bits, or the ratio of truncated to shortened bits.

7. The system of claim 1, wherein the one or more processors are configured to: The number of available bits is calculated based on the length of the payload data for error correction.

8. A system comprising: Transmitter; and One or more processors, configured as follows: The bit indicating whether the codeword size is selected from the first group of codeword sizes or the second group of codeword sizes; The number of codewords is determined at least based on the bits and the number of available bits; The payload data is encoded using LDPC codes via a low-density parity-check LDPC encoder, generating encoded data using the stated number of codewords; and A frame containing the bits and the encoded data is transmitted via the transmitter.

9. The system according to claim 8, wherein The size of the first group of codewords includes the first value, and The second group of codewords contains a second value that is twice the size of the first value.

10. The system according to claim 9, wherein The first group is a subgroup of the second group.

11. The system of claim 9, wherein the one or more processors are configured to: Identify the percentage of truncated bits during the encoding process performed via LDPC encoding; It is determined that the percentage of truncated bits is greater than the threshold; and The bit is set to a first value to indicate that the codeword size is selected from the first group of codeword sizes.

12. The system according to claim 8, wherein The first group of codeword sizes includes codeword sizes of 648, 1296, or 1944 bits, and The second group of codeword sizes contains 3888 bits of codeword size.

13. The system of claim 8, wherein the number of codewords is determined using the bits, the number of available bits, and the code rate of the LDPC code.

14. A method comprising: One or more processors identify whether the bit indicating the codeword size is selected from the first group of codeword sizes or the second group of codeword sizes; The one or more processors select a codeword size from either the first codeword size or the second codeword size based at least on the bits; The codeword size is determined by one or more processors from the selected set of codeword sizes, based at least on the number of available bits; The payload data is encoded using LDPC codes by one or more processors via a low-density parity-check (LDPC) encoder to generate encoded data containing codewords of the stated codeword size; and A frame containing the bits and the encoded data is transmitted by one or more processors via the transmitter.

15. The method of claim 14, wherein The size of the first group of codewords includes the first value, and The second group of codewords contains a second value that is twice the size of the first value.

16. The method of claim 15, wherein The first group is a subgroup of the second group.

17. The method of claim 15, further comprising: Identify the percentage of truncated bits during the encoding process performed via LDPC encoding; Determine that the percentage of truncated bits is greater than the threshold; and The bit is set to a first value to indicate that the codeword size is selected from the first set of codeword sizes.

18. The method of claim 14, wherein The first group of codeword sizes includes codeword sizes of 648, 1296, or 1944 bits, and The second group of codeword sizes contains 3888 bits of codeword size.

19. The method of claim 14, further comprising: The value of the bit is determined using at least one of the following: the length of the payload data, the modulation and coding scheme (MCS), the modulation size, the bandwidth, the resource unit, the data rate, the application's latency requirements, the percentage of truncated bits, or the ratio of truncated to shortened bits.

20. The method of claim 14, further comprising: The number of available bits is calculated based on the length of the payload data for error correction.

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