Multi-task real-time communication and management method, device and medium

Abstract

The invention relates to a multi-task real-time communication and management method and device and a medium, and the method comprises the steps: based on a master-slave response type frame structure definition, each message frame comprises a frame header with a fixed length and a frame data content with a variable length; performing memory allocation on each child node on the bus according to the device tree to realize memory sharing and mapping; task types are defined as burst tasks and periodic tasks, and time slices are dynamically distributed according to task states; the main controller loads and executes the tasks in the task pool according to the task types; when a task is executed, accessing the child nodes through a frame structure, including unicast, broadcast and read-write operation; the priority of the burst task is set to be higher than that of the periodic task, and the task type is switched according to the current task state during execution. According to the invention, the problems of low multi-task processing efficiency and low bus utilization rate under a single-master-node and multi-slave-node architecture in the field of industrial control are solved.

Description

Technical Field

[0001] This invention relates to the field of industrial control, specifically to a method, device, and medium for multi-task real-time communication and management. Background Technology

[0002] In current industrial control, equipment typically employs an architecture with a single master node and multiple cascaded slave nodes to achieve low-cost and simple application scenarios. In this environment, bus communication generally uses a traditional master-slave communication bus structure. In this structure, the master node (master device) actively initiates access to and read / write operations on each slave node via the bus. This management method helps improve system scalability.

[0003] However, in the current master-slave architecture, the master controller needs to access each node one by one and execute tasks such as writing, querying, waiting, and reading responses in sequence. This process is prone to inefficiency, especially when multitasking is involved, as the increased load on the master controller affects bus utilization and overall task execution efficiency. Summary of the Invention

[0004] This invention provides a method, device, and medium for multi-task real-time communication and management, which aims to solve the problems of low multi-task processing efficiency and low bus utilization in the field of industrial control under a single master node and multiple slave node architecture.

[0005] To achieve the above objectives, the first aspect of the present invention provides a method for real-time communication and management of multi-task tasks, comprising the following steps:

[0006] Receive commands from the master controller and initialize the bus topology of one master node and multiple child nodes;

[0007] Based on the device tree information, memory mapping is performed on the periodic task data of each child node, and a shared memory region is allocated on the master node for the burst tasks of all child nodes.

[0008] Define a frame structure for communication, which includes a frame header and frame data content. The frame header contains information such as access length, toggle signal, task type, and access type.

[0009] When the master node receives an instruction to execute a burst task, it extracts data from the shared memory area and sends a task request to the corresponding child node according to the defined frame structure.

[0010] After receiving a task request, the child node performs a unicast read, unicast write, broadcast write, or unicast write feedback operation according to the access type in the frame structure.

[0011] By initializing the device tree state, the status information and task length of the child nodes are obtained, a task pool is established according to the task level, and the periodic tasks are scheduled according to a preset priority.

[0012] When a periodic task command is received from the main controller, tasks are scheduled from the task pool according to the task level, and the periodic tasks of each child node are executed in the order of the set priority.

[0013] If a periodic task is currently being executed and a sudden task request is received, the periodic task will be paused and the sudden task will be executed after the current periodic task is completed.

[0014] If a burst task is currently being executed and a periodic task request is received, the burst task will be paused and a new round of periodic tasks will begin after the current burst task is completed.

[0015] Furthermore, the frame header contains 4 bytes, where the first byte is the lower 8 bits of the access length, the second byte contains the sent toggle signal and the higher 4 bits of the access length, the third byte contains the target child node address and the lower 3 bits of the task type, and the fourth byte contains the higher 2 bits of the task type and the access type; the frame data content contains custom data, and its data length N supports 4091 bytes.

[0016] Furthermore, methods for creating task pools based on task levels include:

[0017] Define multiple task levels, each corresponding to a different access frequency and time consumption;

[0018] Tasks in the task pool are executed in priority order during the task cycle.

[0019] Furthermore, it also includes task management and bus communication between child nodes via a coprocessor.

[0020] Furthermore, in the switching settings for sudden tasks and periodic tasks, the priority of sudden tasks is set higher than that of periodic tasks.

[0021] Furthermore, during the communication process, the master node only needs to load information including the location of the child node, the task type, the access type, and the access length, and transmit the data according to the frame structure.

[0022] Furthermore, after completing the device tree state initialization, obtaining the child node state information includes: obtaining the child node's in-situ status; obtaining the input / output length of the child node's periodic tasks, and performing memory mapping of the host rack device for each child node; and obtaining the child node's task level settings.

[0023] Furthermore, within the defined frame structure, the task type and frame data content are tailored based on user resources.

[0024] To achieve the above objectives, a second aspect of the present invention provides an electronic device including a memory and a processor, the memory being used to store a program supporting the processor to execute the method for multi-tasking real-time communication and management, and the processor being configured to execute the program stored in the memory.

[0025] To achieve the above objectives, a third aspect of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the method for multi-tasking real-time communication and management.

[0026] The beneficial effects of this invention are:

[0027] Compared with existing technologies, this invention provides a method, device, and medium for multi-task real-time communication and management. By designing different task types and access types, it enables richer functional and content access to child nodes. Task types are divided into event-triggered burst tasks that share the same read / write memory area; periodic tasks are executed by a coprocessor, with memory allocation based on data from the bus device tree. Time slices are dynamically allocated based on task priority and status to ensure efficient execution of periodic tasks, while also supporting forced coprocessor execution of burst tasks.

[0028] The multi-task real-time communication and management method of this invention enables multiple tasks to share the same frame structure through a customized frame structure and master-slave access mode, and supports single-point access and broadcasting to each node. Bursting tasks utilize time-division multiplexing of memory to reduce waste, while periodic tasks reduce the requirements on the main controller and improve bus access efficiency through memory mapping. In addition, the combination of the main controller and coprocessor enables proxy access and execution in multiple cycles, thereby reducing the workload of the main controller and optimizing bus performance.

[0029] In summary, this invention provides an effective solution in the field of industrial control, enabling real-time management and bus optimization of multiple tasks while maintaining low cost and high efficiency. It is suitable for promotion and application in various industrial applications that require real-time control. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0031] Figure 1 This is a flowchart of a method for real-time communication and management of multiple tasks disclosed in an embodiment of the present invention.

[0032] Figure 2 This is a system linear topology diagram disclosed in an embodiment of the present invention.

[0033] Figure 3 This is a memory region mapping diagram disclosed in an embodiment of the present invention.

[0034] Figure 4 This is a schematic diagram of a multi-task cycle task execution disclosed in an embodiment of the present invention. Detailed Implementation

[0035] like Figure 1 As shown, the present invention provides a method, device, and medium for multi-task real-time communication and management, comprising the following steps:

[0036] Step S100: Receive a command from the main controller and initialize the bus topology of one master node and multiple child nodes;

[0037] The system receives commands from the master controller and initializes and establishes an efficient communication connection between the master node and multiple child nodes. Specifically, when the master controller issues an initialization command, the system configures each child node on the bus according to a preset frame structure and master-slave access method, including setting their addresses, task types, and access permissions, thus forming an ordered and flexible bus topology. The topology of the master device and child nodes is as follows: Figure 2 As shown.

[0038] It should be noted that a bus is a common communication trunk line for transmitting information between various functional components of a computer. It is a transmission line bundle composed of wires. According to the types of information transmitted by the computer, the computer bus can be divided into a data bus, an address bus, and a control bus, which are used to transmit data, data addresses, and control signals, respectively.

[0039] Step S200: Based on the device tree information, perform memory mapping on the periodic task data of each child node, and allocate a shared memory area for the burst tasks of all child nodes on the master node.

[0040] The device tree information is used to configure the memory of each child node, ensuring correct data flow and smooth task execution. Specifically, step S200 can be divided into the following stages:

[0041] 1) Based on the information provided by the device tree, the master node understands the configuration and requirements of each child node, such as the data read / write length and frequency of each node.

[0042] 2) Memory Mapping: The master node performs memory mapping for the periodic task data of each child node based on the device tree information. Each child node's data has a corresponding region in the master node's memory. Through this mapping, the master node can effectively read or modify the child node's data.

[0043] 3) Shared memory region allocation: In addition to fixed memory mapping, the master node also needs to allocate a shared memory region for any sudden tasks that may occur on all child nodes. Sudden tasks require rapid response due to emergencies, so shared memory allows the master node to quickly exchange data with any child node without going through the conventional memory mapping path.

[0044] 4) Memory Management for Periodic and Bursting Tasks: Periodic and bursty tasks have different memory requirements. The memory mapping for periodic tasks is fixed, while that for bursty tasks is dynamically allocated. The master node needs to manage the memory requirements of these two types of tasks to ensure optimal utilization of memory resources and fast task execution.

[0045] from Figure 3 As can be seen, in this embodiment, the master node and each child node map the data of each node's periodic tasks to the corresponding memory region based on the task type and device tree information, while the data of burst tasks uniformly share a single memory area. Taking a maximum of 32 child nodes as an example: the master controller is responsible for reading and writing to the shared memory area during burst tasks, and the co-controller communicates with all child nodes through frame structure definitions; during periodic tasks, it accesses the memory-mapped region to indirectly complete access to all child nodes. For the master controller, accessing child nodes is simplified to accessing memory. Task management and bus communication between child nodes are both handled by the co-processor.

[0046] Step S300: Define a frame structure for communication. The frame structure includes a frame header and frame data content. The frame header contains information such as access length, toggle signal, task type, and access type.

[0047] In the frame structure, the frame header is the beginning of the communication frame. It contains crucial control information that guides how to process the data in the entire frame. The frame header typically contains four bytes, each responsible for a different control command:

[0048] The first byte (lower 8 bits) represents the access length, that is, the length of the frame data content.

[0049] The second byte contains the high 4 bits of the access length and a toggle signal, which is used to confirm the correctness of the information transmission.

[0050] The third byte includes the address of the target child node and low-order information about the task type.

[0051] The fourth byte covers the high-order bits of the task type and the access type, which specifies operations such as unicast read, unicast write, broadcast write, or unicast write with feedback required.

[0052] It should be noted that when a host sends a frame to all other hosts on the network, it is called broadcasting.

[0053] In the frame structure, the frame data content follows the frame header and contains the actual data to be transmitted. This data can be commands, parameters, or other data that needs to be transmitted. The length of the frame data content is determined by the access length in the frame header. The complete frame length is (4+N) bytes, with N supporting a maximum of 4091 bytes to accommodate different communication needs. The task type, length, and data content can be customized according to user resources, such as the master node sending parameters, remote updates, and child nodes uploading status information. Functionality and task types can be tailored based on the resources of the slave nodes.

[0054] Understandably, by dynamically defining the length and content of frame data, the system can transmit data of different sizes and types according to different task requirements. Through the access type defined in the frame header, the system can perform unicast read / write operations, broadcast write operations, and write operations requiring feedback. The explicit identification of the target child node address and task type in the frame structure ensures that data is correctly sent to the specified child node and that the corresponding task is executed.

[0055] Step S400: When the master node receives the instruction to execute a burst task, it extracts data from the shared memory area and sends a task request to the corresponding child node according to the defined frame structure.

[0056] The device tree provides the read and write lengths of each child node on the bus and dynamically allocates the data mapping of each node in the main device rack based on the read and write lengths. The main rack device allocates a 2kByte or 4kByte shared memory as the memory read area for burst tasks of all nodes as needed.

[0057] After receiving a sudden task command from the main controller, the host rack device directly obtains the complete frame structure from the write memory mapping, accesses the target child nodes, and realizes functions such as downloading task type parameters and remote updates.

[0058] Step S500: After the child node receives the task request, it performs a unicast read, unicast write, broadcast write, or unicast write feedback operation according to the access type in the frame structure.

[0059] For child nodes, it is only necessary to identify whether it is a task of this child node and whether it is a task type supported by this node. It is not necessary to identify whether it is a bursty or periodic task.

[0060] Step S600: By initializing the device tree state, obtain the status information and task length of the child nodes, establish a task pool according to the task level, and perform preset priority scheduling for periodic tasks.

[0061] After initializing the device tree of the main rack device, obtain the following statuses for each child node: the presence status of the child node, the input / output length of the periodic task of the child node, perform memory mapping of the main rack device for each child node, and set the task level of the child node.

[0062] Example of task level execution: There are three task levels. Task level 1 requires access to a node in each cycle (ComT), occupying RT1 time. Task level 2 requires accessing one or more child nodes in each cycle until only one task level 3 task remains to be executed, occupying RT2 time in each cycle's ComT time. This time is dynamically allocated based on the task being executed, but will not exceed the maximum access length. Task level 3 requires accessing one child node in each cycle, with an execution time interval of URT. If the cycle's ComT time is filled by RT1 and RT2, then URT may be 0. This can result in multiple nested cycle tasks, see [link to documentation]. Figure 4 As shown.

[0063] Based on the above regulations, three task pools of different task levels are generated. Upon receiving the command for a periodic task from the main controller (i.e., proxy access mode), the following steps are executed:

[0064] (1) Load the task pool of task level one, query the tasks of the 32 child nodes of the task pool of task level one, execute the nodes with tasks in sequence, and skip the nodes without tasks.

[0065] (2) Then, when the time for task level two is reached, query the 32 child nodes of the task pool for task level two. If there are remaining tasks, execute them. If not, load them and check if the task pool is empty. If not, skip them. If the time for task level two is exceeded, but the task pool for task level two is not completed, cache the remaining task pool for task level two until the time for task level two is reached again.

[0066] (3) Then enter the task level three time. If the remaining time is not enough to execute one task level three, then go to (1) to start the next ComT cycle. If one task level three can be executed, then execute one task level three, cache the remaining task level three task pool until the time of re-entering task level three, and then go to (1) to start the next ComT cycle.

[0067] After steps (1) to (3) are completed, it is only necessary to simplify to implementing a single task proxy. When proxying a single task, the host rack device only needs to dynamically load the child node position, task type, access type, access length, encapsulate it according to the frame structure, and then access it.

[0068] Step S700: When a periodic task command is received from the main controller, tasks are scheduled from the task pool according to the task level, and the periodic tasks of each child node are executed in the order of the set priority.

[0069] A task pool is established based on task levels, with each level corresponding to a different access frequency and time commitment. After initializing the device tree state, the system obtains the status information and task length of child nodes, which helps in correctly configuring the task pool. When the main controller receives a periodic task command, it schedules tasks from the task pool according to the task level. The system determines the execution order of tasks based on their priority, ensuring that high-priority tasks are processed first.

[0070] Step S800: If a periodic task is currently being executed and a sudden task request is received, then after completing the current periodic task, pause the periodic task and execute the sudden task.

[0071] If a sudden task request is received during the execution of a periodic task, the system will pause the periodic task upon completion and begin executing the sudden task. Since sudden tasks typically handle emergencies, their priority is set higher than that of periodic tasks to ensure a rapid response.

[0072] Step S900: If a burst task is currently being executed and a periodic task request is received, then after completing the current burst task, pause the burst task and start a new round of periodic tasks.

[0073] After completing the current emergency task, the system will pause the emergency task and begin a new round of cyclical tasks. This ensures a smooth transition between tasks, maintaining operational continuity and system stability, whether switching from emergency tasks to cyclical tasks or vice versa.

[0074] Steps S700-S99 implement dynamic time-slice allocation based on task priority, as well as flexible switching between bursty and periodic tasks. This not only improves bus utilization but also optimizes task execution efficiency. Through this method, the main controller can effectively manage the task execution of multiple child nodes, reducing the load on the main controller and improving the overall system performance and response speed.

[0075] It is understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described herein, or combinations thereof.

[0076] For software implementation, the techniques described herein can be implemented by units that perform the functions described herein. Software code can be stored in memory and executed by a processor. Electronic devices include memory and a processor; wherein the memory stores readable programs, which are loaded and executed by the processor to implement the methods described above.

[0077] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0078] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and unit can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0079] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0080] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0081] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0082] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.

Claims

1. A method for real-time communication and management of multiple tasks, characterized in that, Includes the following steps: Receive commands from the master controller and initialize the bus topology of one master node and multiple child nodes; Based on the device tree information, memory mapping is performed on the periodic task data of each child node, and a shared memory region is allocated on the master node for the burst tasks of all child nodes. Define a frame structure for communication, which includes a frame header and frame data content. The frame header contains information such as access length, toggle signal, task type, and access type. When the master node receives an instruction to execute a burst task, it extracts data from the shared memory area and sends a task request to the corresponding child node according to the defined frame structure. After receiving a task request, the child node performs a unicast read, unicast write, broadcast write, or unicast write feedback operation according to the access type in the frame structure. By initializing the device tree state, the status information and task length of the child nodes are obtained, a task pool is established according to the task level, and the periodic tasks are scheduled according to a preset priority. When a periodic task command is received from the main controller, tasks are scheduled from the task pool according to the task level, and the periodic tasks of each child node are executed in the order of the set priority. If a periodic task is currently being executed and a sudden task request is received, the periodic task will be paused and the sudden task will be executed after the current periodic task is completed. If a burst task is currently being executed and a periodic task request is received, the burst task will be paused and a new round of periodic tasks will begin after the current burst task is completed.

2. The method for multi-task real-time communication and management as described in claim 1, characterized in that, The frame header contains 4 bytes, where the first byte is the lower 8 bits of the access length, the second byte contains the sent toggle signal and the higher 4 bits of the access length, the third byte contains the target child node address and the lower 3 bits of the task type, and the fourth byte contains the higher 2 bits of the task type and the access type; the frame data content contains custom data, and its data length N supports 4091 bytes.

3. The method for multi-task real-time communication and management as described in claim 1, characterized in that, Methods for creating task pools based on task level include: Define multiple task levels, each corresponding to a different access frequency and time consumption; Tasks in the task pool are executed in priority order during the task cycle.

4. The method for real-time communication and management of multiple tasks as described in claim 1, characterized in that, It also includes task management and bus communication between child nodes via a coprocessor.

5. The method for real-time multi-task communication and management as described in claim 1, characterized in that, In the settings for switching between emergency tasks and periodic tasks, the priority of emergency tasks is set higher than that of periodic tasks.

6. The method for real-time multi-task communication and management as described in claim 1, characterized in that, During communication, the master node only needs to load information including the location of the child node, the task type, the access type, and the access length, and then transmit the data according to the frame structure.

7. The method for real-time communication and management of multiple tasks as described in claim 1, characterized in that, After completing the device tree state initialization, the following information is obtained about the child node status: the presence status of the child node; the input and output lengths of the periodic tasks of the child node, and memory mapping of the host rack device for each child node; and the task level settings of the child node.

8. The method for real-time communication and management of multiple tasks as described in claim 1, characterized in that, In the defined frame structure, the task type and frame data content are tailored according to user resources.

9. An electronic device, comprising a memory and a processor, characterized in that, The memory is used to store programs that support the processor in executing any of the methods for multi-tasking real-time communication and management as described in claims 1-8, wherein the processor is configured to execute the programs stored in the memory.

10. A computer-readable storage medium storing a computer program thereon, characterized in that, When the computer program is run by the processor, it performs the steps of any one of the methods for multi-task real-time communication and management as described in claims 1-8.

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