Semiconductor device and preparation method thereof, and electronic equipment
By forming cross trenches on a substrate, vertical channel transistors are fabricated, solving the problems of device density and cost in integrated circuits and achieving a reduction in transistor area and an increase in integration density.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-10-16
- Publication Date
- 2026-04-17
AI Technical Summary
With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the impact of minute differences on device performance is increasing. How to increase memory cells on a limited substrate and reduce fabrication costs has become a challenge.
Transistors with vertical channels are fabricated by forming intersecting first and second trenches on a substrate. The transistor's electrode, gate electrode, and channel layer are formed using semiconductor, insulating, and conductive layers within the intersecting trenches, simplifying the fabrication process and reducing costs.
This has resulted in a reduction in the area occupied by transistors, an increase in the integration density of semiconductor devices, a simplification of the fabrication process, and a reduction in fabrication costs.
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Figure CN121888593A_ABST
Abstract
Description
Technical Field
[0001] This article relates to, but is not limited to, the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and electronic equipment. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, while the types and number of devices contained in a single chip are increasing. This means that even minor differences in the manufacturing process can affect device performance. To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0003] This disclosure provides a semiconductor device, a method for fabricating the same, and an electronic device.
[0004] On one hand, this disclosure provides a method for fabricating a semiconductor device, the semiconductor device including a substrate and at least one transistor located on the substrate; the fabrication method includes: A first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer are sequentially formed on the substrate to form a stacked structure; A first trench is formed, and the first trench extends along a first direction, and the stacked structure located within the first trench is etched away; A second trench is formed, and the second trench extends along a second direction, and the stacked structure located within the second trench is etched away, such that the first conductive layer forms the first electrode of the transistor, and the second conductive layer forms the second electrode of the transistor; the first direction and the second direction intersect and the plane formed thereby is parallel to the plane of the substrate; A semiconductor layer, an insulating layer, and a third conductive layer are sequentially formed within the second trench, and the third conductive layer forms the third trench. Based on the third trench, the semiconductor layer, insulating layer, and third conductive layer are etched such that the third conductive layer forms the gate electrode of the transistor, the insulating layer forms the gate insulating layer, and the semiconductor layer forms the channel layer of the transistor; wherein, the channel layer includes a first channel portion and a second channel portion spaced apart along the first direction, both the first channel portion and the second channel portion extending along a third direction, the first electrode and the second electrode being located between the first channel portion and the second channel portion, and both the first electrode and the second electrode being connected to the first channel portion and the second channel portion; the gate electrode extends along the third direction and is located on the side of the channel layer away from the first electrode, the third direction being perpendicular to the plane of the substrate.
[0005] The semiconductor device fabrication method provided in this disclosure has a simple fabrication process and fewer fabrication steps, which can reduce the fabrication cost of semiconductor devices. This fabrication method can form transistors with vertical channels, which can reduce the occupied area of transistors and increase the integration density of semiconductor devices.
[0006] In some exemplary embodiments, the gate electrode includes a first gate electrode and a second gate electrode spaced apart along the first direction, wherein the first gate electrode is located on the side of the first channel portion away from the first electrode, and the second gate electrode is located on the side of the second channel portion away from the first electrode.
[0007] In some exemplary embodiments, the material of the semiconductor layer includes metal oxides.
[0008] In some exemplary embodiments, after forming the first trench and before forming the second trench, the fabrication method further includes: A sacrificial part is formed within the first trench.
[0009] In some exemplary embodiments, the third conductive layer includes a connected trench bottom and trench walls, wherein the trench bottom extends along a direction parallel to the plane of the substrate, and the trench walls extend along the third direction and surround the trench bottom, the trench bottom and the trench walls together forming the third trench; the etching of the semiconductor layer, the insulating layer and the third conductive layer based on the third trench includes: The semiconductor layer, the insulating layer, and the third conductive layer located on the surface of the stacked structure away from the substrate are all etched away, and the bottom of the trench and the semiconductor layer and the insulating layer located at the bottom of the trench are all etched away to form a fourth trench, such that the semiconductor layer forms a prefabricated structure, the insulating layer forms the gate insulating layer, and the third conductive layer forms the gate electrode.
[0010] In some exemplary embodiments, the preparation method further includes: A first isolation section is formed within the fourth trench.
[0011] In some exemplary embodiments, the etching of the semiconductor layer, insulating layer, and third conductive layer based on the third trench further includes: The prefabricated structure is etched to form the channel layer.
[0012] In some exemplary embodiments, etching the prefabricated structure includes: The sacrificial portion located within the first trench is etched away; Based on the first trench, the prefabricated structure exposed by the first trench is etched away, so that the prefabricated structure forms the trench layer.
[0013] In some exemplary embodiments, after forming the channel layer, the fabrication method further includes: A second isolation section is formed within the first trench.
[0014] In some exemplary embodiments, the semiconductor device further includes at least one bit line extending along the first direction; the fabrication method further includes: The first conductive layer simultaneously forms the first electrode of the transistor and the bit line.
[0015] On the other hand, embodiments of this disclosure provide a semiconductor device including a substrate and at least one memory cell located on the substrate, the memory cell including at least one transistor; the transistor includes a first electrode, a second electrode, a gate electrode, a channel layer and a gate insulating layer located between the gate electrode and the channel layer, the second electrode being located on the side of the first electrode away from the substrate; The channel layer includes a first channel portion and a second channel portion spaced apart along a first direction, both the first channel portion and the second channel portion extending along a third direction, the first electrode and the second electrode located between the first channel portion and the second channel portion, and both the first electrode and the second electrode connected to the first channel portion and the second channel portion; the gate electrode extends along a third direction and is located on the side of the channel layer away from the first electrode; the first direction is parallel to the plane of the substrate, and the third direction is perpendicular to the plane of the substrate.
[0016] In some exemplary embodiments, the gate electrode includes a first gate electrode and a second gate electrode spaced apart along the first direction, wherein the first gate electrode is located on the side of the first channel portion away from the first electrode, and the second gate electrode is located on the side of the second channel portion away from the first electrode.
[0017] In some exemplary embodiments, a plurality of first gate electrodes arranged along the second direction are integrally formed and form a word line; a plurality of second gate electrodes arranged along the second direction are integrally formed and form another word line; the second direction intersects the first direction and the plane formed therein is parallel to the plane of the substrate.
[0018] In some exemplary embodiments, the memory cell further includes a capacitor located on the side of the transistor away from the substrate, and the capacitor is connected to the second electrode; the orthographic projection of the capacitor onto the plane of the substrate at least partially overlaps with the orthographic projection of the transistor onto the plane of the substrate.
[0019] On the other hand, embodiments of this disclosure provide an electronic device, including a semiconductor device formed according to the semiconductor device fabrication method described in any of the preceding embodiments, or a semiconductor device described in any of the preceding embodiments.
[0020] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description
[0021] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.
[0022] Figure 1 This is a plan view of a semiconductor device according to an embodiment of the present disclosure; Figure 2A for Figure 1 A cross-sectional view at point AA in the middle; Figure 2B for Figure 1 Cross-sectional view of the area marked BB in the middle; Figure 2C for Figure 1 Cross-sectional view at the CC mark; Figure 2D for Figure 1 Cross-sectional view at the DD mark in the middle; Figures 3A to 3DA cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming a first photoresist layer pattern; Figures 4A to 4D This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming a first trench; Figures 5A to 5D This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure after the sacrificial portion has been formed; Figures 6A to 6D This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming a second photoresist layer pattern; Figures 7A to 7D This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming a second trench; Figures 8A to 8D This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after the formation of the third conductive layer; Figures 9A to 9D This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after the first isolation portion has been formed; Figures 10A to 10D This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after the sacrificial portion has been etched away; Figures 11A to 11D This is a cross-sectional schematic diagram of a semiconductor device after a channel layer has been formed, according to an embodiment of the present disclosure. Figures 12A to 12D This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after the second isolation portion has been formed; Figures 13A to 13D This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming a capacitor. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.
[0024] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values shown in the drawings.
[0025] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.
[0026] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.
[0027] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.
[0028] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.
[0029] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.
[0030] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.
[0031] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.
[0032] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".
[0033] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.
[0034] This disclosure provides a method for fabricating a semiconductor device, the semiconductor device including a substrate and at least one transistor located on the substrate; the fabrication method includes: A first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer are sequentially formed on the substrate to form a stacked structure; A first trench is formed, and the first trench extends along a first direction, and the stacked structure located within the first trench is etched away; A second trench is formed, and the second trench extends along a second direction, and the stacked structure located within the second trench is etched away, such that the first conductive layer forms the first electrode of the transistor, and the second conductive layer forms the second electrode of the transistor; the first direction and the second direction intersect and the plane formed thereby is parallel to the plane of the substrate; A semiconductor layer, an insulating layer, and a third conductive layer are sequentially formed within the second trench, and the third conductive layer forms the third trench. Based on the third trench, the semiconductor layer, insulating layer, and third conductive layer are etched such that the third conductive layer forms the gate electrode of the transistor, the insulating layer forms the gate insulating layer, and the semiconductor layer forms the channel layer of the transistor; wherein, the channel layer includes a first channel portion and a second channel portion spaced apart along the first direction, both the first channel portion and the second channel portion extending along a third direction, the first electrode and the second electrode being located between the first channel portion and the second channel portion, and both the first electrode and the second electrode being connected to the first channel portion and the second channel portion; the gate electrode extends along the third direction and is located on the side of the channel layer away from the first electrode, the third direction being perpendicular to the plane of the substrate.
[0035] The semiconductor device fabrication method provided in this disclosure has a simple fabrication process and fewer fabrication steps, which can reduce the fabrication cost of semiconductor devices. This fabrication method can form transistors with vertical channels, which can reduce the occupied area of transistors and increase the integration density of semiconductor devices.
[0036] Figure 1 This is a plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 2A for Figure 1 Cross-sectional view at point AA (marked in the middle). Figure 2B for Figure 1 Cross-sectional view of the area marked BB. Figure 2C for Figure 1 A cross-sectional view at the point marked CC. Figure 2D for Figure 1 A cross-sectional view at point DD. In this embodiment, three directions are defined: a first direction X, a second direction Y, and a third direction Z. The first direction X and the second direction Y are perpendicular to each other, and the plane containing the semiconductor device is parallel to the plane formed by the first direction X and the second direction Y. The third direction Z is perpendicular to the plane containing the semiconductor device.
[0037] like Figure 1 As shown, a semiconductor device may include a substrate 10 and at least one memory cell layer located on the substrate 10. For example, the semiconductor device may include two memory cell layers, three memory cell layers, or five memory cell layers, etc., and multiple memory cell layers may be stacked sequentially along a third direction Z. In this embodiment of the disclosure, a semiconductor device including one memory cell layer is taken as an example; however, this embodiment of the disclosure does not limit the number of memory cell layers included in the semiconductor device.
[0038] The storage cell layer may include at least one storage cell. For example, the storage cell layer may include one storage cell, two storage cells, or three storage cells, etc. In this embodiment of the disclosure, taking a storage cell layer including eight storage cells as an example, the eight storage cells may be arranged in a matrix of 4 rows (first direction X) and 2 columns (second direction Y). However, this embodiment of the disclosure does not limit the number of storage cells included in the storage cell layer.
[0039] The memory cell may include at least one transistor 20 and at least one capacitor 30, in Figure 1 The capacitor and separator are not shown in the image. Transistor 20 is shown in the image. Figure 1As shown within the dashed box. For example, a memory cell may include a transistor 20 and a capacitor 30. Transistor 20 and capacitor 30 located in the same memory cell can be stacked and connected along a third-direction Z-layer. Transistor 20 is closer to the substrate 10 than capacitor 30 within the same memory cell. See [link to documentation]. Figure 2B , Figure 2D .
[0040] In some exemplary embodiments, such as Figure 1 , Figure 2D As shown, transistor 20 may include a first electrode 21, a second electrode 22, a gate electrode 23, a channel layer 24, and a gate insulating layer 25 located between the channel layer 24 and the gate electrode 23. The first electrode 21 and the second electrode 22 may be stacked along a third direction Z, with the first electrode 21 closer to the substrate 10 than the second electrode 22. The channel layer 24 may include a first channel portion 24a and a second channel portion 24b spaced apart along a first direction X. The first electrode 21 and the second electrode 22 are located between the first channel portion 24a and the second channel portion 24b, and the first channel portion 24a is connected to both the first electrode 21 and the second electrode 22, and the second channel portion 24b is connected to both the first electrode 21 and the second electrode 22. The gate electrode 23 is located on the side of the channel layer 24 away from the first electrode 21 and the second electrode 22. The gate electrode 23 may include a first gate electrode 23a and a second gate electrode 23b spaced apart along a first direction X. The first gate electrode 23a may be located on the side of the first channel portion 24a away from the first electrode 21 and the second electrode 22, and the second gate electrode 23b may be located on the side of the second channel portion 24b away from the first electrode 21 and the second electrode 22. The first gate electrode 23a and the first channel portion 24a are insulated from each other by a gate insulating layer 25, and the second gate electrode 23b and the second channel portion 24b are insulated from each other by a gate insulating layer 25. In this embodiment, the transistor is a transistor with a vertical channel, and the area of the orthographic projection of the memory cell onto the plane of the substrate can be 4F. 2 (F is the minimum feature size of the storage cell in the plane of the substrate), which can improve the integration density of semiconductor devices, and transistors have the advantages of simple and easy fabrication process and low fabrication cost.
[0041] In some exemplary embodiments, such as Figure 2D As shown, a memory cell layer may include at least one bit line BL, which may extend along a first direction X, and multiple bit lines BL may be arranged at intervals along a second direction Y. Multiple memory cells located in the same memory cell layer and arranged along the first direction may be connected to the same bit line BL.
[0042] In some exemplary embodiments, the first pole 21 and the bit line BL can be an integral structure interconnected. In some exemplary embodiments, such as... Figure 1As shown, the memory cell layer may further include at least one word line WL, which may extend along the second direction Y. The gate electrodes of a plurality of transistors 20 arranged along the second direction Y may be connected to the same word line WL. Alternatively, the gate electrodes of a plurality of transistors 20 arranged along the second direction Y may be an integral structure forming a single word line WL.
[0043] In some exemplary embodiments, such as Figure 1 As shown, the word line WL may include a first word line WL1 and a second word line WL2 spaced apart along a first direction X. The first word line WL1 may be located on the side of the first channel portion 24a away from the second electrode 22, and the second word line WL2 may be located on the side of the second channel portion 24b away from the second electrode 22. The first gate electrode 23a is connected to the first word line WL1; for example, the first gate electrode 23a and the first word line WL1 may be an integral structure. The second gate electrode 23b is connected to the second word line WL2; for example, the second gate electrode 23b and the second word line WL2 may be an integral structure. In this embodiment of the present disclosure, by setting the transistor to be connected to both the first word line and the second word line, the reliability and accuracy of the word line's control over the transistor can be improved.
[0044] In some exemplary embodiments, such as Figure 2D As shown, capacitor 30 may include a first electrode 31, a second electrode 32, and a dielectric layer 33 located between the first electrode 31 and the second electrode 32. The first electrode 31 may surround the sidewall of the second electrode 32. The first electrode 31 of capacitor 30 may be connected to the second electrode 22 of transistor 20 via a connection hole K. The orthographic projection of capacitor 30 onto the plane of substrate 10 at least partially overlaps with the orthographic projection of transistor 20 onto the plane of substrate 10; for example, the orthographic projection of capacitor 30 onto the plane of substrate 10 includes the orthographic projection of transistor 20 onto the plane of substrate 10. In embodiments of this disclosure, stacking capacitors and transistors of the same memory cell along a third direction can reduce the occupied area of the memory cell and improve the integration density of semiconductor devices.
[0045] The following example illustrates the structure of a semiconductor device through its fabrication process. The fabrication process of a semiconductor device may include the following steps:
[0046] (01) A dielectric layer 13 and a conductive layer are sequentially formed on one side of the substrate 10. Multiple dielectric layers 13 and multiple conductive layers can be alternately arranged along the third direction Z to form a stacked structure, such as... Figure 3A , Figure 3B , Figure 3C as well as Figure 3D As shown, Figure 3A for Figure 1 A cross-sectional view of the semiconductor device at point AA after the first photoresist layer pattern has been formed. Figure 3B for Figure 1 A cross-sectional view of the semiconductor device at point BB after the first photoresist layer pattern has been formed. Figure 3C for Figure 1 A cross-sectional view of the semiconductor device at the CC mark after the first photoresist layer pattern has been formed. Figure 3D for Figure 1 The diagram shows a cross-sectional view of the semiconductor device at point DD after the formation of the first photoresist layer pattern. For example, the orthographic projection of the stacked structure onto the plane of substrate 10 can be rectangular. For example, the stacked structure can include three dielectric layers 13 and two conductive layers, which are arranged alternately along the third direction Z. In this embodiment, the two conductive layers can also be referred to as the first conductive layer 11 and the second conductive layer 12, respectively. The first conductive layer 11 is closer to substrate 10 than the second conductive layer 12. The first conductive layer 11 is used to form the first electrode and bit line of the transistor in subsequent processes, and the second conductive layer 12 is used to form the second electrode of the transistor in subsequent processes. In this embodiment, the dielectric layer closer to the substrate can also be referred to as the first dielectric layer, and the dielectric layer located between the first and second conductive layers can also be referred to as the second dielectric layer. In this embodiment, the number of dielectric layers and the number of conductive layers included in the stacked structure are not limited. For example, the dielectric layer and the conductive layer can be prepared by a deposition process, which may include at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or vapor deposition.
[0047] Subsequently, a first mask layer 14 and a first photoresist layer are sequentially formed on the stacked structure. The first photoresist layer is then exposed using ultraviolet light. Following this, the exposed first photoresist layer is developed to form a first photoresist layer pattern 15. The first photoresist layer pattern 15 has multiple first cutout areas 15a. The first photoresist layer located within the first cutout areas 15a is removed, and the first cutout areas 15a expose a portion of the surface of the first mask layer 14 away from the substrate 10, such as... Figure 3A , Figure 3B , Figure 3C as well as Figure 3D As shown. For example, the first photoresist layer pattern 15 may have three first cutout areas 15a. As... Figure 3B , Figure 3C As shown, the orthographic projection of the first cutout area 15a onto the plane of the substrate 10 can be a rectangle extending along the first direction X. In subsequent processes, the stacked structure can be etched through the first cutout area 15a to form the first trench.
[0048] In some exemplary embodiments, substrate 10 may include a single-crystal silicon substrate or a semiconductor-on-insulator (SOI) substrate, etc. For example, the SOI substrate may be a silicon-on-sapphire (SOS) substrate or a silicon-on-glass (SOG) substrate, etc. Substrate 10 may be a single-layer or composite-layer structure.
[0049] In some exemplary embodiments, the material of the dielectric layer 13 may include an inorganic material. Inorganic materials include, for example, silicon oxynitride (SiO₂). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x ) or silicon dioxide (SiO) x C y The dielectric layer 13 can be any one or more of the following: (e.g., silicon oxide). The dielectric layer 13 can be a multilayer or composite layer structure. For example, the material of the dielectric layer 13 can be silicon oxide.
[0050] In some exemplary embodiments, the material of the conductive layer may include a metallic material. For example, the metallic material may include at least one of the following: tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the above metals. The conductive layer may be a single-layer or multi-layer structure. For example, the material of the conductive layer may be titanium nitride. For example, the materials of the two conductive layers may be the same or different. For example, the film structures of the two conductive layers may be the same or different.
[0051] In some exemplary embodiments, the first mask layer 14 may include a first sublayer 14-1 and a second sublayer 14-2 stacked sequentially, with the first sublayer 14-1 being closer to the substrate 10 than the second sublayer 14-2. For example, the material of the first sublayer 14-1 may include carbon, and the material of the second sublayer 14-2 may be silicon oxynitride. For example, the first sublayer may be prepared using a coating process, and the second sublayer may be prepared using a deposition process.
[0052] (02) Based on the first cutout area 15a, the stacked structure is etched to form a first trench 41. The stacked structure located within the first trench 41 is etched away, exposing the portion of the dielectric layer 13 closest to the substrate 10. This causes the first conductive layer 11 to form multiple first conductive structures 11a, and the second conductive layer 12 to form multiple second conductive structures 12a. The orthographic projection of the first trench 41 onto the plane of the substrate 10 can be a rectangle extending along the first direction X, such as... Figure 4A , Figure 4B , Figure 4C as well as Figure 4D As shown, Figure 4A for Figure 1 A cross-sectional view of the semiconductor device at point AA after the first trench has been formed. Figure 4B for Figure 1 A cross-sectional view of the semiconductor device after the first trench is formed at the location marked BB. Figure 4C for Figure 1 A cross-sectional view of the semiconductor device after the first trench is formed at the CC mark. Figure 4D for Figure 1 This is a cross-sectional view of the semiconductor device after the first trench is formed at the location marked DD. For example, etching may include at least one of physical etching and chemical etching. Chemical etching may include at least one of dry etching and wet etching. The orthographic projection of the first conductive structure 11a onto the plane of the substrate 10 can be a rectangle extending along the first direction X. Multiple first conductive structures 11a can be arranged at intervals along the second direction Y; for example, they can be arranged at equal intervals. The orthographic projection of the second conductive structure 12a onto the plane of the substrate 10 can be a rectangle extending along the first direction X. Multiple second conductive structures 12a can be arranged at intervals along the second direction Y; for example, they can be arranged at equal intervals. The first conductive structure 11a is used to form the first electrode and bit line of a transistor in subsequent processes, and the second conductive structure 12a is used to form the second electrode of a transistor in subsequent processes.
[0053] Subsequently, the first mask layer 14 and the first photoresist layer pattern 15 are peeled off, as follows: Figure 4A , Figure 4B , Figure 4C as well as Figure 4D As shown.
[0054] (03) Based on the first trench 41, a sacrificial portion 16 is formed on the substrate 10 forming the aforementioned structure. The sacrificial portion 16 is located within the first trench 41, and the surface of the sacrificial portion 16 away from the substrate 10 can be substantially flush with the surface of the stacked structure away from the substrate 10, such as... Figure 5A , Figure 5B , Figure 5C as well as Figure 5D As shown, Figure 5A for Figure 1A cross-sectional view of the semiconductor device after the sacrificial portion is formed at point AA. Figure 5B for Figure 1 A cross-sectional view of the semiconductor device after the sacrificial portion is formed at the BB mark. Figure 5C for Figure 1 A cross-sectional view of the semiconductor device after the sacrificial portion is formed at the CC mark. Figure 5D for Figure 1 This is a cross-sectional view of the semiconductor device after the sacrificial portion is formed at the DD mark. For example, the surface of the sacrificial portion 16 away from the substrate 10 can be subjected to chemical mechanical polishing (CMP). For example, the sacrificial portion can be fabricated using a deposition process. For example, the material of the sacrificial portion can be polycrystalline silicon, etc.
[0055] (04) A second mask layer 17 and a second photoresist layer are sequentially formed on the substrate 10 on which the aforementioned structure is formed. The second photoresist layer is exposed using ultraviolet light. Subsequently, the exposed second photoresist layer is developed to form a second photoresist layer pattern 18. The second photoresist layer pattern 18 has multiple second cutout areas 18a. The second photoresist layer located within the second cutout areas 18a is removed, and the second cutout areas 18a can expose a portion of the surface of the second mask layer 17 away from the substrate 10, such as... Figure 6A , Figure 6B , Figure 6C as well as Figure 6D As shown, Figure 6A for Figure 1 A cross-sectional view of the semiconductor device at point AA after the formation of the second photoresist layer pattern. Figure 6B for Figure 1 A cross-sectional view of the semiconductor device at point BB after the formation of the second photoresist layer pattern. Figure 6C for Figure 1 A cross-sectional view of the semiconductor device at the CC mark after the formation of the second photoresist layer pattern. Figure 6D for Figure 1 A cross-sectional view of the semiconductor device at the DD location after the formation of the second photoresist layer pattern. For example, the second photoresist layer pattern 18 may have three second cutout areas 18a. Figure 6A , Figure 6C As shown, the orthographic projection of the second cutout area 18a onto the plane of the substrate 10 can be a rectangle extending along the second direction Y. In subsequent processes, the stacked structure can be etched via the second cutout area 18a to form the second trench.
[0056] In some exemplary embodiments, the second mask layer 17 may include a third sublayer 17-3 and a fourth sublayer 17-4 sequentially stacked, with the third sublayer 17-3 closer to the substrate 10 than the fourth sublayer 17-4. For example, the material of the third sublayer 17-3 may include carbon, and the material of the fourth sublayer 17-4 may be silicon oxynitride. For example, the third sublayer may be prepared using a coating process, and the fourth sublayer may be prepared using a deposition process.
[0057] (05) The stacked structure is etched based on the second cutout area 18a to form the second trench 42. The stacked structure and the sacrificial portion 16 located within the second trench 42 are etched away, exposing part of the sacrificial portion 16 and part of the first conductive structure 11a. The first conductive structure 11a forms the first electrode 21 of the transistor and the bit line BL, and the second conductive structure 12a forms the second electrode 22 of the transistor. The orthographic projection of the second trench 42 onto the plane of the substrate 10 can be a rectangle extending along the second direction Y, such as... Figure 7A , Figure 7B , Figure 7C as well as Figure 7D As shown, Figure 7A for Figure 1 A cross-sectional view of the semiconductor device at point AA after the second trench has been formed. Figure 7B for Figure 1 A cross-sectional view of the semiconductor device after the second trench is formed at the location marked BB. Figure 7C for Figure 1 A cross-sectional view of the semiconductor device after the second trench is formed at the CC mark. Figure 7D for Figure 1 This is a cross-sectional view of the semiconductor device after the second trench is formed at the DD mark. For example, etching may include at least one of physical etching and chemical etching. Chemical etching may include at least one of dry etching and wet etching. The orthographic projection of the first electrode 21 onto the plane of the substrate 10 may be a rectangle, and the orthographic projection of the bit line BL onto the plane of the substrate 10 may be a rectangle extending along the first direction X. Multiple first electrodes 21 formed by the same first conductive structure 11a and the bit line BL are an integral structure interconnected, and the multiple first electrodes 21 formed by the same first conductive structure 11a are arranged at intervals along the first direction X. The orthographic projection of the second electrode 22 onto the plane of the substrate 10 may be a rectangle, and multiple second electrodes 22 formed by the same second conductive structure 12a are arranged at intervals along the first direction X.
[0058] Subsequently, the second mask layer 17 and the second photoresist layer pattern 18 are peeled off, as follows: Figure 7A , Figure 7B , Figure 7C as well as Figure 7D As shown.
[0059] (06) Based on the second trench 42, a semiconductor layer 26, an insulating layer 27, and a third conductive layer 28 are sequentially formed on the substrate 10 on which the aforementioned structure is formed, such as Figure 8A , Figure 8B , Figure 8C as well as Figure 8D As shown, Figure 8A for Figure 1 A cross-sectional view of the semiconductor device at point AA after the formation of the third conductive layer. Figure 8B for Figure 1 A cross-sectional view of the semiconductor device after the third conductive layer has been formed at the location marked BB. Figure 8C for Figure 1 A cross-sectional view of the semiconductor device after the third conductive layer has been formed at the CC mark. Figure 8D for Figure 1 This is a cross-sectional view of the semiconductor device at point DD after the formation of the third conductive layer. Semiconductor layer 26 is used to form the channel layer of the transistor in subsequent processes, insulating layer 27 is used to form the gate insulating layer of the transistor in subsequent processes, and the third conductive layer 28 is used to form the gate electrode and word line of the transistor in subsequent processes. For example, semiconductor layer 26, insulating layer 27, and third conductive layer 28 can be fabricated using a deposition process.
[0060] The orthographic projections of the semiconductor layer 26, the insulating layer 27, and the third conductive layer 28 onto the plane of the substrate 10 can overlap. The orthographic projection of the semiconductor layer 26 onto the plane of the substrate 10 can include the orthographic projection of the stacked structure onto the plane of the substrate 10 and the orthographic projection of the second trench 42 onto the plane of the substrate 10. The semiconductor layer 26, the insulating layer 27, and the third conductive layer 28 are sequentially located within the second trench 42, but do not completely fill the second trench 42.
[0061] In some exemplary embodiments, such as Figure 8D As shown, the third conductive layer 28 forms at least one third trench 43, with the third trench 43 and the second trench 42 arranged in pairs. The orthographic projection of the third trench 43 onto the plane of the substrate 10 can lie within the orthographic projection of the corresponding second trench 42 onto the plane of the substrate 10. The third trench 43 is used to accommodate the first isolation portion formed in a subsequent process. The third conductive layer 28 includes a connected trench bottom 28a and trench wall 28b. The trench bottom 28a extends in a direction parallel to the plane of the substrate 10, and the trench wall 28b extends in a direction perpendicular to the plane of the substrate 10, and the trench wall 28b surrounds the trench bottom 28a. The trench bottom 28a and the trench wall 28b together form the third trench 43.
[0062] In some exemplary embodiments, the material of the semiconductor layer 26 may include a metal oxide material, such as indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the transistor's leakage current is relatively small (leakage current less than or equal to 10). -15 A), thus ensuring a low refresh rate for the dynamic memory. It should be noted that the metal oxide material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the transistor leakage current meets the requirements. Specific adjustments can be made according to the actual situation.
[0063] In this embodiment, the semiconductor layer is made of metal oxide, which, compared to silicon, allows the transistor to have a lower off-state current and a higher current-to-on ratio, improving the electrical performance of the semiconductor device. Furthermore, using metal oxide for the semiconductor layer reduces the material requirements of the substrate, lowering the cost of semiconductor device fabrication. Moreover, using silicon for the semiconductor layer typically involves epitaxial growth, which requires a substrate with the same crystal structure, increasing fabrication costs. Fabricating source and drain electrodes with single-crystal silicon requires multiple ion implantation and annealing processes, making the fabrication process complex and costly. Finally, metal oxides offer better deep-hole filling capabilities compared to single-crystal silicon.
[0064] In some exemplary embodiments, the material of the insulating layer 27 may include a high dielectric constant material, which can improve the insulation between the subsequently formed channel layer and the gate electrode, thereby improving the performance of the semiconductor device. In embodiments of this disclosure, the high dielectric constant material may be a material with a dielectric constant equal to or greater than 3.9. The high dielectric constant material may include any one or more of hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), and strontium titanate (SrTiO3). The insulating layer 27 may be a multilayer or composite layer structure.
[0065] In some exemplary embodiments, the material of the third conductive layer 28 may include a metallic material. For example, the metallic material may include at least one of tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the above metals, or an oxide of the above metals. For example, the material of the third conductive layer may be ITO. For example, the material of the third conductive layer may be TiN.
[0066] (07) The semiconductor layer 26, insulating layer 27, and third conductive layer 28 on the surface of the stacked structure away from the substrate 10 are etched away, and based on the third trench 43, the semiconductor layer 26, insulating layer 27, and third conductive layer 28 are etched away, and the trench bottom 28a and the semiconductor layer 26 and insulating layer 27 located at the trench bottom 28a are etched away to form a fourth trench 44, and the semiconductor layer 26 forms at least one prefabricated structure 26a for forming a channel layer, the insulating layer 27 forms at least one gate insulating layer 25, and the third conductive layer 28 forms at least one gate electrode 23 and at least one word line WL, as shown. Figure 9A , Figure 9B , Figure 9C as well as Figure 9D As shown, Figure 9A for Figure 1 A cross-sectional view of the semiconductor device at point AA after the first isolation section has been formed. Figure 9B for Figure 1 A cross-sectional view of the semiconductor device after the first isolation section is formed at the BB mark. Figure 9C for Figure 1 A cross-sectional view of the semiconductor device after the first isolation section is formed at the CC mark. Figure 9D for Figure 1 A cross-sectional view of the semiconductor device after the first isolation portion is formed at the location marked DD. For example, etching may include at least one of physical etching and chemical etching. Chemical etching may include at least one of dry etching and wet etching. In embodiments of this disclosure, the semiconductor layer located at the bottom of the trench refers to the semiconductor layer whose orthographic projection onto the plane of the substrate overlaps with the orthographic projection onto the bottom of the trench. The insulating layer located at the bottom of the trench refers to the insulating layer whose orthographic projection onto the plane of the substrate overlaps with the orthographic projection onto the bottom of the trench. Figure 9DAs shown, the prefabricated structure 26a includes two parts spaced apart along a first direction X, and each part includes a first structure extending along a third direction and a second structure extending along the first direction, each part being an "L" shape and a mirror image of an "L" shape, respectively. The two parts of the prefabricated structure 26a are used to form a first channel portion and a second channel portion of a channel layer in subsequent processes. Both the first channel portion and the second channel portion include a first channel structure portion extending along a third direction and a second channel structure portion extending along the first direction, the first channel portion and the second channel portion being an "L" shape and a mirror image of an "L" shape, respectively. Figure 9D As shown, the gate insulating layer 25 includes a first gate insulating portion 25a and a second gate insulating portion 25b disposed at intervals along a first direction X. Both the first gate insulating portion 25a and the second gate insulating portion 25b include a first gate insulating portion structure extending along a third direction and a second gate insulating portion structure extending along the first direction. The first gate insulating portion 25a and the second gate insulating portion 25b are respectively "L"-shaped and "L"-shaped mirror images.
[0067] Subsequently, the first isolation section 29a is formed based on the fourth trench 44, as follows: Figure 9A , Figure 9B as well as Figure 9C As shown, the orthographic projection of the first isolation portion 29a onto the plane of the substrate 10 can be a rectangle extending along the second direction Y. For example, the first isolation portion 29a can be fabricated using a deposition process. The first isolation portion 29a is located within the fourth trench 44, and the surface of the first isolation portion 29a away from the substrate 10 can be substantially flush with the surface of the stacked structure away from the substrate 10. For example, the surface of the first isolation portion 29a away from the substrate 10 can be treated with chemical mechanical polishing (CMP). In this embodiment, by providing the first isolation portion, two transistors arranged at adjacent intervals along the first direction X can be isolated, signal crosstalk between adjacent transistors can be avoided, and the electrical performance of the transistors can be improved.
[0068] In some exemplary embodiments, the semiconductor layer 26, the insulating layer 27, and the third conductive layer 28 can be etched in a single etching process. Alternatively, the third conductive layer 28 can be etched first, and the etched third conductive layer 28 can be used as a mask for etching the semiconductor layer 26 and the insulating layer 27. Alternatively, the third conductive layer 28 and the insulating layer 27 can be etched first, and the etched third conductive layer 28 and the insulating layer 27 can be used as a mask for etching the semiconductor layer 26.
[0069] In some exemplary embodiments, the material of the first isolation portion 29a may include a high dielectric constant material, which may include any one or more of hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), and strontium titanate (SrTiO3). The material of the first isolation portion 29a may also include a low dielectric constant material, that is, a dielectric material with a dielectric constant less than 3.9, such as silicon dioxide (SiO2) or silicon oxide (SiO).
[0070] (08) The sacrificial portion 16 located within the first trench 41 is etched away, such as... Figure 10A , Figure 10B , Figure 10C as well as Figure 10D As shown, Figure 10A for Figure 1 A cross-sectional view of the semiconductor device at point AA after the sacrificial portion has been etched away. Figure 10B for Figure 1 A cross-sectional view of the semiconductor device at the BB mark after the sacrificial part has been etched away. Figure 10C for Figure 1 A cross-sectional view of the semiconductor device after the sacrificial portion has been etched away at the CC mark. Figure 10D for Figure 1 A cross-sectional view of the semiconductor device after the sacrificial part has been etched away at the DD mark.
[0071] (09) Based on the first trench 41, the prefabricated structure 26a exposed by the first trench 41 is etched away, so that the prefabricated structure 26a forms at least one channel layer 24, at least a portion of the channel layer 24 extends along a third direction Z, and the channel layer 24 includes a first channel portion 24a and a second channel portion 24b spaced apart along a first direction X, such as Figure 11A , Figure 11B , Figure 11C as well as Figure 11D As shown, Figure 11A for Figure 1 A cross-sectional view of the semiconductor device after the channel layer has been formed at point AA. Figure 11B for Figure 1 A cross-sectional view of the semiconductor device after the channel layer has been formed at the location marked BB. Figure 11C for Figure 1 A cross-sectional view of the semiconductor device after the channel layer has been formed at the CC mark. Figure 11D for Figure 1The diagram shows a cross-sectional view of the semiconductor device at point DD after the formation of the channel layer. In this embodiment, the channel layer is formed by etching the prefabricated structure using a first trench. This avoids interference between two transistors spaced adjacent to each other along the second direction Y, prevents the generation of parasitic electric fields, and improves transistor performance. For example, the channel layer 24 may include a portion extending along a third direction Z and a portion extending along the first direction X. In some possible examples, the channel layer 24 may only include a portion extending along a third direction Z.
[0072] (10) A second isolation portion 29b is formed on the substrate 10 on which the aforementioned structure is formed, the second isolation portion 29b being located within the first trench 41, such as Figure 12A , Figure 12B , Figure 12C as well as Figure 12D As shown, Figure 12A for Figure 1 A cross-sectional view of the semiconductor device at point AA after the second isolation section has been formed. Figure 12B for Figure 1 A cross-sectional view of the semiconductor device after the second isolation section is formed at the BB mark. Figure 12C for Figure 1 A cross-sectional view of the semiconductor device after the second isolation section is formed at the CC mark. Figure 12D for Figure 1 The diagram shows a cross-sectional view of the semiconductor device at point DD after the formation of the second isolation portion. For example, the second isolation portion 29b can be fabricated using a deposition process. For example, the surface of the second isolation portion 29b away from the substrate 10 can be treated with chemical mechanical polishing (CMP). In this embodiment, by providing the second isolation portion, two transistors spaced adjacent to each other along the second direction Y can be isolated, signal crosstalk between adjacent transistors can be avoided, and the electrical performance of the transistors can be improved.
[0073] In some exemplary embodiments, the material of the second isolation portion may be the same as or different from the material of the first isolation portion. In the accompanying drawings of embodiments of this disclosure, the second isolation portion and the first isolation portion are filled with different patterns only for easy identification of different film layers, and not to indicate that the two components are made of different materials.
[0074] (11) A capacitor 30 is formed on the substrate 10 on which the aforementioned structure is formed, such as Figure 13A , Figure 13B , Figure 13C as well as Figure 13D As shown, Figure 13A for Figure 1 A cross-sectional view of the semiconductor device at point AA after it has been used to form a capacitor. Figure 13B for Figure 1 A cross-sectional view of the semiconductor device formed into a capacitor at the location marked BB. Figure 13C for Figure 1 A cross-sectional view of the semiconductor device formed as a capacitor at the CC mark in the diagram. Figure 13D for Figure 1 The diagram shows a cross-sectional view of the semiconductor device after a capacitor has been formed at the DD location. For example, forming the capacitor 30 may include forming a separator layer 34 on a substrate 10 forming the aforementioned structure; etching the substrate 10 to form at least one connection hole K; the separator layer 34 and the stacked structure located within the connection hole K are etched away, and a portion of the second electrode 22 is exposed in the connection hole K; subsequently, a first electrode 31, a dielectric layer 33, and a second electrode 32 are formed sequentially. A portion of the first electrode 31 is located within the connection hole K and connected to the second electrode 22, thus realizing the connection between the capacitor 30 and the transistor within the same memory cell.
[0075] This disclosure provides a method for fabricating a semiconductor device, the semiconductor device including a substrate and at least one transistor located on the substrate; the fabrication method includes: A first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer are sequentially formed on the substrate to form a stacked structure; A first trench is formed, and the first trench extends along a first direction, and the stacked structure located within the first trench is etched away; A second trench is formed, and the second trench extends along a second direction, and the stacked structure located within the second trench is etched away, such that the first conductive layer forms the first electrode of the transistor, and the second conductive layer forms the second electrode of the transistor; the first direction and the second direction intersect and the plane formed thereby is parallel to the plane of the substrate; A semiconductor layer, an insulating layer, and a third conductive layer are sequentially formed within the second trench, and the third conductive layer forms the third trench. Based on the third trench, the semiconductor layer, insulating layer, and third conductive layer are etched such that the third conductive layer forms the gate electrode of the transistor, the insulating layer forms the gate insulating layer, and the semiconductor layer forms the channel layer of the transistor; wherein, the channel layer includes a first channel portion and a second channel portion spaced apart along the first direction, both the first channel portion and the second channel portion extending along a third direction, the first electrode and the second electrode being located between the first channel portion and the second channel portion, and both the first electrode and the second electrode being connected to the first channel portion and the second channel portion; the gate electrode extends along the third direction and is located on the side of the channel layer away from the first electrode, the third direction being perpendicular to the plane of the substrate.
[0076] In some exemplary embodiments, the gate electrode includes a first gate electrode and a second gate electrode spaced apart along the first direction, wherein the first gate electrode is located on the side of the first channel portion away from the first electrode, and the second gate electrode is located on the side of the second channel portion away from the first electrode.
[0077] In some exemplary embodiments, the material of the semiconductor layer includes metal oxides.
[0078] In some exemplary embodiments, after the formation of the first trench and before the formation of the second trench, the preparation method further includes: forming a sacrificial portion within the first trench.
[0079] In some exemplary embodiments, the third conductive layer includes a connected trench bottom and trench walls, wherein the trench bottom extends along a direction parallel to the plane of the substrate, and the trench walls extend along the third direction and surround the trench bottom, the trench bottom and the trench walls together forming the third trench; the etching of the semiconductor layer, the insulating layer and the third conductive layer based on the third trench includes: The semiconductor layer, the insulating layer, and the third conductive layer located on the surface of the stacked structure away from the substrate are all etched away, and the bottom of the trench and the semiconductor layer and the insulating layer located at the bottom of the trench are all etched away to form a fourth trench, such that the semiconductor layer forms a prefabricated structure, the insulating layer forms the gate insulating layer, and the third conductive layer forms the gate electrode.
[0080] In some exemplary embodiments, the preparation method further includes forming a first isolation portion within the fourth trench.
[0081] In some exemplary embodiments, the etching of the semiconductor layer, insulating layer and third conductive layer based on the third trench further includes: etching the prefabricated structure to form the channel layer.
[0082] In some exemplary embodiments, etching the prefabricated structure includes: The sacrificial portion located within the first trench is etched away; Based on the first trench, the prefabricated structure exposed by the first trench is etched away, so that the prefabricated structure forms the trench layer.
[0083] In some exemplary embodiments, after forming the trench layer, the preparation method further includes forming a second isolation portion within the first trench.
[0084] In some exemplary embodiments, the semiconductor device further includes at least one bit line extending along the first direction; the fabrication method further includes: the first conductive layer simultaneously forming the first electrode of the transistor and the bit line.
[0085] The semiconductor device fabrication method provided in this disclosure has the advantages of simple and easy-to-implement fabrication process, fewer fabrication steps, and low fabrication cost.
[0086] This disclosure also provides an electronic device, which includes the semiconductor device provided in any of the above embodiments. The electronic device can be any electronic product with storage function, such as a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.
[0087] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes a substrate and at least one transistor located on the substrate; the fabrication method includes: A first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer are sequentially formed on the substrate to form a stacked structure; A first trench is formed, and the first trench extends along a first direction, and the stacked structure located within the first trench is etched away; A second trench is formed, and the second trench extends along a second direction, and the stacked structure located within the second trench is etched away, such that the first conductive layer forms the first electrode of the transistor, and the second conductive layer forms the second electrode of the transistor; the first direction and the second direction intersect and the plane formed thereby is parallel to the plane of the substrate; A semiconductor layer, an insulating layer, and a third conductive layer are sequentially formed within the second trench, and the third conductive layer forms the third trench. Based on the third trench, the semiconductor layer, insulating layer, and third conductive layer are etched such that the third conductive layer forms the gate electrode of the transistor, the insulating layer forms the gate insulating layer, and the semiconductor layer forms the channel layer of the transistor; wherein, the channel layer includes a first channel portion and a second channel portion spaced apart along the first direction, both the first channel portion and the second channel portion extending along a third direction, the first electrode and the second electrode being located between the first channel portion and the second channel portion, and both the first electrode and the second electrode being connected to the first channel portion and the second channel portion; the gate electrode extends along the third direction and is located on the side of the channel layer away from the first electrode, the third direction being perpendicular to the plane of the substrate.
2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The gate electrode includes a first gate electrode and a second gate electrode spaced apart along the first direction, wherein the first gate electrode is located on the side of the first channel portion away from the first electrode, and the second gate electrode is located on the side of the second channel portion away from the first electrode.
3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The semiconductor layer is made of metal oxide.
4. The method for fabricating a semiconductor device according to any one of claims 1 to 3, characterized in that, After the formation of the first trench and before the formation of the second trench, the preparation method further includes: A sacrificial part is formed within the first trench.
5. The method for fabricating a semiconductor device as described in claim 4, characterized in that, The third conductive layer includes a connected trench bottom and trench wall, wherein the trench bottom extends along a direction parallel to the plane of the substrate, and the trench wall extends along the third direction and surrounds the trench bottom, and the trench bottom and the trench wall together form the third trench; The etching of the semiconductor layer, insulating layer, and third conductive layer based on the third trench includes: The semiconductor layer, the insulating layer, and the third conductive layer located on the surface of the stacked structure away from the substrate are all etched away, and the bottom of the trench and the semiconductor layer and the insulating layer located at the bottom of the trench are all etched away to form a fourth trench, such that the semiconductor layer forms a prefabricated structure, the insulating layer forms the gate insulating layer, and the third conductive layer forms the gate electrode.
6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The preparation method further includes: A first isolation section is formed within the fourth trench.
7. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The etching of the semiconductor layer, insulating layer, and third conductive layer based on the third trench further includes: The prefabricated structure is etched to form the channel layer.
8. The method for fabricating a semiconductor device as described in claim 7, characterized in that, The etching of the prefabricated structure includes: The sacrificial portion located within the first trench is etched away; Based on the first trench, the prefabricated structure exposed by the first trench is etched away, so that the prefabricated structure forms the trench layer.
9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After forming the channel layer, the preparation method further includes: A second isolation section is formed within the first trench.
10. The method for fabricating a semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device further includes at least one bit line extending along the first direction; the fabrication method further includes: The first conductive layer simultaneously forms the first electrode of the transistor and the bit line.
11. A semiconductor device, characterized in that, The device includes a substrate and at least one memory cell located on the substrate. The memory cell includes at least one transistor. The transistor includes a first electrode, a second electrode, a gate electrode, a channel layer, and a gate insulating layer located between the gate electrode and the channel layer. The second electrode is located on the side of the first electrode away from the substrate. The channel layer includes a first channel portion and a second channel portion spaced apart along a first direction, both the first channel portion and the second channel portion extending along a third direction, the first electrode and the second electrode located between the first channel portion and the second channel portion, and both the first electrode and the second electrode connected to the first channel portion and the second channel portion; the gate electrode extends along a third direction and is located on the side of the channel layer away from the first electrode; the first direction is parallel to the plane of the substrate, and the third direction is perpendicular to the plane of the substrate.
12. The semiconductor device as claimed in claim 11, characterized in that, The gate electrode includes a first gate electrode and a second gate electrode spaced apart along the first direction, wherein the first gate electrode is located on the side of the first channel portion away from the first electrode, and the second gate electrode is located on the side of the second channel portion away from the first electrode.
13. The semiconductor device as claimed in claim 12, characterized in that, Multiple first gate electrodes arranged along the second direction are integrally formed and form a word line; multiple second gate electrodes arranged along the second direction are integrally formed and form another word line; the second direction intersects the first direction and the plane formed thereby is parallel to the plane of the substrate.
14. The semiconductor device according to any one of claims 11 to 13, characterized in that, The storage cell further includes a capacitor located on the side of the transistor away from the substrate, and the capacitor is connected to the second electrode; the orthographic projection of the capacitor onto the plane of the substrate at least partially overlaps with the orthographic projection of the transistor onto the plane of the substrate.
15. An electronic device, characterized in that, The semiconductor device includes a semiconductor device formed by the method of fabrication of a semiconductor device according to any one of claims 1 to 10, or a semiconductor device according to any one of claims 11 to 14.