Semiconductor structure and method of forming the same
By forming a protective structure within the substrate, the protective layer formed by P-type doping elements solves the substrate damage problem and improves the reliability and yield of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2026-03-16
- Publication Date
- 2026-07-24
AI Technical Summary
Existing substrates are easily damaged during semiconductor device manufacturing, leading to decreased device yield and short circuits or leakage.
A protective structure is formed within the substrate, including a first protective layer and an optional second protective layer, formed by p-type doping elements, with an etching rate lower than that of the substrate, providing protection to avoid substrate damage.
It improves the structural integrity and electrical performance of the substrate, prevents short circuits or leakage, and enhances the reliability and yield of the device.
Smart Images
Figure CN121888602B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same. Background Technology
[0002] As the physical carrier and functional foundation of semiconductor devices, the substrate provides physical support and electrical functions for the entire device and is also an important part of process integration. In 3D stacked dynamic random access memory (DRAM), higher requirements are placed on the overall performance of the substrate. Existing substrates are often damaged during device manufacturing, failing to provide complete mechanical support and electrical performance, leading to short circuits or leakage in the device and resulting in a decrease in device yield.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0004] In view of this, a semiconductor structure and a method for forming the same are provided. The semiconductor structure protects the substrate through a protective structure, thereby improving the integrity of the substrate and thus improving the device yield.
[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.
[0006] According to one aspect of this disclosure, a semiconductor structure is provided, the semiconductor structure comprising:
[0007] Substrate;
[0008] A stacked structure is located on the surface of the substrate, the stacked structure comprising alternating layers of semiconductor layers and sacrificial layers, the stacked structure including a first trench extending through the stacked structure and into the substrate along a first direction; the first direction is perpendicular to the surface of the substrate;
[0009] A protective structure is located within the substrate, the first trench exposes a portion of the upper surface of the protective structure, the protective structure includes at least a first protective layer, the first protective layer includes a p-type dopant element, and the etching rate of the first protective layer is less than the etching rate of the substrate.
[0010] In one exemplary embodiment of this disclosure, the protective structure further includes a second protective layer, which is stacked on the surface of the first protective layer facing away from the substrate, and the first trench exposes a portion of the inner surface of the second protective layer; the etching rate of the second protective layer is less than the etching rate of the first protective layer.
[0011] In one exemplary embodiment of this disclosure, the second protective layer includes both a p-type dopant element and an oxygen element.
[0012] In one exemplary embodiment of this disclosure, the semiconductor layer includes a channel region, the doping element of the channel region is the same as the doping element of the first protective layer, and the doping concentration of the first protective layer is greater than the doping concentration of the channel region.
[0013] In one exemplary embodiment of this disclosure, the semiconductor layer does not include doping elements.
[0014] In one exemplary embodiment of this disclosure, the first protective layer includes boron, and the doping concentration of boron in the first protective layer is greater than 1× .
[0015] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, the method comprising:
[0016] Provide substrate;
[0017] A stacked structure is formed on the substrate, the stacked structure including alternating layers of semiconductor layers and sacrificial layers, the stacked structure including a first trench that penetrates the stacked structure along a first direction and extends into the substrate, the first trench exposing a portion of the substrate; the first direction is perpendicular to the surface of the substrate;
[0018] The exposed portion of the substrate is doped with a p-type dopant to form a first protective layer within the substrate, the etching rate of the first protective layer being lower than the etching rate of the substrate.
[0019] In one exemplary embodiment of this disclosure, a stacked structure is formed on the substrate, including:
[0020] The semiconductor layer and the sacrificial layer are alternately stacked on the substrate;
[0021] The semiconductor layer, the sacrificial layer, and the substrate are etched sequentially along the first direction to form the first trench.
[0022] In one exemplary embodiment of this disclosure, after forming the stacked structure on the substrate, the process includes:
[0023] A first dielectric layer and a second dielectric layer are sequentially formed on the sidewall and bottom wall of the first trench;
[0024] Remove the second dielectric layer located on the bottom wall of the first trench to expose the first dielectric layer located on the bottom wall of the first trench;
[0025] The first dielectric layer located within the substrate is removed to form a first gap between the second dielectric layer and the substrate.
[0026] In one exemplary embodiment of this disclosure, a first protective layer is formed within the substrate, comprising:
[0027] The substrate is doped with a p-type dopant along the first gap to form the first protective layer within the substrate, wherein the doping concentration of the first protective layer is greater than 1× .
[0028] In one exemplary embodiment of this disclosure, after forming the first protective layer within the substrate, the process includes:
[0029] The first protective layer is oxidized along the first gap to convert a portion of the first protective layer into a second protective layer.
[0030] In one exemplary embodiment of this disclosure, a stacked structure is formed on the substrate, including:
[0031] An initial stacked structure is formed on the substrate, the initial stacked structure comprising the semiconductor layers and intermediate sacrificial layers alternately stacked on the substrate;
[0032] The semiconductor layer, the intermediate sacrificial layer, and the substrate are etched sequentially along the first direction to form the first trench;
[0033] The intermediate sacrificial layer is removed along a second direction, and an oxide insulating material is filled between two adjacent semiconductor layers to form the sacrificial layer; the second direction is parallel to the surface of the substrate.
[0034] The sacrificial layer is etched along the second direction to expose a portion of the surface of the semiconductor layer;
[0035] The semiconductor layer and the substrate are simultaneously doped with a P-type dopant to form a channel region in the semiconductor layer and an initial first protective layer in the substrate. The doping concentration of the initial first protective layer is less than that of the first protective layer.
[0036] In one exemplary embodiment of this disclosure, after forming an initial first protective layer within the substrate, the process includes:
[0037] A first dielectric layer is formed, which simultaneously covers the exposed surface of the semiconductor layer and the surface of the initial first protective layer;
[0038] A second dielectric layer is formed, which fills the remaining gaps between adjacent semiconductor layers and conformally covers the surface of the first dielectric layer;
[0039] Remove the second dielectric layer located on the bottom wall of the first trench to expose the first dielectric layer;
[0040] The first dielectric layer located within the substrate is removed to form a first gap between the second dielectric layer and the substrate.
[0041] In one exemplary embodiment of this disclosure, a first protective layer is formed within the substrate, comprising:
[0042] The initial first protective layer is doped with a p-type dopant along the first gap to form the first protective layer within the substrate, wherein the doping concentration of the first protective layer is greater than 1× .
[0043] In one exemplary embodiment of this disclosure, after forming the first protective layer within the substrate, the process includes:
[0044] The first protective layer is oxidized along the first gap to convert a portion of the first protective layer into a second protective layer.
[0045] In one exemplary embodiment of this disclosure, after forming the first protective layer, the process includes:
[0046] The first protective layer is subjected to heat treatment.
[0047] The semiconductor structure disclosed herein includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes a first trench and a protective structure located within the substrate. The first trench exposes a portion of the upper surface of the protective structure. During subsequent processing of the stacked structure through the first trench, the protective structure can protect the substrate from damage, ensuring the structural integrity of the substrate and thus improving the physical support performance of the substrate. It can also improve the electrical performance of the substrate, preventing short circuits or leakage, and improving the reliability of the device. Furthermore, the first protective layer within the protective structure is obtained by p-type doping of the substrate. The first protective layer is located within the substrate, and the etching rate of the first protective layer is lower than the etching rate of the substrate. While the first protective layer protects the substrate, its formation does not affect the overall flatness and integrity of the substrate. Moreover, the first protective layer formed by p-type doped ions within the substrate avoids the formation of an additional protective layer on the substrate, which would cause strain deformation of the substrate, ensuring the flatness of the substrate and thus improving its functionality.
[0048] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0050] Figure 1 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0051] Figure 2 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0052] Figure 3 This is a flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0053] Figure 4 This is a schematic diagram of a stacked structure in an exemplary embodiment of the present disclosure.
[0054] Figure 5 This is a schematic diagram of the structure of a first trench in an exemplary embodiment of the present disclosure.
[0055] Figure 6 This is a schematic diagram of the structure of a first dielectric layer and a second dielectric layer in an exemplary embodiment of the present disclosure.
[0056] Figure 7 This is a schematic diagram of the structure of a first dielectric layer and a second dielectric layer in an exemplary embodiment of the present disclosure.
[0057] Figure 8 This is a schematic diagram of the structure of a first gap in an exemplary embodiment of the present disclosure.
[0058] Figure 9 This is a schematic diagram of the structure of a first protective layer in an exemplary embodiment of the present disclosure.
[0059] Figure 10 This is a schematic diagram of the structure of a second protective layer in an exemplary embodiment of this disclosure.
[0060] Figure 11 This is a schematic diagram of an initial stacking structure in an exemplary embodiment of the present disclosure.
[0061] Figure 12 This is a schematic diagram of the structure of a first trench in an exemplary embodiment of the present disclosure.
[0062] Figure 13 This is a schematic diagram of a stacked structure in an exemplary embodiment of the present disclosure.
[0063] Figure 14 This is a schematic diagram of the structure of an initial first protective layer in an exemplary embodiment of the present disclosure.
[0064] Figure 15 This is a schematic diagram of the structure of a first dielectric layer in an exemplary embodiment of the present disclosure.
[0065] Figure 16 This is a schematic diagram of the structure of a second dielectric layer in an exemplary embodiment of the present disclosure.
[0066] Figure 17 This is a schematic diagram of the structure of a first gap in an exemplary embodiment of the present disclosure.
[0067] Figure 18 This is a schematic diagram of the structure of a first protective layer in an exemplary embodiment of the present disclosure.
[0068] Figure 19 This is a schematic diagram of the structure of a second protective layer according to an exemplary embodiment of the present disclosure. The reference numerals are explained as follows:
[0069] 100, Substrate; 2000, Initial stacked structure; 200, Stacked structure; 210, Semiconductor layer; 211, Channel region; 220, Sacrificial layer; 221, Intermediate sacrificial layer; 230, First trench; 300, Protective structure; 301, First protective layer; 311, Initial first protective layer; 302, Second protective layer; 401, First dielectric layer; 402, Second dielectric layer; 403, Third dielectric layer; 500, First gap; 600, Gate structure; 601, Gate layer; 602, Gate oxide layer; X, First direction; Y, Second direction. Detailed Implementation
[0070] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.
[0071] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.
[0072] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.
[0073] In related technologies, to improve the integration of semiconductor devices, vertical stacking technology is commonly used to form 3D stacked semiconductor structures, breaking the limitations of planar semiconductor layouts on device integration. The substrate, as the main structure of a semiconductor device, provides physical support and ensures the structural integrity of the device during manufacturing, packaging, and use. The flatness and integrity of the substrate directly affect the accuracy and reliability of the device fabrication process. Existing substrates are often damaged during device fabrication, affecting their physical and electrical properties.
[0074] Based on this, the present disclosure provides a semiconductor structure, such as... Figure 1 and Figure 2 As shown, the semiconductor structure includes a substrate 100, a stacked structure 200, and a protective structure 300.
[0075] The stacked structure 200 is located on the surface of the substrate 100. The stacked structure 200 includes alternating semiconductor layers 210 and sacrificial layers 220. The stacked structure 200 includes a first trench 230 that penetrates the stacked structure 200 along a first direction X and extends into the substrate 100. The protective structure 300 is located within the substrate 100. The first trench 230 exposes a portion of the upper surface of the protective structure 300. The protective structure 300 includes at least a first protective layer 301 that includes P-type doped elements. The etching rate of the first protective layer 301 is less than the etching rate of the substrate 100.
[0076] The semiconductor structure disclosed herein includes a substrate 100 and a stacked structure 200 disposed on the substrate 100. The stacked structure 200 includes a first trench 230 and a protective structure 300 located within the substrate 100. The first trench 230 exposes a portion of the upper surface of the protective structure 300. During subsequent processing of the stacked structure 200 through the first trench 230, the protective structure 300 can protect the substrate 100 from damage, ensuring the structural integrity of the substrate 100 and thus improving the physical support performance of the substrate 100. Simultaneously, it can also improve the electrical performance of the substrate 100, preventing short circuits or leakage, and improving the device's performance. The reliability of the substrate 100 is ensured. In addition, the first protective layer 301 in the protective structure 300 is obtained by p-type doping of the substrate 100. The first protective layer 301 is located in the substrate 100, and the etching rate of the first protective layer 301 is less than the etching rate of the substrate 100. While the first protective layer 301 protects the substrate 100, the formation of the first protective layer 301 does not affect the overall flatness and integrity of the substrate 100. Moreover, the first protective layer 301 formed by p-type doped ions in the substrate 100 avoids the formation of an additional protective layer on the substrate 100, which would cause the substrate 100 to undergo strain deformation, thus ensuring the flatness of the substrate 100 and improving the functionality of the substrate 100.
[0077] It should be noted that, in the embodiments provided in this disclosure, such as Figure 1 , Figure 2 as well as Figures 4 to 19 As shown, the first direction X is perpendicular to the surface of the substrate 100, and the first direction X can be understood as the vertical direction in this embodiment of the disclosure; the second direction Y is parallel to the surface of the substrate 100 and intersects with the first direction X, and the second direction Y can be understood as the horizontal direction in this embodiment of the disclosure. The first direction X and the second direction Y can form a two-dimensional rectangular coordinate system. The first direction X and the second direction Y will not be repeated in the following embodiments. However, it should be understood that the above two directions do not have a specific limiting effect on the actual structural layout and formation process of the device. When the relative position of the device is changed, the above two directions will also be adaptively changed. This disclosure does not make specific limitations.
[0078] The various parts of the semiconductor structure provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings:
[0079] In the embodiments provided in this disclosure, such as Figure 1 and Figure 2 As shown, the semiconductor structure includes a substrate 100.
[0080] The substrate 100 can be a single-element semiconductor substrate, a compound semiconductor substrate, or a wide-bandgap semiconductor substrate. In some embodiments, the single-element semiconductor substrate can be a silicon (Si) substrate, a germanium (Ge) substrate, etc. In some embodiments, the compound semiconductor substrate can be indium phosphide (InP), gallium arsenide (GaAs), or gallium antimonide (GaSb), etc. In some embodiments, the wide-bandgap semiconductor substrate can be silicon carbide (SiC), aluminum nitride (AlN), diamond, etc. Of course, the substrate 100 can also be a substrate of other materials, for example, a gallium oxide / sapphire composite substrate, a two-dimensional material substrate, etc. The substrate 100 can be selected according to the actual design requirements of the semiconductor structure, and this disclosure does not make specific limitations. The embodiments provided in this disclosure are illustrated using silicon as an example for the substrate 100, but do not limit the specific material of the substrate 100. When the substrate 100 includes other elements, the protective structure 300 in the following embodiments of this disclosure can be adapted and modified, and is still within the protection scope of this disclosure.
[0081] In the embodiments provided in this disclosure, such as Figure 1 and Figure 2 As shown, the semiconductor structure includes a stacked structure 200 located on the surface of the substrate 100.
[0082] In some embodiments, such as Figure 2As shown, the stacked structure 200 includes alternating layers of semiconductor layers 210 and sacrificial layers 220. Semiconductor layers 210 and 220 can be heterogeneous single-crystal semiconductor layers. For example, semiconductor layers 210 and 220 can be one of the following: silicon / germanium-silicon (Si / SiGe) stack, germanium-silicon / silicon (SiGe / Si) stack, germanium-silicon / germanium (SiGe / Ge) stack, germanium / germanium-silicon (Ge / SiGe) stack, silicon / germanium (Si / Ge) stack, or germanium / silicon (Ge / Si) stack. In the subsequent process of forming a semiconductor device, the sacrificial layer 220 can be replaced by an interlayer dielectric layer before the semiconductor layer 210 is processed to fabricate an active device.
[0083] In some embodiments, refer again Figure 1 The stacked structure 200 includes alternating layers of semiconductor layers 210 and sacrificial layers 220. The sacrificial layer 220 can be an interlayer dielectric layer; for example, the semiconductor layers 210 and the sacrificial layer 220 can be a silicon / silicon oxide stack. The semiconductor layer 210 may include a channel region 211, which can be formed by doping. The sacrificial layer 220 serves as an isolation film between two adjacent semiconductor layers 210 in the first direction X, preventing mutual interference between the two adjacent semiconductor layers 210 during the process and ensuring the yield of the subsequently formed device.
[0084] Among them, such as Figure 1 and Figure 2 As shown, the stacked structure 200 includes a first trench 230, which extends through the stacked structure 200 and into the substrate 100 along a first direction X. The first trench 230 can provide a channel for the subsequent fabrication of active devices within the stacked structure 200.
[0085] In the embodiments provided in this disclosure, since the first trench 230 exposes part of the upper surface of the substrate 100, in subsequent device fabrication processes, such as when the semiconductor layer 210 in the stacked structure 200 is laterally etched, the substrate 100 will be damaged by the etching solution, etching ions, etc., thus failing to provide effective support for the stacked structure 200, which may cause the stacked structure 200 to deform or even be damaged. In addition, the damaged substrate 100 may also cause electrical defects such as short circuits or leakage in subsequent devices, affecting the electrical function of the devices. Therefore, in order to prevent damage to the substrate 100, this disclosure provides a protective structure 300 located within the substrate 100. The first trench 230 exposes a portion of the upper surface of the protective structure 300, preventing the substrate 100 from being directly exposed within the first trench 230. The protective structure 300 provides effective protection for the substrate 100 in subsequent processes, ensuring the structural integrity and electrical functionality of the substrate 100. Furthermore, since the protective structure 300 is located within the substrate 100, it forms an integral structure with the substrate 100, avoiding the formation of an additional protective layer on the substrate 100 that would cause stress deformation on the substrate 100, thus ensuring the flatness of the substrate 100.
[0086] Among them, such as Figure 1 and Figure 2 As shown, the protective structure 300 includes a first protective layer 301, which includes a p-type dopant. The first protective layer 301 is located within the substrate 100 and can be obtained by p-type doping a portion of the substrate 100.
[0087] In some embodiments, the p-type dopant element can be a group III element, such as at least one of boron (B), gallium (Ga), indium (In), and aluminum (Al).
[0088] To further enhance the protective effect of the first protective layer 301 on the substrate 100, the first protective layer 301 may include element B, and the doping concentration of element B in the first protective layer 301 must be greater than 1× This allows the etching rate of the first protective layer 301 to be less than or much less than the etching rate of the substrate 100, thereby improving the protective effectiveness of the first protective layer 301 on the substrate 100.
[0089] In some embodiments, since the first trench 230 extends into the substrate 100 and the first protective layer 301 is formed on a portion of the surface of the substrate 100 exposed by the first trench 230, the cross-sectional shape of the first protective layer 301 in the plane containing the first direction X and the second direction Y can be U-shaped or U-shaped, so that the first protective layer 301 simultaneously protects the substrate 100 in the first direction X and the second direction Y.
[0090] In one implementation, such as Figure 2 As shown, when the semiconductor layer 210 does not contain doping elements, that is, when the semiconductor layer 210 and the sacrificial layer 220 in the stacked structure 200 are heterogeneous single crystal semiconductor layers, the exposed portion of the substrate 100 of the first trench 230 can be directly p-type heavily doped to form the first protective layer 301 in the substrate 100.
[0091] In one implementation, such as Figure 1 As shown, when the semiconductor layer 210 includes a channel region 211, the doping element of the channel region 211 is the same as the doping element of the first protective layer 301. The doping concentration of the first protective layer 301 is greater than that of the channel region 211. That is, when the sacrificial layer 220 in the stacked structure 200 is an interlayer dielectric layer, when the semiconductor layer 210 is doped to form the channel region 211, the same doping element can be used to simultaneously dope the semiconductor layer 210 and the exposed part of the substrate 100. While forming the channel region 211 in the semiconductor layer 210, the exposed part of the substrate 100 is initially doped. Then, through secondary doping, the doping ion concentration in the exposed part of the substrate 100 is made to at least reach a preset value. This ensures that the etching rate of the first protective layer 301 formed in the substrate 100 is less than or much less than the etching rate of the substrate 100, thus ensuring the effectiveness of the first protective layer 301 in protecting the substrate 100.
[0092] In the above embodiment, element B can be used to simultaneously dope the semiconductor layer 210 and the exposed portion of the substrate 100. After forming the channel region 211 within the semiconductor layer 210, element B is used again to perform a secondary doping on the region of the substrate 100 that already contains element B, thereby increasing the concentration of element B in this region of the substrate 100. The concentration of element B is greater than 1× At this time, a first protective layer 301 is formed in the substrate 100. The etching rate of the first protective layer 301 is less than the etching rate of the substrate 100. In subsequent processes, the first protective layer 301 can protect the substrate 100 from damage caused by etching solutions and other factors, ensuring the structural integrity and good electrical function of the substrate 100, thereby improving the overall reliability and yield of the device.
[0093] In the above embodiments, such as Figure 1 As shown, the semiconductor structure also includes a first dielectric layer 401, which covers a portion of the outer surface of the semiconductor layer 210, and the first dielectric layer 401 exposes at least the channel region 211. The setting of the first dielectric layer 401 can define the range of the channel region 211 within the semiconductor layer 210, providing a structural basis for the subsequent formation of the gate structure 600.
[0094] Refer again Figure 1The semiconductor structure also includes a gate structure 600, which at least covers a portion of the outer surface of the channel region 211. In the first direction X, a second dielectric layer 402 is provided between two adjacent gate structures 600. In the second direction Y, the first dielectric layer 401, the gate structure 600, and the third dielectric layer 403 are adjacent to each other. By providing the first dielectric layer 401, the second dielectric layer 402, and the third dielectric layer 403, electrical isolation can be formed between two adjacent active devices, avoiding crosstalk between two adjacent active devices and ensuring the electrical reliability of the device.
[0095] The first dielectric layer 401, the second dielectric layer 402, and the third dielectric layer 403 can be made of insulating materials such as silicon nitride and silicon oxide. The first dielectric layer 401 and the second dielectric layer 402 are made of different materials, and the second dielectric layer 402 and the third dielectric layer 403 are made of different materials, so that the etching rate of the second dielectric layer 402 is different from that of the first dielectric layer 401 and the third dielectric layer 403, in order to meet the requirements of the film etching process in the active device.
[0096] The gate structure 600 may include a gate oxide layer 602 and a gate layer 601 that sequentially cover the channel region 211. After an active device is formed in the structure, the conduction state of the active device can be controlled by controlling the gate structure 600.
[0097] The gate layer 601 can be made of a metallic material, such as titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), titanium aluminum carbide (TiAlC), or tantalum aluminum carbide (TaAlC).
[0098] The gate oxide layer 602 can be made of a high dielectric constant material, such as hafnium-based oxides, zirconium-based oxides, lanthanide oxides, yttrium-based oxides, tantalum-based oxides, titanate systems, etc. For example, the gate oxide layer 602 can be made of one or more of the following materials: hafnium dioxide (HfO2), hafnium silicate (HfSiO4), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), strontium titanate (SrTiO3), gadolinium oxide (Gd2O3), yttrium oxide (Y2O3), scandium oxide (Sc2O3), tantalum-hafnium oxide (HfTaO).
[0099] In some embodiments, such as Figure 1 and Figure 2In the two semiconductor structures shown, the protective structure 300 may further include a second protective layer 302. The second protective layer 302 is stacked on the surface of the first protective layer 301 facing away from the substrate 100. The first trench 230 exposes part of the inner surface of the second protective layer 302. The etching rate of the second protective layer 302 is less than that of the first protective layer 301. The second protective layer 302 can provide further protection for the substrate 100. The second protective layer 302 and the first protective layer 301 form a protective structure 300 with dual protection, which can further improve the protection effect of the protective structure 300 on the substrate 100, further ensure that the substrate 100 is not damaged in the device fabrication process, and ensure the integrity of the mechanical and electrical properties of the substrate 100.
[0100] The second protective layer 302 may include both p-type dopant and oxygen. The second protective layer 302 can be formed within the exposed first protective layer 301 by oxidizing the first protective layer 301. The second protective layer 302 has good uniformity and provides better protection for the substrate 100 than a protective layer with only oxygen. In addition, the second protective layer 302 has a smaller impact on the bending value of the substrate 100, ensuring the flatness of the substrate 100 and thus ensuring the physical support performance of the substrate 100 for the stacked structure 200.
[0101] In some specific embodiments, the thickness ratio of the second protective layer 302 to the first protective layer 301 can be 1:1 to 1:5, which ensures that the second protective layer 302 has sufficient thickness while avoiding long-term oxidation from adversely affecting the semiconductor layer 210 in the stacked structure 200.
[0102] The semiconductor structure provided in this disclosure includes a protective structure 300, which includes a first protective layer 301 and a second protective layer 302. Through the synergistic effect of the first protective layer 301 and the second protective layer 302, the substrate 100 can be provided with dual protection. When the semiconductor layer 210 in the stacked structure 200 is subsequently processed, the substrate 100 can be prevented from being damaged, so that the substrate 100 can provide effective physical support for the upper structure, while avoiding leakage or short circuit problems, thus ensuring the structural integrity and functional effectiveness of the substrate 100.
[0103] The semiconductor structure disclosed herein can be applied to semiconductor devices, which may be one or more of the following: dynamic random access memory (DRAM), embedded DRAM, NAND memory, ferroelectric RAM (FeRAM), spin-transfer torque RAM (STTRAM), phase-change RAM (PCRAM), or resistive RAM (ReRAM).
[0104] This disclosure provides a method for forming a semiconductor structure, used to prepare the semiconductor structure provided in any of the above embodiments, such as... Figure 3 As shown, combined with Figure 1 , Figure 2 as well as Figures 4 to 19 The formation method includes steps S10 to S30.
[0105] Step S10: Provide substrate 100;
[0106] Step S20: A stacked structure 200 is formed on the substrate 100. The stacked structure 200 includes alternating semiconductor layers 210 and sacrificial layers 220. The stacked structure 200 includes a first trench 230. The first trench 230 penetrates the stacked structure 200 along a first direction X and extends into the substrate 100. The first trench 230 exposes a portion of the substrate 100. The first direction X is perpendicular to the surface of the substrate 100.
[0107] Step S30: The exposed portion of the substrate 100 is doped with a P-type dopant to form a first protective layer 301 within the substrate 100. The etching rate of the first protective layer 301 is less than the etching rate of the substrate 100.
[0108] The semiconductor structure formation method provided in this disclosure involves doping an exposed portion of the substrate 100 to form a first protective layer 301 within the substrate 100. The etching rate of the first protective layer 301 is lower than the etching rate of the substrate 100. The first protective layer 301 can effectively protect the substrate 100, preventing damage to the substrate 100 in subsequent processes, ensuring the structural integrity and functionality of the substrate 100, and ensuring that the substrate 100 can provide effective physical support for the stacked structure 200. At the same time, it overcomes electrical defects such as leakage or short circuits caused by damage to the substrate 100, thereby improving the device yield.
[0109] The steps of the method for forming a semiconductor structure according to the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings:
[0110] In the embodiments provided in this disclosure, such as Figure 4 and Figure 11 As shown, in step S10, a substrate 100 is provided.
[0111] The substrate 100 can be a single-element semiconductor substrate, a compound semiconductor substrate, or a wide-bandgap semiconductor substrate. In some embodiments, the single-element semiconductor substrate can be a silicon (Si) substrate, a germanium (Ge) substrate, etc. In some embodiments, the compound semiconductor substrate can be indium phosphide (InP), gallium arsenide (GaAs), or gallium antimonide (GaSb), etc. In some embodiments, the wide-bandgap semiconductor substrate can be silicon carbide (SiC), aluminum nitride (AlN), diamond, etc. Of course, the substrate 100 can also be a substrate of other materials, for example, a gallium oxide / sapphire composite substrate, a two-dimensional material substrate, etc. The substrate 100 can be selected according to the actual design requirements of the semiconductor structure, and this disclosure does not make specific limitations. The embodiments provided in this disclosure are illustrated using silicon as an example for the substrate 100, but do not limit the specific material of the substrate 100. When the substrate 100 includes other elements, the protective structure 300 in the following embodiments of this disclosure can be adapted and modified, and is still within the protection scope of this disclosure.
[0112] In the embodiments provided in this disclosure, in steps S20 and S30, a stacked structure 200 is formed on the substrate 100; and a first protective layer 301 is formed within the substrate 100.
[0113] In one exemplary embodiment, performing step S20 includes: as follows Figure 4 As shown, semiconductor layers 210 and sacrificial layers 220 are alternately stacked on substrate 100; as Figure 5 As shown, the semiconductor layer 210, the sacrificial layer 220 and the substrate 100 are etched sequentially along the first direction X to form the first trench 230.
[0114] The semiconductor layer 210 and the sacrificial layer 220 can be heterogeneous single-crystal semiconductor layers. For example, the semiconductor layer 210 and the sacrificial layer 220 can be silicon / germanium silicon (Si / SiGe) stacks.
[0115] The semiconductor layer 210, sacrificial layer 220, and substrate 100 can be etched sequentially along the first direction X using one or a combination of wet etching, dry etching, and other methods. Wet etching can include chemical solution etching, electrochemical etching, or photo-enhanced wet etching, while dry etching can include plasma etching, atomic layer etching, or vapor phase etching. Furthermore, etching methods can also include other special etching methods, such as laser etching and thermal reactive etching. The first trench 230 is formed by etching the stacked structure 200, exposing a portion of the substrate 100 surface. This provides a structural basis for the subsequent formation of the protective structure 300. Additionally, the first trench 230 can serve as a channel for forming active devices within the stacked structure 200. Capacitors or bit lines can also be formed within the first trench 230 to ensure the overall structural integrity of the device.
[0116] In this embodiment, after executing step S20 and before executing step S30, the method further includes: Figure 6 As shown, a first dielectric layer 401 and a second dielectric layer 402 are sequentially formed on the sidewall and bottom wall of the first trench 230; as Figure 7 As shown, the second dielectric layer 402 located on the bottom wall of the first trench 230 is removed to expose the first dielectric layer 401 located on the bottom wall of the first trench 230; as Figure 8 As shown, the first dielectric layer 401 located within the substrate 100 is removed to form a first gap 500 between the second dielectric layer 402 and the substrate 100. The first dielectric layer 401 protects the sidewalls of the stacked structure 200, preventing doping elements from entering the stacked structure 200 when the protective structure 300 is formed within the substrate 100, thus providing a good structural foundation for the subsequent formation of active devices within the stacked structure 200. Furthermore, by forming the first gap 500 between the second dielectric layer 402 and the substrate 100, the first gap 500 serves as a channel for doping elements to subsequently form the first protective layer 301, ensuring the formation shape of the first protective layer 301 and improving the comprehensive protection of the substrate 100 by the first protective layer 301.
[0117] During the doping process of substrate 100, since the deposition rate of dopant elements is different on different materials, in order to further enable the selective deposition of dopant elements on substrate 100, the deposition capacity of dopant elements on the first dielectric layer 401 and the second dielectric layer 402 must be less than or much less than the deposition capacity of dopant elements on substrate 100. For example, the first dielectric layer 401 may include silicon nitride, and the second dielectric layer 402 may include silicon oxide. Since the deposition capacity of dopant elements on silicon oxide and silicon nitride is less than the doping capacity of dopant elements on silicon, the negative effects of dopant elements on other film layers in the structure other than the substrate are avoided.
[0118] Furthermore, the first dielectric layer 401 and the second dielectric layer 402 may be formed by one or more of the following methods: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal oxidation, and sol-gel method. This disclosure does not impose any specific limitations.
[0119] like Figure 9As shown, step S30 includes: doping the substrate 100 with a p-type dopant element along the first gap 500 to form a first protective layer 301 within the substrate 100, wherein the doping concentration of the first protective layer 301 is greater than 1× This ensures that the etching rate of the first protective layer 301 is less than the etching rate of the substrate 100, thereby achieving a protective effect on the substrate 100.
[0120] Since the first gap 500 is U-shaped or U-like, the doping element does doping on the substrate 100 through the first gap 500, forming a U-shaped or U-like first protective layer 301 in the substrate 100. The first protective layer 301 can protect the substrate 100 in the first direction X and the second direction Y at the same time, and the first protective layer 301 can provide comprehensive protection for the substrate 100 in multiple directions.
[0121] After performing step S30, the method further includes: heat-treating the first protective layer 301. Heat treatment can improve the uniformity of the doped elements, thereby improving the uniformity and stability of the first protective layer 301.
[0122] like Figure 10 As shown, after performing step S30, the method may further include: oxidizing the first protective layer 301 along the first gap 500 to convert a portion of the first protective layer 301 into the second protective layer 302.
[0123] The oxidation process involves subjecting the first protective layer 301 to water vapor oxidation at a temperature of 500℃~800℃ for 1h~2h to form a second protective layer 302 within the first protective layer 301. Using water vapor oxidation of the first protective layer 301 results in a second protective layer 302 with better uniformity. Furthermore, the second protective layer 302 has minimal impact on the curvature of the substrate 100, preventing strain and bending problems in the substrate 100 and improving the flatness of the substrate 100.
[0124] In this embodiment, by forming a second protective layer 302 that simultaneously includes doped elements and oxygen elements, the etching rate of the second protective layer 302 is lower than that of the first protective layer 301. The second protective layer 302 provides further protection for the substrate 100, thereby improving the effectiveness and reliability of the protection structure 300 in protecting the substrate 100.
[0125] Refer again Figure 2 After forming the second protective layer 302, the method may further include: removing the remaining first dielectric layer 401 and second dielectric layer 402 to expose the inner surface of the first trench 230. Subsequently, active devices may be formed within the stacked structure 200, and structures such as bit lines or capacitors may be formed within the first trench 230 to form the memory cells of the devices.
[0126] In one exemplary embodiment, performing step S20 includes: as follows Figure 11 As shown, an initial stacked structure 2000 is formed on the substrate 100. The initial stacked structure 2000 includes semiconductor layers 210 and intermediate sacrificial layers 221 alternately stacked on the substrate 100; as Figure 12 As shown, the semiconductor layer 210, the intermediate sacrificial layer 221, and the substrate 100 are sequentially etched along the first direction X to form the first trench 230; as Figure 13 As shown, the intermediate sacrificial layer 221 is removed along the second direction Y, and an oxide insulating material is filled between two adjacent semiconductor layers 210 to form a sacrificial layer 220; the sacrificial layer 220 is etched along the second direction Y to expose a portion of the surface of the semiconductor layer 210; as shown Figure 14 As shown, P-type doping elements are used to simultaneously dope the semiconductor layer 210 and the substrate 100 to form a channel region 211 in the semiconductor layer 210 and an initial first protective layer 311 in the substrate 100. The doping concentration of the initial first protective layer 311 is less than that of the first protective layer 301.
[0127] The initial stacked structure 2000 includes a semiconductor layer 210 and an intermediate sacrificial layer 221. The semiconductor layer 210 and the intermediate sacrificial layer 221 can be heterogeneous single-crystal semiconductor layers, for example, a silicon / silicon germanium (Si / SiGe) stack. After forming the first trench 230, the intermediate sacrificial layer 221 is replaced by the sacrificial layer 220 to form an electrically isolated film between the semiconductor layers 210, preventing the processes of two adjacent semiconductor layers 210 from interfering with each other.
[0128] In this embodiment, the substrate 100 is first doped while the channel region 211 is formed in the semiconductor layer 210, and an initial first protective layer 311 is formed in the substrate 100. That is, the substrate 100 is pre-doped during the formation of the channel region 211, which can shorten the doping time of the subsequent first protective layer 301 and reduce the amount of doped ions required for the formation of the subsequent first protective layer 301.
[0129] The removal of the intermediate sacrificial layer 221 and the etching of the sacrificial layer 220 along the second direction Y can be performed using one or a combination of wet etching, dry etching, and other methods. Wet etching can be chemical solution etching, electrochemical etching, or photo-enhanced wet etching, while dry etching can be plasma etching, atomic layer etching, vapor phase etching, etc. In addition, etching methods can also include other special etching methods, such as laser etching and thermal reactive etching.
[0130] In this embodiment, after executing step S20 and before executing step S30, the method further includes: Figure 15 As shown, a first dielectric layer 401 is formed, which simultaneously covers the exposed surface of the semiconductor layer 210 and the surface of the initial first protective layer 311; as Figure 16 As shown, a second dielectric layer 402 is formed, which fills the remaining gaps between adjacent semiconductor layers 210 and conformally covers the surface of the first dielectric layer 401; the second dielectric layer 402 located on the bottom wall of the first trench 230 is removed to expose the first dielectric layer 401; as shown Figure 17 As shown, the first dielectric layer 401 located within the substrate 100 is removed to form a first gap 500 between the second dielectric layer 402 and the substrate 100. The first dielectric layer 401 protects the sidewalls of the stacked structure 200, preventing doping elements from entering the stacked structure 200 when the protective structure 300 is formed within the substrate 100, thus providing a good structural foundation for the subsequent formation of active devices within the stacked structure 200. Furthermore, by forming the first gap 500 between the second dielectric layer 402 and the substrate 100, the first gap 500 serves as a channel for doping elements to subsequently form the first protective layer 301, ensuring the formation shape of the first protective layer 301 and improving the comprehensive protection of the substrate 100 by the first protective layer 301.
[0131] During the doping process of substrate 100, since the deposition rate of dopant elements is different on different materials, in order to further enable the selective deposition of dopant elements on substrate 100, the deposition capacity of dopant elements on the first dielectric layer 401 and the second dielectric layer 402 must be less than or much less than the deposition capacity of dopant elements on substrate 100. For example, the first dielectric layer 401 may include silicon nitride, and the second dielectric layer 402 may include silicon oxide. Since the deposition capacity of dopant elements on silicon oxide and silicon nitride is less than the doping capacity of dopant elements on silicon, the negative effects of dopant elements on other film layers in the structure other than the substrate are avoided.
[0132] Furthermore, the first dielectric layer 401 and the second dielectric layer 402 may be formed by one or more of the following methods: PVD, CVD, ALD, thermal oxidation, sol-gel, etc. This disclosure does not impose any specific limitations.
[0133] Execution step S30 includes: such as Figure 18 As shown, a p-type dopant element is used to dope the substrate 100 along the first gap 500 to form a first protective layer 301 within the substrate 100. The doping concentration of the first protective layer 301 is greater than 1× This ensures that the etching rate of the first protective layer 301 is less than the etching rate of the substrate 100, thereby achieving a protective effect on the substrate 100.
[0134] Since the first gap 500 is U-shaped or U-like, the doping element does doping on the substrate 100 through the first gap 500, forming a U-shaped or U-like first protective layer 301 in the substrate 100. The first protective layer 301 can protect the substrate 100 in the first direction X and the second direction Y at the same time, and the first protective layer 301 can provide comprehensive protection for the substrate 100 in multiple directions.
[0135] After performing step S30, the method further includes: heat-treating the first protective layer 301. Heat treatment can improve the uniformity of the doped elements, thereby improving the uniformity and stability of the first protective layer 301.
[0136] After performing step S30, the method may further include: Figure 19 As shown, the first protective layer 301 is oxidized along the first gap 500 so that a portion of the first protective layer 301 is transformed into the second protective layer 302.
[0137] The oxidation process involves subjecting the first protective layer 301 to water vapor oxidation at a temperature of 500℃~800℃ for 1h~2h to form a second protective layer 302 within the first protective layer 301. Using water vapor oxidation of the first protective layer 301 results in a second protective layer 302 with better uniformity. Furthermore, the second protective layer 302 has minimal impact on the curvature of the substrate 100, preventing strain and bending problems in the substrate 100 and improving the flatness of the substrate 100.
[0138] In some embodiments, the oxidation process can be performed on the first protective layer 301 at a temperature of 700°C for 1 hour using water vapor oxidation. Using the above processing conditions to perform water vapor oxidation on the first protective layer 301 can reduce the adverse effects of water vapor oxidation on the active layer (semiconductor layer 210) and improve the quality of the active device subsequently formed. In addition, the second protective layer 302 formed under the above processing conditions has better uniformity and can improve the etch selectivity of the second protective layer 302. When performing the etching process on the stacked structure 200, the protection effect of the second protective layer 302 on the substrate 100 can be improved, further improving the structural integrity of the substrate 100.
[0139] In this embodiment, by forming a second protective layer 302 that simultaneously includes doped elements and oxygen elements, the etching rate of the second protective layer 302 is lower than that of the first protective layer 301. The second protective layer 302 provides further protection for the substrate 100, thereby improving the effectiveness and reliability of the protection structure 300 in protecting the substrate 100.
[0140] Refer again Figure 1 After forming the second protective layer 302, the method may further include forming a gate structure 600 within the stacked structure 200.
[0141] In some embodiments, forming the gate structure 600 includes: removing Figure 19 The portion of the first dielectric layer 401 and the portion of the second dielectric layer 402 shown are used to expose the outer surface of the channel region 211 and the sidewalls of the semiconductor layer 210 located within the first trench 230, forming a structure as shown in the diagram. Figure 19 The structure shown includes a final first dielectric layer 401 and a final second dielectric layer 402; a gate oxide layer 602 and a gate layer 601 are sequentially deposited on the outer surface of the exposed channel region 211, the gate oxide layer 602 and the gate layer 601 forming a gate structure 600; and a third dielectric layer 403 is filled in the remaining gap between two adjacent semiconductor layers 210.
[0142] Active devices are formed within the stacked structure 200 of the semiconductor structure provided in this disclosure. Subsequently, bit lines or capacitors or other structures can be formed within the first trench 230 to form the memory cells of the device.
[0143] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0144] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; A stacked structure located on the surface of the substrate, the stacked structure comprising alternating layers of semiconductor layers and sacrificial layers, the stacked structure including a first trench extending through the stacked structure and into the substrate along a first direction; The first direction is perpendicular to the surface of the substrate; A protective structure is located within the substrate, with a first trench exposing a portion of the upper surface of the protective structure. The protective structure includes a first protective layer and a second protective layer. The first protective layer includes a p-type dopant element and is obtained by doping the substrate. The etching rate of the first protective layer is lower than the etching rate of the substrate. The second protective layer is stacked on the surface of the first protective layer facing away from the substrate. The first trench exposes a portion of the inner surface of the second protective layer. The etching rate of the second protective layer is lower than the etching rate of the first protective layer. The second protective layer is obtained by oxidizing the first protective layer and includes both a p-type dopant element and an oxygen element.
2. The semiconductor structure according to claim 1, characterized in that, The semiconductor layer includes a channel region, the doping element of the channel region is the same as the doping element of the first protective layer, and the doping concentration of the first protective layer is greater than the doping concentration of the channel region.
3. The semiconductor structure according to claim 1, characterized in that, The semiconductor layer does not contain doping elements.
4. The semiconductor structure according to any one of claims 1-3, characterized in that, The first protective layer includes boron, and the doping concentration of boron in the first protective layer is greater than 1× .
5. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A stacked structure is formed on the substrate, the stacked structure including alternating layers of semiconductor layers and sacrificial layers, the stacked structure including a first trench that penetrates the stacked structure along a first direction and extends into the substrate, the first trench exposing a portion of the substrate; The first direction is perpendicular to the surface of the substrate; The exposed portion of the substrate is doped with a p-type dopant to form a first protective layer within the substrate, the etching rate of the first protective layer being lower than the etching rate of the substrate. The first protective layer is oxidized to convert a portion of the first protective layer into a second protective layer, wherein the etching rate of the second protective layer is less than that of the first protective layer.
6. The method for forming a semiconductor structure according to claim 5, characterized in that, Forming a stacked structure on the substrate includes: The semiconductor layer and the sacrificial layer are alternately stacked on the substrate; The semiconductor layer, the sacrificial layer, and the substrate are etched sequentially along the first direction to form the first trench.
7. The method for forming a semiconductor structure according to claim 6, characterized in that, After forming the stacked structure on the substrate, the following is included: A first dielectric layer and a second dielectric layer are sequentially formed on the sidewall and bottom wall of the first trench; Remove the second dielectric layer located on the bottom wall of the first trench to expose the first dielectric layer located on the bottom wall of the first trench; The first dielectric layer located within the substrate is removed to form a first gap between the second dielectric layer and the substrate.
8. The method for forming a semiconductor structure according to claim 7, characterized in that, A first protective layer is formed within the substrate, comprising: The substrate is doped with a p-type dopant along the first gap to form the first protective layer within the substrate, wherein the doping concentration of the first protective layer is greater than 1× .
9. The method for forming a semiconductor structure according to claim 8, characterized in that, After forming the first protective layer within the substrate, the process includes: The first protective layer is oxidized along the first gap to convert a portion of the first protective layer into a second protective layer.
10. The method for forming a semiconductor structure according to claim 5, characterized in that, Forming a stacked structure on the substrate includes: An initial stacked structure is formed on the substrate, the initial stacked structure comprising the semiconductor layers and intermediate sacrificial layers alternately stacked on the substrate; The semiconductor layer, the intermediate sacrificial layer, and the substrate are etched sequentially along the first direction to form the first trench; The intermediate sacrificial layer is removed along a second direction, and an oxide insulating material is filled between two adjacent semiconductor layers to form the sacrificial layer; the second direction is parallel to the surface of the substrate. The sacrificial layer is etched along the second direction to expose a portion of the surface of the semiconductor layer; The semiconductor layer and the substrate are simultaneously doped with a P-type dopant to form a channel region in the semiconductor layer and an initial first protective layer in the substrate. The doping concentration of the initial first protective layer is less than that of the first protective layer.
11. The method for forming a semiconductor structure according to claim 10, characterized in that, After forming an initial first protective layer within the substrate, the process includes: A first dielectric layer is formed, which simultaneously covers the exposed surface of the semiconductor layer and the surface of the initial first protective layer; A second dielectric layer is formed, which fills the remaining gaps between adjacent semiconductor layers and conformally covers the surface of the first dielectric layer; Remove the second dielectric layer located on the bottom wall of the first trench to expose the first dielectric layer; The first dielectric layer located within the substrate is removed to form a first gap between the second dielectric layer and the substrate.
12. The method for forming a semiconductor structure according to claim 11, characterized in that, A first protective layer is formed within the substrate, comprising: The initial first protective layer is doped with a p-type dopant along the first gap to form the first protective layer within the substrate, wherein the doping concentration of the first protective layer is greater than 1× .
13. The method for forming a semiconductor structure according to claim 12, characterized in that, After forming the first protective layer within the substrate, the process includes: The first protective layer is oxidized along the first gap to convert a portion of the first protective layer into a second protective layer.
14. The method for forming a semiconductor structure according to claim 8 or 12, characterized in that, After the first protective layer is formed, the process includes: The first protective layer is subjected to heat treatment.