Semiconductor device

Abstract

There is provided a semiconductor device including: a base pattern; channel layers disposed to be spaced apart from each other in a first direction perpendicular to the front side of the base pattern on the front side of the base pattern; a first source / drain region and a second source / drain region electrically connected to the channel layer on the front side of the base pattern; a backside contact plug electrically connected to the first source / drain region from a backside of the base pattern; and a front side contact plug electrically connected to the second source / drain region over a front side of the base pattern, and the first source / drain region includes: first first layers disposed on side surfaces of the channel layer each perpendicular to a second direction crossing the first direction; and a first second layer disposed on the first first layer, and the backside contact plug is spaced apart from the first first layer.

Description

[0001] This application claims that No. 10, filed with the Korean Intellectual Property Office on October 15, 2024. 2024 The priority of the benefit of Korean Patent Application No. 0140565, the entire publication of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices. Background Technology

[0003] FinFETs and nanosheet field-effect transistors have been adopted as a technology for integrated circuits with highly integrated devices and high performance. A FinFET includes a channel layer whose at least three surfaces are surrounded by a gate structure and has one or more horizontally arranged vertical fin structures. Gate-all-around (GAA) transistors or multi-bridge channel transistors are known as examples of nanosheet field-effect transistors, and nanosheet field-effect transistors include one or more nanosheet channel layers vertically stacked on a substrate and a gate structure surrounding each nanosheet channel layer.

[0004] To address wiring complexity and prevent excessive voltage drop at the front side of the field-effect transistor (FET), a back-side power distribution network (BSPDN) has been formed on the back side of the FET using at least a portion of the back-end process (BEOL). The back-side power distribution network may include back-side wiring lines that supply voltage to the source / drain regions of the FET.

[0005] The back-side power distribution network can be directly connected to the source / drain region via a back-side contact plug (e.g., a direct back-side contact (DBC)). The source / drain region may include a first layer at least at its edges and a second layer filling the region excluding the area where the first layer is located. Here, the first and second layers may include silicon (Si), and each of the first and second layers may be doped with an impurity (e.g., germanium (Ge)). For example, an epitaxial growth scheme can be applied to the source / drain region, and the first layer may be a base / seed layer for growing the second layer, which essentially performs the source / drain function. Due to the difference in impurity concentration, the first and second layers may have different contact resistances R at the contact area where they contact the back-side contact plug. cnt In some cases, the contact resistance increases compared to the case where only the second layer is connected, because the impurity concentration in the first layer is lower than that in the second layer, and because the back-side contact plug inevitably contacts the first layer when directly connected to the source / drain region.

[0006] In the gate structure, a spacer can be disposed between the gate electrode and the source / drain region. In this case, since the gate electrode and the second layer, which essentially performs the source / drain function, do not contact each other due to the spacer, the second layer can be grown in the bottom region after the first layer is grown. Since the first layer is formed only in the bottom region, a back-side contact plug can be connected to or contact the second layer after the first layer is completely removed. However, since the second layer is grown on a wide layer / region with various surface properties (such as the side surface of the spacer), the second layer is grown with defects and is not conformal. In this case, contact resistance R can be prevented. cnt The increase is due to the back-side contact plug not contacting the first layer. However, since the second layer, which essentially performs the source / drain function, is grown to be defective and does not apply quantum stress to the channel layer, the mobility of electrons in the channel layer may not be improved.

[0007] When the first layer is formed and grown not only in the bottom region but also at the edges including the side surface regions, the second layer can be grown conformally to apply quantum stress to the channel layer. However, since the back-side contact plug needs to contact the first layer in order to contact the second layer, the contact resistance R... cnt It will increase. Summary of the Invention

[0008] One aspect of this disclosure provides a semiconductor device that minimizes contact resistance at the contact region where the back-side contact plug contacts the source / drain region, and applies sufficient quantum stress to the source / drain region in the semiconductor device to improve the mobility of electrons in the channel layer.

[0009] However, the objectives to be achieved by the exemplary embodiments of this disclosure are not limited to the above objectives, and other objectives may be clearly understood by those skilled in the art from the following exemplary embodiments.

[0010] According to one aspect, a semiconductor device is provided, comprising: a substrate pattern; channel layers configured to be spaced apart from each other on a front side of the substrate pattern in a first direction perpendicular to the front side of the substrate pattern; an inner gate structure disposed between the channel layers; a first source / drain region electrically connected to the channel layers on the front side of the substrate pattern; a second source / drain region spaced apart from the first source / drain region in a second direction intersecting the first direction and electrically connected to the channel layers on the front side of the substrate pattern; a back-side contact plug electrically connected from the back side of the substrate pattern opposite to the front side of the substrate pattern to the first source / drain region; and a front-side contact plug electrically connected to the second source / drain region on the front side of the substrate pattern, wherein the first source / drain region includes: a first The first layer is disposed on the side surface of the channel layer, the side surface of the channel layer being perpendicular to the second direction; and the first The second layer is set in the first layer. On the first layer, and the back side contact plug with the first The first layer is separated.

[0011] According to another aspect, a semiconductor device is also provided, comprising: a substrate pattern; a first active pattern formed in a first active region extending in a second direction on a front side of the substrate pattern; a second active pattern spaced apart from the first active pattern in a third direction intersecting the second direction and formed in a second active region extending in the second direction on a front side of the substrate pattern; gate structures configured to be spaced apart from each other in the second direction on a front side of the substrate pattern and intersecting each of the first and second active patterns, each of the gate structures including an inner gate structure; a back-side contact plug; and a front-side contact plug, wherein each of the first and second active patterns includes: a channel layer, The active pattern is configured to be spaced apart from each other in a first direction intersecting a second direction and a third direction on the front side of the substrate pattern; a first source / drain region is connected to a channel layer on the front side of the substrate pattern; and a second source / drain region is spaced apart from the first source / drain region in the second direction and connected to the channel layer on the front side of the substrate pattern, an inner gate structure is disposed between the channel layers, a back-side contact plug is connected from the back side of the substrate pattern opposite to the front side of the substrate pattern to the first source / drain region, and a front-side contact plug is connected to the second source / drain region on the front side of the substrate pattern. Each of the first source / drain regions of the first active pattern and the second active pattern includes: a first... The first layer is disposed on the side surface of each of the channel layers, said side surface of each of the channel layers being perpendicular to the second direction; and the first The second layer is set in the first layer. On the first layer, the back-side contact plug in the first active region is connected to the first source / drain region. The first layer is spaced apart, and the back-side contact plug in the second active region is connected to the first layer of the second source / drain region. The first layer is separated.

[0012] According to another aspect, a semiconductor device is also provided, comprising: a substrate pattern; a first active pattern extending in a second direction on a front side of the substrate pattern; a second active pattern spaced apart from the first active pattern in a third direction intersecting the second direction and extending in the second direction on a front side of the substrate pattern; a gate structure configured to be spaced apart from each other in the second direction on a front side of the substrate pattern and intersecting each of the first and second active patterns, the gate structure including an inner gate structure; a back-side contact plug; and a front-side contact plug, wherein each of the first and second active patterns includes: a channel layer configured on the front side of the substrate pattern. The active and passive active patterns are spaced apart from each other in a first direction intersecting the second and third directions; a first source / drain region contacts a channel layer on the front side of the substrate pattern; and a second source / drain region is spaced apart from the first source / drain region in the second direction and contacts a channel layer on the front side of the substrate pattern, an inner gate structure is disposed between the channel layers, a back contact plug contacts the first source / drain region from the back side of the substrate pattern opposite to the front side of the substrate pattern, and a front contact plug contacts the second source / drain region on the front side of the substrate pattern. Each of the first source / drain regions of the first active pattern and the second active pattern includes: a first... A first layer, comprising impurities and disposed on the side surface of each of the channel layers, the side surface being perpendicular to the second direction; and a first The second layer is set in the first layer. On the first layer, and including concentrations higher than the first The first layer of impurities, the back-side contact plug in the first active region and the first source / drain region The first layer is separated, and the back-side contact plug in the second active region is connected to the first layer of the second source / drain region. The first layer is separated, the first source / drain region is the first At least a portion of the first layer is configured to be conformal on the side surface of the channel layer, with the first source / drain region being closer to the front side of the substrate pattern. The length of the first layer's end adjacent to the front side of the substrate pattern gradually decreases in the second direction, and the first source / drain region's first... The first layer has an inclined surface at its end, the inclined surface having an acute angle of inclination relative to the side surface of the channel layer, and the first source / drain region of the second layer... At least a portion of the first layer is configured to be conformal on the side surface of the channel layer, with the first source / drain region approaching the front side of the substrate pattern. The length of the first layer's end adjacent to the front side of the substrate pattern gradually decreases in the second direction, and the first of the second source / drain regions... The end of the first layer has an inclined surface, which has an acute angle of inclination relative to the side surface of the channel layer.

[0013] Additional aspects of the example embodiments will be set forth in part in the description which follows, and will also be apparent from the description in part. Attached Figure Description

[0014] The above and / or other aspects, features, and advantages of the invention will become clearer and more readily understood from the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is an example layout diagram illustrating a semiconductor device according to an example embodiment of the present disclosure; Figure 2 It shows along Figure 1 Line A Example diagram of the cross-section taken from section A'; Figure 3 It shows along Figure 1 Line A A' shows a cross-section and an example diagram illustrating the shape of the front wiring lines, front wiring vias, and front contact plugs. Figure 4 It is shown Figure 2 An enlarged example of part P; Figure 5 It shows along Figure 1 Line B Example diagram of the cross-section taken by B'; Figure 6 It shows along Figure 1 Line B A cross-sectional view of B' and an example diagram showing the shape of the front wiring lines, front wiring vias and front contact plugs; Figure 7 It shows along Figure 1 Line C Example diagram of the cross-section taken by C'; Figure 8 It shows along Figure 1 line D Example diagram of the cross section taken by D'; Figure 9 It shows along Figure 1 line E Example diagram of the cross-section taken by E'; Figure 10 This is an example layout diagram illustrating a semiconductor device according to an example embodiment of the present disclosure; Figure 11 It shows along Figure 10 line F Example diagram of the cross section taken by F'; Figure 12 It shows along Figure 1 Line A A' shows the cross-section and illustrates the first growth. First and Second Example diagram of the shape of the first layer; Figure 13 It shows along Figure 1 Line A A' shows a cross-section and illustrates the damage to the first layer via ion implantation (IIP). First and Second The first layer is part of the damaged first layer. The first layer and the damaged second layer Example diagram of the shape of the first layer; Figure 14 It shows along Figure 1 Line A A' shows a cross-section and illustrates the removal of damage caused by the ion implantation (IIP) process. The first layer and the damaged second layer Example diagram of the shape of the first layer; Figure 15 It shows along Figure 1 Line A A' shows a cross-section and illustrates the removal of the first layer via an etching process. First and Second The first layer is part of the first depression. The first layer and the recessed second layer Example diagram of the shape of the first layer; Figure 16 It shows along Figure 1 Line A A' shows the cross-section and illustrates the first growth. Second layer and second Example diagram of the shape of the second layer; Figure 17 It shows along Figure 1 Line A A diagram showing the cross-section taken at point A and the section shown at point B. An example diagram showing the shape of the front contact plug formed on the second layer; and Figure 18 It shows along Figure 1 Line A A diagram showing the cross-section taken from section A and the section shown in the first section. Example diagram showing the shape of the back contact plug formed on the second layer. Detailed Implementation

[0015] Prior to the description of this disclosure, the terms or words used in this disclosure and the appended claims are not limited to their general or dictionary definitions. Terms and words should be interpreted in accordance with the principle that the inventor can appropriately define the concepts of the terms in order to best describe his invention. The exemplary embodiments described in this disclosure and the constructions shown in the accompanying drawings are merely the most desirable exemplary embodiments and do not represent all the technical spirit of this disclosure. Therefore, it will be understood that various equivalents and modifications that can replace the exemplary embodiments and constructions may exist at the time of filing this application.

[0016] The same reference numerals or symbols shown in the accompanying drawings denote components or elements that perform substantially the same or identical functions. For ease of description and understanding, different exemplary embodiments may be described using the same reference numerals or symbols. For example, although multiple drawings show elements with the same reference numerals, the multiple drawings do not necessarily imply the same exemplary embodiment, but may show embodiments that differ from each other.

[0017] In this disclosure, when an element is described as being "directly on" another element or "in contact with" another element, it can be understood that the element is connected to said other element and there are no other elements between them. For example, it will be understood that when an element is referred to as being "connected" or "bonded" to another element or "on" another element, the element may be directly connected to or bonded to said other element or directly on said other element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly connected" or "directly bonded" to another element, or referred to as being "in contact" with another element or "in contact with" another element (or using any form of the word "in contact"), there are no intermediate elements at the point of contact.

[0018] As used herein, a component described as an “electrical connection” is configured such that an electrical signal can be transmitted from one component to another (although such an electrical signal may attenuate in strength as it is transmitted and may be transmitted selectively).

[0019] As used herein, terms such as “identical,” “equal,” “plane,” “coplanar,” “parallel,” and “perpendicular” encompass similarity or near-identity, including variations that may occur, for example, due to manufacturing processes. Unless the context or other statement otherwise indicates otherwise, the term “basically” may be used herein to emphasize that meaning.

[0020] Furthermore, in this disclosure, when an element is described as "above" or "on the upper surface of another element," it can be understood that the element exists vertically above the other element. For example, an element can be understood as existing vertically (e.g., Figure 1 In the direction D1), it is above another element. The elements may be in contact with each other or directly connected, or it can be understood that another element may exist between the elements. This can be similarly applied to situations where an element is described as being "above" another element.

[0021] Additionally, in this disclosure, when an element is described as "below" or "on the lower surface of another element," it can be understood that the element exists vertically below the other element. For example, an element can be understood as existing vertically (e.g., Figure 1 In the direction D1), it is below another element. The elements may be in contact with each other or directly connected, or it can be understood that another element may exist between the elements. This can be similarly applied to situations where an element is described as being "below" another element.

[0022] Other expressions used to describe the positional relationships between elements can be interpreted similarly to those above.

[0023] In the following description, unless there is an obvious and contextual conflict, singular terms include plural terms. Terms such as “comprising” or “including” are used to indicate the presence of features, numbers, operations, actions, elements, components, or combinations thereof. It should be understood that these terms do not preclude the possibility that one or more other features, numbers, operations, actions, elements, components, or combinations thereof may be present or added.

[0024] Furthermore, it should be noted beforehand that descriptions such as upper side, upper surface, lower side, lower surface, side surface, front surface, or rear surface are based on the orientation shown in the accompanying drawings, and that these descriptions may change when the orientation of the corresponding object changes. This also applies to other spatial relative terms.

[0025] Terms including ordinal numbers such as "first" or "second" as used in this specification and claims are used to distinguish elements. Such ordinal numbers are used to differentiate identical or similar elements from one another in context. The meaning of the terms may not be limited by the use of ordinal numbers. For example, the order of use, arrangement, etc., of elements having such ordinal numbers may be interpreted without numerical limitation. For example, ordinal numbers may be interchanged with each other.

[0026] Unless otherwise specified, the physical properties described in this disclosure can be measured at normal temperature and normal pressure. Normal temperature in this disclosure can be room temperature or non-operating natural temperature in the range of 10°C to 30°C, 20°C to 28°C, or 22°C to 26°C. In an example embodiment, normal temperature can be 25°C. Normal pressure in this disclosure can be atmospheric pressure or non-operating natural pressure in the range of 700 mmHg to 800 mmHg or 720 mmHg to 780 mmHg. In an example embodiment, normal pressure can be 760 mmHg.

[0027] Throughout this specification, unless the context clearly and / or explicitly states the opposite, when an component is described as “comprising” a particular element or group of elements, it will be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component.

[0028] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. Figure 1 This is an example layout diagram illustrating a semiconductor device 10 according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, the semiconductor device 10 may include one or more of a fin field-effect transistor and a nanosheet field-effect transistor, but the inventive concept is not limited thereto. The semiconductor device 10 shown in the figures is an example, and the inventive concept is not limited thereto.

[0029] Furthermore, the semiconductor device 10 may include one or more of a tunneling field-effect transistor (FET), a three-dimensional transistor, and a vertical FET. In some embodiments, the semiconductor device 10 may include a planar transistor. In example embodiments, the semiconductor device 10 may be applied to FETs based on two-dimensional (2D) materials and their heterostructures. The semiconductor device 10 according to example embodiments may include a bipolar junction transistor, a laterally diffused transistor (e.g., a laterally diffused metal-oxide-semiconductor (LDMOS) transistor), etc.

[0030] Figure 2 It shows along Figure 1 Line A Example diagram of the cross section A'. Figure 3 It shows along Figure 1 Line A A' shows a cross-sectional view and an example diagram illustrating the shape of the front wiring line (FWL), front wiring via (FWV), and front contact plug (FCA). Figure 4 It is shown Figure 2 An example magnified view of part P. Figure 5 It shows along Figure 1 Line B Example diagram of the cross section taken by B'. Figure 6 It shows along Figure 1 Line A A' shows a cross-section and an example diagram illustrating the shape of the front wiring line FWL, the front wiring via FWV, and the front contact plug FCA'. Figure 7 It shows along Figure 1 Line C Example diagram of the cross section taken by C'. Figure 8 It shows along Figure 1 line D Example diagram of the cross section taken by D'. Figure 9 It shows along Figure 1 line E Example diagram of the cross section taken by E'.

[0031] In this disclosure, the first direction D1 can be a direction perpendicular to the front side 100FS of the substrate pattern. The front side 100FS of the substrate pattern can be the upper surface of the substrate pattern. The second direction D2 can be a direction intersecting the first direction D1. In an example embodiment, the second direction D2 can be the same as or parallel to the horizontal direction of the front side 100FS of the substrate pattern. The third direction D3 can be a direction intersecting the first direction D1 and the second direction D2. In an example embodiment, the third direction D3 can be the same as or parallel to the horizontal direction of the front side 100FS of the substrate pattern. In an example embodiment, the first direction D1 and the second direction D2 can be perpendicular to each other, the second direction D2 and the third direction D3 can be perpendicular to each other, and the third direction D3 and the first direction D1 can be perpendicular to each other.

[0032] In an example embodiment, the semiconductor device 10 may include a substrate pattern 100, channel layers CH and CH', an inner gate structure IGS, first source / drain regions 130 and 130', second source / drain regions 140 and 140', back contact plugs BCA and BCA', and front contact plugs FCA and FCA'.

[0033] In an example embodiment, the substrate pattern 100 may be disposed on the back-side interlayer insulating film BILD. The substrate pattern 100 may be disposed below the first active pattern AP1 and the second active pattern AP2. For example, the substrate pattern 100 may be disposed between the back-side interlayer insulating film BILD and the first active pattern AP1. The substrate pattern 100 may be disposed between the back-side interlayer insulating film BILD and the second active pattern AP2. The back-side interlayer insulating film BILD may be a single layer in an example embodiment, and may have multiple layers having a stacked structure in another example embodiment. The back-side interlayer insulating film BILD may include an insulating material. The back-side interlayer insulating film BILD may include one or more materials selected from the group consisting of silicon oxide, germanium silicon oxide, germanium oxide, silicon oxynitride, silicon nitride, and low dielectric constant materials.

[0034] In this disclosure, the insulating material may include one or more selected from the group consisting of silicon oxide, silicon germanium oxide, germanium oxide, silicon oxynitride, silicon nitride, high dielectric constant materials having a dielectric constant higher than that of silicon oxide, and low dielectric constant materials having a dielectric constant lower than that of silicon oxide. High dielectric constant materials may include, for example, one or more selected from the group consisting of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, but the inventive concept is not limited thereto. Low dielectric constant materials may include, for example, one or more selected from the group consisting of tetraethyl fluorinated silicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl silicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilylborate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonen silaZen (TOSZ), fluorosilicate glass (FSG), polyimide nanofoam (e.g., polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica degel, and mesoporous silica, but the inventive concept is not limited thereto.

[0035] In an example embodiment, substrate pattern 100 may include a semiconductor material. Substrate pattern 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Substrate pattern 100 may include silicon-germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, gallium arsenide, or gallium antimonide, but the material of substrate pattern 100 is not limited thereto. In another example embodiment, substrate pattern 100 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric-constant material.

[0036] In an example embodiment, the semiconductor device 10 may include a first active region AR1, a second active region AR2, and a field region FR. In an example embodiment, each of the first active region AR1 and the second active region AR2 may extend in a second direction D2 (e.g., longitudinally). The first active region AR1 and the second active region AR2 may be spaced apart from each other in a third direction D3. In an example embodiment, the field region FR may be disposed between the first active region AR1 and the second active region AR2 to separate the first active region AR1 and the second active region AR2. The field region FR may form a boundary between the first active region AR1 and the second active region AR2.

[0037] In an example embodiment, a device separation film (not shown) may be disposed around a first active region AR1 and a second active region AR2 spaced apart from each other. The region of the device separation film between the first active region AR1 and the second active region AR2 may be a field region FR. In an example embodiment, in the semiconductor device 10, the regions where the channel layer CH is formed may be active regions AR1 and AR2, and the region dividing the channel layer CH formed in the active regions AR1 and AR2 may be the field region FR. For example, active regions AR1 and AR2 may be regions where fin patterns or nanosheets applied as channel layer CH for transistors are formed, and the field region FR may be regions where fin patterns or nanosheets are not formed as channel layer CH. It is clear that those skilled in the art to which this disclosure pertains can distinguish what the field region FR represents and what the active regions AR1 and AR2 represent.

[0038] In an example embodiment, the first active region AR1 and the second active region AR2 may be regions in which at least a portion of a p-channel metal-oxide-semiconductor (PMOS) is formed. In an example embodiment, the first active region AR1 and the second active region AR2 may be regions in which at least a portion of an n-channel metal-oxide-semiconductor (NMOS) is formed. In an example embodiment, one of the first active region AR1 and the second active region AR2 may be a region in which at least a portion of a PMOS is formed, and the other of the first active region AR1 and the second active region AR2 may be a region in which at least a portion of an NMOS is formed.

[0039] In an example embodiment, the first active region AR1 may include a first active pattern AP1 disposed on the front side 100FS of the substrate pattern in one direction (e.g., a second direction D2). The second active region AR2 may include a second active pattern AP2 disposed on the front side 100FS of the substrate pattern in one direction (e.g., a second direction D2). The first active pattern AP1 and the second active pattern AP2 may be spaced apart from each other in a direction intersecting the arrangement directions of the first active pattern AP1 and the second active pattern AP2 (e.g., a third direction D3).

[0040] According to some example embodiments, each of the first active pattern AP1 and the second active pattern AP2 may have an upper surface and a lower surface opposite to each other in a first direction D1. The lower surface of each of the first active pattern AP1 and the second active pattern AP2 may face the substrate pattern 100.

[0041] In an example embodiment, the first active pattern AP1 and the second active pattern AP2 may each include channel layers CH and CH' spaced apart from each other in a first direction D1 on the front side 100FS of the substrate pattern. In the figures, the channel layer CH of the first active pattern AP1 and the channel layer CH' of the second active pattern AP2 are shown as each comprising three nanosheets. However, this is only for ease of description, and the inventive concept is not limited thereto.

[0042] In an example embodiment, the channel layer CH of the first active pattern AP1 and the channel layer CH' of the second active pattern AP2 may independently comprise one or more of silicon (Si) and germanium (Ge). In an example embodiment, the channel layer CH of the first active pattern AP1 and the channel layer CH' of the second active pattern AP2 may comprise compound semiconductors, for example, may comprise IV. Group IV compound semiconductors or III Group V compound semiconductors. In an example embodiment, IV... Group IV compound semiconductors can be binary or ternary compounds comprising at least two of group IV elements, including carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or they can be compounds obtained by doping the aforementioned compounds with group IV elements. In an example embodiment, III Group V compound semiconductors can be, for example, binary, ternary, and quaternary compounds formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimony (Sb).

[0043] In an example embodiment, the field insulating film 105 may be disposed in the field region FR. The field insulating film 105 may be disposed on the back-side interlayer insulating film BILD. In an example embodiment, the field insulating film 105 may surround at least a portion of the side surface of the substrate pattern 100. For example, the field insulating film 105 contacts the side surface of the substrate pattern 100. The field insulating film 105 may include an insulating material. In an example embodiment, the field insulating film 105 may include the same insulating material as the insulating material included in the substrate pattern 100. In this case, the boundary between the field insulating film 105 and the substrate pattern 100 may not be clearly defined, and the substrate pattern 100 and the field insulating film 105 may be considered as a single entity.

[0044] In an example embodiment, the first active pattern AP1 and the second active pattern AP2 may each include first source / drain regions 130 and 130' electrically connected to and / or contacting the front side 100FS of the substrate pattern. The first active pattern AP1 and the second active pattern AP2 may each include second source / drain regions 140 and 140' spaced apart from the first source / drain regions 130 and 130' in the second direction D2 and electrically connected to and / or contacting the front side 100FS of the substrate pattern.

[0045] In an example embodiment, the first source / drain region 130 and the second source / drain region 140 of the first active pattern AP1 may have the same conductivity type. In an example embodiment, the first source / drain region 130 and the second source / drain region 140 of the first active pattern AP1 may be N-type or P-type. In an example embodiment, the first source / drain region 130 and the second source / drain region 140 of the first active pattern AP1 may have different conductivity types. For example, one of the first source / drain regions 130 and 140 of the first active pattern AP1 may be N-type, while the other may be P-type. In an example embodiment, each of the first source / drain region 130 and the second source / drain region 140 may include an impurity, and the type of impurity may vary depending on the conductivity type. For example, the N-type source / drain region may include an N-type dopant, which is an impurity including at least one of phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi), and the P-type source / drain region may include a P-type dopant, which is an impurity including at least one of boron (B) and gallium (Ga).

[0046] In an example embodiment, the first source / drain region 130' and the second source / drain region 140' of the second active pattern AP2 may have the same conductivity type. In an example embodiment, the first source / drain region 130' and the second source / drain region 140' of the second active pattern AP2 may be N-type or P-type. In an example embodiment, the first source / drain region 130' and the second source / drain region 140' of the second active pattern AP2 may have different conductivity types. For example, one of the first source / drain regions 130' and the second source / drain region 140' of the second active pattern AP2 may be N-type, while the other may be P-type. In an example embodiment, each of the first source / drain region 130' and the second source / drain region 140' may include an impurity, and as described above, the type of impurity may vary depending on the conductivity type.

[0047] In an example embodiment, the first source / drain region 130 of the first active pattern AP1 may include first [missing information - likely referring to a specific type of electrode] disposed on each side surface of the channel layer CH perpendicular to the second direction D2. The first layer 131 and set in the first The first one on the first floor, 131 Second layer 132. In an example embodiment, the first source / drain region 130' of the second active pattern AP2 may include a first source / drain region 'disposed on each side surface of the channel layer CH' perpendicular to the second direction D2'. The first layer 131' and set in the first The first one on the first layer 131' Second layer 132'.

[0048] Reference Figures 2 to 4 ,First The lower surface of the second layer 132 is shown as being in contact with the inner spacer IA in the second direction D2. However, the first The first layer 131 can be in the direction of the back-side wiring BWL (i.e., direction). Extending D1) further to make the first The second layer 132 is separated from the inner spacer IA. This structure can be applied similarly. Figure 5 and Figure 6 The first in First layer 131' and first The second layer is 132'. For example, the first... The lowest point of the first layer 131 and 131' can be located below the lowest surface of the gate insulating film GD in the first direction D1.

[0049] In the example embodiment, the first The first layers 131 and 131' may include silicon (Si) or silicon germanium (SiGe), but the inventive concept is not limited thereto. In an example embodiment, the first... The second layers 132 and 132' may include silicon germanium (SiGe), but the inventive concept is not limited thereto.

[0050] In an example embodiment, the second source / drain region 140 of the first active pattern AP1 may include a second source / drain region disposed on each side surface of the channel layer CH perpendicular to the second direction D2. The first layer 141 and set in the second The second one on the first floor, 141 Second layer 142. In an example embodiment, the second source / drain region 140' of the second active pattern AP2 may include a second source / drain region disposed on each side surface of the channel layer CH' perpendicular to the second direction D2. The first layer 141' and set in the second The second one on the first layer 141' Second layer 142'.

[0051] Reference Figures 2 to 4 ,second The lower surface of the second layer 142 is shown as being in contact with the inner spacer IA, which is placed adjacent to it in the second direction D2. However, the second The first layer 141 can be in the direction of the back-side wiring line BWL (i.e., direction). Extending D1) further to make the second The second layer 142 is separated from the inner spacer IA. This structure can be applied similarly. Figure 5 and Figure 6 The second one in First layer 141' and second The second layer is 142'. For example, the second... The lowest points of the first layers 141 and 141' can be located below the lowest surface of the gate insulating film GD in the first direction D1. In the example embodiment, the second... The first layers 141 and 141' may include silicon (Si) or silicon germanium (SiGe), but the inventive concept is not limited thereto. In an example embodiment, the second... The second layers 142 and 142' may include silicon germanium (SiGe), but the inventive concept is not limited thereto.

[0052] In an example embodiment, the semiconductor device 10 may include gate structures GS, which are spaced apart from each other on the front side 100FS of the substrate pattern in a direction in which the first active pattern AP1 is disposed or extends longitudinally (e.g., a second direction D2), and the gate structures GS are connected to each of the first active pattern AP1 and the second active pattern AP2. The distance between adjacent gate structures GS in the second direction D2 may be the same. In an example embodiment, the gate structures GS may be disposed on the first active pattern AP1 and the second active pattern AP2, and may be intersecting or vertically stacked with the first active pattern AP1 and the second active pattern AP2 at a portion thereof. In an example embodiment, the gate structures GS may surround the channel layer CH of the first active pattern AP1. Furthermore, the gate structures GS may surround the channel layer CH' of the second active pattern AP2.

[0053] In the example embodiment, the number of gate structures GS can be greater than or equal to three. The spacing distances L1 and L2 between adjacent gate structures GS in a number of three or more gate structures can be substantially equal or the same.

[0054] In an example embodiment, the gate structure GS may include a gate electrode 120, a gate insulating film GD, a gate spacer GA, and a gate cover film GC.

[0055] In an example embodiment, the gate electrode 120 of the gate structure GS may surround the channel layer CH of the first active pattern AP1 and the channel layer CH' of the second active pattern AP2. In an example embodiment, the gate electrode 120 may be disposed across the first active region AR1 and the second active region AR2.

[0056] In an example embodiment, the gate electrode 120 may be configured to extend longitudinally in the third direction D3. The gate electrode 120 may be disposed between a first source / drain region 130 and a second source / drain region 140 adjacent to each other along the second direction D2, and between a first source / drain region 130' and a second source / drain region 140' adjacent to each other along the second direction D2. The gate electrodes 120 may be configured to be spaced apart from each other in the second direction D2.

[0057] In an example embodiment, the gate electrode 120 may be electrically connected to and / or contact a gate contact plug (not shown). At least a portion of the gate electrode 120 may be stacked in a first direction D1 with a gate contact plug in a first active region AR1, a second active region AR2, or a field region FR.

[0058] In an example embodiment, the gate electrode 120 may include a conductive material. In this disclosure, the conductive material may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxide nitride. For example, the conductive material may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), and titanium aluminum carbonitride (TiAlC). N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni) The invention may be made of at least one material selected from the group consisting of Pt, niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), and vanadium (V), but the inventive concept is not limited thereto. Conductive metal oxides and conductive metal nitrides may include the oxidized forms of the aforementioned substances, but the inventive concept is not limited thereto.

[0059] In an example embodiment, the gate electrode 120 may be disposed on two side surfaces of the first source / drain regions 130 and 130' and two side surfaces of the second source / drain regions 140 and 140'. In an example embodiment, at least a portion of the gate electrode 120 or some of the gate electrodes 120 may be normal / conventional gate electrodes used as the gate of a transistor, and another portion of the gate electrode 120 or some other gate electrodes 120 may be dummy gate electrodes.

[0060] In an example embodiment, the gate insulating film GD of the gate structure GS may surround and / or contact at least a portion of the gate electrode 120. The gate insulating film GD may include an insulating material. In an example embodiment, the gate spacer GA may surround and / or contact at least a portion of the gate insulating film GD. The gate spacer GA may include an insulating material. In an example embodiment, a high-dielectric interface layer (not shown) may be disposed between the gate insulating film GD and the gate spacer GA. The high-dielectric interface layer may include, for example, a high-dielectric-constant material. In an example embodiment, the high-dielectric-constant material included in the high-dielectric interface layer may have a higher dielectric constant than the dielectric constant of the insulating material included in the gate spacer GA and the insulating material included in the gate insulating film GD.

[0061] In an example embodiment, the gate capping film GC of the gate structure GS can be formed on the gate spacer GA and the gate electrode 120. The gate capping film GC can be disposed on the first active pattern AP1 and the second active pattern AP2. In an example embodiment, the gate capping film GC may include an insulating material.

[0062] In an example embodiment, the semiconductor device 10 may include a first front-side interlayer insulating film FILD_1, in which a gate structure GS is disposed. The first front-side interlayer insulating film FILD_1 may include an insulating material. The first front-side interlayer insulating film FILD_1 may include one or more materials selected from the group consisting of silicon oxide, germanium silicon oxide, germanium oxide, silicon oxynitride, silicon nitride, and low dielectric constant materials.

[0063] In an example embodiment, the semiconductor device 10 may include a source / drain etch stop film 150 disposed between the gate structure GS and the first front-side interlayer insulating film FILD_1, between the first front-side interlayer insulating film FILD_1 and each of the first source / drain regions 130 and 130', and between the first front-side interlayer insulating film FILD_1 and each of the second source / drain regions 140 and 140'. In an example embodiment, the source / drain etch stop film 150 may include at least one selected from the group consisting of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), and silicon carbonitride (SiOC).

[0064] In an example embodiment, the semiconductor device 10 may include an inner gate structure IGS disposed between channel layers CH or CH'. In an example embodiment, each gate structure GS may include an inner gate structure IGS disposed between channel layers CH or CH'. In an example embodiment, the inner gate structure IGS may be disposed on the front side 100FS of the substrate pattern. In an example embodiment, the inner gate structure IGS may be disposed between the front side 100FS of the substrate pattern and each of the lower surfaces of the first active pattern AP1 and the second active pattern AP2. In an example embodiment, the inner gate structure IGS may contact at least a portion of the channel layers CH and CH' in a first direction D1, and may contact at least a portion of the first source / drain regions 130 and 130' and the second source / drain regions 140 and 140', which will be described below.

[0065] In an example embodiment, the inner gate structure IGS may include a gate electrode 120, a gate insulating film GD, and an inner spacer IA. In an example embodiment, the gate insulating film GD may surround at least a portion of the gate electrode 120. As an example, the inner spacer IA may be disposed between the gate insulating film GD and each of the first source / drain regions 130 and 130', and between the gate insulating film GD and each of the second source / drain regions 140 and 140'. In an example embodiment, the inner spacer IA may be disposed between the gate insulating film GD and each of the channel layers CH and CH'. As another example, although the inner spacer IA is disposed between the gate insulating film GD and each of the first source / drain regions 130 and 130', and between the gate insulating film GD and each of the second source / drain regions 140 and 140', the inner spacer IA may not be disposed between the gate insulating film GD and each of the channel layers CH and CH'. The inner spacer IA may include an insulating material. The inner spacer IA may include an insulating material different from the insulating material of the gate insulating film GD.

[0066] In an example embodiment, the semiconductor device 10 may not include the inner spacer IA. In such a case, each of the first source / drain regions 130 and 130' and the second source / drain regions 140 and 140' may be in contact with the gate insulating film GD on a side surface perpendicular to the second direction D2.

[0067] In an example embodiment, the back contact plugs BCA and BCA' and the front contact plugs FCA and FCA' may independently comprise conductive material. In an example embodiment, the back contact plugs BCA and BCA' may be electrically connected to the back wiring line BWL. In an example embodiment, the back wiring line BWL may be one of the power lines supplying power to the semiconductor device 10. In an example embodiment, the front contact plugs FCA and FCA' may be electrically connected to the front wiring via FWV, and the front wiring via FWV may be electrically connected to the front wiring line FWL. In an example embodiment, the front wiring line FWL may be one of the signal lines transmitting electrical signals to the semiconductor device 10. For example, the front wiring line FWL may be a signal line receiving electrical signals from outside the semiconductor device 10.

[0068] In an example embodiment, the front contact plugs FCA and FCA' may be / have a single-layer structure. However, in another example embodiment, the front contact plugs FCA and FCA' may be / have an FCA including a front contact filler film. f and FCA f' and the front contact barrier membrane FCA b and FCA b' has a multi-layered structure. In an example embodiment, the front-side contact filler film FCA f and FCA f' may include one selected from the group consisting of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo). In an example embodiment, the front contact barrier membrane FCA b and FCA b' may include one selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), nickel (Ni), nickel boron (NiB), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and two-dimensional (2D) materials.

[0069] In this disclosure, the two-dimensional material can be a metallic material and / or a semiconductor material. The 2D material can include two-dimensional allotropes or two-dimensional compounds, and can include at least one of, for example, graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2), but the inventive concept is not limited thereto. For example, since the above-described 2D materials are mentioned as examples, the 2D materials that can be included in the semiconductor device 10 of this disclosure are not limited to the materials described above.

[0070] In an example embodiment, the semiconductor device 10 may include a second front-side interlayer insulating film FILD_2 disposed on a first front-side interlayer insulating film FILD_1, and a front-side wiring via (FWV) disposed within the second front-side interlayer insulating film FILD_2. In the example embodiment, the front-side wiring via (FWV) may be / have a single-layer structure. However, in another example embodiment, the front-side wiring via (FWV) may be / have a front-side via filling film (FWV). f and front through-hole blocking membrane FWV b has a multi-layered structure. In an example embodiment, it includes a front-side contact filler film FCA. f and FCA The materials mentioned above in f' can be referenced / used for inclusion in the front-side via filler membrane FWV. The material in f, including the front contact barrier membrane FCA b and FCA The materials mentioned above in b' can be referenced / used in FWV front-side via barrier membrane. The material in b.

[0071] In an example embodiment, the first etch stop film 160 may, in some cases, be disposed between the second front-side interlayer insulating film FILD_2 and the first front-side interlayer insulating film FILD_1 in the semiconductor device 10. In an example embodiment, the first etch stop film 160 may be disposed between the second front-side interlayer insulating film FILD_2 and the first front-side interlayer insulating film FILD_1, and between the second interlayer insulating film FILD_2 and the source / drain etch stop film 150. In an example embodiment, a front-side wiring via (FWV) may penetrate the first etch stop film 160 and may thereby be electrically connected to a front-side contact plug (FCA). In an example embodiment, the aforementioned material included in the source / drain etch stop film 150 may refer to / be used for materials included in and / or forming the first etch stop film 160.

[0072] In an example embodiment, the semiconductor device 10 may include a third front-side interlayer insulating film FILD_3 disposed on a second front-side interlayer insulating film FILD_2, and at least a portion of the front-side wiring line (FWL) is disposed within the third front-side interlayer insulating film FILD_3. In an example embodiment, the front-side wiring line (FWL) may be / have a single-layer structure. However, in another example embodiment, the front-side wiring line (FWL) may be / have a front-side wiring filler film (FWL). f and front wiring barrier film FWL b has a multi-layered structure. In an example embodiment, it includes a front-side contact filler film FCA. f and FCA The materials mentioned above in f' can be referenced / used for including the front-side wiring filler film FWL. The material in f, including the front contact barrier membrane FCA b and FCA The materials mentioned above in b' can be referenced / used in the front wiring barrier film FWL. The material in b.

[0073] In an example embodiment, the second etch stop film 170 may, in some cases, be disposed between the third front-side interlayer insulating film FILD_3 and the second front-side interlayer insulating film FILD_2 in the semiconductor device 10. In an example embodiment, the second etch stop film 170 may be disposed between the third front-side interlayer insulating film FILD_3 and the second front-side interlayer insulating film FILD_2. In an example embodiment, the front-side wiring line FWL may penetrate the second etch stop film 170 and may thereby be electrically connected to the front-side wiring via FWV. In an example embodiment, the aforementioned material included in the source / drain etch stop film 150 may refer to / be used for the material included in the second etch stop film 170. In an example embodiment, the second front-side interlayer insulating film FILD_2 and the third front-side interlayer insulating film FILD_3 may be a single body, and in such a case, the aforementioned second etch stop film 170 may not be present.

[0074] In an example embodiment, back-side contact plugs BCA and BCA' can be electrically connected to and / or contact the first source / drain regions 130 and 130' from the back side 100BS of the substrate pattern opposite to the front side 100FS of the substrate pattern. The back side 100BS of the substrate pattern can be the lower surface of the substrate pattern, and the front side 100FS of the substrate pattern can be the upper surface of the substrate pattern. In an example embodiment, the back-side contact plug BCA in the first active region AR1 can be electrically connected to and / or contact the first source / drain region 130 from the back side 100BS of the substrate pattern. In an example embodiment, the back-side contact plug BCA' in the second active region AR2 can be electrically connected to and / or contact the first source / drain region 130' from the back side 100BS of the substrate pattern.

[0075] In an example embodiment, front contact plugs FCA and FCA' may be electrically connected to and / or contact the second source / drain regions 140 and 140' on the front side 100FS of the substrate pattern. In an example embodiment, the front contact plug FCA in the first active region AR1 may be electrically connected to and / or contact the second source / drain region 140 on the front side 100FS of the substrate pattern. In an example embodiment, the front contact plug FCA' in the second active region AR2 may be electrically connected from the front side 100FS of the substrate pattern to and / or contact the second source / drain region 140'.

[0076] In an example embodiment, the front contact plugs FCA and FCA' can be electrically connected to and / or contact the second source / drain regions 140 and 140' by penetrating the first front interlayer insulating film FILD_1. In another example embodiment, the front contact plugs FCA and FCA' can be connected to and / or contact the second source / drain regions 140 and 140' by penetrating the first front interlayer insulating film FILD_1 and the source / drain etch stop film 150.

[0077] In the example embodiment, the back-side contact plugs BCA and BCA' in the active regions AR1 and AR2 can be connected to the first The first layers 131 and 131' are spaced apart. In an example embodiment, the back-side contact plug BCA in the first active region AR1 can be adjacent to the first active pattern AP1. The first layer 131 is spaced apart. In an example embodiment, the back-side contact plug BCA' in the second active region AR2 can be separated from the first layer of the second active pattern AP2. The first layer 131' is spaced apart. Therefore, the contact resistance R at the contact area where the back-side contact plugs BCA and BCA' contact the first source / drain regions 130 and 130' is... cnt It can be minimized.

[0078] In the example embodiment, the back-side contact plugs BCA and BCA' in the active regions AR1 and AR2 can be electrically connected to the first Second layer 132 and 132' and / or contact first The second layer 132 and 132', simultaneously with the first The first layers 131 and 131' are spaced apart. In an example embodiment, the back-side contact plug BCA in the first active region AR1 can be electrically connected to and / or contact the first The second layer 132, simultaneously with the first active pattern AP1 The first layer 131 is spaced apart. In an example embodiment, the back-side contact plug BCA' in the second active region AR2 can be electrically connected to the first... Second layer 132' and / or contact first The second layer 132', simultaneously with the first of the second active pattern AP2 The first layer is spaced 131' apart.

[0079] In the example embodiment, the first active pattern AP1 is the first First layer 131 and first Each of the second layer 132 may include impurities. In an example embodiment, the first The impurity concentration in the second layer (132) can be higher than that in the first layer. The impurity concentration of the first layer 131. In an example embodiment, the first... The impurity concentration in the second layer 132 can be greater than or equal to that in the first layer. The impurity concentration of the first layer 131 is three times that of the second active pattern AP2. In the example embodiment, the first... First layer 131' and first Each of the second layer 132' may include impurities. In an example embodiment, the first The concentration of impurities in the second layer 132' can be higher than that in the first layer. The concentration of impurities in the first layer 131'. In an example embodiment, the first... The concentration of impurities in the second layer 132' can be greater than or equal to that in the first layer. The concentration of impurities in the first layer 131' is three times that of the first layer.

[0080] In an example embodiment, the back-side contact plug BCA in the first active region AR1 may include a first The second layer 132 surrounds and / or connects with the first. The first region BCA is horizontally stacked in the second layer (132). 1 and as a region other than the first area BCA The second region BCA outside of region 1 2. Here, the semiconductor device 10 may include a first region BCA of the back-side contact plug BCA. 1. Above and First The second layer 132 contacts the back-side silicide layer BSC. In an example embodiment, the back-side silicide layer BSC in the first active region AR1 can be connected to the first... The first layer is separated by 131, and can be separated from the first layer. Second layer 132 contact.

[0081] In an example embodiment, the back contact plug BCA' of the second active region AR2 may include a first The second layer 132' surrounds and / or connects with the first. The first region BCA' is horizontally stacked in the second layer at 132'. 1. And as for the first region BCA' The second region BCA' outside of region 1 2. Here, the semiconductor device 10 may include a first region BCA' of the back-side contact plug BCA'. 1. Above and First The second layer 132' contacts the back-side silicide layer BSC'. In an example embodiment, the back-side silicide layer BSC' in the second active region AR2 can be connected to the first... The first layer is spaced apart by 131', and can be separated from the first... Second layer 132' contact.

[0082] In an example embodiment, the back-side silicide layers BSC and BSC' may include metal silicides and allow back-side contact plugs BCA and BCA' to make ohmic contact with the first source / drain regions 130 and 130'.

[0083] In the example embodiment, in the first active region AR1, and in the first region BCA of the back-side contact plug BCA. In step 1, the maximum length of the back-side contact plug BCA in the second direction D2 can be shorter than that in the first direction. The second layer 132 has a maximum length in the second direction D2. In the example embodiment, this is in the second active region AR2, and in the first region BCA' of the back-side contact plug BCA'. In section 1, the maximum length of the back-side contact plug BCA' in the second direction D2 can be shorter than that in the first direction. The second layer 132' is the maximum length in the second direction D2.

[0084] In the example embodiment, the first active pattern AP1 is the first At least a portion of the first layer 131 may be configured to be conformal on the side surface of the channel layer CH. In an example embodiment, the channel layer CH and the first The interface between the first layer 131 and the first First layer 131 and first The interfaces between the second layers 132 can be parallel or substantially parallel. In the example embodiment, the first of the second active pattern AP2 At least a portion of the first layer 131' may be configured to be conformal on the side surface of the channel layer CH'. In an example embodiment, the channel layer CH' and the first The interface between the first layer 131' and the first The first layer 131' and the first The interfaces between the second layers 132' can be parallel or substantially parallel. Thus, the first source / drain regions 130 and 130' can apply sufficient quantum stress to the channel layers CH and CH' to improve the mobility of electrons in the channel layers CH and CH'.

[0085] In the example embodiment, as the first active pattern AP1 approaches the front side 100FS of the substrate pattern, the first active pattern AP1... The length or width of the end of the first layer 131 adjacent to the front side 100FS of the substrate pattern in the second direction D2 can gradually decrease. In the example embodiment, as it approaches the front side 100FS of the substrate pattern, the first of the second active pattern AP2... The length or width of the end of the first layer 131' adjacent to the front side 100FS of the substrate pattern in the second direction D2 can gradually decrease.

[0086] In the example embodiment, the first active pattern AP1 is the first The end of the first layer 131 may have a slope or inclined surface 131lc based on or relative to the side surface of the channel layer CH, and the inclination angle θ of the inclined surface 131lc relative to the side surface of the channel layer CH may be an acute angle. In the example embodiment, the first of the second active pattern AP2 The end of the first layer 131' may have a bevel or inclined surface based on or relative to the side surface of the channel layer CH', and the inclination angle of the inclined surface relative to the side surface of the channel layer CH' may be an acute angle. This facilitates allowing the back-side contact plugs BCA and BCA' to not be engaged with the first... The first layer 131 and 131' are in contact.

[0087] In the example embodiment, the front contact plugs FCA and FCA' in the active regions AR1 and AR2 can be connected to the second The first layers 141 and 141' are spaced apart. In an example embodiment, the front contact plug FCA in the first active region AR1 can be adjacent to the second of the first active pattern AP1. The first layer 141 is spaced apart. In an example embodiment, the front contact plug FCA' in the second active region AR2 can be separated from the second active pattern AP2. The first layer 141' is spaced apart. Therefore, the contact resistance R at the contact area where the front contact plugs FCA and FCA' contact the second source / drain regions 140 and 140' is... cnt It can be minimized.

[0088] In the example embodiment, the front contact plugs FCA and FCA' in the active regions AR1 and AR2 can be electrically connected to and / or contact the second The second layer 142 and 142', simultaneously with the second The first layers 141 and 141' are spaced apart. In an example embodiment, the front contact plug FCA in the first active region AR1 can be electrically connected to and / or contact the second... The second layer 142, simultaneously with the second active pattern AP1 The first layer 141 is spaced apart. In an example embodiment, the front contact plug FCA' in the second active region AR2 can be electrically connected to and / or contact the second The second layer 142', simultaneously with the second active pattern AP2's second... The first layer is spaced 141' apart.

[0089] In the example embodiment, the second of the first active pattern AP1 First layer 141 and second Each of the second layer 142 may include impurities. In an example embodiment, the second... The concentration of impurities in the second layer 142 can be higher than that in the second layer. The concentration of impurities in the first layer 141. In an example embodiment, the second... The concentration of impurities in the second layer 142 can be greater than or equal to that in the second layer. The concentration of impurities in the first layer 141 is three times that of the second layer. In the example embodiment, the second active pattern AP2 is... First layer 141' and second Each of the second layer 142' may include impurities. In an example embodiment, the second... The concentration of impurities in the second layer 142' can be higher than that in the second layer. The concentration of impurities in the first layer 141'. In the example embodiment, the second... The concentration of impurities in the second layer 142' can be greater than or equal to that in the second layer. The concentration of impurities in the first layer 141' is three times that of the first layer.

[0090] In an example embodiment, the front contact plug FCA in the first active region AR1 may include a second The second layer 142 surrounds and / or is connected to the second The first region FCA is horizontally stacked in the second layer 142. 1 and as an exception to the first region FCA The second region of FCA outside of region 1 2. Here, the semiconductor device 10 may include a first region FCA of the front-side contact plug FCA. 1. Above and 2. The second layer 142 contacts the front silicide layer FSC. In an example embodiment, the front silicide layer FSC in the first active region AR1 can be connected to the second... The first layer is separated by 141, and can be connected to the second layer. Second layer 142 contact.

[0091] In an example embodiment, the front contact plug FCA' in the second active region AR2 may include a second The second layer 142' surrounds and / or is connected to the second The second layer 142' is horizontally stacked with the first region FCA' 1. And as for FCA's first region The second region of FCA' outside of region 1 2. Here, the semiconductor device 10 may include a first region FCA' of the front-side contact plug FCA'. 1. Above and 2. The second layer 142' contacts the front silicide layer FSC'. In the example embodiment, the front silicide layer FSC' in the second active region AR2 can be connected to the second The first layer is spaced 141' apart, and can be connected with the second layer. Second layer 142' contact.

[0092] In an example embodiment, the front silicide layers FSC and FSC' may include metal silicides and allow the front contact plugs FCA and FCA' to make ohmic contact with the second source / drain regions 140 and 140'.

[0093] In the example embodiment, in the first active region AR1, and in the first region FCA of the front contact plug FCA In section 1, the maximum length or width of the front contact plug FCA in the second direction D2 can be shorter than the second... The second layer 142 has a maximum length or width in the second direction D2. In an example embodiment, it is in the second active region AR2, and in the first region FCA' of the front contact plug FCA'. In section 1, the maximum length or width of the front contact plug FCA' in the second direction D2 can be shorter than the second... The second layer 142' has the maximum length or width in the second direction D2.

[0094] In the example embodiment, the second of the first active pattern AP1 At least a portion of the first layer 141 may be configured to be conformal on the side surface of the channel layer CH. In an example embodiment, the channel layer CH and the second The interface between the first layer 141 and the second layer First layer 141 and second The interfaces between the second layers 142 can be parallel or substantially parallel. In the example embodiment, the second active pattern AP2 is the second At least a portion of the first layer 141' may be configured to be conformal on the side surface of the channel layer CH'. In an example embodiment, the channel layer CH' and the second The interface between the first layer 141' and the second First layer 141' and second The interfaces between the second layers 142' can be parallel or substantially parallel. Thus, the second source / drain regions 140 and 140' can apply sufficient quantum stress to the channel layers CH and CH' to improve the mobility of electrons in the channel layers CH and CH'.

[0095] In the example embodiment, as the first active pattern AP1 approaches the front side 100FS of the substrate pattern, the second... The length or width of the end of the first layer 141 adjacent to the front side 100FS of the substrate pattern (e.g., the bottom end) in the second direction D2 can gradually decrease. In the example embodiment, as it approaches the front side 100FS of the substrate pattern, the first... The length or width of the end of the first layer 141' adjacent to the front side 100FS of the substrate pattern (e.g., the bottom end) in the second direction D2 can gradually decrease.

[0096] In the example embodiment, the second of the first active pattern AP1 The end of the first layer 141 may have a slope or inclined surface based on or relative to the side surface of the channel layer CH, and the inclination angle of the inclined surface relative to the side surface of the channel layer CH may be an acute angle. In the example embodiment, the second active pattern AP2... The end of the first layer 141' may have a slope or inclined surface based on or relative to the side surface of the channel layer CH', and the inclination angle of the inclined surface relative to the side surface of the channel layer CH' may be an acute angle.

[0097] In an exemplary embodiment, the semiconductor device 10 may include supports 110 and 110' on the front side 100FS of a substrate pattern. The supports 110 and 110' extend in a first direction D1 (e.g., longitudinally) and, at portions of the second source / drain regions 140 and 140' opposite to the portions to which the front contact plugs FCA and FCA' are connected, are connected to and / or contact the second source / drain regions 140 and 140' in the first direction D1. In an exemplary embodiment, the supports 110 and 110' may comprise silicon (Si) or silicon germanium (SiGe), but the inventive concept is not limited thereto.

[0098] In the example embodiment, the concentration of impurities in the support 110 in the first active region AR1 can be higher than that in the second active region AR1. The concentration of impurities in the first layer 141. In the example embodiment, the concentration of impurities in the support 110 may be greater than or equal to that in the second layer. The concentration of impurities in the first layer 141 is twice that of the second layer. In an example embodiment, the concentration of impurities in the support 110' in the second active region AR2 can be higher than that in the second layer. The concentration of impurities in the first layer 141'. In the example embodiment, the concentration of impurities in the support 110' may be greater than or equal to that in the second layer. The concentration of impurities in the first layer 141' is twice that of the first layer.

[0099] In the example embodiment, the second of the first active pattern AP1 The impurity concentration in the second layer 142 can be higher than the impurity concentration in the support 110. In the example embodiment, the second active pattern AP2... The concentration of impurities in the second layer 142' can be higher than the concentration of impurities in the support 110'.

[0100] In the example embodiment, supports 110 and 110' can be connected with the second The second layers 142 and 142' are in contact. In the example embodiment, when viewed in the first direction D1, the supports 110 and 110' may not be in contact with the second layer. The first layer consists of 141 and 141' stacked. For example, supports 110 and 110' may not be stacked with the second layer. The first layers 141 and 141' are vertically stacked. In the example embodiment, the support 110 in the first active region AR1 can be connected to the second... The second layer 142 contacts, and when viewed in the first direction D1, the second The first layer 141 and the support member 110 may not be stacked. For example, the second The first layer 141 and the support member 110 can be stacked on top of each other without being vertical. In the example embodiment, the support member 110' in the second active region AR2 can be with the second The second layer 142' contact, and when viewed in the first direction D1, the second The first layer 141' and the support member 110' may not be stacked. For example, the second The first layer 141' and the support member 110' can be stacked on top of each other without being vertical.

[0101] exist Figure 9 In the illustration, for ease of illustration, the gate insulating film GD and the inner spacer IA disposed between the gate electrode 120 and each of the channel layers CH and CH' have been omitted.

[0102] Figure 10 This is an example layout diagram illustrating a semiconductor device according to an example embodiment of the present disclosure. Figure 11 It shows along Figure 10 line F Example diagram of the cross-section taken by F'. Figure 11 In the illustration, for ease of illustration, the gate insulating film GD and the inner spacer IA disposed between the gate electrode 120 and each of the channel layers CH and CH' have been omitted.

[0103] In an example embodiment, the field region FR may include a trench region TA. In an example embodiment, the trench region TA may have a shallow trench isolation (STI) structure, but the inventive concept is not limited thereto. For example, the field region FR may be defined by the trench region TA. In an example embodiment, the trench region TA may be disposed between a first active region AR1 and a second active region AR2, which are spaced apart from each other along a third direction D3 and may extend in a second direction D2.

[0104] In an example embodiment, at least a portion of the gate structure GS may not extend continuously across the first active region AR1 and the second active region AR2 in the third direction D3, and may be separated in the field region FR. For example, the gate electrode 120 may be cut by a trench region TA in the field region FR. In such a case, the gate structure GS extending in the third direction D3 and intersecting the first active region AR1 and the gate structure GS extending in the third direction D3 and intersecting the second active region AR2 may be spaced apart from each other in the third direction D3.

[0105] In the example embodiments, known methods can be applied to the method of manufacturing the semiconductor device 10, provided they are compatible with the description of this disclosure. Hereinafter, methods for ensuring / manufacturing the above-described structural properties of the semiconductor device 10 will be primarily described. Furthermore, for convenience, the first active pattern AP1 will be described below with reference, but it will be clear to those skilled in the art that its description can be similarly applied to the second active pattern AP2. For example, the following description of the first active pattern AP1 can also be applied to the second active pattern AP2.

[0106] Figure 12 It shows along Figure 1 Line A A' shows a cross-sectional view and illustrates the first stage of the manufacturing process of semiconductor device 10. First layer 131 and second An example diagram of the shape in step 141 of the first layer. In the example embodiment, the first layer can be grown by an epitaxial growth scheme / process. First layer 131 and second First floor 141.

[0107] Figure 13 It shows along Figure 1 Line A A' shows a cross-section and illustrates the manufacturing process through damage to the first layer via ion implantation (IIP). First layer 131 and second The first layer 141 is part of the damaged first layer The first layer 131D and the damaged second An example diagram of the shape in the first layer 141D step. In the example embodiment, the damaged first layer can be easily removed by ion implantation. The first layer 131D and the damaged second First layer 141D. Damaged first layer. The first layer 131D and the damaged second The first 141D layer may be in a state where the crystallinity of the layer has been damaged due to ion implantation. This can be corrected by etching or similar methods compared to an undamaged first layer. First layer 131 and second The first layer 141 makes it easier to remove the damaged first layer. The first layer 131D and the damaged second The first layer is 141D. The element used in ion implantation can be boron (B) or phosphorus (P), but the inventive concept is not limited to these.

[0108] Figure 14 It shows along Figure 1 Line A A' shows a cross-section and illustrates the removal of damage caused by the manufacturing process via ion implantation (IIP). The first layer 131D and the damaged second An example diagram of the shape in the first layer 141D step. In an example embodiment, the damaged first layer can be removed by an etch-back scheme / process. The first layer 131D and the damaged second The first layer 141D allows for the formation of a first layer from which damage is removed. The first layer 131D region 131E and the second layer from which the damage was removed Region 141E of the first layer 141D. In this process, the support 110 can be partially etched from the top.

[0109] Figure 15 It shows along Figure 1 Line A A' shows a cross-section and illustrates the manufacturing process by removing the first [part] via an etching process. Part of the first layer 131 and the second A portion of the first layer 141 is used to form the first depression. The first layer 131R and the recessed second layer Example diagram of the shape in step 141R of the first layer. (Related to the above regarding...) Figure 13 and Figure 14 The described ion implantation process schemes / processes differ, and can be... Figure 15 The process shown uses an etching scheme / process. In this process, the support member 110 can be partially etched from the top.

[0110] Figure 16 It shows along Figure 1 Line A A' shows a cross-section and illustrates the first step of the manufacturing process. Second layer 132 and second Example diagram of the shape in step 142 of the second layer. This can be seen through... Figure 14 and Figure 15 The first structure shown in each of the diagrams grows. Second layer 132 and second The second layer 142 ensures the structure and properties of the semiconductor device 10. This allows the semiconductor device 10 to provide a contact resistance R at the contact region where the back-side contact plug BCA contacts the first source / drain region 130. cnt Minimize, and in the semiconductor device 10, the first source / drain region 130 and the second source / drain region 140 are subjected to sufficient quantum stress to improve the mobility of electrons in the channel layers CH and CH'.

[0111] Figure 17 It shows along Figure 1 Line A A' shows a cross-section and the manufacturing process is shown in the second section. Example diagram of the shape of the step of forming the front contact plug FCA on the second layer 142. Figure 18 It shows along Figure 1 Line A A' shows a cross-section and illustrates the manufacturing process in the first section. An example diagram illustrating the shape of the step of forming the back-side contact plug BCA on the second layer 132. In the example embodiment, a portion of the first front-side interlayer insulating film FILD_1 and the second layer can be etched using photolithography or similar processes. Part of the second layer 142, and a front-side contact plug (FCA) can be formed / set in the etched area. In an example embodiment, the front-side silicide layer (FSC) can be formed earlier than the front-side contact plug (FCA). In an example embodiment, in this process, and in order to first The second layer 132 forms / is set with a back-side contact plug BCA, which allows the semiconductor device 10 in a semi-finished state to be flipped. The support 110 and the first layer can be etched by photolithography or other processes. A portion of the second layer 132 and the back-side interlayer insulating film BILD (see...) Figure 7 As part of the etched area, the back-side contact plug BCA can be formed / set in the etched area. In the example embodiment, the back-side silicide layer BSC can be formed earlier than the back-side contact plug BCA.

[0112] According to an example embodiment, the semiconductor device minimizes the contact resistance at the contact area where the back-side contact plug contacts the source / drain region, and applies sufficient quantum stress to the source / drain region to improve the mobility of electrons in the channel layer.

[0113] The effects of this disclosure are not limited to those described above, and other effects will be apparent to those skilled in the art from the foregoing description and the appended claims.

[0114] Example embodiments have been described above with reference to the accompanying drawings. However, this disclosure is not limited to the above example embodiments and can be made in various forms that differ from each other. Those skilled in the art to which this disclosure pertains will understand that other embodiments can be implemented without changing the technical spirit or characteristics of this disclosure. Therefore, in all respects, the above example embodiments should be understood as illustrative rather than restrictive. For example, even though different drawings illustrate variations of the example embodiments, and different embodiments disclose different features, these drawings and embodiments are not necessarily intended to exclude each other. Rather, when the drawings and related descriptions of the embodiments are considered as a whole, features depicted in different drawings and / or described above in different embodiments can be combined with other features from other drawings / embodiments to produce additional variations of the embodiments. For example, unless the context clearly indicates otherwise, components and / or features of the different embodiments above can be combined interchangeably or additionally with components and / or features of other embodiments to form additional embodiments, and this disclosure includes additional embodiments.

Claims

1. A semiconductor device, comprising: Base pattern; Multiple channel layers are configured to be spaced apart from each other on the front side of the substrate pattern in a first direction perpendicular to the front side of the substrate pattern; An inner gate structure is disposed between the plurality of channel layers; The first source / drain region is electrically connected to the plurality of channel layers on the front side of the substrate pattern; The second source / drain region is spaced apart from the first source / drain region in a second direction that intersects the first direction, and is electrically connected to the plurality of channel layers on the front side of the substrate pattern; A back-side contact plug is electrically connected to the first source / drain region from the back side of the substrate pattern, which is opposite to the front side of the substrate pattern. as well as The front contact plug is electrically connected to the second source / drain region on the front side of the substrate pattern. The first source / drain region includes: First A first layer is disposed on the side surfaces of the plurality of channel layers, the side surfaces of the plurality of channel layers being perpendicular to the second direction; and First The second layer is set in the first layer. On the first layer, and Back side contact plug and first The first layer is separated.

2. The semiconductor device according to claim 1, wherein, First First layer and first Each of the second layers includes impurities, and First The concentration of impurities in the second layer is higher than that in the first layer. The concentration of impurities in the first layer.

3. The semiconductor device according to claim 1, wherein, The back contact plug includes: First The first area surrounded by the second layer; and The second region, in addition to the first region, and The semiconductor device further includes: a back-side silicide layer, which is attached to the first region of the back-side contact plug. Second layer of contact.

4. The semiconductor device according to claim 3, wherein, Backside silicide layer and first The first layer is separated.

5. The semiconductor device according to claim 3, wherein, In the first region of the back-side contact plug, the maximum length of the back-side contact plug in the second direction is shorter than that in the first region. The maximum length of the second layer in the second direction.

6. The semiconductor device according to claim 1, wherein, First At least a portion of the first layer is configured to be conformal on the side surfaces of the plurality of channel layers.

7. The semiconductor device according to claim 6, wherein, As it approaches the front side of the base pattern, the first The length of the end of the first layer adjacent to the front side of the substrate pattern gradually decreases in the second direction.

8. The semiconductor device according to claim 7, wherein, First The end of the first layer has an inclined surface based on the side surface of the plurality of channel layers, and The angle of inclination of the inclined surface relative to the side surfaces of the plurality of channel layers is acute.

9. The semiconductor device according to claim 1, wherein, The second source / drain region includes: second The first layer is disposed on the side surface of the plurality of channel layers; and second The second layer, set in the second On the first layer, and Front contact plug and second The first layer is separated.

10. The semiconductor device according to claim 9, wherein, The front contact plug includes: Second The first area surrounded by the second layer; and The second region, in addition to the first region, and The semiconductor device further includes: a front silicide layer, which, on a first region of the front contact plug, is connected to a second... Second layer of contact.

11. The semiconductor device according to claim 10, wherein, Front silicide layer and second The first layer is separated.

12. The semiconductor device according to claim 10, wherein, In the first region of the front contact plug, the maximum length of the front contact plug in the second direction is shorter than that in the second region. The maximum length of the second layer in the second direction.

13. The semiconductor device according to claim 9, further comprising: The support member extends in a first direction on the front side of the substrate pattern and is connected in the first direction to the second source / drain region at a portion opposite to the portion to which the front contact plug is connected.

14. The semiconductor device according to claim 13, wherein, second First layer, second layer Each of the second layer and the support includes impurities. second The concentration of impurities in the second layer is higher than that in the support. The concentration of impurities in the support component is higher than that in the second component. The concentration of impurities in the first layer.

15. The semiconductor device according to claim 13, wherein, Support and second Second layer of contact, and second The first layer and the supporting components are stacked on top of each other without being vertical.

16. The semiconductor device according to claim 9, wherein, second At least a portion of the first layer is configured to be conformal on the side surfaces of the plurality of channel layers.

17. A semiconductor device, comprising: Base pattern; The first active pattern is formed on the front side of the substrate pattern in a first active region extending in a second direction; The second active pattern is spaced apart from the first active pattern in a third direction intersecting the second direction, and is formed on the front side of the substrate pattern in the second active region extending in the second direction; Gate structures are configured to be spaced apart from each other in a second direction on the front side of a substrate pattern and to intersect each of a first active pattern and a second active pattern, each of the gate structures including an inner gate structure. Back-side contact plug; as well as Front contact plug, Each of the first active pattern and the second active pattern includes: Multiple channel layers are configured to be spaced apart from each other on the front side of the substrate pattern in a first direction that intersects with the second and third directions; The first source / drain region is connected to the plurality of channel layers on the front side of the substrate pattern; and The second source / drain region is spaced apart from the first source / drain region in a second direction and is connected to the plurality of channel layers on the front side of the substrate pattern. The inner gate structure is disposed between the plurality of channel layers. The back-side contact plug connects to the first source / drain region from the back side of the substrate pattern, which is opposite to the front side of the substrate pattern. The front contact plug is connected to the second source / drain region on the front side of the substrate pattern. Each of the first source / drain regions of the first active pattern and the first source / drain regions of the second active pattern includes: First A first layer is disposed on the side surface of each of the plurality of trench layers, the side surface of each of the plurality of trench layers being perpendicular to the second direction; and First The second layer is set in the first layer. On the first floor, The back contact plug in the first active region and the first active pattern The first layer is separated, and The back contact plug in the second active region and the first of the second active patterns The first layer is separated.

18. The semiconductor device according to claim 17, wherein, The distance between adjacent gate structures is equal to that between each other.

19. The semiconductor device of claim 17, further comprising: The trench region is disposed between the first active pattern and the second active pattern, spaced apart from each of the first active pattern and the second active pattern in a third direction, and extending in a second direction.

20. A semiconductor device, comprising: Base pattern; A first active pattern is formed on the front side of a substrate pattern in a first active region extending in a second direction; The second active pattern is spaced apart from the first active pattern in a third direction intersecting the second direction, and is formed on the front side of the substrate pattern in the second active region extending in the second direction; A gate structure is configured to be spaced apart from each other in a second direction on the front side of a substrate pattern and to intersect with each of a first active pattern and a second active pattern, the gate structure including an inner gate structure. Back-side contact plug; as well as Front contact plug, Each of the first active pattern and the second active pattern includes: Multiple channel layers are configured to be spaced apart from each other on the front side of the substrate pattern in a first direction that intersects with the second and third directions; The first source / drain region contacts the plurality of channel layers on the front side of the substrate pattern; and The second source / drain region is spaced apart from the first source / drain region in a second direction and contacts the plurality of channel layers on the front side of the substrate pattern. The inner gate structure is disposed between the plurality of channel layers. The back-side contact plug contacts the first source / drain region from the back side of the substrate pattern, which is opposite to the front side of the substrate pattern. The front contact plug contacts the second source / drain region on the front side of the substrate pattern. Each of the first source / drain regions of the first active pattern and the first source / drain regions of the second active pattern includes: First The first layer includes impurities and is disposed on the side surface of each of the plurality of channel layers, the side surface being perpendicular to the second direction; and First The second layer is set in the first layer. The first layer and including concentrations higher than the first The concentration of impurities in the first layer, The back contact plug in the first active region and the first active pattern The first layer is separated. The back contact plug in the second active region and the first of the second active patterns The first layer is separated, the first active pattern is the first At least a portion of the first layer is configured to be conformal on the side surfaces of the plurality of channel layers. As it approaches the front side of the substrate pattern, the first active pattern... The length of the end of the first layer adjacent to the front side of the substrate pattern gradually decreases in the second direction. The first active pattern The first layer has an inclined surface at its end, the inclined surface having an acute angle of inclination relative to the side surfaces of the plurality of channel layers. The first of the second active pattern At least a portion of the first layer is configured to be conformal on the side surfaces of the plurality of channel layers. As it approaches the front side of the substrate pattern, the first of the second active pattern The length of the end of the first layer adjacent to the front side of the substrate pattern gradually decreases in the second direction, and The first of the second active pattern The first layer has an inclined surface at its end, the inclined surface having an acute angle of inclination relative to the side surfaces of the plurality of channel layers.

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