Display device

Abstract

The display device includes a substrate. The first semiconductor layer is disposed over the substrate. The first gate layer is disposed over the first semiconductor layer. The second gate layer is disposed over the first gate layer. A first interlayer insulating layer is disposed over the second gate layer. The first interlayer insulating layer includes a groove pattern having a downwardly recessed shape. The second semiconductor layer is disposed over the first interlayer insulating layer. The second semiconductor layer includes an oxide semiconductor. A third gate layer is disposed over the second semiconductor layer. A first conductive layer is disposed over the third gate layer. The first conductive layer is electrically connected to the second gate layer. The second semiconductor layer is arranged in the groove pattern.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0140544, filed on October 15, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to display devices, methods of manufacturing display devices, and electronic devices, and more particularly, to display devices, methods of manufacturing display devices, and electronic devices including thin-film transistors having enhanced electrical characteristics. Background Technology

[0004] A display device can display an image in response to receiving electrical signals about the image. Display devices can be used as display units in various electronic products, including small electronic products such as mobile phones and large electronic products such as televisions.

[0005] A display device may include multiple pixels that receive electrical signals and emit light to display an image to the outside (e.g., the external environment). Each pixel may include a light-emitting device, for example, in the case of an organic light-emitting display device, the light-emitting device may be an organic light-emitting diode (OLED). Typically, in an organic light-emitting display device, thin-film transistors and organic light-emitting diodes are formed on a substrate, and the organic light-emitting diodes emit light and operate through themselves.

[0006] Electronic devices can provide users with the visual interface they need through display devices. Summary of the Invention

[0007] One or more embodiments include a display device comprising a thin-film transistor having enhanced electrical characteristics, a method of manufacturing the display device, and an electronic device. However, these are merely examples, and the scope of this disclosure is not limited thereto.

[0008] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0009] According to embodiments of the present disclosure, a display device includes a substrate. A first semiconductor layer is disposed on the substrate. A first gate layer is disposed on the first semiconductor layer. A second gate layer is disposed on the first gate layer. A first interlayer insulating layer is disposed on the second gate layer. The first interlayer insulating layer includes a groove pattern having a downwardly recessed shape. A second semiconductor layer is disposed on the first interlayer insulating layer. The second semiconductor layer includes an oxide semiconductor. A third gate layer is disposed on the second semiconductor layer. A first conductive layer is disposed on the third gate layer. The first conductive layer is electrically connected to the second gate layer. The second semiconductor layer is disposed in the groove pattern.

[0010] In one embodiment, the first interlayer insulating layer may include: a first inorganic protective layer including an opening that exposes a portion of the upper surface of the second gate layer; and a second inorganic protective layer disposed over the first inorganic protective layer and covering the inner surface of the opening and a portion of the upper surface of the second gate layer.

[0011] In this implementation, the thickness of the second inorganic protective layer may be less than the thickness of the first inorganic protective layer.

[0012] In an embodiment, the first inorganic protective layer may include: a first-1 inorganic protective layer having a first-1 thickness and directly disposed on the second gate layer; and a first-2 inorganic protective layer having a first-2 thickness greater than the first-1 thickness and directly disposed on the first-1 inorganic protective layer.

[0013] In an embodiment, the first inorganic protective layer may include: a first-1 inorganic protective layer, comprising silicon nitride (SiN). x And directly disposed on the second gate layer; and the first-second inorganic protective layer, including silicon oxide (SiO2). x ), and is directly set on the first-1 inorganic protective layer.

[0014] In an implementation, the second inorganic protective layer may include SiN. x A single layer.

[0015] In this implementation, the thickness of the second inorganic protective layer can be greater than the thickness of the first-1 layer.

[0016] In an embodiment, the second inorganic protective layer may include: a second-first inorganic protective layer having a second-first thickness and disposed directly on the first inorganic protective layer; and a second-second inorganic protective layer having a second-second thickness greater than or equal to the second-first thickness and disposed directly on the second-first inorganic protective layer.

[0017] In an implementation, the thickness of the second-second layer can be less than the thickness of the first inorganic protective layer.

[0018] In this embodiment, the second inorganic protective layer may include: a second-first inorganic protective layer, comprising SiN x And it is directly disposed on the first inorganic protective layer; and the second-second inorganic protective layer, including SiO x And it is directly set on the 2-1 inorganic protective layer.

[0019] In one embodiment, the thickness of the portion of the first interlayer insulating layer disposed between the second gate layer and the second semiconductor layer may be less than the thickness of the remaining portion of the first interlayer insulating layer.

[0020] In one implementation, the first conductive layer may be electrically connected to the second semiconductor layer.

[0021] In one embodiment, the display device may further include pixel electrodes disposed on a first conductive layer, wherein a second semiconductor layer may be electrically connected to the pixel electrodes.

[0022] According to embodiments of the present disclosure, a display device includes a substrate. A first semiconductor layer is disposed on the substrate. A first gate layer is disposed on the first semiconductor layer. A second gate layer is disposed on the first gate layer. A first interlayer insulating layer is disposed on the second gate layer. The first interlayer insulating layer includes a groove pattern having a downwardly recessed shape. A second semiconductor layer is disposed on the first interlayer insulating layer and includes an oxide semiconductor. A third gate layer is disposed on the second semiconductor layer and electrically connected to the second gate layer. A first conductive layer is disposed on the third gate layer and electrically connected to the second semiconductor layer. The second semiconductor layer is disposed in the groove pattern.

[0023] In one embodiment, the first interlayer insulating layer may include: a first inorganic protective layer including an opening that exposes a portion of the upper surface of the second gate layer; and a second inorganic protective layer disposed over the first inorganic protective layer and covering the inner surface of the opening and a portion of the upper surface of the second gate layer.

[0024] In this implementation, the thickness of the second inorganic protective layer may be less than the thickness of the first inorganic protective layer.

[0025] In an embodiment, the first inorganic protective layer may include: a first-1 inorganic protective layer having a first-1 thickness and directly disposed on the second gate layer; and a first-2 inorganic protective layer having a first-2 thickness greater than the first-1 thickness and directly disposed on the first-1 inorganic protective layer.

[0026] In an embodiment, the first inorganic protective layer may include: a first-1 inorganic protective layer, comprising silicon nitride (SiN). x And directly disposed on the second gate layer; and the first-second inorganic protective layer, including silicon oxide (SiO2). x), and is directly set on the first-1 inorganic protective layer.

[0027] In one embodiment, the thickness of the portion of the first interlayer insulating layer disposed between the second gate layer and the second semiconductor layer may be less than the thickness of the remaining portion of the first interlayer insulating layer.

[0028] According to embodiments of the present disclosure, a method for manufacturing a display device includes: forming a first semiconductor layer on a substrate; forming a first gate layer on the first semiconductor layer; forming a second gate layer on the first gate layer; forming a first interlayer insulating layer including a recessed pattern on the second gate layer; forming a second semiconductor layer including an oxide semiconductor on the recessed pattern; forming a third gate layer on the second semiconductor layer; and forming a first conductive layer on the third gate layer, wherein the recessed pattern corresponds to the shape of the second semiconductor layer.

[0029] In one embodiment, forming a first interlayer insulating layer including a recessed pattern may include: forming a first inorganic protective layer over a second gate layer; forming an opening in the first inorganic protective layer to expose a portion of the upper surface of the second gate layer; and forming a second inorganic protective layer covering the first inorganic protective layer, a portion of the upper surface of the second gate layer, and the inner surface of the opening.

[0030] In an embodiment, forming the first inorganic protective layer may include: forming a layer having a first-1 thickness and comprising silicon nitride (SiN). x The first-1 inorganic protective layer; and the formation of a first-2 thickness comprising silicon oxide (SiO2) x The first and second inorganic protective layers.

[0031] In an implementation, the thickness of the first-second layer can be greater than the thickness of the first-first layer.

[0032] In one embodiment, the first conductive layer can be electrically connected to the second gate layer via a via defined in a layer between the first conductive layer and the second gate layer, and can also be electrically connected to the second semiconductor layer via a via defined in a layer between the first conductive layer and the second semiconductor layer.

[0033] In one embodiment, the first conductive layer can be electrically connected to the second semiconductor layer via a via defined in a layer between the first conductive layer and the second semiconductor layer, and the third gate layer can be electrically connected to the second gate layer via a via defined in a layer between the third gate layer and the second gate layer.

[0034] According to one or more embodiments, an electronic device includes: a memory for storing commands; a processor for executing operations according to the commands and generating control commands; and a display panel for displaying images according to the control commands. The display panel includes: a substrate; a first semiconductor layer disposed on the substrate; a first gate layer disposed on the first semiconductor layer; a second gate layer disposed on the first gate layer; and a first interlayer insulating layer disposed on the second gate layer. The first interlayer insulating layer includes a groove pattern having a downwardly recessed shape. The second semiconductor layer is disposed on the first interlayer insulating layer and includes an oxide semiconductor. A third gate layer is disposed on the second semiconductor layer. A first conductive layer is disposed on the third gate layer and electrically connected to the second gate layer. A portion of the second semiconductor layer is disposed in the groove pattern.

[0035] In one embodiment, the first interlayer insulating layer may include: a first inorganic protective layer including an opening that exposes a portion of the upper surface of the second gate layer; and a second inorganic protective layer disposed over the first inorganic protective layer and covering the inner surface of the opening and a portion of the upper surface of the second gate layer. Attached Figure Description

[0036] The above and other aspects, features, and advantages of specific non-limiting embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic plan view of a display panel included in a display device according to an embodiment of the present disclosure; Figure 2 This is an illustrative representation of an embodiment according to the present disclosure. Figure 1 An example of the equivalent circuit diagram of the sub-pixels of the display panel; Figure 3 This is an illustrative representation of an embodiment according to the present disclosure. Figure 1 Another example of the equivalent circuit diagram of the subpixels of the display panel; Figure 4 This is an illustrative representation of an embodiment according to the present disclosure. Figure 1 Another example of the equivalent circuit diagram of the subpixels of the display panel; Figure 5 This is an illustrative representation of an embodiment according to the present disclosure. Figure 1 An example of a cross-sectional view of the sub-pixel and the surrounding area of ​​the sub-pixel; Figure 6 This is an illustrative representation of an embodiment according to the present disclosure. Figure 1 An example of a cross-sectional view of the sub-pixel and the surrounding area of ​​the sub-pixel; Figures 7 to 10 This is an illustrative representation of manufacturing according to an embodiment of the present disclosure. Figure 5 or Figure 6 A cross-sectional view of the common process of the second type of thin-film transistor; Figure 11 and Figure 12 This is an illustrative representation of manufacturing according to an embodiment of the present disclosure. Figure 5 or Figure 6 A cross-sectional view of the common process of the second type of thin-film transistor; Figures 13 to 15 This is an illustrative representation of manufacturing according to an embodiment of the present disclosure. Figure 5 or Figure 6 A cross-sectional view of the common process of the second type of thin-film transistor; Figure 16 This illustrates the measurement based on embodiments of the present disclosure. Figures 7 to 10 A graph showing the variation in the thickness of the first-1 inorganic protective layer and the variation in the threshold voltage of the first thin-film transistor; Figure 17 This is a graph showing the subthreshold slope (SS) of a first thin-film transistor based on the variation of parasitic capacitance according to an embodiment of the present disclosure; Figure 18 This is a graph showing the variation of the IV curve of the first thin-film transistor based on the SS variation according to an embodiment of the present disclosure; Figure 19 This is an illustrative representation of an embodiment according to the present disclosure. Figure 1 A floor plan showing the layout of a portion of the display area; Figures 20 to 29 This is a schematic illustration of embodiments of the present disclosure in their stacking order. Figure 19 A floor plan of the layout shown; Figure 30 This is an illustrative representation of an embodiment according to the present disclosure. Figure 1 A floor plan showing the layout of a portion of the display area; Figures 31 to 39 This is a schematic illustration of embodiments of the present disclosure in their stacking order. Figure 30 A floor plan of the layout shown; and Figure 40 This is a block diagram of an electronic device according to embodiments of the present disclosure. Detailed Implementation

[0037] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein similar reference numerals always denote similar elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, non-limiting embodiments are described below only with reference to the accompanying drawings to explain aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0038] This disclosure may include various embodiments and modifications, and specific non-limiting embodiments of this disclosure are shown in the accompanying drawings and will be described in detail herein. Reference is made to the following and accompanying drawings. Figure 1 The effects and features of this disclosure, as well as the methods for implementing them, will become apparent from the detailed description of the embodiments described below. However, this disclosure is not limited to the embodiments described below and can be implemented in various forms.

[0039] In the following description, non-limiting embodiments will be described in detail with reference to the accompanying drawings, and similar reference numerals will refer to similar elements in the following description, and redundant descriptions will be omitted for the sake of brevity.

[0040] It will be understood that although terms such as “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms, and these terms are used only to distinguish one element from another. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise.

[0041] It will be understood that when an element such as a layer, region, or plate is referred to as being "on" another element, it can be "directly on" another element, or it can be "indirectly on" another element with one or more intervening elements between them. When an element such as a layer, region, or plate is referred to as being "directly on" another element, there may be no intervening elements.

[0042] Furthermore, for ease of description, the dimensions of the components in the accompanying drawings may be exaggerated. In other words, because the dimensions and shapes of the components in the accompanying drawings can be arbitrarily shown for ease of description, the embodiments of this disclosure are not necessarily limited thereto.

[0043] It will be understood that terms such as “comprise,” “include,” and “have” used herein specify the presence of the said feature or element, but do not exclude the presence or addition of one or more other features or elements.

[0044] When a particular implementation can be carried out differently, the particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of the described sequence.

[0045] As used herein, “A and / or B” means either A, B, or A and B. Furthermore, “at least one of A and B” means either A, B, or A and B.

[0046] It will be understood that when a layer, region, or component is referred to as being "connected to" another layer, region, or component, it can be "directly connected to" another layer, region, or component, or it can be "indirectly connected to" another layer, region, or component, with one or more intermediary layers, regions, or components between them. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected to" another layer, region, or component, it can be "directly electrically connected to" another layer, region, or component, or it can be "indirectly electrically connected to" another layer, region, or component, with one or more intermediary layers, regions, or components between them.

[0047] Furthermore, in this paper, the x-axis, y-axis, and z-axis are not necessarily limited to the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0048] In the following text, a display device, a method for manufacturing a display device, and an electronic device according to the embodiments will be described in detail based on the above description.

[0049] This disclosure relates to a display device including a first interlayer insulating layer disposed between a second gate layer and a third gate layer. The first interlayer insulating layer has a recessed pattern having a downwardly recessed shape. A second semiconductor layer is disposed within the recessed pattern. The recessed pattern may have a shape corresponding to the shape of the second semiconductor layer. The downwardly recessed shape of the recessed pattern increases the distance between the conductive material of the second semiconductor layer and the third gate layer disposed within the recessed pattern. Therefore, parasitic capacitance between the second semiconductor layer and the third gate layer can be prevented or reduced to enhance the electrical characteristics of the thin-film transistor.

[0050] Figure 1 This is a schematic plan view illustrating a display panel included in a display device according to an embodiment.

[0051] like Figure 1 As shown, the display panel 10 may include a display area DA and (e.g., in a plan view) a peripheral area PA located outside the display area DA. Figure 1 In the diagram, the display area DA is shown as having a rectangular shape. However, embodiments of this disclosure are not necessarily limited to this. For example, the display area DA can (e.g., in a plan view) have any shape of various shapes such as a circle, an ellipse, a polygon, or a particular graphic shape.

[0052] The display area DA can be an area for displaying an image, and a plurality of sub-pixels PX can be arranged in the display area DA. Each of the plurality of sub-pixels PX can include a display device such as an organic light-emitting device. In an embodiment, each of the plurality of sub-pixels PX can emit, for example, red light, green light, or blue light. The sub-pixels PX can be connected to a pixel circuit (e.g., electrically connected to the pixel circuit) including thin-film transistors (TFTs), storage capacitors, etc. The pixel circuit can be connected (e.g., electrically connected to) a scan line SL configured to transmit scan signals, a data line DL intersecting the scan line SL and configured to transmit data signals, and a drive voltage line PL configured to supply drive voltage. For example, in an embodiment, the data line DL and the drive voltage line PL can extend in the y-axis direction (hereinafter referred to as the first direction), and the scan line SL can extend in the x-axis direction (hereinafter referred to as the second direction).

[0053] Subpixels PX can emit light with a brightness corresponding to the electrical signal received from the data line DL. The display area DA can display a specific image using the light emitted from the subpixels PX. For example, subpixels PX can be defined as an emitting area that emits any one of red, green, and blue light.

[0054] The peripheral region PA can be an area where no sub-pixels PX are disposed, and it can be an area where no image is displayed. Power supply lines for driving the sub-pixels PX can be located in the peripheral region PA. In addition, pads can be disposed in the peripheral region PA, and printed circuit boards or integrated circuit (IC) devices (such as driver ICs) including driving circuit units can be electrically connected to the pads in the peripheral region PA.

[0055] For reference, since the display panel 10 includes a substrate 100, the substrate 100 can be considered to include a display area DA and a peripheral area PA. The substrate 100 will be described in detail below.

[0056] Multiple transistors can be arranged in the display area DA. Regarding the multiple transistors, based on the transistor type (e.g., n-type or p-type) and / or operating conditions, the first terminal of the transistor can be a source electrode or a drain electrode, and the second terminal of the transistor can be an electrode different from the first terminal, either the source electrode or the drain electrode. For example, in an embodiment where the first terminal is the source electrode, the second terminal can be the drain electrode.

[0057] In the following description, an organic light-emitting display device will be used as an example of a display device according to an embodiment. However, the embodiments of this disclosure are not necessarily limited thereto. For example, in an embodiment, the display device may be an inorganic light-emitting display device (or an inorganic electroluminescent (EL) display device) or a display device such as a quantum dot light-emitting display device. For example, the emitting layer included in the display device may include organic or inorganic materials. In some embodiments, the display device may include an emitting layer and quantum dots located in the path of light emitted from the emitting layer.

[0058] Figure 2 It is shown schematically. Figure 1 An example of the equivalent circuit diagram of the subpixels of the display panel. Figure 2 The equivalent circuit diagram can be the basic equivalent circuit diagram, and can be obtained by applying... Figure 2 At least one of the equivalent circuit diagrams modified in various ways can be applied to the display device according to the embodiment.

[0059] For ease of description, Figure 2 The diagram illustrates a pMOS-type thin-film transistor. However, embodiments of this disclosure are not necessarily limited to this, and various modifications can be made to the pixel circuitry.

[0060] like Figure 2 As shown, each sub-pixel PX may include a pixel circuit PC connected to the scan line SL and the data line DL (e.g., electrically connected to the scan line SL and the data line DL) and a light-emitting device OLED connected to the pixel circuit PC.

[0061] For example, in one embodiment, the pixel circuit PC may include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. The second thin-film transistor T2 may be electrically connected to the scan line SL and the data line DL, and may be configured to transmit the data signal Dm input from the data line DL to the first thin-film transistor T1 according to the scan signal Sn input from the scan line SL.

[0062] For example, in one embodiment, the first thin-film transistor T1 may be a driving thin-film transistor, and the second thin-film transistor T2 may be a switching thin-film transistor.

[0063] For example, the storage capacitor Cst can be connected to the second thin-film transistor T2 and the drive voltage line PL (e.g., electrically connected to the second thin-film transistor T2 and the drive voltage line PL), and can be configured to store a voltage corresponding to the difference between the voltage received from the second thin-film transistor T2 and the first power supply voltage ELVDD provided to the drive voltage line PL.

[0064] For example, a first thin-film transistor T1 can be connected to a drive voltage line PL and a storage capacitor Cst (e.g., electrically connected to the drive voltage line PL and the storage capacitor Cst), and can be configured to control the drive current flowing from the drive voltage line PL through the light-emitting device OLED in response to the voltage value stored in the storage capacitor Cst. The light-emitting device OLED can emit light with a specific brightness according to the drive current.

[0065] The OLED can receive a second power supply voltage ELVSS (e.g., a common voltage). For example, the OLED can receive the second power supply voltage ELVSS (e.g., a common voltage) through a counter electrode (e.g., a cathode), and the OLED can emit light with a specific brightness by a drive current based on the voltage difference between the first power supply voltage ELVDD (e.g., a driving voltage) and the second power supply voltage ELVSS (e.g., a common voltage).

[0066] Figure 2 An embodiment of the pixel circuit PC is shown, comprising two thin-film transistors and a storage capacitor Cst. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, the pixel circuit PC may include two or more capacitors, and may also include three or more thin-film transistors.

[0067] Figure 3 It is shown schematically. Figure 1 An example of the equivalent circuit diagram of the subpixels of the display panel. Figure 3 The equivalent circuit diagram can be obtained by applying Figure 2 An example of an equivalent circuit diagram that has undergone various modifications.

[0068] like Figure 3 As shown, each sub-pixel PX may include connections to the data line DL and... Figure 2 The pixel circuit PC corresponding to the scan line SL and multiple scan lines GWL, GRL, GIL, EML and EMBL (e.g., electrically connected to the data line DL and multiple scan lines GWL, GRL, GIL, EML and EMBL) and the light-emitting device OLED connected to the pixel circuit PC (e.g., electrically connected to the pixel circuit PC). Figure 3The scan signals GW, GR, GI, EM and EMB can be transmitted through multiple scan lines GWL, GRL, GIL, EML and EMBL.

[0069] The first thin-film transistor T1 can receive a data signal Dm and transmit a driving current to the light-emitting device OLED based on the data signal Dm. For example, in one embodiment, the first thin-film transistor T1 may have a dual-gate structure including two gate electrodes.

[0070] For example, in an embodiment, the first thin-film transistor T1 may be an nMOS thin-film transistor, and may be a thin-film transistor including an oxide semiconductor layer.

[0071] For example, one of the gate electrodes of the first thin-film transistor T1 can be used as the upper gate electrode in a dual-gate structure, and the other of the gate electrodes of the first thin-film transistor T1 can be used as the lower gate electrode in a dual-gate structure.

[0072] For example, in one embodiment, the upper gate electrode of the first thin-film transistor T1 may be electrically connected to the second thin-film transistor T2, the storage capacitor Cst, and the third thin-film transistor T3. For example, the upper gate electrode of the first thin-film transistor T1 may be electrically connected to one of the source and drain electrodes of the second thin-film transistor T2, one of the electrodes of the storage capacitor Cst, and one of the source and drain electrodes of the third thin-film transistor T3.

[0073] For example, in one implementation, the third thin-film transistor T3 may be the first initialization thin-film transistor.

[0074] In one implementation, the second thin-film transistor T2 can receive a data signal Dm from the data line DL and transmit the data signal Dm to the first thin-film transistor T1. For example, the second thin-film transistor T2 may include a gate electrode for receiving a first scan signal GW. For example, one of the source and drain electrodes of the second thin-film transistor T2 may be electrically connected to one of the upper gate electrode of the first thin-film transistor T1, the first electrode CEs1 of the storage capacitor Cst, and the source and drain electrodes of the third thin-film transistor T3. For example, the other source and drain electrode of the second thin-film transistor T2 may be electrically connected to the data line DL.

[0075] For example, in one embodiment, the second thin-film transistor T2 may be an nMOS thin-film transistor, and may be a thin-film transistor including an oxide semiconductor layer.

[0076] In one implementation, the third thin-film transistor T3 can receive a reference voltage Vref from the reference voltage line VL1 and transmit the reference voltage Vref to the storage capacitor Cst. For example, the third thin-film transistor T3 may include a gate electrode that receives a second scan signal GR from the scan line GRL. For example, one of the source and drain electrodes of the third thin-film transistor T3 may be electrically connected to the first thin-film transistor T1, the second thin-film transistor T2, and the storage capacitor Cst. For example, the other source and drain electrode of the third thin-film transistor T3 may be electrically connected to the reference voltage line VL1 and can receive the reference voltage Vref from the reference voltage line VL1.

[0077] For example, in an embodiment, the third thin-film transistor T3 may be an nMOS thin-film transistor, and may be a thin-film transistor including an oxide semiconductor layer.

[0078] In this implementation, the storage capacitor Cst can receive a reference voltage Vref and hold the reference voltage Vref for a certain period of time. For example, the storage capacitor Cst can hold a voltage equal to the difference between the reference voltage Vref and the data signal Dm for a certain period of time. For example, the first electrode CEs1 of the storage capacitor Cst can be electrically connected to one of the upper gate electrode of the first thin-film transistor T1, one of the source / drain electrodes of the second thin-film transistor T2, and one of the source / drain electrodes of the third thin-film transistor T3. For example, the second electrode CEs2 of the storage capacitor Cst can be electrically connected to one of the source / drain electrodes of the first thin-film transistor T1, one of the source / drain electrodes of the sixth thin-film transistor T6, and the second electrode CEh2 of the holding capacitor Chold.

[0079] In this embodiment, the holding capacitor Chold can be electrically connected to the first thin-film transistor T1, the third thin-film transistor T3, the sixth thin-film transistor T6, and the power supply line PL1. The first electrode CEh1 of the holding capacitor Chold can be electrically connected to the power supply line PL1 and can receive the first power supply voltage ELVDD from the power supply line PL1. The second electrode CEh2 of the holding capacitor Chold can be electrically connected to one of the lower gate electrode of the first thin-film transistor T1, the source and drain electrodes of the first thin-film transistor T1, and the second electrode CEs2 of the storage capacitor Cst.

[0080] In one implementation, the fourth thin-film transistor T4 can receive an initialization voltage Vaint from the initialization voltage line VL2 and transmit the initialization voltage Vaint to the light-emitting device OLED. For example, the fourth thin-film transistor T4 can be a second initialization thin-film transistor.

[0081] For example, the fourth thin-film transistor T4 may include a gate electrode that receives a third scan signal GI from the scan line GIL. For example, one of the source and drain electrodes of the fourth thin-film transistor T4 may be electrically connected to the sixth thin-film transistor T6 and the light-emitting device OLED. For example, one of the source and drain electrodes of the fourth thin-film transistor T4 may be electrically connected to the other of the source and drain electrodes of the sixth thin-film transistor T6 and the light-emitting device OLED. For example, the other source and drain electrode of the fourth thin-film transistor T4 may be electrically connected to the initialization voltage line VL2 and may receive an initialization voltage Vaint from the initialization voltage line VL2.

[0082] For example, in an embodiment, the fourth thin-film transistor T4 may be an nMOS thin-film transistor, and may be a thin-film transistor including an oxide semiconductor layer.

[0083] In one implementation, the fifth thin-film transistor T5 can receive a first power supply voltage ELVDD from the power supply line PL1 and transmit the first power supply voltage ELVDD to the first thin-film transistor T1. For example, the fifth thin-film transistor T5 may include a gate electrode that receives a fourth scan signal EM from the scan line EML.

[0084] For example, in one implementation, the fifth thin-film transistor T5 may be the first emitter control thin-film transistor.

[0085] For example, one of the source and drain electrodes of the fifth thin-film transistor T5 can be electrically connected to the other of the source and drain electrodes of the first thin-film transistor T1. For example, the other of the source and drain electrodes of the fifth thin-film transistor T5 can be electrically connected to the power supply line PL1 and can receive the first power supply voltage ELVDD from the power supply line PL1.

[0086] For example, in an embodiment, the fifth thin-film transistor T5 may be a pMOS thin-film transistor, and may be a thin-film transistor including a semiconductor layer.

[0087] The sixth thin-film transistor T6 can be electrically connected to the first thin-film transistor T1, the holding capacitor Chold, the storage capacitor Cst, the fourth thin-film transistor T4, and the light-emitting device OLED.

[0088] For example, in one implementation, the sixth thin-film transistor T6 may be the second emitter control thin-film transistor.

[0089] For example, the sixth thin-film transistor T6 may include a gate electrode that receives the fifth scan signal EMB from the scan line EMBL. For example, one of the source / drain electrodes of the sixth thin-film transistor T6 may be electrically connected to one of the source / drain electrodes of the first thin-film transistor T1, the second electrode CEs2 of the storage capacitor Cst, and the second electrode CEh2 of the holding capacitor Chold. For example, the other source / drain electrode of the sixth thin-film transistor T6 may be electrically connected to one of the source / drain electrodes of the fourth thin-film transistor T4 and the light-emitting device OLED.

[0090] For example, in an implementation, the sixth thin-film transistor T6 may be a pMOS thin-film transistor, and may be a thin-film transistor including a semiconductor layer.

[0091] The OLED light-emitting device can receive a second power supply voltage ELVSS (e.g., a common voltage) through a second power supply line PL2. For example, the OLED light-emitting device can receive the second power supply voltage ELVSS (e.g., a common voltage) through a counter electrode (e.g., a cathode), and the OLED light-emitting device can emit light with a specific brightness by a drive current based on the voltage difference between a first power supply voltage ELVDD (e.g., a driving voltage) and a second power supply voltage ELVSS (e.g., a common voltage).

[0092] Figure 4 It is shown schematically. Figure 1 An example of the equivalent circuit diagram of the subpixels of the display panel. Figure 4 The equivalent circuit diagram can be obtained by applying Figure 2 This is one example of an equivalent circuit diagram that has undergone various modifications. For the sake of brevity, some parts may be omitted. Figure 4 and Figure 3 The description is redundant.

[0093] like Figure 4 As shown, the scan signal EM transmitted to the fourth thin-film transistor T4 can be the same signal as the scan signal EM transmitted to the fifth thin-film transistor T5.

[0094] and Figure 3 The fourth thin-film transistor T4 and the fifth thin-film transistor T5 have different electrical connections to different scan lines GIL and EML. Figure 4 The fourth thin-film transistor T4 and the fifth thin-film transistor T5 can be electrically connected to the same scan line EML.

[0095] Figure 4The equivalent circuit diagram may also include a seventh thin-film transistor T7 for transmitting the reference voltage Vref to the holding capacitor Chold. For example, the seventh thin-film transistor T7 may include a gate electrode that receives the sixth scan signal GC from the scan line GCL. For example, the reference voltage Vref received by the seventh thin-film transistor T7 may be the same voltage as the reference voltage Vref received by the third thin-film transistor T3. For example, the seventh thin-film transistor T7 and the third thin-film transistor T3 may be electrically connected to the same reference voltage line VL1.

[0096] and Figure 3 The equivalent circuit diagrams are different. Figure 4 The first electrode CEh1 of the holding capacitor Chold can be electrically connected to the seventh thin-film transistor T7, instead of the power line PL1.

[0097] and Figure 3 The equivalent circuit diagrams are different. The sixth thin-film transistor T6 can be an nMOS thin-film transistor, and it can be a thin-film transistor that includes an oxide semiconductor layer.

[0098] Figure 5 It is shown schematically. Figure 1 An example of a cross-sectional view of a subpixel and the area surrounding the subpixel.

[0099] As described above, substrate 100 may (e.g., in a plan view) include regions corresponding to display area DA and peripheral region PA outside display area DA. Substrate 100 may include various materials having flexible or bendable properties. For example, in embodiments, substrate 100 may include glass, metal, or polymer resin. Furthermore, substrate 100 may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0100] The substrate 100 can be modified in various ways, such as including a multilayer structure comprising two layers containing a polymer resin and a barrier layer disposed between the two layers and containing an inorganic material (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

[0101] Barrier layer 101 may be disposed on substrate 100 (e.g., directly on the upper surface of substrate 100). In embodiments, barrier layer 101 may comprise inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may be disposed between substrate 100 and lower metal layer 110. In embodiments, barrier layer 101 may have a shape corresponding to the entire surface of substrate 100, and may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). Barrier layer 101 may prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and planarize the surface.

[0102] The lower metal layer 110 may be disposed above the barrier layer 101 (e.g., directly on the upper surface of the barrier layer 101). In embodiments, the lower metal layer 110 may be disposed below the first semiconductor layer 120 and may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu). For example, in a plan view, at least a portion of the lower metal layer 110 may overlap with at least a portion of the first semiconductor layer 120. For example, in a plan view, at least a portion of the lower metal layer 110 may overlap with at least a portion of the first gate layer 130.

[0103] Buffer layer 102 may be disposed above lower metal layer 110 (e.g., directly on lower metal layer 110). In embodiments, buffer layer 102 may comprise inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may be disposed between first semiconductor layer 120 and lower metal layer 110. Buffer layer 102 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). Buffer layer 102 may prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and adjust the heat supply rate during the crystallization process for forming first semiconductor layer 120, so that first semiconductor layer 120 can crystallize uniformly.

[0104] The first semiconductor layer 120 may be disposed on top of the buffer layer 102 (e.g., directly on the upper surface of the buffer layer 102). The first semiconductor layer 120 may include polysilicon (e.g., low-temperature polysilicon) and may include an undoped channel region and source / drain regions formed through both sides of the doped channel region. In embodiments, the dopant may vary depending on the type of thin-film transistor and may be an n-type or p-type dopant.

[0105] A first gate insulating layer 103a may be disposed on the first semiconductor layer 120 (e.g., directly on the first semiconductor layer 120). The first gate insulating layer 103a may be configured to ensure insulation between the first semiconductor layer 120 and the first gate layer 130. In embodiments, the first gate insulating layer 103a may comprise an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may be disposed between the first semiconductor layer 120 and the first gate layer 130. The first gate insulating layer 103a may have a shape corresponding to the entire surface of the substrate 100 and may have a structure in which contact holes are formed at predetermined portions. The first gate insulating layer 103a may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0106] The first gate layer 130 may be disposed on the first gate insulating layer 103a (e.g., directly disposed on the upper surface of the first gate insulating layer 103a). In an embodiment, the first gate layer 130 may be disposed at a position that vertically overlaps with the first semiconductor layer 120, and may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu).

[0107] The second gate insulating layer 103b may be disposed over the first gate layer 130 (e.g., directly over the first gate layer 130). The second gate insulating layer 103b may be configured to ensure insulation between the first gate layer 130 and the second gate layer 140. In embodiments, the second gate insulating layer 103b may comprise an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may be disposed between the first gate layer 130 and the second gate layer 140. The second gate insulating layer 103b may have a shape corresponding to the entire surface of the substrate 100 and may have a structure in which contact holes are formed at predetermined portions. The second gate insulating layer 103b may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0108] The second gate layer 140 may be disposed on the second gate insulating layer 103b (e.g., directly disposed on the upper surface of the second gate insulating layer 103b). In an embodiment, the second gate layer 140 may be disposed at a position overlapping the first gate layer 130 or the second semiconductor layer 150 in a plan view, and may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu).

[0109] The first interlayer insulating layer 104a may be disposed on the second gate layer 140 and the second gate insulating layer 103b (e.g., directly disposed on the second gate layer 140 and the second gate insulating layer 103b). The first interlayer insulating layer 104a may cover the second gate layer 140. The first interlayer insulating layer 104a may include an inorganic material. For example, in an embodiment, the first interlayer insulating layer 104a may include a metal oxide or a metal nitride, and in particular, the inorganic material may include silicon oxide (SiO2) or silicon nitride (SiN). x The first interlayer insulating layer 104a may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). For example, the first interlayer insulating layer 104a may include SiO2. x / SiN y or SiN x / SiO y Its dual structure.

[0110] The second semiconductor layer 150 may be disposed on top of the first interlayer insulating layer 104a (e.g., directly on the first interlayer insulating layer 104a). In embodiments, the second semiconductor layer 150 may comprise polysilicon (e.g., low-temperature polysilicon) or may be an oxide semiconductor (e.g., IGZO or IZO) layer. The second semiconductor layer 150 may comprise a channel region undoped or doped with a relatively small amount of dopant and a source / drain region formed by doping both sides of the channel region with a relatively large amount of dopant (compared to the amount of dopant in the channel region).

[0111] For example, in embodiments where the second semiconductor layer 150 comprises polysilicon, the dopant can vary depending on the type of thin-film transistor and can be an n-type dopant or a p-type dopant. For example, in embodiments where the second semiconductor layer 150 is an oxide semiconductor layer, the second semiconductor layer 150 can typically be an n-type semiconductor layer.

[0112] The third gate insulating layer 103c may be disposed over the second semiconductor layer 150 and the first interlayer insulating layer 104a (e.g., directly over the second semiconductor layer 150 and the first interlayer insulating layer 104a). The third gate insulating layer 103c may be configured to ensure insulation between the second semiconductor layer 150 and the third gate layer 160. In embodiments, the third gate insulating layer 103c may comprise an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may be disposed between the second semiconductor layer 150 and the third gate layer 160. The third gate insulating layer 103c may have a shape corresponding to the entire surface of the substrate 100 and may have a structure in which contact holes are formed at predetermined portions. The third gate insulating layer 103c may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0113] The third gate layer 160 may be disposed on the third gate insulating layer 103c (e.g., directly on the upper surface of the third gate insulating layer 103c). In an embodiment, the third gate layer 160 may be disposed at a position that vertically overlaps with the second semiconductor layer 150, and may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu).

[0114] The second interlayer insulating layer 104b may be disposed above the third gate layer 160 and the third gate insulating layer 103c (e.g., directly disposed above the third gate layer 160 and the third gate insulating layer 103c). The second interlayer insulating layer 104b may cover the third gate layer 160 and / or the third gate insulating layer 103c. The second interlayer insulating layer 104b may include an inorganic material. For example, in an embodiment, the second interlayer insulating layer 104b may include a metal oxide or a metal nitride, and in particular, the inorganic material may include silicon oxide (SiO2) or silicon nitride (SiN). x The second interlayer insulating layer 104b may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). For example, the second interlayer insulating layer 104b may include SiO2. x / SiN y or SiN x / SiO y Its dual structure.

[0115] The first conductive layer SD1 may be disposed on top of the second interlayer insulating layer 104b (e.g., directly on the upper surface of the second interlayer insulating layer 104b). In an embodiment, the first conductive layer SD1 may serve as an electrode connected to the source / drain regions of the first semiconductor layer 120 and / or the second semiconductor layer 150 via vias included in the first gate insulating layer 103a to the second interlayer insulating layer 104b and / or vias included in the third gate insulating layer 103c and the second interlayer insulating layer 104b. Furthermore, the first conductive layer SD1 may also be electrically connected to the second gate layer 140.

[0116] In an embodiment, the first conductive layer SD1 may include one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). For example, the first conductive layer SD1 may include a Ti layer, an Al layer, and / or a Cu layer. For example, the first conductive layer SD1 may include a Ti / Al / Ti structure.

[0117] The first organic insulating layer 105 may be disposed on the first conductive layer SD1 (e.g., directly on the first conductive layer SD1). The first organic insulating layer 105 may be an organic insulating layer used as a planarization layer by covering the upper portion of the first conductive layer SD1 and having a substantially flat upper surface. In embodiments, for example, the first organic insulating layer 105 may comprise organic materials such as acrylic acid, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). The first organic insulating layer 105 may be modified in various ways, such as comprising a single layer or multiple layers.

[0118] The second conductive layer SD2 can be disposed on top of the first organic insulating layer 105 (e.g., directly disposed on the upper surface of the first organic insulating layer 105). In an embodiment, the second conductive layer SD2 can be connected to the portion of the first conductive layer SD1 connected to the second semiconductor layer 150 through vias included in the first organic insulating layer 105 (e.g., directly connected to the portion of the first conductive layer SD1 connected to the second semiconductor layer 150), and thus can be used as an electrode. In an embodiment, the second conductive layer SD2 can include one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). For example, the second conductive layer SD2 can include a Ti layer, an Al layer, and / or a Cu layer. For example, the second conductive layer SD2 can include a Ti / Al / Ti structure.

[0119] The second organic insulating layer 106 may be disposed on top of the second conductive layer SD2 and the first organic insulating layer 105 (e.g., directly on top of the second conductive layer SD2 and the first organic insulating layer 105). The second organic insulating layer 106 may be an organic insulating layer used as a planarization layer by covering the upper portion of the second conductive layer SD2 and having a substantially flat upper surface. In embodiments, for example, the second organic insulating layer 106 may comprise organic materials such as acrylic acid, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). The second organic insulating layer 106 may be modified in various ways, such as comprising a single layer or multiple layers.

[0120] The third conductive layer SD3 can be disposed on top of the second organic insulating layer 106 (e.g., directly on the upper surface of the second organic insulating layer 106). The third conductive layer SD3 can be used as a power line, etc., and can also be used as various wires. In embodiments, the third conductive layer SD3 may include one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). For example, the third conductive layer SD3 may include a Ti layer, an Al layer, and / or a Cu layer. For example, the third conductive layer SD3 may include a Ti / Al / Ti structure. In some cases, the third conductive layer SD3 may be omitted.

[0121] The third organic insulating layer 107 may be disposed on top of the third conductive layer SD3 (e.g., directly on the upper surface of the third conductive layer SD3). The third organic insulating layer 107 may be an organic insulating layer used as a planarization layer by covering the upper portion of the third conductive layer SD3 and having a substantially flat upper surface. In embodiments, for example, the third organic insulating layer 107 may comprise organic materials such as acrylic acid, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). The third organic insulating layer 107 may be modified in various ways, such as comprising a single layer or multiple layers. However, embodiments of this disclosure are not necessarily limited thereto. For example, in some embodiments, the third organic insulating layer 107 may be omitted.

[0122] The pixel electrode layer 170 may be disposed on the third organic insulating layer 107 (e.g., directly disposed on the third organic insulating layer 107). Alternatively, in embodiments where the third organic insulating layer 107 is omitted, the pixel electrode layer 170 may be disposed on the second organic insulating layer 106 (e.g., directly disposed on the second organic insulating layer 106).

[0123] In one embodiment, the pixel electrode layer 170 can be connected to the second conductive layer SD2 (e.g., directly connected to the second conductive layer SD2) through contact holes formed in the second organic insulating layer 106 and the third organic insulating layer 107. In another embodiment, the pixel electrode layer 170 may include pixel electrodes, and the pixel electrodes can be electrically connected to the second semiconductor layer 150 through the first conductive layer SD1 and the second conductive layer SD2. A display device can be disposed on the pixel electrode layer 170. For example, in one embodiment, the display device can be a light-emitting device using organic materials. For example, in one embodiment, the pixel electrode layer 170 may include a transparent conductive layer formed of a transparent conductive oxide such as ITO, In2O3, or IZO and / or a reflective layer formed of a metal such as Al or Ag. For example, the pixel electrode layer 170 may have a three-layer structure of ITO / Ag / ITO.

[0124] The pixel defining layer 108 may be located above (e.g., directly above) the third organic insulating layer 107 and may be arranged to cover the edges of the pixel electrodes implemented for each sub-pixel PX by the pixel electrode layer 170. For example, the pixel defining layer 108 may cover the edges of the pixel electrodes implemented for each sub-pixel PX. In an embodiment, the pixel defining layer 108 may include openings corresponding to the sub-pixels PX, and the openings may be formed to expose at least a central portion of the pixel electrodes implemented for each sub-pixel PX. The openings may be defined by the pixel defining layer 108 (such as the inner edges of the pixel defining layer 108).

[0125] For example, in one embodiment, the pixel defining layer 108 may include an organic material such as polyimide or hexamethyldisiloxane (HMDSO). Spacers may be disposed on the pixel defining layer 108.

[0126] In one embodiment, an intermediate layer and a counter electrode may be disposed over the aforementioned opening. The intermediate layer may comprise a low molecular weight material or a high molecular weight material, and in embodiments where the intermediate layer comprises a low molecular weight material, the intermediate layer may comprise a hole injection layer, a hole transport layer, an emitter layer, an electron transport layer, and / or an electron injection layer. In embodiments where the intermediate layer comprises a high molecular weight material, the intermediate layer may typically have a structure including a hole transport layer and an emitter layer.

[0127] The structure of the intermediate layer is not necessarily limited to the structures described above and can have various structures. For example, at least one of the layers constituting the intermediate layer can be integrally formed similarly to the opposing electrode. In an embodiment, the intermediate layer may include a layer patterned to correspond to each of a plurality of pixel electrodes.

[0128] In one embodiment, the opposing electrode may comprise a transparent conductive layer formed of a transparent conductive oxide such as ITO, In₂O₃, or IZO. The pixel electrode may serve as the anode, and the opposing electrode may serve as the cathode. However, the polarity of the electrodes may be reversed.

[0129] In one implementation, the opposing electrodes can be arranged throughout the display area DA, and can be arranged across the entire surface of the display area DA. The opposing electrodes can be integrally formed to cover multiple sub-pixels.

[0130] The first type of thin-film transistor TFT1 can be a thin-film transistor including the aforementioned first semiconductor layer 120. Based on the type of the first semiconductor layer 120, the first type of thin-film transistor TFT1 can be pMOS or nMOS. For example, in... Figure 5 In the embodiment where the first type of thin-film transistor TFT1 is a pMOS type, the first type of thin-film transistor TFT1 can be a fifth thin-film transistor T5.

[0131] The second type of thin-film transistor TFT2 and the third type of thin-film transistor TFT3 can be thin-film transistors including the aforementioned second semiconductor layer 150. Based on the type of the second semiconductor layer 150, the second type of thin-film transistor TFT2 and the third type of thin-film transistor TFT3 can be pMOS or nMOS type. For example, in... Figure 5 In the pMOS-type implementation shown, the second type thin-film transistor TFT2 and the third type thin-film transistor TFT3 can be a sixth thin-film transistor T6. For example, in an implementation where the second semiconductor layer 150 includes an oxide semiconductor, the second type thin-film transistor TFT2 and the third type thin-film transistor TFT3 can be nMOS-type, depending on the characteristics of the oxide semiconductor. For example, in... Figure 5 The second type thin-film transistor TFT2 and the third type thin-film transistor TFT3 shown are in an nMOS type embodiment. The second type thin-film transistor TFT2 can be one of the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, and the sixth thin-film transistor T6, and the third type thin-film transistor TFT3 can be one of the others.

[0132] The storage capacitor Cst may include a portion of a first gate layer 130 and a portion of a second gate layer 140. The portion of the first gate layer 130 and the portion of the second gate layer 140 may be vertically spaced apart from each other. One electrode of the storage capacitor Cst may be one of the portion of the first gate layer 130 and the portion of the second gate layer 140, and the other electrode of the storage capacitor Cst may be the other of the portion of the first gate layer 130 and the portion of the second gate layer 140.

[0133] For example, the second type thin-film transistor TFT2 can be the first thin-film transistor T1. In an embodiment where the second type thin-film transistor TFT2 is the first thin-film transistor T1, a portion of the second type thin-film transistor TFT2 in the second gate layer 140 can be used as the lower gate electrode in a dual-gate structure.

[0134] Figure 6 It is shown schematically. Figure 1 An example of a cross-sectional view of a subpixel and its surrounding region. For reference, this can be omitted for brevity. Figure 6 and Figure 5 The description is redundant.

[0135] exist Figure 5 In this configuration, the second semiconductor layer 150 and the second gate layer 140 are electrically connected to each other via the first conductive layer SD1 in the second type thin-film transistor TFT2. However, in Figure 6 In this process, the second semiconductor layer 150 can be electrically connected to the first conductive layer SD1, and the second gate layer 140 can be electrically connected to the third gate layer 160 in the second type thin film transistor TFT2.

[0136] Figures 7 to 10 It is a schematic representation of manufacturing. Figure 5 or Figure 6 A cross-sectional view of the common process of the second type of thin-film transistor. For reference, this can be omitted for brevity. Figures 7 to 10 The above description is redundant.

[0137] For ease of description, some components may be omitted. Figures 7 to 10 As shown, and from which those skilled in the art can... Figure 5 or Figure 6 Clearly inferred that there was no Figures 7 to 10 The components shown in the image, and can also be found from... Figure 5 or Figure 6 Clearly inferred that there was no Figures 7 to 10 The manufacturing process and sequence of the components are shown in the diagram.

[0138] like Figures 7 to 10As shown, a second gate layer 140 can be formed on the second gate insulating layer 103b (e.g., directly on the upper surface of the second gate insulating layer 103b). A first interlayer insulating layer 104a can be formed on the second gate layer 140 and the second gate insulating layer 103b (e.g., directly on the second gate layer 140 and the second gate insulating layer 103b). In an embodiment, the first interlayer insulating layer 104a may be an inorganic protective layer and may include a recessed groove pattern CP. The groove pattern CP may be referred to as a "recessed pattern". For example, the groove pattern CP may (e.g., in a cross-sectional view) have a recessed shape. For example, a second semiconductor layer 150 may be disposed on the groove pattern CP (e.g., directly on the groove pattern CP), and the groove pattern CP may correspond to the shape of the second semiconductor layer 150.

[0139] In this embodiment, the first interlayer insulating layer 104a may include a first inorganic protective layer 104a1. The first inorganic protective layer 104a1 may include a first-1 inorganic protective layer 104a1-1 and a first-2 inorganic protective layer 104a1-2. The first-1 inorganic protective layer 104a1-1 may be disposed on the second gate layer 140 (e.g., directly disposed on the second gate layer 140) and may cover the upper surface and side surface of the second gate layer 140. The first-2 inorganic protective layer 104a1-2 may be disposed on the first-1 inorganic protective layer 104a1-1 (e.g., directly disposed on the first-1 inorganic protective layer 104a1-1).

[0140] In an embodiment, the first inorganic protective layer 104a1 may include SiN. x The first-1 inorganic protective layer 104a1-1 and containing SiO x The first inorganic protective layer 104a1-2 is multilayered. Since the first inorganic protective layer 104a1 is multilayered, it can effectively prevent impurities from penetrating into the second semiconductor layer 150.

[0141] For example, the first-1 inorganic protective layer 104a1-1 can be disposed on the second gate layer 140 (e.g., directly disposed on the second gate layer 140). The first-1 inorganic protective layer 104a1-1 can have a first-1 thickness d1-1 (e.g., a length in the vertical direction). In an embodiment, the first-1 inorganic protective layer 104a1-1 may include SiN. x .

[0142] For example, the first-second inorganic protective layer 104a1-2 can be disposed on top of the first-first inorganic protective layer 104a1-1 (e.g., directly disposed on the first-first inorganic protective layer 104a1-1). The first-second inorganic protective layer 104a1-2 can have a first-second thickness d1-2 (e.g., a length in the vertical direction). In an embodiment, the first-second inorganic protective layer 104a1-2 may include SiO2. x .

[0143] The first-1 inorganic protective layer 104a1-1 includes SiN x In the implementation method, due to SiN x The superior layer performance allows for the effective implementation of a barrier function to prevent impurities (e.g., F) from penetrating into the second semiconductor layer 150. Therefore, because impurities do not penetrate into the second semiconductor layer 150, the characteristics of the first thin-film transistor T1, which includes the second semiconductor layer 150, can be enhanced.

[0144] The first-second inorganic protective layer 104a1-2 includes SiO x In this implementation, the possibility of the presence of additional oxygen atoms can be increased. Since additional oxygen atoms (exO) are generated in the first-second inorganic protective layer 104a1-2, the first-second inorganic protective layer 104a1-2 can perform a barrier function during high-temperature thermal processes to effectively prevent impurities (e.g., F) from penetrating into the second semiconductor layer 150. Therefore, because impurities do not penetrate into the second semiconductor layer 150, the characteristics of the first thin-film transistor T1 including the second semiconductor layer 150 can be enhanced.

[0145] Furthermore, since the first inorganic protective layer 104a1 has a bilayer structure including the first-1 inorganic protective layer 104a1-1 and the first-2 inorganic protective layer 104a1-2, the first inorganic protective layer 104a1 can perform a barrier function to prevent impurities (e.g., F) from penetrating into the second semiconductor layer 150 during high-temperature thermal processes.

[0146] The first-1 thickness d1-1 can be smaller than the first-2 thickness d1-2. For example, in an embodiment, the first-1 thickness d1-1 can be in the range of about 300 angstroms to about 1000 angstroms. For example, the first-1 thickness d1-1 can be about 500 angstroms.

[0147] The first-second thickness d1-2 can be greater than the first-first thickness d1-1. For example, in an embodiment, the first-second thickness d1-2 can be in the range of about 2000 angstroms to about 4000 angstroms. For example, the first-second thickness d1-2 can be about 3000 angstroms.

[0148] like Figure 8As shown, an opening OP1 exposing at least a portion of the upper surface of the second gate layer 140 can be formed in the first inorganic protective layer 104a1. For example, a first-1 opening OP1-1 exposing at least a portion of the upper surface of the second gate layer 140 can be formed in the first-1 inorganic protective layer 104a1-1, and a first-2 opening OP1-2 having an inner surface continuous and aligned with the inner surface of the first-1 opening OP1-1 can be formed in the first-2 inorganic protective layer 104a1-2. In an embodiment, the first-1 opening OP1-1 and the first-2 opening OP1-2 can be formed in the same process. The inner surface of each of the first-1 opening OP1-1 and the first-2 opening OP1-2 can include a sloped surface, and the inner surface of each of the first-1 opening OP1-1 and the first-2 opening OP1-2 can form a continuous aligned surface.

[0149] like Figure 9 As shown in the illustration, in this embodiment, the first interlayer insulating layer 104a may further include a second inorganic protective layer 104a2. The second inorganic protective layer 104a2 may be formed on the first inorganic protective layer 104a1 (e.g., directly disposed on the first inorganic protective layer 104a1).

[0150] The second inorganic protective layer 104a2 may cover the portion of the upper surface of the second gate layer 140 exposed upwards by the first-1 opening OP1-1. The second inorganic protective layer 104a2 may cover the inner surfaces of the first-1 opening OP1-1 and the first-2 opening OP1-2. The second inorganic protective layer 104a2 may cover the upper surface of the first inorganic protective layer 104a1. The second inorganic protective layer 104a2 may be disposed above the first-2 inorganic protective layer 104a1-2 (e.g., directly disposed above the first-2 inorganic protective layer 104a1-2), and may cover the upper surface of the first-2 inorganic protective layer 104a1-2.

[0151] In an embodiment, the second inorganic protective layer 104a2 may include a second-first inorganic protective layer 104a2-1 and a second-second inorganic protective layer 104a2-2. The second-first inorganic protective layer 104a2-1 may be disposed on top of the first-second inorganic protective layer 104a1-2 (e.g., directly disposed on the first-second inorganic protective layer 104a1-2), and the second-second inorganic protective layer 104a2-2 may be disposed on top of the second-first inorganic protective layer 104a2-1 (e.g., directly disposed on the second-first inorganic protective layer 104a2-1).

[0152] In the implementation, the second inorganic protective layer 104a2 may include SiN. x The second-first inorganic protective layer 104a2-1 and containing SiOx The second inorganic protective layer 104a2-2 is multilayered. Since the second inorganic protective layer 104a2 is multilayered, it can effectively prevent impurities from penetrating into the second semiconductor layer 150.

[0153] For example, the second-1 inorganic protective layer 104a2-1 may have a second-1 thickness d2-1. The second-1 inorganic protective layer 104a2-1 may include SiN. x For example, the second-second inorganic protective layer 104a2-2 may have a second-second thickness d2-2. The second-second inorganic protective layer 104a2-2 may include SiO2. x .

[0154] The second-first thickness d2-1 can be less than or equal to the second-second thickness d2-2. For example, in an embodiment, the second-first thickness d2-1 can be in the range of about 200 angstroms to about 600 angstroms. For example, in an embodiment, the second-second thickness d2-2 can be in the range of about 500 angstroms to about 700 angstroms. For example, in an embodiment where the second-first thickness d2-1 is 500 angstroms, the second-second thickness d2-2 can be 500 angstroms. For example, in an embodiment where the second-first thickness d2-1 can be 250 angstroms, the second-second thickness d2-2 can be 500 angstroms. The thickness of the portion of the first interlayer insulating layer 104a between the second gate layer 140 and the second semiconductor layer 150 (e.g., directly between the second gate layer 140 and the second semiconductor layer 150) (such as the total thickness of the second inorganic protective layer 104a2 (e.g., the sum of the second-1 thickness d2-1 and the second-2 thickness d2-2)) can be less than the total thickness of the remaining portion of the first interlayer insulating layer 104a that is not disposed between the second gate layer 140 and the second semiconductor layer 150 (e.g., not directly disposed between the second gate layer 140 and the second semiconductor layer 150).

[0155] like Figure 10 As shown, a second semiconductor layer 150 can be formed on the second inorganic protective layer 104a2 (e.g., directly on the second inorganic protective layer 104a2). The second semiconductor layer 150 can be disposed within a groove pattern CP formed by the first inorganic protective layer 104a1 and the second inorganic protective layer 104a2. The groove pattern CP can have a recessed shape corresponding to the shape of the second semiconductor layer 150. The groove pattern CP can be formed in the respective layers 104a1-1, 104a1-2, 104a2-1, and 104a2-2 of the first and second inorganic protective layers 104a1 and 104a2, providing a structure for accommodating the second semiconductor layer 150. In an embodiment, the second semiconductor layer 150 may include an oxide semiconductor, which can be used as a channel region of a second type of thin-film transistor (TFT) 2.

[0156] The thickness of the second inorganic protective layer 104a2 (e.g., the sum of the second-1 thickness d2-1 and the second-2 thickness d2-2) can be less than the thickness of the first inorganic protective layer 104a1 (e.g., the sum of the first-1 thickness d1-1 and the first-2 thickness d1-2). The respective thicknesses of the first inorganic protective layer 104a1 and the second inorganic protective layer 104a2 can help optimize the arrangement of the second semiconductor layer 150 by adjusting the depth of the groove pattern CP.

[0157] This structure enhances the electrical characteristics of the second-type thin-film transistor (TFT2) by stably arranging the second semiconductor layer 150 within the recessed pattern CP. In an embodiment, the second semiconductor layer 150 can be arranged away from layers containing conductive material (such as the third gate layer 160 disposed around the second-type TFT2) via the recessed pattern CP. As the distance between the second semiconductor layer 150 and the conductive material (such as the conductive material included in the third gate layer 160 disposed around the second-type TFT2) increases, parasitic capacitance between the two components can be prevented or reduced. By preventing or reducing parasitic capacitance, the electrical characteristics of the second-type TFT2 can be enhanced.

[0158] Figure 11 and Figure 12 It is a schematic representation of manufacturing. Figure 5 or Figure 6 A cross-sectional view of a common process for a portion of the second type of thin-film transistor. For reference, this can be omitted for brevity. Figure 11 and Figure 12 The above description is redundant.

[0159] For ease of description, some components may be omitted. Figure 11 and Figure 12 As shown, and from which those skilled in the art can... Figure 5 or Figure 6 Clearly inferred that there was no Figure 11 and Figure 12 The components shown in the image, and can also be found from... Figure 5 or Figure 6 Clearly inferred that there was no Figure 11 and Figure 12 The manufacturing process and sequence of the components are shown in the diagram.

[0160] like Figure 11 As shown, in the embodiment, the second inorganic protective layer 104a2 can be formed as a single layer. Figure 9 The second inorganic protective layer 104a2 in the illustrated embodiment is different. Figure 11 The second inorganic protective layer 104a2 may consist of only a single layer.

[0161] For example, the second inorganic protective layer 104a2 may include SiN x or SiO x For example, the second inorganic protective layer 104a2 may include SiN. x A single layer, or it may include SiO x A single layer. Formed Figure 11 The process of forming the second inorganic protective layer 104a2 can be compared with that of forming Figure 9 The process for the second inorganic protective layer 104a2 is simple and inexpensive.

[0162] For example, the second thickness d2 of the second inorganic protective layer 104a2 can be greater than the first-1 thickness d1-1 of the first-1 inorganic protective layer 104a1-1. Alternatively, the second thickness d2 of the second inorganic protective layer 104a2 can be less than the first-2 thickness d1-2 of the first-2 inorganic protective layer 104a1-2. Therefore, the second thickness d2 can be greater than the first-1 thickness d1-1 and less than the first-2 thickness d1-2.

[0163] like Figure 12 As shown, a second semiconductor layer 150 can be formed on the second inorganic protective layer 104a2 (e.g., directly on the second inorganic protective layer 104a2). The second semiconductor layer 150 can be disposed in a groove pattern CP formed in the first inorganic protective layer 104a1 and the second inorganic protective layer 104a2. In an embodiment, the groove pattern CP can have a recessed shape corresponding to the shape of the second semiconductor layer 150. The groove pattern CP can be formed in the first inorganic protective layer 104a1 and the second inorganic protective layer 104a2, providing a structure for accommodating the second semiconductor layer 150. The second semiconductor layer 150 can include an oxide semiconductor, which can be used as a channel region of a second type of thin-film transistor (TFT) 2.

[0164] The second thickness d2 of the second inorganic protective layer 104a2 can be less than the thickness of the first inorganic protective layer 104a1 (e.g., the sum of the first-1 thickness d1-1 and the first-2 thickness d1-2). The respective thicknesses of the first inorganic protective layer 104a1 and the second inorganic protective layer 104a2 can help optimize the arrangement of the second semiconductor layer 150 by adjusting the depth of the groove pattern CP.

[0165] This structure enhances the electrical characteristics of the second-type thin-film transistor (TFT2) by stably arranging the second semiconductor layer 150 within the recessed pattern CP. In this embodiment, due to the recessed pattern CP, the second semiconductor layer 150 can be arranged away from layers comprising conductive material (such as the third gate layer 160 disposed around the second-type TFT2). As the distance between the second semiconductor layer 150 and the conductive material (such as the conductive material included in the third gate layer 160 disposed around the second-type TFT2) increases, parasitic capacitance between the two components can be prevented or reduced. By preventing or reducing parasitic capacitance, the electrical characteristics of the second-type TFT2 can be enhanced.

[0166] Figures 13 to 15 It is a schematic representation of manufacturing. Figure 5 or Figure 6 A cross-sectional view of the common process of the second type of thin-film transistor. For reference, this can be omitted for brevity. Figures 13 to 15 The above description is redundant.

[0167] For ease of description, some components may be omitted. Figures 13 to 15 As shown, and from which those skilled in the art can... Figure 5 or Figure 6 Clearly inferred that there was no Figures 13 to 15 The components shown in the image, and also available from... Figure 5 or Figure 6 Clearly inferred that there was no Figures 13 to 15 The manufacturing process and sequence of the components are shown in the diagram.

[0168] like Figure 13 As shown, in this embodiment, the second type of thin-film transistor TFT2 may not include the second inorganic protective layer 104a2. In this embodiment, the first inorganic protective layer 104a1 may include a first-1 inorganic protective layer 104a1-1 and a first-2 inorganic protective layer 104a1-2. In this embodiment, the first-1 inorganic protective layer 104a1-1 may include SiN as described above. x Furthermore, the first-second inorganic protective layer 104a1-2 may include SiO2 as described above. x .

[0169] like Figure 14 As shown, a groove CP can be formed in the first-second inorganic protective layer 104a1-2. The groove CP formed in the first-second inorganic protective layer 104a1-2 can provide a structure for accommodating the second semiconductor layer 150. The groove CP formed in the first-second inorganic protective layer 104a1-2 can have a recessed shape corresponding to the shape of the second semiconductor layer 150.

[0170] like Figure 15 As shown, a second semiconductor layer 150 can be formed on the first-second inorganic protective layer 104a1-2 (e.g., directly on the first-second inorganic protective layer 104a1-2). The second semiconductor layer 150 can be disposed in a groove CP formed in the first-second inorganic protective layer 104a1-2. The groove CP formed in the first-second inorganic protective layer 104a1-2 can have a recessed shape corresponding to the shape of the second semiconductor layer 150.

[0171] The thickness d1 of the first-1 inorganic protective layer 104a1-1 can be less than the thickness d2 of the first-2 inorganic protective layer 104a1-2. The respective thicknesses of the first-1 inorganic protective layer 104a1-1 and the first-2 inorganic protective layer 104a1-2 can be adjusted by modifying the depth of the recess CP formed in the first-2 inorganic protective layer 104a1-2 to help optimize the arrangement of the second semiconductor layer 150. The thickness of the portion of the first interlayer insulating layer 104a between the second gate layer 140 and the second semiconductor layer 150 (e.g., directly between the second gate layer 140 and the second semiconductor layer 150) can be less than the thickness of the remaining portion of the first interlayer insulating layer 104a not disposed between the second gate layer 140 and the second semiconductor layer 150 (e.g., not directly disposed between the second gate layer 140 and the second semiconductor layer 150).

[0172] This structure enhances the electrical characteristics of the second-type thin-film transistor TFT2 by stably arranging the second semiconductor layer 150 within the recess CP. In this embodiment, due to the recess CP, the second semiconductor layer 150 can be arranged away from layers comprising conductive material (such as the third gate layer 160 disposed around the second-type thin-film transistor TFT2). As the distance between the second semiconductor layer 150 and the conductive material (such as the conductive material included in the third gate layer 160 disposed around the second-type thin-film transistor TFT2) increases, parasitic capacitance between the two components can be prevented or reduced. By preventing or reducing parasitic capacitance, the electrical characteristics of the second-type thin-film transistor TFT2 can be enhanced.

[0173] Figure 16 It shows the measurement based on Figures 7 to 10 The graph shows the variation in the thickness of the first-1 inorganic protective layer and the variation in the threshold voltage of the first thin-film transistor. Figure 17 This is a graph showing the subthreshold slope (SS) of the first thin-film transistor based on the aforementioned parasitic capacitance variation, and Figure 18 This is a graph showing the change in the IV curve of the first thin-film transistor based on the change in SS.

[0174] refer to Figure 16The threshold voltage of the first thin-film transistor T1 should satisfy a range of approximately -3.43V to approximately 2.37V (hereinafter referred to as the optimal range). The first-1 inorganic protective layer 104a1-1 may include SiN x The thickness of the first inorganic protective layer 104a1-1 is 300 angstroms, and the threshold voltage of the first thin-film transistor T1 is 0.11V, which is within the optimal range. Even when the thickness of the first inorganic protective layer 104a1-1 is increased to 1000 angstroms, the threshold voltage of the first thin-film transistor T1 is still within the optimal range.

[0175] The thickness of the first-1 inorganic protective layer 104a1-1 can be 300 angstroms or greater. When the thickness of the first-1 inorganic protective layer 104a1-1 is 300 angstroms or greater, the threshold voltage of the first thin-film transistor T1 can be within the optimal range, and the electrical characteristics of the first thin-film transistor T1 can also be enhanced.

[0176] In this embodiment, the thickness of the first-1 inorganic protective layer 104a1-1 can be in the range of about 300 angstroms to about 1000 angstroms. When the thickness of the first-1 inorganic protective layer 104a1-1 is in the range of about 300 angstroms to about 1000 angstroms, the threshold voltage of the first thin-film transistor T1 can be within the optimal range, and the electrical characteristics of the first thin-film transistor T1 can also be enhanced.

[0177] refer to Figure 17 The x-axis of the figure represents the magnitude of the parasitic capacitance that decreases as the thickness of the first-second inorganic protective layer 104a1-2 decreases. The parasitic capacitance can be the capacitance generated by the line layer (e.g., the third gate layer 160) comprising conductive material arranged between the second-type thin-film transistors TFTs 2 and the second semiconductor layer 150 of the second-type thin-film transistors TFTs 2.

[0178] like Figure 17 As shown, the SS of the first thin-film transistor T1 also decreases as the parasitic capacitance decreases. Therefore, it can be interpreted that the parasitic capacitance decreases as the thickness of the first-second inorganic protective layer 104a1-2 decreases, and the characteristics of the first thin-film transistor T1 are enhanced by the reduced parasitic capacitance.

[0179] refer to Figure 18 ,along with Figure 17 As the SS increases, the IV curve of the first thin-film transistor T1 can move along the arrow. As the IV curve moves upward, the operating characteristics of the first thin-film transistor T1 based on the threshold voltage can be enhanced.

[0180] Figure 19 It is shown schematically. Figure 1A floor plan of a portion of the display area. For simplicity, redundant descriptions of components may be omitted. For reference, it can be based on... Figure 4 Understanding the equivalent circuit diagram Figures 19 to 29 The layout.

[0181] like Figure 19 As shown, components can be arranged symmetrically with respect to the virtual center line FX. Components arranged on one side of the virtual center line FX and components arranged on the other side of the virtual center line FX can be symmetrical with respect to the virtual center line FX.

[0182] The first pixel region PX1 to the third pixel region PX3 can be pixel regions defined by the pixel defining layer 108, and can be regions that emit light corresponding to each pixel region toward the outside of the display device (e.g., the external environment). For example, the first pixel region PX1 and the third pixel region PX3 can be arranged to overlap with the virtual center line FX, and the second pixel region PX2 can be multiple pixel regions, and can be arranged not to overlap with the virtual center line FX and to be laterally symmetrical with respect to the virtual center line FX.

[0183] For example, in one embodiment, the first pixel region PX1 may be a region emitting red visible light within the visible light range, the second pixel region PX2 may be a region emitting green visible light within the visible light range, and the third pixel region PX3 may be a region emitting blue visible light within the visible light range. However, the embodiments of this disclosure are not necessarily limited to these.

[0184] A first thin-film transistor T1 may be disposed around a first pixel region PX1. The first thin-film transistor T1 may overlap with a storage capacitor Cst in a planar view. A second thin-film transistor T2 may be disposed above and / or below the first thin-film transistor T1 and / or the storage capacitor Cst in a planar view.

[0185] In the plan view, the holding capacitor Chold can be arranged between the first thin-film transistor T1 and the second thin-film transistor T2. In the plan view, the holding capacitor Chold may not overlap with the second thin-film transistor T2.

[0186] The storage capacitor Cst can be arranged in the planar diagram between the first thin-film transistor T1, the fourth thin-film transistor T4, the fifth thin-film transistor T5, and the sixth thin-film transistor T6.

[0187] Power line PL1 can extend along the virtual center line FX or along the y-axis. Power line PL1 can overlap with the first pixel region PX1 in the planar view. Power line PL1 can overlap with the third pixel region PX3 in the planar view.

[0188] The data line DL can be arranged around the virtual center line FX and can extend in the y-axis direction. The data line DL can overlap with the holding capacitor Chold in the planar view. The data line DL can overlap with the second thin-film transistor T2 in the planar view. The data line DL can overlap with the fifth thin-film transistor T5 in the planar view.

[0189] The reference voltage line VL1 can extend in the y-axis direction and can overlap with the second pixel region PX2 in the planar view. The initialization voltage line VL2 can overlap with the storage capacitor Cst and the first thin-film transistor T1 in the planar view. The initialization voltage line VL2 can overlap with the holding capacitor Chold in the planar view.

[0190] The first pixel circuit region PP1 and the second pixel circuit region PP2 can be defined around the first thin-film transistor T1. A virtual center line FX can be arranged between the first pixel circuit region PP1 and the second pixel circuit region PP2. In the following description of the plan view showing the layout, the focus will be on the components arranged in the first pixel circuit region PP1, and for ease of description, descriptions of components arranged in the second pixel circuit region PP2 and other regions may be omitted. For example, the components arranged in the second pixel circuit region PP2 can be arranged symmetrically with respect to the virtual center line FX relative to the components arranged in the first pixel circuit region PP1.

[0191] Figures 20 to 29 It is shown schematically in its stacking order. Figure 19 The layout shown is a floor plan.

[0192] like Figure 20 As shown, the lower metal layer 110 can be disposed on the substrate 100 (see Figure 100). Figure 5 or Figure 6 Above. For example, the lower metal layer 110 may be disposed between the upper surface of the substrate 100 and the first semiconductor layer 120 of the first type thin film transistor TFT1.

[0193] In an embodiment, the lower metal layer 110 may include a first portion 1101 to a third portion 1103. The first portion 1101 of the lower metal layer 110 may extend in the y-axis direction and overlap with the virtual center line FX in a plan view. The second portion 1102 of the lower metal layer 110 may extend substantially in the x-axis direction and may connect to the third portion 1103 of the lower metal layer 110. A portion of the third portion 1103 of the lower metal layer 110 may extend in a diagonal direction between the x-axis and y-axis directions and directly connect to the first portion 1101 and the second portion 1102. An opening region BIP may be formed in the third portion 1103 of the lower metal layer 110. The opening region BIP may be defined by the boundary region of the third portion 1103 of the lower metal layer 110. For example, in an embodiment, the opening region BIP of the third portion 1103 of the lower metal layer 110 may have a polygonal shape in a plan view. However, the embodiments of this disclosure are not necessarily limited to this.

[0194] like Figure 21 As shown, the first semiconductor layer 120 may be disposed above the lower metal layer 110. For example, the first semiconductor layer 120 may be disposed (e.g., in the vertical direction) between the lower metal layer 110 and the first gate layer 130.

[0195] In an embodiment, the first semiconductor layer 120 may include a first portion 1201 and a second portion 1202. The first portion 1201 of the first semiconductor layer 120 may extend substantially in the x-axis direction. For example, the first portion 1201 of the first semiconductor layer 120 may include a channel region A5 of a fifth thin-film transistor T5 and source-drain regions SD5a and SD5b. The channel region A5 of the fifth thin-film transistor T5 may be disposed between the source-drain regions SD5a and SD5b of the fifth thin-film transistor T5. The first source-drain region SD5a of the source-drain regions SD5a and SD5b may be disposed around the central region of the first portion 1201 of the first semiconductor layer 120, and the second source-drain region SD5b of the source-drain regions SD5a and SD5b may be disposed at or around one end (e.g., a side end) of the first portion 1201.

[0196] The second portion 1202 of the first semiconductor layer 120 may extend substantially in the y-axis direction, and the second portion 1202 of the first semiconductor layer 120 may overlap with the virtual center line FX in a plan view. The second portion 1202 of the first semiconductor layer 120 may be connected to the central region of the first portion 1201 of the first semiconductor layer 120 (e.g., directly connected to the central region of the first portion 1201 of the first semiconductor layer 120). The second portion 1202 of the first semiconductor layer 120 may overlap with the first portion 1101 of the lower metal layer 110 in a plan view.

[0197] like Figure 22 As shown, the first gate layer 130 may be disposed above the first semiconductor layer 120. For example, the first gate layer 130 may be disposed (e.g., in the vertical direction) between the first semiconductor layer 120 and the second gate layer 140. In an embodiment, the first gate layer 130 may include a first electrode CEs1 among the electrodes of the storage capacitor Cst. The first gate layer 130 may include a first electrode CEh1 among the electrodes of the holding capacitor Chold. For example, the first electrode CEs1 of the storage capacitor Cst and the first electrode CEh1 of the holding capacitor Chold may be spaced apart from each other in a plan view.

[0198] The first electrode CEs1 of the storage capacitor Cst may be spaced apart from a portion of the third portion 1303 of the first gate layer 130 (e.g., the gate electrode G5 of the fifth thin-film transistor T5) in the y-axis direction in a planar view. The first electrode CEs1 of the storage capacitor Cst may have a specific width, and the first electrode CEs1 of the storage capacitor Cst may be spaced apart from the first electrode CEh1 of the holding capacitor Chold in the x-axis direction. The first electrode CEh1 of the holding capacitor Chold may have a specific width, and the first electrode CEh1 of the holding capacitor Chold may be spaced apart from the first electrode CEs1 of the storage capacitor Cst in the -x-axis direction. For example, in an embodiment, each of the first electrode CEs1 of the storage capacitor Cst and the first electrode CEh1 of the holding capacitor Chold may have an isolated shape.

[0199] The first gate layer 130 may further include a first portion 1301 to a third portion 1303. The first portion 1301 and the second portion 1302 of the first gate layer 130 may extend substantially in the x-axis direction, and the first electrode CEs1 of the storage capacitor Cst may be arranged in a planar view (e.g., in the y-axis direction) between the first portion 1301 and the second portion 1302 of the first gate layer 130.

[0200] The third portion 1303 of the first gate layer 130 may extend substantially in the x-axis direction. In an embodiment, the third portion 1303 of the first gate layer 130 may be a scan line EML for transmitting a scan signal applied to the fifth thin-film transistor T5. For example, a portion of the third portion 1303 of the first gate layer 130 may protrude in the y-axis direction in a planar view.

[0201] For example, a portion of the third portion 1303 of the first gate layer 130 may be the gate electrode G5 of the fifth thin-film transistor T5. For example, a portion of the third portion 1303 of the first gate layer 130 may overlap with the first portion 1201 of the first semiconductor layer 120 in a planar view. For example, a portion of the third portion 1303 of the first gate layer 130 may overlap with the channel region A5 of the first portion 1201 of the first semiconductor layer 120 in a planar view.

[0202] like Figure 23 As shown, the second gate layer 140 may be disposed above the first gate layer 130. In an embodiment, the second gate layer 140 may include a second electrode CEs2 among the electrodes of the storage capacitor Cst and a second electrode CEh2 among the electrodes of the holding capacitor Chold. In a plan view, the second gate layer 140 may not overlap with the lower metal layer 110.

[0203] The second gate layer 140 may include a first portion 1401 that does not overlap with the lower metal layer 110, the first semiconductor layer 120, and the first gate layer 130 in a plan view, and a second portion 1402 that overlaps with the first electrodes CEs1 and CEh1 included in the first gate layer 130 in a plan view. In an embodiment, the second portion 1402 of the second gate layer 140 may be integrally formed.

[0204] In an embodiment, the portion of the second portion 1402 of the second gate layer 140 that overlaps with the first electrode CEs1 of the storage capacitor Cst in a plan view can be the second electrode CEs2 of the storage capacitor Cst. The portion of the second portion 1402 of the second gate layer 140 that overlaps with the first electrode CEh1 of the holding capacitor Chold in a plan view can be the second electrode CEh2 of the holding capacitor Chold.

[0205] An opening portion OPP can be formed in the central region of the second electrode CEs2 of the storage capacitor Cst in the second portion 1402 of the second gate layer 140. Through the opening portion OPP, the first electrode CEs1 of the storage capacitor Cst and the components above the second gate layer 140 (e.g., a portion of the first conductive layer SD1) can be electrically connected to each other.

[0206] In an implementation, the shape of the second electrode CEh2 of the holding capacitor Chold can substantially correspond to the shape of the first electrode CEh1 of the holding capacitor Chold. When viewed from above the second gate layer 140 downwards (e.g., in a plan view), the first electrode CEh1 of the holding capacitor Chold can be largely covered by the second electrode CEh2 of the holding capacitor Chold.

[0207] In this embodiment, the shape of the second electrode CEs2 of the storage capacitor Cst can substantially correspond to the shape of the first electrode CEs1 of the storage capacitor Cst. When viewed from above the second gate layer 140, the first electrode CEs1 of the storage capacitor Cst can be completely covered by the second electrode CEs2 of the storage capacitor Cst.

[0208] like Figure 24 As shown, the groove pattern CP can be formed in the first interlayer insulating layer 104a and the second interlayer insulating layer 104b disposed on the second gate layer 140. Although the transparent first interlayer insulating layer 104a and the second interlayer insulating layer 104b are not shown in the layout diagram, they are included for ease of description. Figure 24 The groove pattern CP is shown in the figure.

[0209] The recessed pattern CP may overlap with a portion of the second electrode CEs2 of the storage capacitor Cst in the second gate layer 140 in a planar view. The recessed pattern CP may overlap with a portion of the first electrode CEs1 of the storage capacitor Cst in the first gate layer 130 in a planar view. A portion of the second semiconductor layer 150, described below, may be disposed within the recessed pattern CP.

[0210] like Figure 25 As shown, the second semiconductor layer 150 may be disposed above the second gate layer 140. Furthermore, the second semiconductor layer 150 may be disposed above the first interlayer insulating layer 104a. In an embodiment, the second semiconductor layer 150 may include a first portion 1501, a second portion 1502, and a third portion 1503. In a plan view, the second portion 1502 of the second semiconductor layer 150 may (e.g., in the y-axis direction) be disposed between the first portion 1501 and the third portion 1503 of the second semiconductor layer 150.

[0211] The first portion 1501 of the second semiconductor layer 150 may include a channel region A3 and source / drain regions SD3a and SD3b of the third thin-film transistor T3. In an embodiment, the channel region A3 and source / drain regions SD3a and SD3b of the third thin-film transistor T3 in the first portion 1501 of the second semiconductor layer 150 may extend in the y-axis direction. The channel region A3 of the third thin-film transistor T3 may be arranged between the source / drain regions SD3a and SD3b of the third thin-film transistor T3 in a planar view. The channel region A3 of the third thin-film transistor T3 may overlap with the first portion 1301 of the first gate layer 130 in a planar view.

[0212] The first portion 1501 of the second semiconductor layer 150 may include a channel region A2 and source / drain regions SD2a and SD2b of the second thin-film transistor T2. In an embodiment, the channel region A2 and source / drain regions SD2a and SD2b of the second thin-film transistor T2 in the first portion 1501 of the second semiconductor layer 150 may extend in the x-axis direction. The channel region A2 of the second thin-film transistor T2 may be arranged between the source / drain regions SD2a and SD2b of the second thin-film transistor T2 in a planar view. The channel region A2 of the second thin-film transistor T2 may overlap with the first portion 1401 of the second gate layer 140 in a planar view.

[0213] The second portion 1502 of the second semiconductor layer 150 may include a channel region A7 and source / drain regions SD7a and SD7b of the seventh thin-film transistor T7. In an embodiment, the channel region A7 and source / drain regions SD7a and SD7b of the seventh thin-film transistor T7 in the second portion 1502 of the second semiconductor layer 150 may extend in the y-axis direction. The channel region A7 of the seventh thin-film transistor T7 may be arranged in a planar view between the source / drain regions SD7a and SD7b of the seventh thin-film transistor T7. The channel region A7 of the seventh thin-film transistor T7 may overlap with a portion of the first electrode CEs1 and a portion of the second electrode CEs2 of the storage capacitor Cst in a planar view.

[0214] The third portion 1503 of the second semiconductor layer 150 may include the channel region A1 and source-drain regions SD1a and SD1b of the first thin-film transistor T1. In an embodiment, the channel region A1 and source-drain regions SD1a and SD1b of the first thin-film transistor T1 in the third portion 1503 of the second semiconductor layer 150 may extend in the x-axis direction. The channel region A1 of the first thin-film transistor T1 may be arranged between the source-drain regions SD1a and SD1b of the first thin-film transistor T1 in a planar view. The channel region A1 and source-drain regions SD1a and SD1b of the first thin-film transistor T1 may overlap with the aforementioned groove pattern CP in a planar view. The channel region A1 and source-drain regions SD1a and SD1b of the first thin-film transistor T1 may be arranged above the aforementioned groove pattern CP. The channel region A1 and source-drain regions SD1a and SD1b of the first thin-film transistor T1 may be arranged in the aforementioned groove pattern CP in a planar view.

[0215] The third portion 1503 of the second semiconductor layer 150 may include a channel region A6 and source / drain regions SD6a and SD6b of the sixth thin-film transistor T6. In an embodiment, the channel region A6 and source / drain regions SD6a and SD6b of the sixth thin-film transistor T6 in the third portion 1503 of the second semiconductor layer 150 may extend in the y-axis direction. The channel region A6 of the sixth thin-film transistor T6 may be arranged between the source / drain regions SD6a and SD6b of the sixth thin-film transistor T6 in a planar view. The channel region A6 and source / drain regions SD6a and SD6b of the sixth thin-film transistor T6 may overlap with the second portion 1302 of the first gate layer 130 in a planar view.

[0216] The third portion 1503 of the second semiconductor layer 150 may include a channel region A4 and source / drain regions SD4a and SD4b of a fourth thin-film transistor T4. In an embodiment, the channel region A4 and source / drain regions SD4a and SD4b of the fourth thin-film transistor T4 in the third portion 1503 of the second semiconductor layer 150 may extend in the y-axis direction. The channel region A4 of the fourth thin-film transistor T4 may be arranged between the source / drain regions SD4a and SD4b of the fourth thin-film transistor T4 in a planar view. The channel region A4 and source / drain regions SD4a and SD4b of the fourth thin-film transistor T4 may overlap with the third portion 1303 of the first gate layer 130 in a planar view.

[0217] like Figure 26As shown, the third gate layer 160 may be disposed on the second semiconductor layer 150. In an embodiment, the third gate layer 160 may include a first portion 1601 to a seventh portion 1607, and each of the first portion 1601 to the seventh portion 1607 may be separated in a plan view and may have an isolated shape.

[0218] A first portion 1601 of the third gate layer 160 may extend substantially in the x-axis direction. The first portion 1601 of the third gate layer 160 may include the gate electrode G3 of the third thin-film transistor T3. The gate electrode G3 of the third thin-film transistor T3 may overlap with the channel region A3 of the third thin-film transistor T3 in the second semiconductor layer 150 in a planar view. In an embodiment, the first portion 1601 of the third gate layer 160 may be a scan line GRL for transmitting a scan signal to the gate electrode G3 of the third thin-film transistor T3.

[0219] For example, in one embodiment, the first portion 1601 of the third gate layer 160 can be electrically connected to the first portion 1301 of the first gate layer 130 via a first type via CNT1 formed downwardly.

[0220] The second portion 1602 of the third gate layer 160 may extend in the x-axis direction. A region protruding in the y-axis direction within the second portion 1602 of the third gate layer 160 may be the gate electrode G2 of the second thin-film transistor T2. Therefore, the second portion 1602 of the third gate layer 160 may include the gate electrode G2 of the second thin-film transistor T2. The gate electrode G2 of the second thin-film transistor T2 may overlap with the channel region A2 of the second thin-film transistor T2 in the second semiconductor layer 150 in a planar view. In an embodiment, the second portion 1602 of the third gate layer 160 may be a scan line GWL for transmitting a scan signal to the gate electrode G2 of the second thin-film transistor T2.

[0221] For example, in one embodiment, the second portion 1602 of the third gate layer 160 can be electrically connected to the first portion 1401 of the second gate layer 140 via a first type via CNT1 formed downwards.

[0222] The third portion 1603 of the third gate layer 160 may extend in the x-axis direction. A portion of the third portion 1603 of the third gate layer 160 may be the gate electrode G7 of the seventh thin-film transistor T7. Therefore, the third portion 1603 of the third gate layer 160 may include the gate electrode G7 of the seventh thin-film transistor T7. The gate electrode G7 of the seventh thin-film transistor T7 may overlap with the channel region A7 of the seventh thin-film transistor T7 in the second semiconductor layer 150 in a planar view. In an embodiment, the third portion 1603 of the third gate layer 160 may be a scan line GCL for transmitting a scan signal to the gate electrode G7 of the seventh thin-film transistor T7.

[0223] The fourth portion 1604 of the third gate layer 160 may extend substantially in the x-axis direction. A portion of the fourth portion 1604 of the third gate layer 160 may be the gate electrode G6 of the sixth thin-film transistor T6. Therefore, the fourth portion 1604 of the third gate layer 160 may include the gate electrode G6 of the sixth thin-film transistor T6. The gate electrode G6 of the sixth thin-film transistor T6 may overlap with the channel region A6 of the sixth thin-film transistor T6 in the second semiconductor layer 150 in a planar view. In an embodiment, the fourth portion 1604 of the third gate layer 160 may be a scan line EMBL for transmitting a scan signal to the gate electrode G6 of the sixth thin-film transistor T6.

[0224] For example, in one embodiment, the fourth portion 1604 of the third gate layer 160 can be electrically connected to the second portion 1302 of the first gate layer 130 via a first-type via CNT1 formed downwards.

[0225] The fifth portion 1605 of the third gate layer 160 may extend substantially in the x-axis direction. A portion of the fifth portion 1605 of the third gate layer 160 may be the gate electrode G4 of the fourth thin-film transistor T4. Therefore, the fifth portion 1605 of the third gate layer 160 may include the gate electrode G4 of the fourth thin-film transistor T4. The gate electrode G4 of the fourth thin-film transistor T4 may overlap with the channel region A4 of the fourth thin-film transistor T4 in the second semiconductor layer 150 in a planar view. In an embodiment, the fifth portion 1605 of the third gate layer 160 may be a scan line GIL for transmitting a scan signal to the gate electrode G4 of the fourth thin-film transistor T4.

[0226] For example, in one embodiment, the fifth portion 1605 of the third gate layer 160 can be electrically connected to the third portion 1303 of the first gate layer 130 via a first-type via CNT1 formed downwards.

[0227] The sixth portion 1606 of the third gate layer 160 may extend substantially in the x-axis direction. In an embodiment, the sixth portion 1606 of the third gate layer 160 may be a line for transmitting a reference voltage Vref or a line for transmitting an initialization voltage Vaint.

[0228] The seventh portion 1607 of the third gate layer 160 can be disposed in the opening region BIP of the lower metal layer 110. The seventh portion 1607 of the third gate layer 160 can extend in the x-axis direction and can be disposed in the opening region BIP in a planar view. Figure 20 In the third gate layer 160, the seventh portion 1607 may intersect with the virtual center line FX in the plan view. The seventh portion 1607 of the third gate layer 160 may be configured to electrically connect to the first portion 1701 of the first conductive layer SD1 described below.

[0229] like Figure 27 As shown, a first conductive layer SD1 may be disposed above a third gate layer 160. The first conductive layer SD1 may be disposed (e.g., vertically) between the third gate layer 160 and the second conductive layer SD2. The first conductive layer SD1 may include first portions 1701 to tenth portions 1710. In an embodiment, each of the first portions 1701 to tenth portions 1710 of the first conductive layer SD1 may have an isolated shape in a plan view and may be spaced apart from each other in a plan view.

[0230] The first portion 1701 of the first conductive layer SD1 may extend substantially in the x-axis direction. One end of the first portion 1701 of the first conductive layer SD1 may overlap with the seventh portion 1607 of the third gate layer 160 described above in a plan view.

[0231] For example, in one embodiment, one end of the first portion 1701 of the first conductive layer SD1 can be electrically connected to the seventh portion 1607 of the third gate layer 160 via a downwardly formed second type via CNT2.

[0232] The second portion 1702 of the first conductive layer SD1 may extend substantially in the y-axis direction. One end of the second portion 1702 of the first conductive layer SD1 may overlap with the first portion 1501 of the second semiconductor layer 150 in a plan view, and the other end of the second portion 1702 of the first conductive layer SD1 may overlap with the second portion 1502 of the second semiconductor layer 150 in a plan view.

[0233] For example, one end of the second portion 1702 of the first conductive layer SD1 may overlap with one of the source-drain regions SD3a and SD3b of the third thin-film transistor T3 (e.g., SD3a) in a planar view. For example, the other end of the second portion 1702 of the first conductive layer SD1 may overlap with one of the source-drain regions SD7a and SD7b of the seventh thin-film transistor T7 (e.g., SD7b) in a planar view.

[0234] For example, in one embodiment, one end of the second portion 1702 of the first conductive layer SD1 can be electrically connected to the first portion 1501 of the second semiconductor layer 150 via a downwardly formed second-type via CNT2. In another embodiment, one end of the second portion 1702 of the first conductive layer SD1 can be electrically connected to one of the source and drain regions SD3a and SD3b of the third thin-film transistor T3 (e.g., SD3a) via a downwardly formed second-type via CNT2.

[0235] For example, in one embodiment, the other end of the second portion 1702 of the first conductive layer SD1 can be electrically connected to the second portion 1502 of the second semiconductor layer 150 via a downwardly formed second-type via CNT2. In another embodiment, the other end of the second portion 1702 of the first conductive layer SD1 can be electrically connected to one of the source and drain regions SD7a and SD7b of the seventh thin-film transistor T7 (e.g., SD7b) via a downwardly formed second-type via CNT2.

[0236] One end of the third portion 1703 of the first conductive layer SD1 may overlap with the first portion 1501 of the second semiconductor layer 150 in a planar view, and the other end of the third portion 1703 of the first conductive layer SD1 may overlap with the gate electrode G1 in the third gate layer 160 in a planar view. For example, one end of the third portion 1703 of the first conductive layer SD1 may overlap with one of the source and drain regions SD2a and SD2b of the second thin-film transistor T2 (e.g., SD2b) in a planar view. For example, the other end of the third portion 1703 of the first conductive layer SD1 may overlap with the gate electrode G1 of the first thin-film transistor T1 in the third gate layer 160 in a planar view.

[0237] The third portion 1703 of the first conductive layer SD1 may include a portion extending in the y-axis direction and including one end of the third portion 1703 of the first conductive layer SD1, and another portion extending in the x-axis direction and including the other end of the third portion 1703 of the first conductive layer SD1. The area where one portion and the other portion meet each other may be referred to as the central region of the third portion 1703 of the first conductive layer SD1.

[0238] The central region of the third portion 1703 of the first conductive layer SD1 may overlap with the first gate layer 130 in a planar view. For example, the central region of the third portion 1703 of the first conductive layer SD1 may overlap with the first electrode CEs1 of the storage capacitor Cst in a planar view. For example, the central region of the third portion 1703 of the first conductive layer SD1 may overlap with the opening portion OPP of the second electrode CEs2 of the storage capacitor Cst in the second gate layer 140 in a planar view, and may be electrically connected to the first electrode CEs1 of the storage capacitor Cst through the opening portion OPP.

[0239] For example, one end of the third portion 1703 of the first conductive layer SD1 can be electrically connected to the first portion 1501 of the second semiconductor layer 150 via a downwardly formed second-type via CNT2. In an embodiment, one end of the third portion 1703 of the first conductive layer SD1 can be simultaneously electrically connected to the third thin-film transistor T3 and the second thin-film transistor T2 via a downwardly formed second-type via CNT2.

[0240] For example, the other end of the third portion 1703 of the first conductive layer SD1 can be electrically connected to the third gate layer 160 through a downwardly formed second-type via CNT2. For example, in one embodiment, the other end of the third portion 1703 of the first conductive layer SD1 can be electrically connected to the gate electrode G1 of the first thin-film transistor T1 through a downwardly formed second-type via CNT2.

[0241] For example, the central region of the third portion 1703 of the first conductive layer SD1 can be electrically connected to the first electrode CEs1 of the storage capacitor Cst through a downwardly formed third type via CNT3.

[0242] The fourth portion 1704 of the first conductive layer SD1 may overlap with the first portion 1501 of the second semiconductor layer 150 in a planar view. For example, the fourth portion 1704 of the first conductive layer SD1 may overlap with one of the source and drain regions SD2a and SD2b of the second thin film transistor T2 (e.g., SD2a) in a planar view.

[0243] For example, the fourth portion 1704 of the first conductive layer SD1 can be electrically connected to the first portion 1501 of the second semiconductor layer 150 via a downwardly formed second-type via CNT2. In an embodiment, the fourth portion 1704 of the first conductive layer SD1 can be electrically connected to the second thin-film transistor T2 via a downwardly formed second-type via CNT2.

[0244] The fifth portion 1705 of the first conductive layer SD1 may overlap with the second portion 1502 of the second semiconductor layer 150 in a planar view, and may also overlap with a portion of the first gate layer 130 in a planar view. For example, one end of the fifth portion 1705 of the first conductive layer SD1 may overlap with one of the source and drain regions SD7a and SD7b of the seventh thin-film transistor T7 (e.g., SD7a) in a planar view. For example, another end of the fifth portion 1705 of the first conductive layer SD1 may overlap with the first electrode CEh1 of the holding capacitor Chold in the first gate layer 130 in a planar view.

[0245] For example, the fifth portion 1705 of the first conductive layer SD1 can be electrically connected to the second portion 1502 of the second semiconductor layer 150 via a downwardly formed second-type via CNT2. In an embodiment, the fifth portion 1705 of the first conductive layer SD1 can be electrically connected to the seventh thin-film transistor T7 via a downwardly formed second-type via CNT2.

[0246] The sixth portion 1706 of the first conductive layer SD1 may extend in the y-axis direction. In an embodiment, the sixth portion 1706 of the first conductive layer SD1 may be a power line PL1. The first power supply voltage ELVDD can be transmitted through the sixth portion 1706 of the first conductive layer SD1. In a plan view, the sixth portion 1706 of the first conductive layer SD1 may overlap with the virtual center line FX.

[0247] For example, the sixth portion 1706 of the first conductive layer SD1 can be electrically connected to the sixth portion 1606 of the third gate layer 160 via a downwardly formed third-type via CNT3. In an embodiment, the sixth portion 1706 of the first conductive layer SD1 can be electrically connected to a line for transmitting the reference voltage Vref or a line for transmitting the initialization voltage Vaint via a downwardly formed third-type via CNT3.

[0248] One end of the seventh portion 1707 of the first conductive layer SD1 may overlap with the third portion 1503 of the second semiconductor layer 150 in a planar view, and simultaneously, the other end of the seventh portion 1707 of the first conductive layer SD1 may overlap with a portion of the first semiconductor layer 120 in a planar view. For example, one end of the seventh portion 1707 of the first conductive layer SD1 may overlap with one of the source-drain regions SD1a and SD1b of the first thin-film transistor T1 (e.g., SD1a) in a planar view. For example, the other end of the seventh portion 1707 of the first conductive layer SD1 may overlap with one of the source-drain regions SD5a and SD5b of the fifth thin-film transistor T5 (e.g., SD5b) in a planar view.

[0249] For example, one end of the seventh portion 1707 of the first conductive layer SD1 can be electrically connected to the third portion 1503 of the second semiconductor layer 150 via a downwardly formed second-type via CNT2. In an embodiment, one end of the seventh portion 1707 of the first conductive layer SD1 can be electrically connected to the first thin-film transistor T1 via a downwardly formed second-type via CNT2.

[0250] For example, the other end of the seventh portion 1707 of the first conductive layer SD1 can be electrically connected to the first portion 1201 of the first semiconductor layer 120 through a downwardly formed third-type via CNT3. In an embodiment, the other end of the seventh portion 1707 of the first conductive layer SD1 can be electrically connected to the fifth thin-film transistor T5 through a downwardly formed third-type via CNT3.

[0251] One end of the eighth portion 1708 of the first conductive layer SD1 may overlap with the second electrode CEs2 of the storage capacitor Cst of the second gate layer 140 in a plan view. The other end of the eighth portion 1708 of the first conductive layer SD1 may overlap with the aforementioned groove pattern CP in a plan view.

[0252] For example, one end of the eighth portion 1708 of the first conductive layer SD1 can be electrically connected to the second portion 1402 of the second gate layer 140 via a downwardly formed third-type via CNT3. In an embodiment, one end of the eighth portion 1708 of the first conductive layer SD1 can be electrically connected to the second electrode CEs2 of the storage capacitor Cst via a downwardly formed third-type via CNT3.

[0253] For example, the other end of the eighth portion 1708 of the first conductive layer SD1 can be electrically connected to a portion of the second semiconductor layer 150 via a downwardly formed second-type via CNT2. In an embodiment, the other end of the eighth portion 1708 of the first conductive layer SD1 can be electrically connected to the first thin-film transistor T1 via a downwardly formed second-type via CNT2.

[0254] At least a portion of the ninth portion 1709 of the first conductive layer SD1 may overlap with the third portion 1503 of the second semiconductor layer 150 in a planar view. For example, at least a portion of the ninth portion 1709 of the first conductive layer SD1 may overlap with a region in a planar view between one of the source-drain regions SD6a and SD6b of the sixth thin-film transistor T6 (e.g., SD6b) and one of the source-drain regions SD4a and SD4b of the fourth thin-film transistor T4 (e.g., SD4a).

[0255] For example, the ninth portion 1709 of the first conductive layer SD1 can be electrically connected to the third portion 1503 of the second semiconductor layer 150 through a downwardly formed second-type via CNT2. In an embodiment, the ninth portion 1709 of the first conductive layer SD1 can be simultaneously electrically connected to the fourth thin-film transistor T4 and the sixth thin-film transistor T6 through the downwardly formed second-type via CNT2.

[0256] For example, the tenth portion 1710 of the first conductive layer SD1 can be electrically connected to the third portion 1503 of the second semiconductor layer 150 via a downwardly formed second-type via CNT2. In an embodiment, the tenth portion 1710 of the first conductive layer SD1 can be electrically connected to the fourth thin-film transistor T4 via a downwardly formed second-type via CNT2.

[0257] like Figure 28 As shown, the second conductive layer SD2 can be disposed on top of the first conductive layer SD1. The second conductive layer SD2 can be disposed (e.g., in the vertical direction) between the first conductive layer SD1 and the pixel electrode layer 170. In an embodiment, the second conductive layer SD2 may include first portions 1801 to fifth portions 1805. In an embodiment, each of the first portions 1801 to fifth portions 1805 of the second conductive layer SD2 may have an isolated shape in a plan view and may be spaced apart from each other in a plan view.

[0258] The first portion 1801 of the second conductive layer SD2 may extend substantially in the y-axis direction. The first portion 1801 of the second conductive layer SD2 may be a connection line BRS. The connection line BRS may partially overlap with the sixth portion 1706 of the first conductive layer SD1 in a plan view. In an embodiment, the connection line BRS may have a shape corresponding to the shape of the opening region BIP of the lower metal layer 110. In a plan view, the connection line BRS may partially overlap with the first electrode CEh1 of the holding capacitor Chold of the first gate layer 130.

[0259] In this embodiment, the second portion 1802 of the second conductive layer SD2 may be the aforementioned data line DL. The second portion 1802 of the second conductive layer SD2 may extend substantially in the y-axis direction. The second portion 1802 of the second conductive layer SD2 may overlap with the fourth portion 1704 of the first conductive layer SD1 in a planar view.

[0260] For example, in one embodiment, the second portion 1802 of the second conductive layer SD2 can be electrically connected to the fourth portion 1704 of the first conductive layer SD1 via a downwardly formed fourth type via CNT4.

[0261] For example, the second portion 1802 of the second conductive layer SD2 can be electrically connected to the first portion 1501 of the second semiconductor layer 150 through the fourth portion 1704 of the first conductive layer SD1.

[0262] In this embodiment, the third portion 1803 of the second conductive layer SD2 may be the aforementioned initialization voltage line VL2. The third portion 1803 of the second conductive layer SD2 may extend substantially in the y-axis direction. The third portion 1803 of the second conductive layer SD2 may overlap with the tenth portion 1710 of the first conductive layer SD1 in a planar view.

[0263] For example, in one embodiment, the third portion 1803 of the second conductive layer SD2 can be electrically connected to the tenth portion 1710 of the first conductive layer SD1 via a downwardly formed fourth type via CNT4.

[0264] For example, the third portion 1803 of the second conductive layer SD2 can be electrically connected to the third portion 1503 of the second semiconductor layer 150 via the tenth portion 1710 of the first conductive layer SD1. For example, the third portion 1803 of the second conductive layer SD2 can be electrically connected to one of the source and drain regions SD4a and SD4b of the fourth thin-film transistor T4 (e.g., SD4b) via the tenth portion 1710 of the first conductive layer SD1.

[0265] In this embodiment, the fourth portion 1804 of the second conductive layer SD2 may be the aforementioned reference voltage line VL1. The fourth portion 1804 of the second conductive layer SD2 may extend substantially in the y-axis direction. The fourth portion 1804 of the second conductive layer SD2 may overlap with the second portion 1702 of the first conductive layer SD1 in a planar view.

[0266] For example, the fourth portion 1804 of the second conductive layer SD2 can be electrically connected to the second portion 1702 of the first conductive layer SD1 through a downwardly formed fourth type via CNT4.

[0267] For example, the fourth portion 1804 of the second conductive layer SD2 can be electrically connected to the second portion 1502 of the second semiconductor layer 150 through the other end of the second portion 1702 of the first conductive layer SD1. For example, the fourth portion 1804 of the second conductive layer SD2 can be electrically connected to one of the source and drain regions SD7a and SD7b of the seventh thin film transistor T7 (e.g., SD7b) through the second portion 1702 of the first conductive layer SD1.

[0268] The fifth portion 1805 of the second conductive layer SD2 may be arranged between the third portion 1803 and the fourth portion 1804 of the second conductive layer SD2 in a plan view (e.g., in the x-axis direction). The fifth portion 1805 of the second conductive layer SD2 may overlap with the ninth portion 1709 of the first conductive layer SD1 in a plan view.

[0269] For example, in one embodiment, the fifth portion 1805 of the second conductive layer SD2 can be electrically connected to the ninth portion 1709 of the first conductive layer SD1 via a downwardly formed fourth type via CNT4.

[0270] For example, the fifth portion 1805 of the second conductive layer SD2 can be electrically connected to the third portion 1503 of the second semiconductor layer 150 via the ninth portion 1709 of the first conductive layer SD1. For example, the fifth portion 1805 of the second conductive layer SD2 can be electrically connected via the ninth portion 1709 of the first conductive layer SD1 to one of the source / drain regions SD6a and SD6b of the sixth thin-film transistor T6 (e.g., SD6b) and one of the source / drain regions SD4a and SD4b of the fourth thin-film transistor T4 (e.g., SD4a).

[0271] For example, the fifth portion 1805 of the second conductive layer SD2 can be electrically connected to the first pixel electrode 170a of the pixel electrode layer 170 through a fifth type via CNT5 formed upwards.

[0272] For example, in one embodiment, the fifth portion 1805' of the second conductive layer SD2 can be electrically connected to the second pixel electrode 170b of the pixel electrode layer 170 via a fifth type via CNT5 formed upwards.

[0273] For example, in one embodiment, the 5'' portion 1805'' of the second conductive layer SD2 can be electrically connected to the third pixel electrode 170c of the pixel electrode layer 170 via a fifth type via CNT5 formed upwards.

[0274] like Figure 29 As shown, the pixel electrode layer 170 can be disposed on the second conductive layer SD2. The pixel electrode layer 170 may include a first pixel electrode 170a to a third pixel electrode 170c. In an embodiment, each of the first pixel electrode 170a to the third pixel electrode 170c of the pixel electrode layer 170 may have an isolated shape in a planar view and may be spaced apart from each other in a planar view.

[0275] The first pixel electrode 170a of the pixel electrode layer 170 may be a pixel electrode corresponding to the first pixel region PX1. The first pixel region PX1 may be defined by a pixel defining layer 108 covering the edge of the first pixel electrode 170a. The first pixel electrode 170a may overlap with the virtual center line FX in a planar view. A portion of the first pixel electrode 170a may protrude in one direction (e.g., in the -x-axis direction), and a portion of the first pixel electrode 170a may overlap with the fifth portion 1805 of the second conductive layer SD2 in a planar view.

[0276] The second pixel electrode 170b of the pixel electrode layer 170 may be a pixel electrode corresponding to the second pixel region PX2. The second pixel region PX2 may be defined by a pixel defining layer 108 covering the edge of the second pixel electrode 170b. The second pixel electrode 170b may be spaced apart from the first pixel electrode 170a in a planar view. A portion of the second pixel electrode 170b may protrude in one direction (e.g., in the y-axis direction), and a portion of the second pixel electrode 170b may overlap with the 5' portion 1805' of the second conductive layer SD2 in a planar view.

[0277] The third pixel electrode 170c of the pixel electrode layer 170 may be a pixel electrode corresponding to the third pixel region PX3. The third pixel region PX3 may be defined by a pixel defining layer 108 covering the edge of the third pixel electrode 170c. The third pixel electrode 170c may overlap with the virtual center line FX in a planar view. A portion of the third pixel electrode 170c may protrude in one direction (e.g., in the -x-axis direction), and a portion of the third pixel electrode 170c may overlap with the 5'' portion 1805'' of the second conductive layer SD2 in a planar view.

[0278] Figure 30 It is shown schematically. Figure 1 A floor plan of a portion of the display area. For simplicity, redundant descriptions of components may be omitted. For reference, it can be based on... Figure 4 To understand using the equivalent circuit diagram Figures 30 to 39 The layout.

[0279] like Figure 30 As shown, the components can be arranged symmetrically with respect to a virtual centerline FX extending in the y-axis direction. Components arranged on one side of the virtual centerline FX and components arranged on the other side of the virtual centerline FX can be symmetrical with respect to the virtual centerline FX.

[0280] Figures 31 to 39 It is shown schematically in its stacking order. Figure 30The layout shown is a plan view. For reference, and for the sake of simplicity, the accompanying drawings that are identical to the above drawings can be omitted. Figures 31 to 36 The description.

[0281] like Figure 37 As shown, the first portion 1601 of the third gate layer 160 may extend substantially in the x-axis direction. The first portion 1601 of the third gate layer 160 may not overlap with the opening region BIP in a plan view. A portion of the first portion 1601 of the third gate layer 160 may have a shape corresponding to a portion of the opening region BIP defined by the third portion 1103 of the lower metal layer 110.

[0282] exist Figure 37 In the embodiment shown, the third gate layer 160 may not include Figure 26 Part 7, 1607, is shown. Because... Figure 26 The seventh portion 1607 of the third gate layer 160 shown partially covers the opening region BIP, and therefore can be omitted. Figure 26 The seventh portion 1607 of the third gate layer 160 shown is used to fully open the opening region BIP.

[0283] like Figure 38 As shown, the first portion 1701 of the first conductive layer SD1 can extend substantially in the x-axis direction. Figure 38 The first portion 1701 of the first conductive layer SD1 in the embodiment shown may have the same characteristics as... Figure 27 The first portion 1701 of the first conductive layer SD1 in the illustrated embodiment has a different shape. For example, Figure 38 The first portion 1701 of the first conductive layer SD1 can have a higher conductivity than that of the first conductive layer SD1. Figure 27 The first portion 1701 of the first conductive layer SD1 has a small length so as not to cover the opening region BIP.

[0284] Figure 38 The sixth portion 1706 of the first conductive layer SD1 may have an opening having a shape corresponding to the opening region BIP. In an embodiment, Figure 38 The sixth portion 1706 of the first conductive layer SD1 may include a sixth portion 1706a disposed in the first pixel circuit region PP1 and a sixth portion 1706b disposed in the second pixel circuit region PP2. Figure 38 The sixth portion 1706 of the first conductive layer SD1 can be divided into a sixth portion 1706a and a sixth portion 1706b, and therefore can have an opening having a shape corresponding to the opening region BIP.

[0285] like Figure 39As shown, the first portion 1801 of the second conductive layer SD2 can be disconnected. For example, the first portion 1801 of the second conductive layer SD2 may not cover the opening region BIP. Figure 28 The first portion 1801 of the second conductive layer SD2 shown in the embodiment is different. Figure 39 The first part 1801 of the second conductive layer SD2 can be electrically connected to the sixth part 1706 of the first conductive layer SD1 located thereunder via a through-hole.

[0286] For example, in one embodiment, the first portion 1801 of the second conductive layer SD2 can be electrically connected to the sixth portion 1706 of the first conductive layer SD1 via a downwardly formed fourth-type via CNT4. In another embodiment, the first portion 1801 of the second conductive layer SD2 can be electrically connected to the power line PL1 for transmitting the first power supply voltage ELVDD via the downwardly formed fourth-type via CNT4.

[0287] Figure 40 This is a block diagram of an electronic device according to an embodiment.

[0288] Electronic device 1000 can output various types of information to the operating system through display module 1400. When processor 1100 runs an application stored in memory 1200, display module 1400 can provide application information to the user through display panel 10.

[0289] exist Figure 40 The display panel 10 described herein can be understood as including Figures 1 to 39 A display panel in one of the display devices.

[0290] Processor 1100 can obtain external input through input module 1300 or sensor module 1610 and run the application corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 10, processor 1100 can obtain user input through input sensor 1610-2 and activate camera module 1711. Processor 1100 can then transmit image data corresponding to the captured image obtained by camera module 1711 to display module 1400. Display module 1400 can display the image corresponding to the captured image through display panel 10.

[0291] As another example, when personal information authentication is performed in display module 1400, fingerprint sensor 1610-1 can obtain input fingerprint information as input data. Processor 1100 can compare the input data obtained by fingerprint sensor 1610-1 with authentication data stored in memory 1200, and run the application based on the comparison result. Display module 1400 can display information about the logic executed according to the application through display panel 10.

[0292] As another example, when a music stream icon displayed on display module 1400 is selected, processor 1100 can obtain user input via input sensor 1610-2 and activate the music stream application stored in memory 1200. When a music run command is entered in the music stream application, processor 1100 can activate audio output module 1630 to provide the user with audio information corresponding to the music run command.

[0293] The operation of electronic device 1000 has been briefly described above. The configuration of electronic device 1000 will be described in detail below. Some of the components of electronic device 1000 described below can be integrated and configured as a single component, and a single component can be separated and configured as two or more components.

[0294] refer to Figure 40 Electronic device 1000 can communicate with external electronic device 1020 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to embodiments, electronic device 1000 may include a processor 1100, a memory 1200, an input module 1300, a display module 1400, a power module 1500, an internal module 1600, and an external module 1700. According to embodiments, at least one of the above components may be omitted from electronic device 1000, or one or more other components may be added. According to embodiments, some components (e.g., sensor module 1610, antenna module 1620, or audio output module 1630) may be integrated into another component (e.g., display module 1400).

[0295] The processor 1100 can run software to control at least one other component (e.g., a hardware component or a software component) of the electronic device 1000 connected to the processor 1100, and can perform various data processing or operations. According to an embodiment, as at least part of the data processing or operation, the processor 1100 can store commands or data received from another component (e.g., input module 1300, sensor module 1610, or communication module 1730) in volatile memory 1210, process the commands or data stored in volatile memory 1210, and store the result data in non-volatile memory 1220.

[0296] Processor 1100 may include a main processor 1110 and an auxiliary processor 1120. Main processor 1110 may include one or more of a central processing unit (CPU) 1111 and an application processor (AP). Main processor 1110 may also include one or more of a graphics processing unit (GPU) 1112, a communication processor (CP), and an image signal processor (ISP). Main processor 1110 may also include a neural processing unit (NPU) 1113. NPU 1113 may be a processor dedicated to processing artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. Artificial neural networks may include, but are not limited to, deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), deep Q-networks, or any combination thereof. In addition to hardware architecture, the artificial intelligence model may additionally or optionally include software architecture. At least two of the aforementioned processing units and processors can be implemented as a single integrated component (e.g., a single chip), or they can be implemented as independent components (e.g., multiple chips).

[0297] The auxiliary processor 1120 may include a controller 1120-1. The controller 1120-1 may include interface conversion circuitry and timing control circuitry. The controller 1120-1 can receive image signals from the main processor 1110 and convert the data format of the image signals according to the interface specifications with the display module 1400 to output image data. The controller 1120-1 can output various control signals necessary to drive the display module 1400.

[0298] The auxiliary processor 1120 may further include a data conversion circuit 1120-2, a gamma correction circuit 1120-3, and a rendering circuit 1120-4. The data conversion circuit 1120-2 can receive image data from the controller 1120-1 and can compensate the image data to display an image at the required brightness according to the characteristics of the electronic device 1000 or user settings, or can convert the image data for power consumption reduction or afterimage compensation. The gamma correction circuit 1120-3 can convert image data or a gamma reference voltage so that the image displayed on the electronic device 1000 has the required gamma characteristics. The rendering circuit 1120-4 can receive image data from the controller 1120-1 and render the image data taking into account the pixel arrangement of the display panel 10 applied to the electronic device 1000. At least one of the data conversion circuit 1120-2, the gamma correction circuit 1120-3, and the rendering circuit 1120-4 may be integrated into another component (e.g., the main processor 1110 or the controller 1120-1). At least one of the data conversion circuit 1120-2, the gamma correction circuit 1120-3, and the rendering circuit 1120-4 can be integrated into the data driver DP described below.

[0299] The memory 1200 may store various data used by at least one component of the electronic device 1000 (e.g., processor 1100 or sensor module 1610) and input or output data of commands associated therewith. The memory 1200 may include at least one of volatile memory 1210 and non-volatile memory 1220.

[0300] The input module 1300 can receive commands or data from outside the electronic device 1000 (e.g., from a user or external electronic device 1020) to be used by components of the electronic device 1000 (e.g., processor 1100, sensor module 1610, or audio output module 1630).

[0301] Input module 1300 may include a first input module 1310 into which commands or data are input from a user, and a second input module 1320 into which commands or data are input from an external electronic device 1020. The first input module 1310 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 1320 may support a specified protocol that can be connected to the external electronic device 1020 via wired or wireless connection. According to embodiments, the second input module 1320 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, an SD card interface, or an audio interface. The second input module 1320 may include a connector that can be physically connected to the external electronic device 1020, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0302] Display module 1400 can visually provide information to the user. Display module 1400 may include display panel 10, scan driver GP, and data driver DP. Display module 1400 may also include a window, base, and bracket for protecting display panel 10.

[0303] The display panel 10 may also include a light-emitting driver. The light-emitting driver can output a transmission control signal to the display panel 10 in response to a control signal received from the controller 1120-1. The light-emitting driver may be formed separately from the scan driver GP, or it may be integrated into the scan driver GP.

[0304] The scan driver GP can receive control signals from the controller 1120-1 and output scan signals to the display panel 10 in response to the control signals. For example, the control signals generated by the controller 1120-1 and transmitted to the scan driver GP can be scan input signals for controlling the scan driver GP. The scan input signals can be input signals applied to switching devices included in the stages of the scan driver GP.

[0305] The data driver DP can receive control signals from the controller 1120-1, convert image data into analog voltages (e.g., data voltages) in response to the control signals, and then output the data voltages to the display panel 10. For example, the control signals generated by the controller 1120-1 and transmitted to the data driver DP can be data input signals used to control the data driver DP.

[0306] The data driver DP can be integrated into another component (e.g., controller 1120-1). The functions of the interface conversion circuit and timing control circuit of the controller 1120-1 can also be integrated into the data driver DP.

[0307] The controller 1120-1 can generate the clock signal necessary to drive the scan driver GP. The scan driver GP can generate a scan signal based on the scan input signal, the clock signal, and the scan input voltage. The scan signal can be transmitted to the pixel circuit, and the thin-film transistors included in the pixel circuit can be driven based on the scan signal. The scan signal can be transmitted to the gate included in the pixel circuit.

[0308] The display module 1400 may also include a light-emitting driver and a voltage generation circuit. The voltage generation circuit can output various voltages necessary to drive the display panel 10.

[0309] The power module 1500 can supply power to the components of the electronic device 1000. For example, the power module 1500 can generate the first power supply voltage ELVDD and the second power supply voltage ELVSS mentioned above. The power module 1500 can generate the gate drive voltages (e.g., gate high voltage and gate low voltage) necessary to drive the scan driver GP.

[0310] For example, power module 1500 can refer to a power generation unit, a power supply, etc. For example, power module 1500 may include a battery for charging the power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0311] For example, power module 1500 may include a power management integrated circuit (PMIC). The PMIC can provide optimized power for each of the modules described above and below.

[0312] For example, the power module 1500 may include a wireless power transmitting / receiving component electrically connected to a battery. The wireless power transmitting / receiving component may include multiple coil-type antenna radiators.

[0313] The electronic device 1000 may also include an internal module 1600 and an external module 1700. The internal module 1600 may include a sensor module 1610, an antenna module 1620, and an audio output module 1630. The external module 1700 may include a camera module 1711, an optical module 1720, and a communication module 1730.

[0314] The sensor module 1610 can sense input from the user's body or from the pen of the first input module 1310, and generate an electrical signal or data value corresponding to the input. The sensor module 1610 may include at least one of a fingerprint sensor 1610-1, an input sensor 1610-2, and a digitizer 1610-3.

[0315] The fingerprint sensor 1610-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 1610-1 can include either an optical fingerprint sensor or a capacitive fingerprint sensor.

[0316] The input sensor 1610-2 can generate data values ​​corresponding to the coordinate information of user body input or pen input. The input sensor 1610-2 can also generate capacitance changes caused by input as data values. The input sensor 1610-2 can sense input from a passive pen or send / receive data from an active pen.

[0317] The input sensor 1610-2 can also measure biosignals such as blood pressure, water content, or body fat. For example, when a user touches a part of their body to the sensor layer or sensing panel and does not move it for a certain period of time, the input sensor 1610-2 can sense biosignals based on the change in electric field caused by the part of the user's body and output the information required by the user to the display module 1400.

[0318] The digitizer 1610-3 can generate data values ​​corresponding to the coordinate information of the pen input. The digitizer 1610-3 can generate data values ​​based on electromagnetic changes caused by the input. The digitizer 1610-3 can sense input from a passive pen, or send data to / receive data from an active pen.

[0319] At least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be implemented as a sensor layer formed on the display panel 10 by a continuous process. The fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be arranged on the upper side of the display panel 10, and any one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 (e.g., the digitizer 1610-3) can be arranged on the lower side of the display panel 10.

[0320] At least two of the fingerprint sensor 1610-1, input sensor 1610-2, and digitizer 1610-3 can be formed and integrated into a single sensing panel using the same process. When integrated into a single sensing panel, the sensing panel can be arranged between the display panel 10 and a window disposed on the upper side of the display panel 10. According to an embodiment, the sensing panel can be disposed above the window, and the position of the sensing panel is not particularly limited.

[0321] At least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be built into the display panel 10. That is, at least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be formed simultaneously by a process that forms a device (e.g., a light-emitting device and a transistor) included in the display panel 10.

[0322] Furthermore, sensor module 1610 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 1000. Sensor module 1610 may also include, for example, gesture sensors, gyroscope sensors, pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biometric sensors, temperature sensors, humidity sensors, or illuminance sensors.

[0323] Antenna module 1620 may include one or more antennas for transmitting or receiving signals or power to / from an external source. According to an embodiment, communication module 1730 may transmit or receive signals to / from external electronic device 1020 via an antenna suitable for a communication method. The antenna pattern of antenna module 1620 may be integrated into a component (e.g., display panel 10) such as display module 1400, input sensor 1610-2, etc.

[0324] The audio output module 1630 may be a means for outputting audio signals to the external device 1000, and may include, for example, a speaker for general purposes such as multimedia playback or recording playback and a receiver specifically for telephone reception. Depending on the embodiment, the receiver may be integrally formed with the speaker or formed separately from the speaker. The audio output mode of the audio output module 1630 may be integrated into the display module 1400.

[0325] Camera module 1711 can capture still images and moving images. According to embodiments, camera module 1711 may include one or more lenses, an image sensor, or an image signal processor. Camera module 1711 may also include an infrared camera capable of measuring the presence / absence of a user, the user's position, the user's line of sight, etc.

[0326] The optical module 1720 can provide light. The optical module 1720 may include a light-emitting diode or a xenon lamp. The optical module 1720 can operate in conjunction with the camera module 1711 or independently of the camera module 1711.

[0327] Communication module 1730 can support the establishment of a wired or wireless communication channel between electronic device 1000 and external electronic device 1020 and perform communication through the established communication channel. Communication module 1730 may include any one or all of the following: a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module; and a wired communication module such as a Local Area Network (LAN) communication module or a power-line communication module. Communication module 1730 can communicate with external electronic device 1020 via a short-range communication network such as Bluetooth, WiFi Direct, or Infrared Data Association (IrDA) or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or WAN). The various types of communication modules 1730 described above can be implemented as a single chip or as separate chips.

[0328] The input module 1300, sensor module 1610, and camera module 1711 can be used in conjunction with the processor 1100 to control the operation of the display module 1400.

[0329] The processor 1100 can output commands or data to the display module 1400, audio output module 1630, camera module 1711, or optical module 1720 based on the input data received from the input module 1300. For example, the processor 1100 can generate image data corresponding to input data applied via a mouse, active pen, etc., and output the image data to the display module 1400, or it can generate command data corresponding to the input data and output the command data to the camera module 1711 or optical module 1720. When no input data is received from the input module 1300 for a certain period of time, the processor 1100 can reduce the power consumption of the electronic device 1000 by switching the operating mode of the electronic device 1000 to a low-power mode or a sleep mode.

[0330] The processor 1100 can output commands or data to the display module 1400, audio output module 1630, camera module 1711, or optical module 1720 based on sensing data received from the sensor module 1610. For example, the processor 1100 can compare authentication data authenticated by the fingerprint sensor 1610-1 with authentication data stored in the memory 1200, and then run the application based on the comparison result. Based on sensing data sensed by the input sensor 1610-2 or digitizer 1610-3, the processor 1100 can run commands or output corresponding image data to the display module 1400. When the sensor module 1610 includes a temperature sensor, the processor 1100 can receive temperature data about the measured temperature from the sensor module 1610, and further perform brightness correction, etc., on the image data based on the temperature data.

[0331] The processor 1100 can receive measurement data from the camera module 1711 regarding the presence / absence of a user, the user's position, the user's gaze, etc. The processor 1100 can also perform brightness correction and other functions on the image data based on the measurement data. For example, the processor 1100, having already determined the presence / absence of a user through input from the camera module 1711, can output image data with brightness corrected by the data conversion circuit 1120-2 or the gamma correction circuit 1120-3 to the display module 1400.

[0332] Some of the components described above can be connected to each other via peripheral communication methods (such as bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industrial processor interface (MIPI), or ultrapath interconnect (UPI) links) to exchange signals (e.g., commands or data). The processor 1100 can communicate with the display module 1400 through mutually agreed interfaces and can use any of the communication methods described above, but is not limited thereto.

[0333] The electronic device 1000 according to the various embodiments described herein can be of various types. The electronic device 1000 may include at least one of, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance device. The electronic device 1000 according to the embodiments described herein is not limited to the above devices and may be various other small, medium, or large electronic devices.

[0334] In this embodiment, the electronic device 1000 may include a controller 1120-1, a power supply module 1500, and a display module 1400. The display module 1400 may include a display panel 10 and a scan driver GP. The controller 1120-1 can generate the scan input signals necessary to drive the scan driver GP. Under the control of the processor or the controller 1120-1, the power supply module 1500 can generate the scan input voltage necessary to drive the scan driver GP. For example, the scan input voltage may be a gate drive voltage.

[0335] In an embodiment, the electronic device may include: a memory for storing commands; a processor for executing operations according to commands and generating control commands; and a display panel for displaying images according to the control commands. The display panel may include: a substrate; a first semiconductor layer disposed on the substrate; a first gate layer disposed on the first semiconductor layer; a second gate layer disposed on the first gate layer; a first interlayer insulating layer disposed on the second gate layer; a second semiconductor layer disposed on the first interlayer insulating layer and comprising an oxide semiconductor; a third gate layer disposed on the second semiconductor layer; and a first conductive layer disposed on the third gate layer and electrically connected to the second gate layer. The first interlayer insulating layer may include a recessed groove pattern, and a portion of the second semiconductor layer may be disposed within the groove pattern.

[0336] In one embodiment, the first interlayer insulating layer may include: a first inorganic protective layer including an opening that exposes a portion of the upper surface of the second gate layer upwards; and a second inorganic protective layer disposed above the first inorganic protective layer and covering the inner surface of the opening and a portion of the upper surface of the second gate layer.

[0337] also, Figures 1 to 39 The description can be applied to Figure 40 The display panel 10.

[0338] As described above, according to the embodiments, a display device including a thin-film transistor with enhanced electrical characteristics, a method for manufacturing the display device, and an electronic device can be realized. However, the scope of this disclosure is not limited to these effects.

[0339] It should be understood that the embodiments described herein should be interpreted in a descriptive sense only and are not intended to be limiting. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more non-limiting embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A display device, comprising: Substrate; A first semiconductor layer is disposed on the substrate; A first gate layer is disposed on top of the first semiconductor layer; A second gate layer is disposed on top of the first gate layer; A first interlayer insulating layer is disposed above the second gate layer, the first interlayer insulating layer including a groove pattern having a downwardly recessed shape; A second semiconductor layer is disposed on the first interlayer insulating layer, and the second semiconductor layer includes an oxide semiconductor. A third gate layer is disposed on top of the second semiconductor layer; as well as A first conductive layer is disposed above the third gate layer, and the first conductive layer is electrically connected to the second gate layer. The second semiconductor layer is disposed in the groove pattern.

2. The display device of claim 1, wherein, The first interlayer insulation layer includes: A first inorganic protective layer includes an opening that exposes a portion of the upper surface of the second gate layer; and A second inorganic protective layer is disposed above the first inorganic protective layer, and the second inorganic protective layer covers the inner surface of the opening and a portion of the upper surface of the second gate layer. The thickness of the second inorganic protective layer is less than the thickness of the first inorganic protective layer.

3. The display device of claim 2, wherein, The first inorganic protective layer includes: A first-1 inorganic protective layer, having a first-1 thickness, is directly disposed on the second gate layer; and The first-second inorganic protective layer has a thickness greater than that of the first-first inorganic protective layer, and the first-second inorganic protective layer is directly disposed on the first-first inorganic protective layer. The first-1 inorganic protective layer comprises silicon nitride, and the first-2 inorganic protective layer comprises silicon oxide.

4. The display device of claim 3, wherein, The second inorganic protective layer comprises a monolayer containing silicon nitride, and The thickness of the second inorganic protective layer is greater than the thickness of the first-1 layer.

5. The display device of claim 2, wherein, The second inorganic protective layer includes: A second-1 inorganic protective layer, having a second-1 thickness, is directly disposed on the first inorganic protective layer; and The second-2 inorganic protective layer has a thickness greater than or equal to that of the second-1 inorganic protective layer, and the second-2 inorganic protective layer is directly disposed on the second-1 inorganic protective layer. The second-1 inorganic protective layer comprises silicon nitride, and the second-2 inorganic protective layer comprises silicon oxide.

6. The display device of claim 5, wherein, The thickness of the second-second layer is less than the thickness of the first inorganic protective layer.

7. The display device of claim 1, wherein, The thickness of the portion of the first interlayer insulating layer disposed between the second gate layer and the second semiconductor layer is less than the thickness of the remaining portion of the first interlayer insulating layer.

8. The display device of claim 1, wherein, The first conductive layer is electrically connected to the second semiconductor layer.

9. The display device according to claim 1, further comprising pixel electrodes disposed on the first conductive layer. wherein The second semiconductor layer is electrically connected to the pixel electrode.

10. A display device, comprising: Substrate; A first semiconductor layer is disposed on the substrate; A first gate layer is disposed on top of the first semiconductor layer; A second gate layer is disposed on top of the first gate layer; A first interlayer insulating layer is disposed above the second gate layer, the first interlayer insulating layer including a groove pattern having a downwardly recessed shape; A second semiconductor layer is disposed on the first interlayer insulating layer, and the second semiconductor layer includes an oxide semiconductor. A third gate layer is disposed on top of the second semiconductor layer, and the third gate layer is electrically connected to the second gate layer; as well as A first conductive layer is disposed above the third gate layer, and the first conductive layer is electrically connected to the second semiconductor layer. The second semiconductor layer is disposed in the groove pattern.

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