Method and system for testing SIC MOS channel width and overlay offset

Abstract

The invention relates to the technical field of semiconductor processing, in particular to a test method and system for testing the width and overlay offset of an SIC MOS channel, and the method comprises the following steps: providing a test structure which is integrated on a semiconductor wafer and comprises a reference MOS tube, a first test MOS tube, a second test MOS tube, a third test MOS tube and a fourth test MOS tube, the edge of one side of the grid electrode and the edge of the corresponding side of the preset channel region form a bevel edge with a first preset angle; measurement is directly carried out on the MOS tube structure, the result can truly reflect the overlay condition of a device, tiny horizontal offset is amplified into measurable channel width change through the bevel edge design, the precision is high, only electrical testing is needed, wafer damage is not needed, the method can be used for online monitoring and finished product sampling inspection, and the method is suitable for large-scale popularization and application. The method can be completed by using conventional electrical test equipment, expensive optical measurement equipment is not needed, the monitoring cost is greatly reduced, the offset can be measured, and the offset direction can be judged through differential signals of the two test structures.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, and in particular to a test method and system for testing the channel width and overlay offset of SiC MOS. Background Technology

[0002] Silicon carbide (SiC), as an outstanding representative of third-generation semiconductor materials, has become a core material in the field of high-voltage and high-power electronic devices due to its superior properties such as wide bandgap, high critical breakdown electric field, and high thermal conductivity. As a key component, the performance and manufacturing precision of SiC MOSFETs directly determine the reliability and efficiency of the final power system.

[0003] In the multilayer photolithography process of SiC MOSFETs, the alignment accuracy between the gate pattern and the source / drain regions, i.e., the overlay accuracy, is a decisive factor affecting device performance. Even a tiny overlay offset will directly lead to changes in the channel geometry of the MOSFET, which in turn will cause threshold voltage drift, increased on-resistance, and even source-drain punch-through, seriously damaging the chip yield and long-term reliability.

[0004] Currently, the industry mainly relies on optical overlay accuracy measurement equipment for monitoring. This method assesses the process level by measuring specially made optical marks on the wafer, but it has significant limitations: First, optical marks differ from the actual device structure in size and process environment, and the measurement results are indirect data that cannot fully reflect the actual overlay situation of the device; second, such equipment is expensive and the measurement process is time-consuming, making it difficult to meet the needs of high-frequency online monitoring; finally, it can only provide geometric offsets and cannot directly quantify the actual impact of the offset on the electrical performance of the device.

[0005] Therefore, how to develop a testing technology that can directly, quickly, and at low cost monitor the actual overlay offset of MOSFETs and intuitively reflect its electrical consequences has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing technologies, such as the differences between optical markings and actual device structures in terms of size and process environment, resulting in indirect measurement results that cannot fully reflect the actual overlay situation of the device. Therefore, this invention proposes a test method and system for testing the channel width and overlay offset of SiC MOS.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: The present invention provides a test method for testing the channel width and overlay offset of SiC MOS, comprising the following steps: A test structure is provided, the test structure being integrated on a semiconductor wafer, the test structure comprising: A reference MOSFET, whose gate is designed to completely cover a predetermined channel region; A first test MOS transistor, wherein one edge of its gate forms a bevel at a first preset angle with the corresponding edge of the predetermined channel region; A second test MOS transistor, wherein one edge of its gate forms a bevel at a second preset angle with the corresponding edge of the predetermined channel region; Under the same test conditions, the saturation drain current Id of the reference MOSFET was measured. 参考 The saturation drain current Id of the first test MOSFET 第一 and the saturation drain current Id of the second test MOSFET 第二 ; Based on the Id 参考 、Id 第一 and Id 第二 Based on the direct proportionality between the saturation current and the channel width of the MOSFET, the first actual effective channel width W of the first test MOSFET is calculated. 第一实际 and the second actual effective channel width W of the second test MOSFET 第二实际 ; W 第一实际 and W 第二实际 The overlay offset direction and offset amount of the test structure are determined by comparing them with their respective theoretical design widths.

[0008] Furthermore, the first actual effective channel width W of the first test MOS transistor is calculated respectively. 第一实际 and the second actual effective channel width W of the second test MOSFET 第二实际 Specifically, it includes: According to the formula: W 第一实际 =W 参考 (Id 第一 / Id 参考 ) W 第二实际 =W 参考 (Id 第二 / Id 参考 ); Calculate the first actual effective channel width and the second actual effective channel width, where W 参考 The design channel width of the reference MOS transistor.

[0009] Furthermore, both the first preset angle and the second preset angle are 45°; Wherein, the left edge of the gate of the first test MOS transistor forms a hypotenuse with a first preset angle with the left edge of the predetermined channel region; The right edge of the gate of the second test MOS transistor forms a bevel at a second preset angle with the right edge of the predetermined channel region.

[0010] Furthermore, the W 第一实际 and W 第二实际 The overlay offset direction and offset amount of the test structure are determined by comparing them with their respective theoretical design widths, including: W 第一实际 Its corresponding W 第一理论 By comparing the values, a first size difference is obtained; W 第二实际 Its corresponding W 第二理论 By comparing the values, a second size difference is obtained; Based on the first size difference and the second size difference, the direction and amount of the overlay offset are determined.

[0011] Furthermore, if the first size difference is positive and the second size difference is negative, it is determined to be an offset in the second direction; If the first size difference is negative and the second size difference is positive, it is determined to be an offset in the first direction; The offset is calculated based on at least one of the absolute values ​​of the first size difference and the second size difference, combined with the first preset angle or the second preset angle.

[0012] Furthermore, the reference MOSFET, the first test MOSFET, and the second test MOSFET are designed with the same channel length.

[0013] In a second aspect, the present invention provides a test system for testing the channel width and overlay offset of SiC MOS, the system comprising: A test structure, integrated on a semiconductor wafer, includes: A reference MOSFET, whose gate is designed to completely cover a predetermined channel region; A first test MOS transistor, wherein one edge of its gate forms a bevel at a first preset angle with the corresponding edge of the predetermined channel region; A second test MOS transistor, wherein one edge of its gate forms a bevel at a second preset angle with the corresponding edge of the predetermined channel region; The electrical measurement unit, under the same test conditions, measures the saturation drain current Id of the reference MOSFET. 参考 The saturation drain current Id of the first test MOSFET第一 and the saturation drain current Id of the second test MOSFET 第二 ; The calculation unit, based on the Id 参考 、Id 第一 and Id 第二 Based on the direct proportionality between the saturation current and the channel width of the MOSFET, the first actual effective channel width W of the first test MOSFET is calculated. 第一实际 and the second actual effective channel width W of the second test MOSFET 第二实际 ; The determining unit will determine the W. 第一实际 and W 第二实际 The overlay offset direction and offset amount of the test structure are determined by comparing them with their respective theoretical design widths.

[0014] Furthermore, the computing unit is specifically configured to: According to the formula: W 第一实际 =W 参考 (Id 第一 / Id 参考 ) W 第二实际 =W 参考 (Id 第二 / Id 参考 ); Calculate the first actual effective channel width and the second actual effective channel width, where W 参考 The design channel width of the reference MOS transistor.

[0015] Furthermore, the determining unit is specifically configured to perform the comparison operation as follows: W 第一实际 Its corresponding W 第一理论 By comparing the values, a first size difference is obtained; W 第二实际 Its corresponding W 第二理论 By comparing the values, a second size difference is obtained; Based on the first size difference and the second size difference, the direction and amount of the overlay offset are determined.

[0016] Furthermore, if the first size difference is positive and the second size difference is negative, it is determined to be an offset in the second direction; If the first size difference is negative and the second size difference is positive, it is determined to be an offset in the first direction; The offset is calculated based on at least one of the absolute values ​​of the first size difference and the second size difference, combined with the first preset angle or the second preset angle.

[0017] The present invention proposes a test method and system for testing the channel width and overlay offset of SiC MOS transistors. The advantages of this invention are as follows: the present invention measures directly on the MOS transistor structure, and the results can truly reflect the overlay situation of the device. Through the bevel design, the tiny horizontal offset is amplified into a measurable channel width change, which is highly accurate. It only requires electrical testing and does not damage the wafer. It can be used for online monitoring and finished product sampling inspection.

[0018] Secondly, it can be completed using conventional electrical testing equipment, without the need for expensive optical measurement equipment, which greatly reduces monitoring costs. It can not only measure the offset, but also determine the offset direction through the differential signal of the two test structures, and directly correlate it with the changes in the electrical performance of the device. Attached Figure Description

[0019] Figure 1 This is a flowchart of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the test structure according to Embodiment 1 of the present invention; Figure 3 This is a state diagram of the test structure during offset in Embodiment 1 of the present invention; Figure 4 This is a system block diagram of Embodiment 2 of the present invention.

[0020] In the figure: 100, test structure; 101, reference MOSFET; 101a, reference gate; 102, first test MOSFET; 102a, first test gate; 103, second test MOSFET; 103a, second test gate; A, channel region. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0022] Example 1

[0023] Reference Figures 1 to 3 As one embodiment of the present invention, a test method for testing the channel width and overlay offset of SiC MOS is disclosed, the method comprising the following steps: S10. A test structure is provided, said test structure being integrated on a semiconductor wafer. (See [link]). Figure 2This illustration shows a top view of a test structure 100 for testing the channel width and overlay offset of SiC MOS in one embodiment of the present invention. The test structure 100 is fabricated in the dicing region of a semiconductor wafer to facilitate electrical testing without affecting the integrity and area of ​​the product chip on the wafer. The test structure includes: A reference MOSFET 101 has a gate designed to completely cover a predetermined channel region. The reference gate 101a of the reference MOSFET 101 is designed as a standard rectangle. Ideally, without offset, the reference gate 101a is designed to completely cover the predetermined channel region A below it, and its designed channel width is W. 参考 The designed channel length is L; A first test MOS transistor 102 has a gate edge that forms a bevel at a first preset angle with the corresponding edge of the predetermined channel region A. In this embodiment, specifically, the left edge of the first test gate 102a forms a 45° bevel with the left edge of the predetermined channel region. Its designed channel length is also L, and the theoretically designed channel width is W. 第一理论 ; A second test MOSFET 103 has a gate edge that forms a bevel at a second preset angle with the corresponding edge of the predetermined channel region A. In this embodiment, specifically, the right edge of the second test gate 103a forms a 45° bevel with the right edge of the predetermined channel region. Its designed channel length is also L, and the theoretically designed channel width is W. 第二理论 ; That is to say, in this invention, both the first preset angle and the second preset angle are 45°; Wherein, the left edge of the gate of the first test MOS transistor forms a hypotenuse with a first preset angle with the left edge of the predetermined channel region; The right edge of the gate of the second test MOS transistor and the right edge of the predetermined channel region form a hypotenuse at a second preset angle; In this embodiment, for ease of explanation, we define the rightward offset of the gate relative to the channel region as the "first direction" and the leftward offset as the "second direction". It should be noted that the reference MOS transistor, the first test MOS transistor, and the second test MOS transistor described in this invention have the same design channel length.

[0024] Please see Figure 2 The testing method in this embodiment includes the following steps: S20. Under the same test conditions, measure the saturation drain current Id of the reference MOSFET. 参考 The saturation drain current Id of the first test MOSFET 第一 and the saturation drain current Id of the second test MOSFET第二 ; Specifically, the identical test conditions refer to the same voltage Vg applied to the gate and the same voltage Vd applied to the drain of all three transistors, for example, Vg = 20V and Vd = 1V, to ensure the comparability of the measurement results. Furthermore, the saturation drain current Id of the reference MOS transistor mentioned in this invention... 参考 The principle is mainly based on the following formula; Id=0.5 μ Cox (W / L) (Vg-Vth)² Where Id is the saturated drain current, μ is the carrier mobility, Cox is the gate oxide capacitance per unit area, W is the effective channel width, L is the channel length, Vg is the gate voltage, and Vth is the threshold voltage.

[0025] Similarly, the first test is the saturation drain current Id of the MOSFET. 第一 and the saturation drain current Id of the second test MOSFET 第二 The above formula can also be used for calculation.

[0026] In the test, the same gate voltage Vg and drain voltage Vds were applied to the three MOS transistors to ensure that they operated in the saturation region. Since the three transistors were on the same wafer and the process conditions were the same, their μ, Cox, and Vth were considered to be basically the same. Therefore, the saturation current Id was proportional to the effective channel width W.

[0027] S30, Based on the Id 参考 、Id 第一 and Id 第二 Based on the direct proportionality between the saturation current and the channel width of the MOSFET, the first actual effective channel width W of the first test MOSFET is calculated. 第一实际 and the second actual effective channel width W of the second test MOSFET 第二实际 ; In this embodiment, the first actual effective channel width W of the first test MOS transistor is calculated respectively. 第一实际 and the second actual effective channel width W of the second test MOSFET 第二实际 Specifically, it includes: According to the formula: W 第一实际 =W 参考 (Id 第一 / Id 参考 ) W 第二实际 =W 参考 (Id第二 / Id 参考 ); Calculate the first actual effective channel width and the second actual effective channel width, where W 参考 is the designed channel width of the reference MOS transistor; S40. Compare the W 第一实际 and W 第二实际 with their respective theoretical design widths to determine the overlay shift direction and offset of the test structure.

[0028] In this embodiment, the comparison of the W 第一实际 and W 第二实际 with their respective theoretical design widths to determine the overlay shift direction and offset of the test structure includes: Compare the W 第一实际 with its corresponding W 第一理论 to obtain a first size difference ΔW1; Compare the W 第二实际 with its corresponding W 第二理论 to obtain a second size difference ΔW2; Based on the first size difference and the second size difference, determine the direction and offset of the overlay shift.

[0029] Specifically, if the first size difference is positive and the second size difference is negative, it is determined to be shifted in the second direction, that is, shifted to the left; If the first size difference is negative and the second size difference is positive, it is determined to be shifted in the first direction, that is, shifted to the right; where the offset is calculated based on at least one of the absolute value of the first size difference and the absolute value of the second size difference, in combination with the first preset angle or the second preset angle.

[0030] Specifically, during actual measurement, the following situations are included; Situation 1: Shifted in the first direction (to the right) When the gate is shifted to the right, for the first test MOS transistor 102 with a bevel on the left side, the area where the gate covers the channel decreases, so W first actual < W first theoretical, and ΔW1 is negative.

[0031] At the same time, for the second test MOS transistor 103 with a bevel on the right side, the area where the gate covers the channel increases, so W second actual > W second theoretical, and ΔW2 is positive.

[0032] Determination logic: When ΔW1 is negative and ΔW2 is positive, the determination unit determines that it is shifted in the first direction (to the right).

[0033] Scenario 2: Shifting in the second direction (to the left)

[0034] Conversely, when the gate is shifted to the left, the channel width of the first test MOSFET 102 increases, and ΔW1 is positive; while the channel width of the second test MOSFET 103 decreases, and ΔW2 is negative.

[0035] Judgment logic: When ΔW1 is positive and ΔW2 is negative, the cell is determined to be offset in the second direction (to the left).

[0036] Case 3: No offset

[0037] If the absolute values ​​of ΔW1 and ΔW2 are both within the preset error range (e.g., close to zero), it indicates that the overlay accuracy is good and there is no significant offset.

[0038] Finally, the offset is calculated based on the absolute value of the size difference and the preset angle: Taking a rightward offset as an example, the horizontal offset m can be calculated based on the data of the second test MOSFET: m = |ΔW2| / tan(45°) = |ΔW2|.

[0039] Similarly, the data from the first tested MOSFET can be used to calculate: m = |ΔW1| / tan(45°) = |ΔW1|.

[0040] In practical applications, in order to improve accuracy and eliminate errors caused by process fluctuations, the average of the two can be taken, i.e., m=(|ΔW1|+|ΔW2|) / 2.

[0041] For further explanation, please refer to the following example; Its parameters are as follows: For example, refer to the design channel width W of a MOSFET. 参考 =5μm, designed channel length L=1μm.

[0042] The first test MOSFET (left bevel): Its gate has a 45° bevel on the left side. Under ideal, unoffset conditions, its theoretically designed channel width Wfirst theoretical = 2μm. The second test MOSFET (right bevel): its gate has a 45° bevel on the right side. Under ideal, unoffset conditions, its theoretically designed channel width Wsecond theoretical = 3μm.

[0043] Theoretical state without offset: Under ideal conditions of no offset, the channel widths of all three MOSFETs should be equal to their design values. In this case, based on the direct proportionality between current and channel width, the ratio of our measured saturation drain currents should be equal to the ratio of their channel widths. Id 第一 / Id 参考 =W第一理论 / W参考 =2 / 5=0.4 Id 第二 / Id 参考 =W 第二理论 / W 参考 =3 / 5=0.6 Measurement and calculation when offset occurs: Please see Figure 3 Now, suppose that a rightward offset occurred during the manufacturing process, with an offset amount of x (unit: μm).

[0044] For the first test MOSFET on the left slant side, shifting it to the right will reduce its effective channel width, and its new actual channel width is Wfirst actual = (2-x)μm.

[0045] For the second test MOSFET on the right-hand slant, shifting it to the right will increase its effective channel width. Its new actual channel width is Wsecond actual = (3 + x) μm.

[0046] At this point, we measure the new current ratio using the electrical measurement unit and calculate it according to the formula: For the first test MOSFET: W 第一实际 =W 参考 (Id 第一 / Id 参考 ) After substituting, we get: 2-x=5 (Id 第一 / Id 参考 ) For the second test MOSFET: W 第二实际 =W 参考 (Id 第二 / Id 参考 ) After substituting, we get: 3+x=5 (Id 第二 / Id 参考 ) Determine the offset direction and calculate the offset amount: Step 1: Calculate the actual channel width Assuming the actual measured current ratio is Id 第一 / Id 参考 =0.3, Id 第二 / Id 参考 =0.7.

[0047] W第一实际 =5 0.3 = 1.5 μm

[0048] W 第二实际 =5 0.7 = 3.5 μm

[0049] Step 2: Calculate the dimensional difference

[0050] ΔW1=W 第一实际 -W 第一理论 =1.5-2=-0.5μm

[0051] ΔW2=W 第二实际 -W 第二理论 =3.5-3=+0.5μm

[0052] Step 3: Determine the offset direction

[0053] Based on the above judgment logic: Since ΔW1 is negative and ΔW2 is positive, the system determines that the offset is in the first direction (to the right).

[0054] Step 4: Calculate the offset

[0055] The offset is calculated based on the absolute value of the size difference and the preset angle.

[0056] Since the hypotenuse angle we designed is 45°, tan(45°) = 1.

[0057] Therefore, the offset x = |ΔW1| = |ΔW2| = 0.5 μm.

[0058] verify: Substituting the calculated offset x = 0.5 μm into our initial geometric equation: W 第一实际 =2-x=2-0.5=1.5μm (consistent with the calculated result) W 第二实际 =3+x=3+0.5=3.5μm (consistent with the calculated result) Thus, the system not only accurately determined the direction of the offset but also precisely quantified the amount of offset. This example fully demonstrates the feasibility and accuracy of the technical solution of this invention.

[0059] In a preferred embodiment of the invention, the angle is set to 45°. In other alternative embodiments, the angle can be selected within the range of 30° to 60°. It should be noted that the value of this angle is positively correlated with the sensitivity to drift; that is, the larger the angle, the more sensitive it is to drift.

[0060] Furthermore, the design parameters for the initial MOS gate lengths x1 and x2 are preferably 2 to 4 times the channel length.

[0061] Example 2

[0062] The second aspect of this invention provides a test system for testing the channel width and overlay offset of SiC MOS, the test system comprising: A test structure, integrated on a semiconductor wafer, includes: A reference MOSFET 101 has a gate designed to completely cover a predetermined channel region. The gate 101a of the reference MOSFET 101 is designed as a standard rectangle. Ideally, without offset, the gate 101a is designed to completely cover the underlying predetermined channel region A, and its designed channel width is W. 参考 The designed channel length is L; A first test MOS transistor has a gate edge that forms a bevel at a first preset angle with the corresponding edge of the predetermined channel region A. In this embodiment, specifically, the left edge of the gate 102a forms a 45° bevel with the left edge of the predetermined channel region. Its designed channel length is also L, and the theoretically designed channel width is W. 第一理论 ; A second test MOSFET has a gate edge that forms a bevel at a second preset angle with the corresponding edge of the predetermined channel region A. In this embodiment, specifically, the right edge of the gate 103a forms a 45° bevel with the right edge of the predetermined channel region. Its designed channel length is also L, and the theoretically designed channel width is W. 第二理论 ; That is to say, in this invention, both the first preset angle and the second preset angle are 45°; Wherein, the left edge of the gate of the first test MOS transistor forms a hypotenuse with a first preset angle with the left edge of the predetermined channel region; The right edge of the gate of the second test MOS transistor and the right edge of the predetermined channel region form a hypotenuse at a second preset angle; In this embodiment, for ease of explanation, we define the rightward offset of the gate relative to the channel region as the "first direction" and the leftward offset as the "second direction". It should be noted that the reference MOS transistor, the first test MOS transistor, and the second test MOS transistor described in this invention have the same design channel length.

[0063] The electrical measurement unit, under the same test conditions, measures the saturation drain current Id of the reference MOSFET. 参考 The saturation drain current Id of the first test MOSFET 第一and the saturation drain current Id of the second test MOSFET 第二 ; Specifically, the identical test conditions refer to the same voltage Vg applied to the gate and the same voltage Vd applied to the drain of all three transistors, for example, Vg = 20V and Vd = 1V, to ensure the comparability of the measurement results. Furthermore, the saturation drain current Id of the reference MOS transistor mentioned in this invention... 参考 The principle is mainly based on the following formula; Id=0.5 μ Cox (W / L) (Vg-Vth)² Where Id is the saturated drain current, μ is the carrier mobility, Cox is the gate oxide capacitance per unit area, W is the effective channel width, L is the channel length, Vg is the gate voltage, and Vth is the threshold voltage.

[0064] Similarly, the first test is the saturation drain current Id of the MOSFET. 第一 and the saturation drain current Id of the second test MOSFET 第二 The above formula can also be used for calculation.

[0065] In the test, the same gate voltage Vg and drain voltage Vds were applied to the three MOS transistors to ensure that they operated in the saturation region. Since the three transistors were on the same wafer and the process conditions were the same, their μ, Cox, and Vth were considered to be basically the same. Therefore, the saturation current Id was proportional to the effective channel width W.

[0066] The calculation unit, based on the Id 参考 、Id 第一 and Id 第二 Based on the direct proportionality between the saturation current and the channel width of the MOSFET, the first actual effective channel width W of the first test MOSFET is calculated. 第一实际 and the second actual effective channel width W of the second test MOSFET 第二实际 ; In this embodiment, the first actual effective channel width W of the first test MOS transistor is calculated respectively. 第一实际 and the second actual effective channel width W of the second test MOSFET 第二实际 Specifically, it includes: According to the formula: W 第一实际 =W 参考 (Id 第一 / Id 参考 ) W 第二实际 =W 参考 (Id 第二 / Id 参考 ); Calculate the first actual effective channel width and the second actual effective channel width, where W 参考 is the designed channel width of the reference MOS transistor.

[0067] Determine a unit to compare the W 第一实际 and W 第二实际 with their respective corresponding theoretical design widths to determine the overlay shift direction and shift amount of the test structure.

[0068] Wherein, when the determining unit performs the comparison operation, it is specifically configured to; Compare the W 第一实际 with its corresponding W 第一理论 to obtain a first size difference ΔW1; Compare the W 第二实际 with its corresponding W 第二理论 to obtain a second size difference ΔW2; Based on the first size difference and the second size difference, determine the direction and shift amount of the overlay shift.

[0069] Specifically, if the first size difference is positive and the second size difference is negative, it is determined that the shift is in the first direction; if the first size difference is negative and the second size difference is positive, it is determined that the shift is in the second direction; Wherein, the shift amount is calculated based on at least one of the absolute value of the first size difference and the absolute value of the second size difference, in combination with the first preset angle or the second preset angle.

[0070] Specifically, during actual measurement, the following situations are included; Situation 1: Shift in the first direction (rightward) When the gate shifts rightward, for the first test MOS transistor 102 with a bevel on the left side, the area where the gate covers the channel decreases, so W first actual < W first theoretical, and ΔW1 is negative.

[0071] At the same time, for the second test MOS transistor 103 with a bevel on the right side, the area where the gate covers the channel increases, so W second actual > W second theoretical, and ΔW2 is positive.

[0072] Determination logic: When ΔW1 is negative and ΔW2 is positive, the determining unit determines that the shift is in the first direction (rightward).

[0073] Situation 2: Shift in the second direction (leftward)

[0074] Conversely, when the gate is shifted to the left, the channel width of the first test MOSFET 102 increases, and ΔW1 is positive; while the channel width of the second test MOSFET 103 decreases, and ΔW2 is negative.

[0075] Judgment logic: When ΔW1 is positive and ΔW2 is negative, the cell is determined to be offset in the second direction (to the left).

[0076] Case 3: No offset

[0077] If the absolute values ​​of ΔW1 and ΔW2 are both within the preset error range (e.g., close to zero), it indicates that the overlay accuracy is good and there is no significant offset.

[0078] Finally, the offset is calculated based on the absolute value of the size difference and the preset angle.

[0079] In summary, this invention performs measurements directly on the MOS transistor structure, and the results accurately reflect the overlay status of the device. Through the beveled design, minute horizontal offsets are amplified into measurable channel width changes, resulting in high precision. It only requires electrical testing and does not damage the wafer, making it suitable for online monitoring and finished product sampling inspection.

[0080] Secondly, it can be completed using conventional electrical testing equipment, without the need for expensive optical measurement equipment, which greatly reduces monitoring costs. It can not only measure the offset, but also determine the offset direction through the differential signal of the two test structures, and directly correlate it with the changes in the electrical performance of the device.

[0081] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A test method for testing the channel width and overlay offset of SiC MOS, characterized in that, Includes the following steps: A test structure is provided, the test structure being integrated on a semiconductor wafer, the test structure comprising: A reference MOSFET, whose gate is designed to completely cover a predetermined channel region; A first test MOS transistor, wherein one edge of its gate forms a bevel at a first preset angle with the corresponding edge of the predetermined channel region; A second test MOS transistor, wherein one edge of its gate forms a bevel at a second preset angle with the corresponding edge of the predetermined channel region; Under the same test conditions, the saturation drain current Id of the reference MOSFET was measured. 参考 The saturation drain current Id of the first test MOSFET 第一 and the saturation drain current Id of the second test MOSFET 第二 ; Based on the Id 参考 、Id 第一 and Id 第二 Based on the direct proportionality between the saturation current and the channel width of the MOSFET, the first actual effective channel width W of the first test MOSFET is calculated. 第一实际 and the second actual effective channel width W of the second test MOSFET 第二实际 ; W 第一实际 and W 第二实际 The overlay offset direction and offset amount of the test structure are determined by comparing it with the corresponding theoretical design width.

2. The test method for testing the channel width and overlay offset of SiC MOS according to claim 1, characterized in that: The first actual effective channel width W of the first test MOS transistor is calculated respectively. 第一实际 and the second actual effective channel width W of the second test MOSFET 第二实际 Specifically, it includes: According to the formula: W 第一实际 =W 参考 (Id 第一 / Id 参考 ) W 第二实际 =W 参考 (Id 第二 / Id 参考 ); Calculate the first actual effective channel width and the second actual effective channel width, where W 参考 The design channel width of the reference MOS transistor.

3. The test method for testing the channel width and overlay offset of SiC MOS according to claim 1, characterized in that: Both the first preset angle and the second preset angle are 45°; Wherein, the left edge of the gate of the first test MOS transistor forms a hypotenuse with a first preset angle with the left edge of the predetermined channel region; The right edge of the gate of the second test MOS transistor forms a bevel at a second preset angle with the right edge of the predetermined channel region.

4. The test method for testing the channel width and overlay offset of SiC MOS according to claim 1, characterized in that: The W 第一实际 and W 第二实际 The overlay offset direction and offset amount of the test structure are determined by comparing them with their respective theoretical design widths, including: W 第一实际 Its corresponding W 第一理论 By comparing the values, a first size difference is obtained; W 第二实际 Its corresponding W 第二理论 By comparing the values, a second size difference is obtained; Based on the first size difference and the second size difference, the direction and amount of the overlay offset are determined.

5. The test method for testing the channel width and overlay offset of SiC MOS according to claim 4, characterized in that: If the first size difference is positive and the second size difference is negative, it is determined to be an offset in the second direction; If the first size difference is negative and the second size difference is positive, it is determined to be an offset in the first direction; The offset is calculated based on at least one of the absolute values ​​of the first size difference and the second size difference, combined with the first preset angle or the second preset angle.

6. The test method for testing the channel width and overlay offset of SiC MOS according to claim 1, characterized in that: The reference MOSFET, the first test MOSFET, and the second test MOSFET are designed with the same channel length.

7. A test system for testing the channel width and overlay offset of SiC MOS, characterized in that, include; A test structure, integrated on a semiconductor wafer, includes: A reference MOSFET, whose gate is designed to completely cover a predetermined channel region; A first test MOS transistor, wherein one edge of its gate forms a bevel at a first preset angle with the corresponding edge of the predetermined channel region; A second test MOS transistor, wherein one edge of its gate forms a bevel at a second preset angle with the corresponding edge of the predetermined channel region; The electrical measurement unit, under the same test conditions, measures the saturation drain current Id of the reference MOSFET. 参考 The saturation drain current Id of the first test MOSFET 第一 and the saturation drain current Id of the second test MOSFET 第二 ; The calculation unit, based on the Id 参考 、Id 第一 and Id 第二 Based on the direct proportionality between the saturation current and the channel width of the MOSFET, the first actual effective channel width W of the first test MOSFET is calculated. 第一实际 and the second actual effective channel width W of the second test MOSFET 第二实际 ; The determining unit will determine the W 第一实际 and W 第二实际 The overlay offset direction and offset amount of the test structure are determined by comparing it with the corresponding theoretical design width.

8. The test system for testing the channel width and overlay offset of SiC MOS according to claim 7, characterized in that: The computing unit is specifically configured for: According to the formula: W 第一实际 =W 参考 (Id 第一 / Id 参考 ) W 第二实际 =W 参考 (Id 第二 / Id 参考 ); Calculate the first actual effective channel width and the second actual effective channel width, where W 参考 The design channel width of the reference MOS transistor.

9. The test system for testing the channel width and overlay offset of SiC MOS according to claim 7, characterized in that: The determining unit is specifically configured to perform the comparison operation as follows: W 第一实际 Its corresponding W 第一理论 By comparing the values, a first size difference is obtained; W 第二实际 Its corresponding W 第二理论 By comparing the values, a second size difference is obtained; Based on the first size difference and the second size difference, the direction and amount of the overlay offset are determined.

10. The test system for testing the channel width and overlay offset of SiC MOS according to claim 9, characterized in that: If the first size difference is positive and the second size difference is negative, it is determined to be an offset in the second direction; If the first size difference is negative and the second size difference is positive, it is determined to be an offset in the first direction; The offset is calculated based on at least one of the absolute values ​​of the first size difference and the second size difference, combined with the first preset angle or the second preset angle.

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