Semiconductor package

Abstract

A semiconductor package may include: a package substrate including a plurality of upper pads; a semiconductor chip on the package substrate and electrically connected to at least one of the plurality of upper pads; a sealing layer covering at least a portion of the package substrate and the semiconductor chip; and a capacitor structure including a first conductive layer covering a portion of the sealing layer, a second conductive layer covering one side surface of the package substrate and another portion of the sealing layer, and a dielectric layer between the first conductive layer and the second conductive layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor packaging. Background Technology

[0002] With the reduction in weight and / or improvement in performance of electronic devices, there is a growing demand for packages that can protect semiconductor chips from electromagnetic interference (EMI). Research and development of semiconductor packages with EMI shielding structures on the outside of the semiconductor package are underway. Summary of the Invention

[0003] Some exemplary embodiments of this disclosure provide semiconductor packages with improved electrical storage capacity.

[0004] Some exemplary embodiments of this disclosure provide semiconductor packages with improved shielding properties.

[0005] According to an example embodiment, a semiconductor package may include: a package substrate including a plurality of upper pads; a semiconductor chip on the package substrate and electrically connected to at least one of the plurality of upper pads; a sealing layer covering at least a portion of the package substrate and the semiconductor chip; and a capacitor structure including a first conductive layer, a second conductive layer and a dielectric layer between the first conductive layer and the second conductive layer, the first conductive layer covering a portion of the sealing layer, and the second conductive layer covering one side surface of the package substrate and another portion of the sealing layer.

[0006] According to an example embodiment, a semiconductor package may include: a package substrate including a plurality of upper pads; a semiconductor chip on the package substrate and electrically connected to at least one of the plurality of upper pads; a sealing layer configured to cover at least a portion of the package substrate and the semiconductor chip, the sealing layer including a connection structure electrically connected to a second conductive layer; and a capacitor structure including a first conductive layer, a second conductive layer, and a dielectric layer between the first conductive layer and the second conductive layer, the first conductive layer covering a portion of the sealing layer, and the second conductive layer covering one side surface of the package substrate and another portion of the sealing layer.

[0007] According to an example embodiment, a semiconductor package may include a package body, a capacitor structure, a conductive structure, a substrate, and a first connection bump, a second connection bump, and a third connection bump. The package body includes a package substrate containing a first wiring layer and a second wiring layer, a semiconductor chip on the package substrate and electrically connected to the first wiring layer, and a sealing layer configured to cover at least a portion of the package substrate and the semiconductor chip. The capacitor structure includes a first conductive layer contacting one side surface of the package body, a second conductive layer contacting the other side surface and the top surface of the package body, and a dielectric layer between the first and second conductive layers. The conductive structure is in contact with the second conductive layer of the capacitor structure. The substrate includes a first connection wiring line electrically connected to the first wiring layer, a second connection wiring line electrically connected to the second wiring layer, and a third connection wiring line electrically connected to the conductive structure below the package body and the conductive structure. The first connection bump, the second connection bump, and the third connection bump are below the substrate and electrically connected to the first connection wiring line, the second connection wiring line, and the third connection wiring line, respectively.

[0008] According to an example embodiment, a method of manufacturing a semiconductor package may include: providing a first package assembly by attaching a plurality of semiconductor chips to a surface of a package substrate and surrounding and sealing the plurality of semiconductor chips on the surface of the package substrate using an sealing layer; cutting the first package assembly in a direction perpendicular to the package substrate to provide a plurality of package bodies; placing one of the plurality of package bodies on a support substrate; forming a first conductive layer, the first conductive layer including a first portion covering a first side surface of the one package body and one or more second portions extending horizontally from the first portion and above an upper surface of the one package body; forming a second conductive layer, the second conductive layer including a third portion covering another side surface of the one package body, a fourth portion extending horizontally from the third portion and contacting the upper surface of the one package body, and a fifth portion extending horizontally from the third portion and above the fourth portion, the one or more second portions of the first conductive layer being between the fourth and fifth portions of the second conductive layer; and forming a dielectric layer between the first conductive layer and the second conductive layer.

[0009] Providing a first packaging assembly may further include providing a connection structure on one surface of the packaging substrate and connected to a corresponding upper pad among a plurality of upper pads exposed from the one surface of the packaging substrate, the plurality of upper pads being connected to a plurality of connection bumps on another surface of the packaging substrate via connection wiring in the packaging substrate. Attached Figure Description

[0010] Figure 1This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0011] Figure 2 Viewed from above Figure 1 A top view of a semiconductor package.

[0012] Figure 3 This is a cross-sectional view showing a semiconductor package according to an example embodiment.

[0013] Figure 4 This is a cross-sectional view showing a semiconductor package according to an example embodiment.

[0014] Figure 5 This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0015] Figures 6 to 8 This is a cross-sectional view schematically illustrating a process for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0016] Figure 9 This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0017] Figure 10 Viewed from above Figure 9 A top view of a semiconductor package.

[0018] Figure 11 This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0019] Figure 12 Viewed from above Figure 11 A top view of a semiconductor package.

[0020] Figures 13 to 15 This is an illustrative representation of the manufacture of the disclosed invention. Figure 11 A cross-sectional view of the semiconductor packaging process.

[0021] Figure 16 This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0022] Figure 17 Viewed from above Figure 16 A top view of a semiconductor package. Detailed Implementation

[0023] In the following detailed description, only certain exemplary embodiments of the inventive concept are shown and described, and are for illustrative purposes only. Those skilled in the art will recognize that the described embodiments can be modified in various different ways without departing from the spirit or scope of the inventive concept.

[0024] Therefore, the accompanying drawings and descriptions are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements. In the flowcharts described with reference to the drawings, the order of operations can be changed, operations can be combined, operations can be divided, and some operations can be omitted.

[0025] Furthermore, the singular forms “one” and “the” are intended to include the plural forms as well, unless the context explicitly indicates otherwise (e.g., unless an explicit expression such as “single” is used). Terms including ordinal numbers (such as first and second) are used to describe various constituent elements, but the constituent elements are not limited by the terms. Terms are used only to distinguish one constituent element from the others.

[0026] Furthermore, the dimensions and thicknesses of each component shown in the accompanying drawings are merely examples to illustrate exemplary embodiments, and the inventive concept is not necessarily limited thereto. In the drawings, various layers and regions are shown with arbitrary thicknesses to illustrate the corresponding layers and regions. Additionally, for ease of explanation, the thicknesses of some layers and regions may be exaggerated in the drawings.

[0027] Furthermore, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on said other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Additionally, when an element is referred to as being "on" a reference portion, the element is located above or below the reference portion, and does not necessarily mean that the element is located "above" or "on" in a direction opposite to gravity.

[0028] As used herein, expressions such as “one of,” “one or more,” “any one,” and “at least one of” modify the entire list of elements when they follow the list, without modifying any individual element. Therefore, for example, “at least one of A, B, or C” and “at least one of A, B, and C” both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0029] Although the terms “identical,” “equal,” or “consistent” are used in the description of the example implementations, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that the element or value is identical to the other element within a desired range of manufacturing or operational tolerances (e.g., ±10%).

[0030] When the terms “about,” “substantially,” or “approximately” are used in conjunction with numerical values ​​in this specification, it is intended that the associated numerical values ​​include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical values. Furthermore, when the terms “about,” “substantially,” or “approximately” are used in conjunction with geometry, it is intended that the geometry is not required to be precise, but rather that the tolerance of the shape is within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified to “about” or “substantially,” it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value or shape.

[0031] Furthermore, throughout the instruction manual, when referred to as "on a plane," it means when the target portion is viewed from above; when referred to as "on a cross section," it means when the cross section obtained by vertically cutting the target portion is viewed from the side.

[0032] The present disclosure will be described in more detail below with examples. These examples are for illustrative purposes only, and the scope of protection of the present disclosure is not limited by the examples.

[0033] Figure 1 This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0034] Reference Figure 1 The semiconductor package 1000 according to the example embodiment may include a substrate 10, a conductive structure 20a, an adhesive layer 30, a package body 500, and a capacitor structure 600. The package body 500 may include a package substrate 100, a semiconductor chip 200, an adhesive film 300, and a sealing layer 400.

[0035] Semiconductor chip 200 may include memory chips or memory devices that store or output data based on addresses, commands, and data received from package substrate 100. For example, semiconductor chip 200 may include logic chips (or "logic circuits") (such as central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), application processors (APs), digital signal processors (DSPs), cryptographic processors, microprocessors, microcontrollers, analog-to-digital converters, or application-specific integrated circuits (ASICs)) or memory chips (or "memory circuits") (including volatile memory such as dynamic RAM (DRAM) or static RAM (SRAM) or non-volatile memory such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or flash memory).

[0036] Semiconductor chip 200 can be attached to packaging substrate 100 via adhesive film 300. Adhesive film 300 can be disposed between semiconductor chip 200 and packaging substrate 100. Adhesive film 300 can physically connect semiconductor chip 200 and packaging substrate 100. Adhesive film 300 can electrically connect semiconductor chip 200 and packaging substrate 100. Adhesive film 300 may include silicone-based adhesive or acrylamide-based adhesive.

[0037] Semiconductor chip 200 may include adhesive film 210. Semiconductor chip 200 may be attached to the upper surface of package substrate 100 using adhesive film 210. Adhesive film 210 of semiconductor chip may be bonded to adhesive film 300. Adhesive film 210 may include silicone-based adhesive or acrylamide-based adhesive.

[0038] Semiconductor chip 200 may include conductive pads 220. Semiconductor chip 200 may be electrically connected to package substrate 100 via conductive leads W connected to conductive pads 220 and upper pads 101 of package substrate 100.

[0039] The packaging substrate 100 may include an insulating layer 110, an upper pad 101, lower pads 102 and 103, and multiple wiring layers 120 and 130. The packaging substrate 100 can transmit data signals received from a semiconductor chip 200 disposed on the packaging substrate 100 to the outside. The packaging substrate 100 can also transmit data signals and power signals received from the outside to the semiconductor chip 200.

[0040] Insulating layer 110 may comprise an insulating resin. The insulating resin may include thermosetting resins and thermoplastic resins. Thermosetting resins may include epoxy resins. Thermoplastic resins may include polyimide. The insulating resin may include an insulating resin or thermoplastic resin comprising inorganic fillers impregnated in the resin. For example, the insulating resin may include prepreg, Ajinomoto laminate (ABF), FR-4, and bismaleimide-triazine (BT). Insulating layer 110 may comprise a photosensitive resin. The photosensitive resin may include a photosensitive imaging dielectric (PID) material. Insulating layer 110 may comprise multiple insulating layers (not shown in the figures) stacked in a vertical direction.

[0041] The upper pad 101 may be disposed on the upper part of the package substrate 100. The upper surface of the upper pad 101 may be exposed from the upper surface of the package substrate 100. The upper pad 101 may contain at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). The lower pads 102 and 103 may be disposed on the lower part of the package substrate 100. The lower pads 102 and 103 may contain at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). The materials of the upper pad 101 and the lower pads 102 and 103 are not limited to the materials described above.

[0042] Multiple wiring layers 120 and 130 may be connected to lower pads 102 and 103 at the lower end of the package substrate 100. The multiple wiring layers 120 and 130 may include a first wiring layer 120 electrically connected to the semiconductor chip 200 and a second wiring layer 130 electrically connected to the capacitor structure 600.

[0043] The first wiring layer 120 can be connected to the upper pad 101 exposed from the upper end of the package substrate 100. The first wiring layer 120 can be electrically connected to the semiconductor chip 200 through the upper pad 101 of the package substrate 100. The second wiring layer 130 can contact the first conductive layer 610 and the second conductive layer 630. The second wiring layer 130 can be exposed from two facing side surfaces of the package substrate 100. The second wiring layer 130 can be electrically connected to the first conductive layer 610 and the second conductive layer 630. The first wiring layer 120 and the second wiring layer 130 can be electrically insulated from each other.

[0044] Multiple wiring layers 120 and 130 can be formed as a multilayer structure including wiring patterns and pathways, the wiring patterns and pathways including aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W) or combinations thereof.

[0045] The sealing layer 400 may cover at least some portions of the semiconductor chip 200 and the packaging substrate 100 on the packaging substrate 100. The area of ​​the horizontal region of the sealing layer 400 may be equal to the area of ​​the horizontal region of the packaging substrate 100. "Horizontal region" may refer to the region viewed from above. For example, the side surface 400T of the sealing layer 400 may be coplanar with the side surface 100T of the packaging substrate 100. The sealing layer 400 may be formed of or include an insulating material such as epoxy molding compound (EMC). The insulating material forming the sealing layer 400 is not limited thereto.

[0046] The capacitor structure 600 may include a first conductive layer 610, a dielectric layer 620, and a second conductive layer 630 stacked on the side and top surfaces of the package body 500.

[0047] The second conductive layer 630 can contact and cover the encapsulation substrate 100 and the sealing material 400 with one side surface of the sealing layer 400 and one side surface of the encapsulation substrate 100. The second conductive layer 630 may include a second-first branch region 631, a second-second branch region 632, and a second covering region 633. The second-first branch region 631 and the second-second branch region 632 can branch from the second covering region 633. The second-first branch region 631 and the second-second branch region 632 can extend in the direction of a first axis (X). The length of the second-first branch region 631 in the direction of the first axis (X) can be equal to the length of the second-second branch region 632 in the direction of the first axis (X). The area of ​​the horizontal region of the second-first branch region 631 can be equal to the area of ​​the horizontal region of the second-second branch region 632. The second-first branch region 631 and the second-second branch region 632 can be spaced apart from each other.

[0048] The second-first branch region 631 can be disposed on the upper end of the sealing layer 400. The second-first branch region 631 can contact the sealing layer 400. The second-second branch region 632 can be positioned relative to the second-first branch region 631 in the third axis (Z) direction.

[0049] The second cover region 633 may contact one side surface of the package body 500. The second cover region 633 may include or define an upper region of the capacitor structure 600. This upper region may be positioned relative to the second-second branch region 632 in a third axis (Z) direction. The second cover region 633 may overlap with the package body 500, and the dielectric layer 620 is interposed between the other side surface and the upper surface of the package body 500 and the second cover region 633.

[0050] The first conductive layer 610 can contact another side surface of the sealing layer 400 and another side surface of the encapsulation substrate 100, and cover the encapsulation substrate 100 and the sealing layer 400. The first conductive layer 610 may include a first-1 branch region 611, a first-2 branch region 612, and a first covering region 613. The first-1 branch region 611 and the first-2 branch region 612 can branch from the first covering region 613. The first-1 branch region 611 and the first-2 branch region 612 can extend in the direction of a first axis (X). The length of the first-1 branch region 611 in the direction of the first axis (X) can be equal to the length of the first-2 branch region 612 in the direction of the first axis (X). The area of ​​the horizontal region of the first-1 branch region 611 can be equal to the area of ​​the horizontal region of the first-2 branch region 612. The first-1 branch region 611 and the first-2 branch region 612 can be spaced apart from each other.

[0051] The first-1 branch region 611 can be set between the second-1 branch region 631 and the second-2 branch region 632. The first-1 branch region 611 can be set to be separated from the second-1 branch region 631 and the second-2 branch region 632.

[0052] The first-second branch region 612 can be located between the second-second branch region 632 and the second coverage region 633. The first-second branch region 612 can also be spaced apart from the second-second branch region 632 and the second coverage region 633.

[0053] The first coverage area 613 may contact the other side surface of the package body 500. The first coverage area 613 may be configured to be spaced apart from the second coverage area 633.

[0054] A dielectric layer 620 may be disposed on the other side surface and the top surface of the package body 500. The dielectric layer 620 may be disposed between the first conductive layer 610 and the second conductive layer 630 on the top end of the package body 500 and the other side surface of the package body 500. On the other side surface of the package body 500, the dielectric layer 620 may be disposed between the second covering region 633 and the first covering region 613. On the top surface of the package body 500, the dielectric layer 620 may be disposed in a first region located between the second covering region 633 and the first-second branch region 612. The dielectric layer 620 may be disposed in a second region located between the first-second branch region 612 and the second-second branch region 632. The dielectric layer 620 may be disposed in a third region located between the second-second branch region 632 and the first-first branch region 611. The dielectric layer 620 may be disposed in a fourth region located between the first-first branch region 611 and the second-first branch region 631.

[0055] The first conductive layer 610 and the second conductive layer 630 may include a metallic material, including tin (Sn), iron (Fe), nickel (Ni), or alloys thereof. The dielectric layer 620 may include a dielectric material, such as zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric layer 620 may contain a dielectric material having a dielectric constant equal to or greater than about 20 (e.g., about 20 to about 30 or about 20 to about 25). The conductivity of the first conductive layer 610 may be equal to the conductivity of the second conductive layer 630. The conductivity of the first conductive layer 610 and the second conductive layer 630 may be higher than the conductivity of the dielectric layer 620.

[0056] Each of the first conductive layer 610, the dielectric layer 620, and the second conductive layer 630 may have a constant thickness. The sum of the thicknesses of the plurality of layers 610, 620, and 630 stacked on the upper surface of the package body 500 may be greater than the sum of the thicknesses of the plurality of layers 610, 620, and 630 stacked on the other side surface of the package body 500.

[0057] The dielectric layer 620 disposed on the upper surface of the package body 500 may have a thickness greater than at least one of the first conductive layer 610 and the second conductive layer 630 disposed on the upper surface of the package body 500. For example, the dielectric layer 620 may have a thickness of about 5 μm or less, about 10 nm to about 5 μm, about 50 nm to about 2 μm, or about 100 nm to about 1 μm. Each of the first conductive layer 610 and the second conductive layer 630 may have a thickness of about 1 μm or less, about 100 nm to about 1 μm, or about 200 nm to about 0.5 μm.

[0058] The first conductive layer 610 may contact the second wiring layer 130 of the package substrate 100 on the other side surface of the package substrate 100. The second wiring layer 130 may provide an electrical connection path to the first conductive layer 610. The first conductive layer 610 may receive a first voltage V1 through the second wiring layer 130.

[0059] The second conductive layer 630 may contact the second wiring layer 130 of the package substrate 100 on one side surface of the package substrate 100. The second wiring layer 130 may provide an electrical connection path to the second conductive layer 630. The second conductive layer 630 may receive a first voltage V1 through the second wiring layer 130.

[0060] The conductive structure 20a can provide an electrical connection path to the second conductive layer 630. The second conductive layer 630 can receive a second voltage V2 through the conductive structure 20a. The first voltage V1 applied to the first conductive layer 610 can be greater than the second voltage V2 applied to the second conductive layer 630. The first voltage V1 can be Vdd (e.g., supply voltage), and the second voltage V2 can be Vss (e.g., ground voltage).

[0061] The capacitor structure 600 can be a multilayer capacitor structure in which multiple capacitors are connected in parallel. A first capacitor can be formed by a second branch region 631 to which a second voltage is applied, a first branch region 611 to which a first voltage is applied, and a dielectric layer 620 disposed between the second branch region 631 and the first branch region 611. A second capacitor can be formed by a first branch region 611 to which a first voltage is applied, a second branch region 632 to which a second voltage is applied, and a dielectric layer 620 disposed between the first branch region 611 and the second branch region 632. A third capacitor can be formed by a second branch region 632 to which a second voltage is applied, a first branch region 612 to which a first voltage is applied, and a dielectric layer 620 disposed between the second branch region 632 and the first branch region 612. The first-second branch region 612 to which a first voltage is applied, the second coverage region 633 to which a second voltage is applied, and the dielectric layer 620 disposed between the first-second branch region 612 and the second coverage region 633 can constitute a fourth capacitor. The capacitor structure 600 can be a multilayer capacitor structure in which the first capacitor to the fourth capacitor are connected in parallel.

[0062] Multilayer capacitor structures can store more charge than single-layer capacitor structures. The capacitance of a multilayer capacitor structure can be calculated by summing the capacitances of each capacitor connected in parallel. As the number of capacitors connected in parallel increases, the capacitance of a multilayer capacitor structure can increase. Because multilayer capacitor structures store more charge than single-layer capacitor structures, their electrical storage capacity can be increased.

[0063] Multilayer capacitor structures can improve the shielding effect for protecting internal circuitry from external electromagnetic interference (EMI). Multilayer capacitor structures can also block externally generated high-frequency noise. The structure of multiple conductive layers 610 and 630 and a dielectric layer 620 connected in parallel can distribute electrical paths. In this structure, the dielectric layer 620 can act as a filter to suppress noise.

[0064] A substrate 10 may be disposed on the lower surface of the package body 500. The substrate 10 may include rear surface pads 11, front surface pads 12, 13 and 14, and connection wiring lines 16.

[0065] The substrate 10 may be a substrate comprising circuitry configured by fixing electronic components such as resistors, capacitors and / or integrated circuits to the surface and connecting these components via wiring lines, but the inventive concept is not limited thereto.

[0066] The back surface pad 11 can be disposed on the lower surface of the substrate 10. The back surface pad 11 may include at least one material selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0067] Front surface pads 12, 13, and 14 may be disposed on the front surface of the substrate 10. Front surface pads 12, 13, and 14 may comprise at least one material selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). The materials constituting the rear surface pads 11 and the front surface pads 12, 13, and 14 are not limited thereto.

[0068] At least some of the front surface pads 12, 13 and 14 may be disposed on the same line as at least some of the lower pads 102 and 103 of the package substrate 100. At least some of the front surface pads (e.g., front surface pad 14) may be connection pads disposed below the conductive structure 20a and providing an electrical connection path therethrough.

[0069] The substrate 10 may include multiple connection wiring lines 16 electrically connecting each of the lower pads 102 and 103 of the package substrate 100 and each of the conductive structure 20a to the rear surface pad 11. The multiple connection wiring lines 16 may include a first connection wiring line 16a connecting the rear surface pad 11 and the first lower pad 102 in contact with the first wiring layer 120. The multiple connection wiring lines 16 may include a second connection wiring line 16b connecting the rear surface pad 11 and the second lower pad 103 in contact with the second wiring layer 130. The multiple connection wiring lines 16 may include a third connection wiring line 16c connecting the rear surface pad 11 and the conductive structure 20a.

[0070] The semiconductor chip 200 can be electrically connected to the substrate 10 via the first connection wiring line 16a and the first wiring layer 120. The first conductive layer 610 can be electrically connected to the substrate 10 via the second connection wiring line 16b and the second wiring layer 130. The second conductive layer 630 can be electrically connected to the substrate 10 via the third connection wiring line 16c and the conductive structure 20a.

[0071] Multiple connecting wiring lines 16 can be formed into a multi-layer structure including wiring patterns and pathways, wherein the wiring patterns and pathways include aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or combinations thereof.

[0072] A plurality of bump structures 105 may be disposed between the package body 500 and the substrate 10. The plurality of bump structures 105 may electrically connect at least some of the lower pads 102 and 103 of the package substrate 100 to corresponding front surface pads 12, 13 and 14 of the substrate 10. The plurality of bump structures 105 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb) and / or alloys thereof. The alloys may include Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn, and Sn-Bi-Zn. The materials constituting the plurality of bump structures 105 are not limited thereto.

[0073] On the lower surface of the substrate 10, a plurality of connecting bumps 15, including a first connecting bump, a second connecting bump, and a third connecting bump, may be additionally provided. The plurality of connecting bumps 15 may be configured to contact the rear surface pads 11 provided on the lower surface of the substrate 10, respectively. The plurality of connecting bumps 15 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof. The alloys may include Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn, and Sn-Bi-Zn. The materials constituting the plurality of connecting bumps 15 are not limited thereto.

[0074] A conductive structure 20a may be disposed on the substrate 10. The conductive structure 20a may contact the outer surface of the second conductive layer 630. The second conductive layer 630 may contact the conductive structure 20a to provide an electrical connection path. The conductive structure 20a may include a conductive material, such as iron (Fe), nickel (Ni), tin (Sn), or molybdenum (Mo).

[0075] An adhesive layer 30 may be disposed between the conductive structure 20a and the substrate 10. The adhesive layer 30 may include an adhesive polymer material, such as a polymer adhesive resin, an epoxy resin, a phenolic epoxy curing agent, a curing catalyst, or a silane coupling agent. The adhesive layer 30 may be in the form of a paste or a film.

[0076] The adhesive layer 30 can be configured to surround the front surface pad 14 (e.g., a connection pad) disposed between the conductive structure 20a and the substrate 10. The thickness of the front surface pad 14 (e.g., a connection pad) and the adhesive layer 30 can be equal.

[0077] Figure 2Viewed from above Figure 1 A top view of a semiconductor package.

[0078] Reference Figure 2 Packaging substrate ( Figure 1 The area of ​​the horizontal region 100S in the first axis (X) and second axis (Y) directions (reference numeral "100") can be equal to the area of ​​the sealing layer ( Figure 1 The reference numeral "400" indicates the area of ​​the horizontal region 400S in the first axis (X) direction and the second axis (Y) direction. The side surface 100T of the packaging substrate 100 may be coplanar with the side surface 400T of the sealing layer 400 in the third axis (Z) direction.

[0079] The horizontal region 100S of the packaging substrate 100 can be included in the substrate ( Figure 1 In the horizontal region 10S of the attached figure (reference numeral "10"). Semiconductor chip ( Figure 1 The horizontal region 200S (reference numeral "200") can be included in the horizontal region 100S of the packaging substrate 100. The horizontal region 100S of the packaging substrate 100 can be surrounded by the horizontal region 610S of the first conductive layer and the horizontal region 630S of the second conductive layer. The first edge 1011 and the second edge 1012 in the horizontal region 100S of the packaging substrate 100 can be surrounded by the portion of the horizontal region 630S of the second conductive layer that is arranged in the second axis (Y) direction and extends in the first axis (X) direction. The third edge 1013 in the horizontal region 100S can be surrounded by the portion of the horizontal region 630S of the second conductive layer that extends in the second axis (Y) direction. The fourth edge 1014 in the horizontal region 100S can be surrounded by the portion of the horizontal region 610S of the first conductive layer that extends in the second axis (Y) direction.

[0080] The horizontal region 610S of the first conductive layer can be disposed between the horizontal region 620S of the dielectric layer and the horizontal region 100S of the packaging substrate 100. The horizontal region 620S of the dielectric layer can be positioned relative to the horizontal region 610S of the first conductive layer in the first axis (X) direction.

[0081] The horizontal region 620S of the dielectric layer can be disposed between the horizontal region 630S of the second conductive layer and the horizontal region 610S of the first conductive layer. The horizontal region 630S of the second conductive layer can be positioned relative to the horizontal region 620S of the dielectric layer in the first axis (X) direction.

[0082] The horizontal region 630S of the second conductive layer can be disposed between the region 200a of the conductive structure 20 and the horizontal region 620S of the dielectric layer. The region 200a of the conductive structure 20 can be positioned relative to the horizontal region 630S of the second conductive layer in the first axis (X) direction.

[0083] The horizontal region 610S of the first conductive layer, the horizontal region 620S of the dielectric layer, the horizontal region 630S of the second conductive layer, and the region 200a of the conductive structure can be included in the horizontal region 10S of the substrate 10.

[0084] Figure 3 This is a cross-sectional view showing a semiconductor package according to an example embodiment.

[0085] Reference Figure 3 Semiconductor package 2000 can have the same characteristics as the reference. Figure 1 and Figure 2 The features described are the same or similar, except that the semiconductor chip 200 disposed on the packaging substrate 100 is a chip in which multiple semiconductor chips 2000a, 2000b and 2000c are stacked in sequence.

[0086] The package body 500 may include a package substrate 100, semiconductor chips 200 wherein a plurality of semiconductor chips 2000a, 2000b and 2000c are stacked in sequence, an adhesive film 300, and a sealing layer 400. Each of the plurality of semiconductor chips 2000a, 2000b and 2000c may include an adhesive film 210, conductive leads W and conductive pads 220.

[0087] The plurality of semiconductor chips 2000a, 2000b, and 2000c may include memory chips or memory devices that store or output data based on addresses, commands, and data received from the package substrate 100. Each of the plurality of semiconductor chips 2000a, 2000b, and 2000c may include logic circuitry (including CPU, GPU, FPGA, AP, DSP, encryption processor, microprocessor, microcontroller, analog-to-digital converter, or ASIC) or memory circuitry (including volatile memory containing DRAM or SRAM, or non-volatile memory containing PRAM, MRAM, RRAM, or flash memory), etc.

[0088] Semiconductor chip 2000a can be attached to the upper surface of package substrate 100 using adhesive film 210. Semiconductor chip 2000b can be attached to the upper surface of semiconductor chip 2000a using adhesive film 210. Semiconductor chip 2000c can be attached to the upper surface of semiconductor chip 2000b using adhesive film 210.

[0089] Semiconductor chip 2000a can be electrically connected to package substrate 100 via conductive leads W connecting conductive pad 220 and upper pad 101 of package substrate 100. Semiconductor chip 2000b can be electrically connected to package substrate 100 via conductive leads W connecting conductive pad 220 and upper pad 101 of package substrate 100. Semiconductor chip 2000c can be electrically connected to package substrate 100 via conductive leads W connecting conductive pad 220 and upper pad 101 of package substrate 100.

[0090] The packaging substrate 100 can transmit data signals received from semiconductor chips 200, in which a plurality of semiconductor chips 2000a, 2000b, and 2000c are stacked sequentially, to the outside. The packaging substrate can transmit data signals and power signals received from the outside to semiconductor chips 200, in which a plurality of semiconductor chips 2000a, 2000b, and 2000c are stacked sequentially.

[0091] Figure 4 This is a cross-sectional view showing a semiconductor package according to an example embodiment.

[0092] Reference Figure 4 Semiconductor package 3000 can have the same characteristics as the reference. Figures 1 to 3 Features described are the same or similar, except that they are set on the packaging substrate ( Figure 1 The semiconductor chip (100) in the attached figure (in the figure) Figure 1 The reference numeral "200" in the attached figures indicates a flip-chip configuration. For example, the semiconductor chip 200 can be mounted on the packaging substrate 100 using an adhesive film 300.

[0093] The adhesive film 300 may surround the bump structures 204 disposed between the package substrate 100 and the semiconductor chip 200. The adhesive film 300 may be an underfill layer for securing the semiconductor chip 200 to the package substrate 100. The underfill layer may contain an insulating material. The underfill layer may be formed using a copper finishing (CUF) process.

[0094] Figure 5 This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0095] Reference Figure 5 The semiconductor package 1000A according to the example embodiment may have the same characteristics as the referenced package. Figures 1 to 3 The described features are the same or similar, except that they are conductive structures ( Figure 1A portion of the conductive structure 20b, which is disposed on the substrate 10 and in contact with the outer surface of the capacitor structure 600, is mounted in a recessed portion of the substrate 10, as indicated by reference numeral "20a".

[0096] The partially conductive structure 20b can be inserted into the insertion portion 21b disposed in the upper part of the substrate 10. The insertion portion 21b can be in the form of a socket. The partially conductive structure 20b can be electrically connected to one or more of the multiple connection wiring lines of the substrate 10.

[0097] Figures 6 to 8 This is a cross-sectional view schematically illustrating a process for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0098] Reference Figure 6 A "first packaging assembly" can be provided in an upward-facing position. The first packaging assembly may include a laterally extending packaging substrate 100. A plurality of semiconductor chips 200 may be laterally arranged and disposed, attached to one surface of the packaging substrate 100 by an adhesive film 300. A sealing layer 400 may be disposed on said one surface of the packaging substrate 100 surrounding the plurality of semiconductor chips 200. A plurality of bump structures 105 may be disposed on another surface of the packaging substrate 100.

[0099] Reference Figure 6 For the deposition process, a tape TP can be attached to surround a plurality of bump structures 105 connected to the other surface of the encapsulation substrate 100. The tape TP can comprise a UV-curable polymer. The tape TP can comprise a polyester-acrylate-resin-based material or an epoxy-acrylate-resin-based material. The tape TP can be formed to a desired (or optionally, predetermined) thickness d. T .

[0100] Reference Figure 7 The first packaging assembly can be cut using a cutter 40 via a sawing process. The cutter 40 may include laser technology such as a carbon dioxide laser, fiber laser, or ultraviolet laser. The packaging substrate 100 can be cut in a direction perpendicular to the other surface of the packaging substrate 100. Multiple packaging bodies 500 can be provided via the sawing process. A portion of the second wiring layer 130 of the packaging substrate 100 may be exposed from the side surface 100T of the packaging substrate 100.

[0101] Reference Figure 8 Multiple encapsulation bodies 500 can be picked up using a vacuum adsorption connector 50. Multiple encapsulation bodies 500 can be disposed on a support substrate 60. The support substrate 60 may contain an insulating polymer material such as polyimide and may be provided in the form of a film.

[0102] In multiple conductive layers used for shielding ( Figure 1 In the process of depositing reference numerals "610" and "630" on the side and top surfaces of the package body 500, a dielectric layer can be additionally deposited. Figure 1 The process described in the attached figure (reference numeral "620") involves depositing multiple conductive layers 610 and 630 for shielding on the side and top surfaces of the package body 500. This process creates electrical connections between portions of the conductive layers 610 and 630. The process of depositing multiple conductive layers 610 and 630 for shielding on the side and top surfaces of the package body 500 produces a semiconductor package using the dielectric layer 620 as part of a capacitor. Figure 1 (See the attached figure label "1000").

[0103] Figure 9 This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0104] Reference Figure 9 In semiconductor package 1000B, the area of ​​the horizontal region of package substrate 100 can be larger than the area of ​​the horizontal region of sealing layer 400. One surface and another surface of package substrate 100 can be surrounded by a second conductive layer 630. Package substrate 100 may include a third wiring layer 140. In addition, semiconductor package 1000B may have... Figure 1 The semiconductor package 1000 has the same or similar features.

[0105] The package substrate 100 may include a first wiring layer 120, a second wiring layer 130, and a third wiring layer 140. The first wiring layer 120 may be connected to a first upper pad 101a connected to a conductive lead W of the semiconductor chip 200. The second wiring layer 130 may be connected to a second upper pad 101b in contact with the first conductive layer 610. The second wiring layer 130 may be electrically connected to the first conductive layer 610. The third wiring layer 140 may be connected to a second conductive layer 630 on both the other surface of the package substrate 100. The second wiring layer 130 may be electrically connected to the second conductive layer 630. The plurality of wiring layers 120, 130, and 140 may be electrically insulated from each other.

[0106] The second wiring layer 130 can provide an electrical connection path to the first conductive layer 610. The first conductive layer 610 can receive a first voltage V1 through the second wiring layer 130. The third wiring layer 140 can provide an electrical connection path to the second conductive layer 630. The second conductive layer 630 can receive a second voltage V2 through the third wiring layer 140. The first voltage V1 applied to the first conductive layer 610 can be greater than the second voltage V2 applied to the second conductive layer 630. The first voltage V1 can be Vdd (e.g., supply voltage), and the second voltage V2 can be Vss (e.g., ground voltage).

[0107] Figure 10 Viewed from above Figure 9 A top view of a semiconductor package.

[0108] Reference Figure 10 The area of ​​the horizontal region 400S of the sealing layer 400 covering the semiconductor chip 200 can be smaller than the area of ​​the horizontal region 100S of the packaging substrate 100. The side surface 100T of the packaging substrate 100 can be positioned to protrude from the side surface 400T of the sealing layer 400 in the first axis (X) direction. For example, the side surface 100T of the packaging substrate 100 can be located outside the side surface 400T of the sealing layer 400. The side surface 100T of the packaging substrate 100 can be non-coplanar with the side surface 400T of the sealing layer 400 in the third axis (Z) direction.

[0109] The horizontal region 100S of the packaging substrate 100 can be included in the substrate ( Figure 1 The horizontal region 10S of the figure (reference numeral "10") is located in the sealing layer 400. The horizontal region 400S of the sealing layer 400 may be surrounded by the horizontal region 610S of the first conductive layer and the horizontal region 630S of the second conductive layer.

[0110] The first edge 1011 and the second edge 1012 in the horizontal region 400S of the sealing layer 400 can be surrounded by the portion of the horizontal region 630S of the second conductive layer that is arranged in the second axis (Y) direction and extends in the first axis (X) direction. The third edge 1013 in the horizontal region 400S can be surrounded by the portion of the horizontal region 630S of the second conductive layer that extends in the second axis (Y) direction. The fourth edge 1014 in the horizontal region 400S can be surrounded by the portion of the horizontal region 610S of the first conductive layer that extends in the second axis (Y) direction.

[0111] The horizontal region 610S of the first conductive layer can be disposed between the horizontal region 620S of the dielectric layer and the horizontal region 400S of the sealing layer 400. The horizontal region 620S of the dielectric layer can be positioned relative to the horizontal region 610S of the first conductive layer in the first axis (X) direction.

[0112] The horizontal region 620S of the dielectric layer can be disposed between the horizontal region 630S of the second conductive layer and the horizontal region 610S of the first conductive layer. The horizontal region 630S of the second conductive layer can be positioned relative to the horizontal region 620S of the dielectric layer in the first axis (X) direction.

[0113] The horizontal region 630S of the second conductive layer can be positioned relative to the horizontal region 610S of the first conductive layer and the horizontal region 620S of the dielectric layer in the second axis (Y) direction. The horizontal region 610S of the first conductive layer and the horizontal region 620S of the dielectric layer can be surrounded by the horizontal region 630S of the second conductive layer and the horizontal region 100S of the packaging substrate 100.

[0114] The horizontal region 610S of the first conductive layer, the horizontal region 620S of the dielectric layer, and the horizontal region 630S of the second conductive layer can be included in the horizontal region 10S of the substrate 10.

[0115] Figure 11 This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0116] Reference Figure 11 The semiconductor package 1000C may include a connection structure 70 within a sealing layer 400. The semiconductor package 1000C may include a fourth wiring layer 150. In addition to the configuration of the connection structure 70 and the fourth wiring layer 150, the semiconductor package 1000C may have... Figure 9 The semiconductor package 1000B has the same or similar features.

[0117] Inside the sealing layer 400, a connection structure 70 electrically connecting the second conductive layer 630 and the second upper pad 101b can be provided. The connection structure 70 may contain a conductive material. The connection structure 70 may include a metallic material, including tin (Sn), iron (Fe), nickel (Ni), or alloys thereof. The connection structure 70 may have a columnar structure. The connection structure 70 may be in the form of a lead. Below the connection structure 70, a lead ball may be formed. The lead body may be formed to extend from the lead ball. A lead ball connecting the lead body and the second upper pad 101b can be provided. The connection structure 70 may be configured to extend in a direction perpendicular to the upper surface of the package substrate 100 and be located inside the sealing layer 400.

[0118] The fourth wiring layer 150 can be connected to the second upper pad 101b exposed from the upper end of the package substrate 100. The fourth wiring layer 150 can be electrically connected to the connection structure 70 through the second upper pad 101b.

[0119] The second conductive layer 630 may cover the upper surface of the sealing layer 400. The fourth wiring layer 150 may provide an electrical connection path to the second conductive layer 630 via the second upper pad 101b and the connection structure 70. The second conductive layer 630 may receive a second voltage V2 via the fourth wiring layer 150.

[0120] The second conductive layer 630 may extend along one side surface and the other side surface of the package substrate 100. The second conductive layer 630 may be connected to the third wiring layer 140 of the package substrate 100 on said one side surface and said other side surface. The third wiring layer 140 may provide an electrical connection path to the second conductive layer 630. The second conductive layer 630 may receive a second voltage V2 through the third wiring layer 140.

[0121] The first conductive layer 610 may extend along one side surface of the sealing layer 400. The first conductive layer 610 may be connected to the second wiring layer 130 of the package substrate 100 on the upper surface of the package substrate 100. The second wiring layer 130 may provide an electrical connection path to the first conductive layer 610. The first conductive layer 610 may receive a first voltage V1 through the second wiring layer 130.

[0122] and Figure 11 Unlike the previous example, the first conductive layer 610 can extend along one side surface of the package substrate 100, and the second conductive layer 630 can extend along the other side surface of the package substrate 100. The first conductive layer 610 can be connected to the second wiring layer 130 of the package substrate 100 on said one side surface. The second wiring layer 130 can provide an electrical connection path to the first conductive layer 610. The first conductive layer 610 can receive a first voltage V1 through the second wiring layer 130. The second conductive layer 630 can be connected to the third wiring layer 140 of the package substrate 100 on said other side surface. The third wiring layer 140 can provide an electrical connection path to the second conductive layer 630. The second conductive layer 630 can receive a second voltage V2 through the third wiring layer 140.

[0123] The first voltage V1 applied to the first conductive layer 610 can be greater than the second voltage V2 applied to the second conductive layer 630. The first voltage V1 can be Vdd (e.g., supply voltage), and the second voltage V2 can be Vss (e.g., ground voltage).

[0124] Figure 12 Viewed from above Figure 11 A top view of a semiconductor package.

[0125] Reference Figure 12The area of ​​the horizontal region 400S of the sealing layer 400 covering the semiconductor chip 200 can be smaller than the area of ​​the horizontal region 100S of the packaging substrate 100. The side surface 100T of the packaging substrate 100 can be positioned to protrude from the side surface 400T of the sealing layer 400 in the first axis (X) direction. For example, the side surface 100T of the packaging substrate 100 can be located outside the side surface 400T of the sealing layer 400. The side surface 100T of the packaging substrate 100 can be non-coplanar with the side surface 400T of the sealing layer 400 in the third axis (Z) direction.

[0126] The horizontal region 100S of the packaging substrate 100 can be included in the substrate ( Figure 1 The horizontal region 10S of the figure (reference numeral "10") is located in the sealing layer 400. The horizontal region 400S of the sealing layer 400 may be surrounded by the horizontal region 610S of the first conductive layer and the horizontal region 630S of the second conductive layer.

[0127] The first edge 1011 and the second edge 1012 in the horizontal region 400S of the sealing layer 400 can be surrounded by the portions of the horizontal region 630S of the second conductive layer that are arranged in the second axis (Y) direction and extend in the first axis (X) direction. The third edge 1013 in the horizontal region 400S can be surrounded by the portions of the horizontal region 630S of the second conductive layer that extend in the second axis (Y) direction. The fourth edge 1014 in the horizontal region 400S can be surrounded by the portions of the horizontal region 610S of the first conductive layer that extend in the second axis (Y) direction.

[0128] The horizontal region 610S of the first conductive layer can be disposed between the horizontal region 630S of the second conductive layer and the horizontal region 400S of the sealing layer 400. The horizontal region 630S of the second conductive layer can be positioned relative to the horizontal region 610S of the first conductive layer in the first axis (X) direction.

[0129] The horizontal region 630S of the second conductive layer can be positioned relative to the horizontal region 610S of the first conductive layer in the second axis (Y) direction. The horizontal region 610S of the first conductive layer can be surrounded by the horizontal region 630S of the second conductive layer and the horizontal region 100S of the packaging substrate 100.

[0130] The horizontal region 610S of the first conductive layer and the horizontal region 630S of the second conductive layer can be included in the horizontal region 10S of the substrate 10.

[0131] Figures 13 to 15 This is a cross-sectional view schematically illustrating the process of manufacturing a semiconductor package 1000C according to an exemplary embodiment of the present disclosure.

[0132] Reference Figure 13A plurality of semiconductor chips 200 may be provided, which are attached to at least a portion of the laterally extending upper surface of the insulating layer 110 via an adhesive film 300. A connection structure 70 may be formed to connect to some of the upper pads 101a and 101b exposed from the upper surface of the package substrate 100. The connection structure 70 may be a columnar structure. The connection structure 70 may be formed to extend in a direction perpendicular to the upper surface of the package substrate 100. The connection structure 70 may also be formed in the form of a lead. A lead ball (not shown) may be formed below the connection structure 70 and on the second upper pad 101b. A lead body (not shown) may be formed to extend from the lead ball. In this case, the lead body may be formed to form an arbitrary angle (greater than 0° and less than 90°) with the upper surface of the package substrate 100.

[0133] Reference Figure 14 The sealing layer 400 can encapsulate the semiconductor chip 200 and the connection structure 70 on the packaging substrate 100, so as to surround the semiconductor chip 200 and the connection structure 70.

[0134] Reference Figure 15 The upper surface of the sealing layer 400 can be planarized to be coplanar with the upper surface of the connecting structure 70. As a planarization process, a chemical mechanical polishing (CMP) process can be performed.

[0135] In multiple conductive layers used for shielding ( Figure 1 In the process of depositing reference numerals "610" and "630" on the side and top surfaces of the package body 500, a dielectric layer can be additionally deposited. Figure 1 The process described in the attached figure (reference numeral "620") involves depositing multiple conductive layers 610 and 630 for shielding on the side and top surfaces of the package body 500. This process creates electrical connections between portions of the conductive layers 610 and 630. The process of depositing multiple conductive layers 610 and 630 for shielding on the side and top surfaces of the package body 500 produces a semiconductor package using the dielectric layer 620 as part of a capacitor. Figure 11 (See the attached figure label "1000C").

[0136] Figure 16 This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0137] Reference Figure 16 In the semiconductor package 1000D, the area of ​​the horizontal region of the package substrate 100 can be equal to the area of ​​the horizontal region of the sealing layer 400. One surface and the other surface of the package substrate 100 can be surrounded by a first conductive layer 610 and a second conductive layer 630, respectively. In addition, the semiconductor package 1000D can have... Figure 11The semiconductor package 1000C has the same or similar features.

[0138] The second conductive layer 630 can be configured to cover the upper surface of the sealing layer 400. The fourth wiring layer 150 can provide an electrical connection path to the second conductive layer 630 through the second upper pad 101b and the connection structure 70. The second conductive layer 630 can receive a second voltage V2 through the fourth wiring layer 150.

[0139] The second conductive layer 630 may extend along one surface of the package substrate 100. The second conductive layer 630 may be connected to the second wiring layer 130 of the package substrate 100. The second wiring layer 130 may provide an electrical connection path to the second conductive layer 630. The second conductive layer 630 may receive a second voltage V2 through the second wiring layer 130.

[0140] The first conductive layer 610 may extend along the other surface of the package substrate 100. The first conductive layer 610 may be connected to the second wiring layer 130 of the package substrate 100. The second wiring layer 130 may provide an electrical connection path to the first conductive layer 610. The first conductive layer 610 may receive a first voltage V1 through the second wiring layer 130.

[0141] The first voltage V1 applied to the first conductive layer 610 can be greater than the second voltage V2 applied to the second conductive layer 630. The first voltage V1 can be Vdd (e.g., supply voltage), and the second voltage V2 can be Vss (e.g., ground voltage).

[0142] Figure 17 This shows what you see from above. Figure 16 A top view of a semiconductor package.

[0143] Reference Figure 17 Packaging substrate ( Figure 1 The area of ​​the horizontal region 100S (reference numeral "100") in the first axis (X) and second axis (Y) directions can be equal to the area of ​​the sealing layer ( Figure 1 The area of ​​the horizontal region 400S in the first axis (X) direction and the second axis (Y) direction is indicated by the reference numeral "400" in the attached figure. The side surface 100T of the packaging substrate 100 may be coplanar with the side surface 400T of the sealing layer 400 in the third axis (Z) direction.

[0144] The horizontal region 100S of the packaging substrate 100 can be included in the substrate ( Figure 1The horizontal region 100S of the package substrate 100 (reference numeral "10") is surrounded by the horizontal region 610S of the first conductive layer and the horizontal region 630S of the second conductive layer. The first edge 1011 and the second edge 1012 of the horizontal region 100S of the package substrate 100 are respectively surrounded by the portions of the horizontal region 630S of the second conductive layer that are arranged in the second axis (Y) direction and extend in the first axis (X) direction. The third edge 1013 of the horizontal region 100S is surrounded by the portion of the horizontal region 630S of the second conductive layer that extends in the second axis (Y) direction. The fourth edge 1014 of the horizontal region 100S is surrounded by the portion of the horizontal region 610S of the first conductive layer that extends in the second axis (X) direction.

[0145] The horizontal region 610S of the first conductive layer can be disposed between the horizontal region 620S of the dielectric layer and the horizontal region 100S of the packaging substrate 100. The horizontal region 620S of the dielectric layer can be positioned relative to the horizontal region 610S of the first conductive layer in the first axis (X) direction.

[0146] The horizontal region 620S of the dielectric layer can be disposed between the horizontal region 630S of the second conductive layer and the horizontal region 610S of the first conductive layer. The horizontal region 630S of the second conductive layer can be positioned relative to the horizontal region 620S of the dielectric layer in the first axis (X) direction.

[0147] The horizontal region 610S of the first conductive layer, the horizontal region 620S of the dielectric layer, and the horizontal region 630S of the second conductive layer can be included in the horizontal region 10S of the substrate 10.

[0148] While the inventive concept has been described in conjunction with what are now considered to be practical exemplary embodiments, it will be understood that the inventive concept is not limited to the disclosed exemplary embodiments. Rather, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0149] This application claims priority and benefit to Korean Patent Application No. 10-2024-0138509, filed on October 11, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor package, comprising: The packaging substrate includes multiple upper pads; A semiconductor chip is on the packaging substrate and electrically connected to at least one of the plurality of upper pads; A sealing layer configured to cover at least a portion of the packaging substrate and the semiconductor chip; as well as A capacitor structure includes a first conductive layer, a second conductive layer, and a dielectric layer between the first conductive layer and the second conductive layer, wherein the first conductive layer is configured to cover a portion of the sealing layer, and the second conductive layer is configured to cover one side surface of the packaging substrate and another portion of the sealing layer.

2. The semiconductor package according to claim 1, further comprising: A conductive structure is in contact with the outer surface of the second conductive layer; The substrate is located below the encapsulation substrate and the conductive structure; Multiple connecting protrusions are located below the substrate. as well as Connect the wiring lines by connecting one of the plurality of connecting bumps to the conductive structure.

3. The semiconductor package according to claim 2, wherein The first conductive layer includes: The first covered area is in contact with one side surface of the sealing layer and the other side surface of the encapsulation substrate; The first branch region branches off from the first coverage region and is located on the upper part of the sealing layer; as well as The second branch region branches off from the first coverage area, and the second branch region is spaced apart from the first branch region and is located on the first branch region.

4. The semiconductor package according to claim 3, wherein The second conductive layer includes: A second covering area contacts the other side surface of the sealing layer and the one side surface of the encapsulation substrate, the second covering area defining the upper end of the capacitor structure; The third branch region branches off from the second coverage area and contacts the upper end of the sealing layer; as well as A fourth branch region branches off from the second coverage region, the fourth branch region being spaced apart from the third branch region and situated on the third branch region.

5. The semiconductor package according to claim 4, wherein The dielectric layer includes: The first region is located between the third branch region and the first branch region; The second region is located between the first branch region and the fourth branch region; The third region is located between the fourth branch region and the second branch region; as well as The fourth region is located between the second branch region and the second coverage region.

6. The semiconductor package according to claim 2, wherein The packaging substrate further includes: Multiple first wiring layers are connected to the multiple upper pads; as well as The second wiring layer is connected to the first conductive layer.

7. The semiconductor package according to claim 6, wherein The first conductive layer is further configured to receive a first voltage through the second wiring layer, and The second conductive layer is further configured to receive a second voltage lower than the first voltage through the conductive structure.

8. The semiconductor package according to claim 6, wherein The area of ​​the horizontal region of the packaging substrate is larger than the area of ​​the horizontal region of the sealing layer, and The packaging substrate further includes a third wiring layer connected to each of the one side surface and the other side surface of the packaging substrate.

9. The semiconductor package according to claim 8, wherein The first conductive layer is further configured to receive a first voltage through the second wiring layer, and The second conductive layer is further configured to receive a second voltage lower than the first voltage through the third wiring layer.

10. The semiconductor package of claim 6, wherein The packaging substrate further includes a third wiring layer connected to at least one of the plurality of upper pads. The sealing layer includes at least one connection structure electrically connected to the third wiring layer, and The second conductive layer is electrically connected to the at least one connection structure.

11. The semiconductor package of claim 10, wherein... The first conductive layer is further configured to receive a first voltage through the second wiring layer, and The second conductive layer is further configured to receive a second voltage lower than the first voltage through the third wiring layer and the connection structure.

12. The semiconductor package of claim 10, wherein... The area of ​​the horizontal region of the packaging substrate is larger than the area of ​​the horizontal region of the sealing layer, and The packaging substrate further includes a fourth wiring layer connected to each of the one side surface and the other side surface of the packaging substrate.

13. The semiconductor package of claim 12, wherein... The first conductive layer is further configured to receive a first voltage through the second wiring layer, and The second conductive layer is further configured to receive a second voltage lower than the first voltage through the fourth wiring layer.

14. The semiconductor package of claim 6, further comprising: An adhesive film that bonds the semiconductor chip to the upper surface of the packaging substrate.

15. The semiconductor package of claim 14, wherein The semiconductor package includes a plurality of bump structures between the package substrate and the semiconductor chip. The plurality of bump structures are electrically connected to the corresponding first wiring layers in the first wiring layer, and The adhesive film is configured to surround the plurality of bump structures and to fix the semiconductor chip onto the packaging substrate.

16. The semiconductor package of claim 6, wherein A portion of the conductive structure is inserted into a recessed portion of the substrate.

17. A semiconductor package, comprising: The packaging substrate includes multiple upper pads; A semiconductor chip is on the packaging substrate and electrically connected to at least one of the plurality of upper pads; A sealing layer configured to cover at least a portion of the packaging substrate and the semiconductor chip, the sealing layer including a connection structure electrically connected to a second conductive layer; as well as A capacitor structure includes a first conductive layer, a second conductive layer, and a dielectric layer between the first conductive layer and the second conductive layer, wherein the first conductive layer is configured to cover a portion of the sealing layer, and the second conductive layer is configured to cover one side surface of the packaging substrate and another portion of the sealing layer.

18. The semiconductor package of claim 17, wherein The packaging substrate includes: Multiple first wiring layers are connected to the multiple upper pads; The second wiring layer is connected to the first conductive layer; as well as The third wiring layer is connected to the connection structure.

19. The semiconductor package of claim 18, wherein The first conductive layer is further configured to receive a first voltage through the second wiring layer, and The second conductive layer is further configured to receive a second voltage lower than the first voltage through the connection structure and the third wiring layer.

20. A semiconductor package, comprising: The package body includes: The packaging substrate includes a first wiring layer and a second wiring layer. A semiconductor chip, on the packaging substrate and electrically connected to the first wiring layer, and A sealing layer configured to cover at least a portion of the packaging substrate and the semiconductor chip; Capacitor structure, including: The first conductive layer is in contact with one side surface of the package body. The second conductive layer contacts the other side surface and the top surface of the package body, and A dielectric layer is located between the first conductive layer and the second conductive layer; A conductive structure is in contact with the second conductive layer of the capacitor structure; The substrate includes: A first connection wiring line is located below the package body and the conductive structure and is electrically connected to the first wiring layer. The second connection cabling is electrically connected to the second cabling layer, and A third connecting wiring line is electrically connected to the conductive structure; and A first connecting bump, a second connecting bump, and a third connecting bump are located below the substrate and are electrically connected to the first connecting wiring line, the second connecting wiring line, and the third connecting wiring line, respectively.

Images