Power limiting in a processor-based system based on allocating power budgues for different subsystems according to

Abstract

Power limiting in a processor-based system based on allocating power budgets to different subsystems according to a plurality of time-based power limits is disclosed. A processor-based system has a plurality of power consumption subsystems (e.g., a non-processing unit (PU) subsystem and a PU subsystem) that require and consume power from a power source of the processor-based system. To limit the overall power consumption of a processor-based system within different time-based power limits, the processor-based system includes a power limiter circuit. The power limiter circuit is configured to manage a plurality of different time-based (e.g., time constant) power limits of the processor-based system, and is configured to allocate corresponding power limit budgets to constrain power consumption of different subsystems based on the plurality of time-based power limits. The power limiter circuit may be configured to constrain power consumption of the PU subsystem to within a total PU subsystem power limit predictor based on the plurality of time-based power limits.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 475,371, filed September 27, 2023, entitled “POWER LIMITING IN A PROCESSOR-BASED SYSTEM BASED ON ALLOCATING POWER BUDGETS FOR DIFFERENT SUB-SYSTEMBASED ON MULTIPLE TIME-BASED POWER LIMITS”, the entire contents of which are incorporated herein by reference. background

[0003] I. Technical Field

[0004] This disclosure relates to processor-based systems, such as system-on-a-chip (SoC), that include one or more processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), and / or a neural processing unit (NPU) and more specifically to power allocation of processing units in a processor-based system.

[0005] II. Background Technology

[0006] Typically, processor-based systems include a power management system that controls the supply of power to power rails, which in turn supply power to circuitry for its operation. Processor-based systems may also include multiple power rails, each with an individually configurable voltage level, allowing for the supply of different voltage levels within the system. Some circuitry may require lower voltage levels to operate than others. Furthermore, circuitry that can be powered off during idle periods (e.g., the processor) may need to be placed on a different power rail or power domain than other circuitry with the lowest voltage level (e.g., memory circuitry). Additionally, processor-based systems may include a frequency and voltage scaling system configured to dynamically change or scale the frequency and / or voltage level of a clock-driven circuit for operation. Higher frequencies allow the clock-driven circuitry to operate faster. However, higher voltage levels may be required to support operation at higher frequencies. Moreover, operation at higher frequencies and voltages leads to increased power consumption. Other devices in a processor-based system may not require performance scaling.

[0007] A System-on-a-Chip (SoC) can be provided in a processor-based system, where the SoC includes one or more processors and supporting circuitry, such as memory circuitry and power management circuitry. An SoC is a single semiconductor die that may include multiple processors and different types of processors to efficiently perform different types of operations (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and / or a Neural Processing Unit (NPU)). The SoC can be integrated into a processor-based device, which is a mobile device that uses a battery as its power source. When the processors in the SoC perform workloads at high performance levels, the power requirements of the processors and other supporting circuitry may exceed the available power from the battery in the processor-based system. In more complex SoCs that include multiple processors that may perform workloads concurrently, the need for even greater power demands may be exacerbated. The battery may have multiple time-based power limit specifications for both short-duration power limits / constraints (e.g., burst power limits on millisecond-level windows) and long-duration power limits / constraints (e.g., on second-level windows), which need to be managed in the processor-based device.

[0008] In addition, the processor and circuitry within the SoC generate heat due to energy losses from the powered operation of the circuitry. The SoC and / or its processor-based device may have thermal temperature limits for operation. These thermal limits may be based on circuit performance standards (e.g., the circuitry will have a thermal limit at which performance begins to degrade) to extend battery life and / or maintain the temperature within a “skin temperature limit.” For example, a processor-based device including an SoC may be a wearable device or other devices intended or designed to come into contact with a user’s skin (e.g., a laptop computer). Ambient temperature also affects the temperature of the processor-based device. Thermal temperature limits and / or skin temperature limits may also have multiple time-based power limit specifications for both shorter-duration and longer-duration power consumption limits / constraints. Summary of the Invention

[0009] The aspects disclosed herein include power constraints in processor-based systems based on allocating power budgets to different subsystems according to multiple time-based power limits. A processor-based system has multiple power-consuming subsystems, each containing circuitry that consumes power from the processor-based system's power supply based on its operational requirements. For example, a processor-based system may include a processing unit (PU) subsystem comprising one or more PUs, each of which requests and consumes power based on a workload being performed (which may vary over time). As an example, a PU subsystem having one or more PUs, along with non-PU devices (e.g., memory), may be included within a system-on-a-chip (SoC). A processor-based system may also have other non-PU power-consuming subsystems (such as memory) and power management circuitry that requires power to store data and provide read access to and persistently maintain such data, the power management circuitry being used to deliver power and control the temperature of the processor-based system. Processor-based systems may have power limits based on subsystem performance limits, thermal limits, and / or skin temperature limits, necessitating that the overall power consumption in the processor-based system be limited in a manner that optimizes the performance of the subsystems within the processor-based system. Furthermore, these power limits may have different time constants within which power consumption is limited, such as from the millisecond (ms) to the second (s) level. Therefore, it may be necessary to limit power consumption differently within different time constants or windows based on multiple time-based power limits specified for the processor-based system. Otherwise, for example, the power consumption of a processor-based system may remain within the desired limits over a longer duration but violate the power limits over a shorter duration, which could still negatively impact processor and / or battery performance.

[0010] In this regard, in the exemplary aspects disclosed herein, a processor-based system includes power limiter circuitry to limit the overall power consumption of the processor-based system within different time-based power limits, while attempting to still achieve optimized performance of the PU subsystem. The power limiter circuitry is configured to manage multiple different time-based (e.g., time constant) power limits for the processor-based system and is configured to allocate corresponding power limit budgets based on these multiple time-based power limits to constrain the power consumption of different subsystems. For example, the processor-based system may have multiple different time-based power limits for different time constants, such as burst power limits over shorter time durations (e.g., milliseconds) and average power consumption over longer time durations (e.g., seconds). In this regard, the power limiter circuitry is configured to compare the multiple time-based power limits assigned to the processor-based system with the current power consumption of multiple subsystems within the processor-based system to generate corresponding power limit budgets for constraining the power consumption of the subsystems.

[0011] In one example, time-based power limits that are compared with the current power consumption to generate corresponding power limit budgets are each converted to a common (e.g., the shortest) duration time window of the most time-constrained power limit. This allows the power limiter circuitry to compare each of the generated power limit budgets based on different time-based power limits over the common time window, so as to constrain power consumption based on the determined most constrained power limit budget. In this way, the time-based power limits that generate the most power-constrained power limit budget can be used to limit power consumption in a processor-based system to avoid or reduce the likelihood of violating any of the multiple time-based power limits.

[0012] In this way, the power limit budget of a processor-based system can be optimized dynamically and continuously based on multiple time-based power limits to constrain power consumption within the system. Therefore, the performance of the processor-based system can be optimized in real time within multiple time-based power limits while remaining within the system's thermal and / or skin temperature limits. Limiting power consumption in the processor-based system also allows for the sustainable achievement of the desired overall workload performance of the PU subsystem, as heat and temperature can degrade workload performance. Limiting power consumption in the processor-based system also extends battery life, as temperature can negatively impact battery performance and power supply capacity.

[0013] In one example, the power limiter circuitry can be configured to track current power consumption exceeding or not exceeding a corresponding time-based power limit within a common time window. Current power consumption below its corresponding time-based power limit within the common time window can be used as power credits to offset power debits for current power consumption exceeding its corresponding time-based power limit within the common time window. Therefore, a power limit budget corresponding to the time-based power limit can be generated based on the overall average power consumption within the common time window, avoiding the need to unnecessarily limit the power limit budget based on the highest instantaneous power consumption within the time window. This is possible because the time-based power limit of a processor-based system will not have a shorter duration than the common time window.

[0014] In another example, the power limiter circuit can be configured to continuously generate updated power limit budgets by comparing the updated current power consumption with multiple time-based power limits. In this way, if an excess power budget is available, the power limiter circuit can increase the corresponding power limit budget. If no excess power budget is available, the power limiter circuit can decrease the corresponding power limit budget.

[0015] In another example, because optimizing the power consumption of the PU subsystem to optimize its performance based on its varying workload may be important, the processor-based system can be configured to have separate time-based power limits for the PU subsystem. In this regard, the processor-based system may have PU subsystem time-based power limits for the PU subsystem and system-level time-based power limits for the entire processor-based system. In this example, the power limiter circuitry can be configured to generate multiple system-level power limit budgets for the entire processor-based system based on a comparison of the corresponding time-scaled current power consumption in the processor-based system with multiple system-level time-based power limits for the processor-based system. Furthermore, in this example, the power limiter circuitry can be configured to generate multiple PU subsystem time-based power limit budgets for the PU subsystem based on the corresponding multiple PU subsystem time-based power limits for the PU subsystem. The power limiter circuit can be configured to generate one or more PU subsystem time-based power limit budgets within a PU subsystem time-based power limit budget by comparing the corresponding time-scaled current power consumption of non-PU devices (e.g., memory systems) in the PU subsystem with the corresponding PU subsystem time-based power limit. In this way, the PU subsystem time-based power limit budget will be based on the remaining power budget available after taking into account the power consumption of non-PU devices in the PU subsystem. The power limiter circuit can then be configured to generate corresponding additional PU subsystem power limit budgets for the PU subsystem based on each system-level time-based power limit in the corresponding system-level time-based power limit, and based on the remaining available budget from the corresponding system-level power limit budget.

[0016] In this way, each of the PU subsystem time-based power limits and the system-level time-based power limits can be used to generate a corresponding PU subsystem power limit budget. These PU subsystem power limit budgets are based on each of the PU-level and system-level time-based power limits to constrain their power consumption. In one example, the power limiter circuitry can then use the most constrained PU subsystem power limit budget for each of the corresponding corresponding PU subsystem power limit budgets to provide a total PU subsystem power limit budget to constrain the overall power consumption of the PU subsystem. In this way, the generated total PU subsystem power limit budget for constraining the power consumption of the PU subsystem can be optimized on a dynamic and continuous basis, based on multiple time-based power limits of the processor-based system, to the amount of remaining available power limit budget from the entire processor-based system. Therefore, the performance of the PU subsystem can be optimized in real time across multiple time-based power limits while remaining within the thermal and / or skin temperature limits of the processor-based system. Limiting power consumption in processor-based systems can also help achieve the desired overall workload performance of the PU subsystem in a sustainable manner, as heat and temperature can degrade workload performance. Limiting power consumption in processor-based systems can also extend battery life, as temperature can negatively impact battery performance and power supply capacity.

[0017] In other exemplary aspects, the PU subsystem includes multiple PUs that perform workloads and thus consume power. As an example, these multiple PUs may include a central PU (CPU), a graphics PU (GPU), and / or a neural signal processor (NSP). In an exemplary aspect, to optimize the performance of the multiple PUs in the PU subsystem, power limiter circuitry may be configured to allocate a determined total PU subsystem power limit budget to the different PUs in the PU subsystem to optimize their respective performance. For example, the power limiter circuitry may be configured to allocate a different PU power limit budget from the total PU subsystem power limit budget to each of the different PUs based on the corresponding workload performed by the PU. In this way, as an example, if a workload performed in a first PU consumes more power for performance at a given time than a workload performed in a second PU, the power limiter circuitry may be configured to allocate the larger PU power limit budget from the total PU subsystem power limit budget to the first PU instead of the second PU. In this way, the total PU subsystem power limit budget can be allocated to different PUs in the PU subsystem based on the relative power requirements of different PUs in the PU subsystem and based on the workload being executed, in an attempt to achieve optimal performance, while keeping the total PU subsystem power consumption within the total PU subsystem power limit budget to limit the overall power consumption of the processor-based system.

[0018] In this regard, in one exemplary aspect, a power limiter circuit is provided for limiting power consumption in a processor-based system, the processor-based system including a processing unit (PU) subsystem comprising one or more PUs. The power limiter circuit is configured to: compare a current power consumption of the PU subsystem, indicating a first current power consumption in the PU subsystem, with each of the one or more time-based power limits for the PU subsystem. The power limiter circuit is further configured to: compare a current system power consumption, indicating a second current power consumption in the processor-based system, with each of the one or more time-based power limits for the system. The power limiter circuit is further configured to: generate one or more first PU subsystem power limit budgets based on the comparison of the current power consumption of the PU subsystem with the corresponding one or more time-based power limits for the PU subsystem. The power limiter circuit is further configured to: generate one or more second PU subsystem power limit budgets based on the comparison of the current system power consumption in the processor-based system with the corresponding one or more time-based power limits for the PU subsystem. The power limiter circuit is also configured to generate a total PU subsystem power limit budget based on the lower of the power limit budgets of the one or more first PU subsystems and the one or more second PU subsystems. The power limiter circuit is also configured to constrain the power consumption in the PU subsystem to the total PU subsystem power limit budget.

[0019] In another exemplary aspect, a method for limiting power consumption in a processor-based system, the processor-based system including a PU subsystem, the PU subsystem including one or more PUs. The method includes: comparing a current power consumption of the PU subsystem, indicating a first current power consumption in the PU subsystem, with each of the one or more time-based power limits for the PU subsystem. The method further includes: comparing a current power consumption of the system, indicating a second current power consumption in the processor-based system, with each of the one or more time-based power limits for the system. The method further includes: generating one or more first PU subsystem power limit budgets based on the comparison of the current power consumption of the PU subsystem in the PU subsystem with the corresponding one or more time-based power limits for the PU subsystem. The method further includes: generating one or more second PU subsystem power limit budgets based on the comparison of the current power consumption of the system in the processor-based system with the corresponding one or more time-based power limits for the PU subsystem. The method further includes: generating a total PU subsystem power limit budget based on the lower of the one or more first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets. The method also includes subjecting the power consumption in the PU subsystem to the total PU subsystem power limit budget.

[0020] In another exemplary aspect, a processor-based system is provided. The processor-based system includes a PU subsystem comprising one or more PUs. The processor-based system also includes a non-PU subsystem comprising one or more non-PU devices. The processor-based system further includes a PU subsystem power monitoring circuit configured to monitor the current power consumption of the PU subsystem within the PU subsystem. The processor-based system also includes a system power monitoring circuit configured to monitor the current system power consumption in the processor-based system. The processor-based system further includes a PU power constraint circuit configured to constrain the current power consumption of the PU subsystem within the PU subsystem. The processor-based system also includes a power limiter circuit. The power limiter circuit is configured to compare the current power consumption of the PU subsystem, indicating a first current power consumption in the PU subsystem, with each of one or more time-based power limits for the PU subsystem. The power limiter circuit is also configured to compare the current system power consumption, indicating a second current power consumption in the processor-based system, with each of one or more time-based power limits for the system. The power limiter circuit is further configured to generate one or more first PU subsystem power limit budgets based on a comparison between the current power consumption of the PU subsystem and one or more time-based power limits for the corresponding PU subsystems. The power limiter circuit is also configured to generate one or more second PU subsystem power limit budgets based on a comparison between the current power consumption of the processor-based system and one or more system time-based power limits. The power limiter circuit is further configured to generate a total PU subsystem power limit budget based on the lower of the one or more first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets. The power limiter circuit is also configured to constrain the power consumption of the PU subsystem to the total PU subsystem power limit budget. Attached Figure Description

[0021] Figure 1 This is a block diagram of an exemplary processor-based system, which includes a PU subsystem having multiple processing units (PUs), non-PU devices, and a power limiter circuit configured to allocate a total PU power limit budget to the PU subsystem to constrain its power consumption based on multiple time-based power limits of the processor-based system. Figure 2 This is a table illustrating exemplary time-based power limits, which can be... Figure 1 Desired power consumption constraints for processor-based systems; Figure 3 yes Figure 1 The diagram illustrates a PU subsystem in a processor-based system, wherein the PU subsystem includes a power limiter circuit and a PU power budget management circuit. The power limiter circuit is configured to allocate a determined total PU power limit budget to the PU subsystem based on multiple time-based power limits to constrain the power consumption of the PU subsystem within the total PU subsystem power limit budget. The PU power budget management circuit is configured to allocate the total PU subsystem power limit budget to different PUs in the PU subsystem to optimize their respective performance. Figure 4 This is an example Figure 3 A flowchart of an exemplary process of a power limiter circuit and its PU subsystem power budget allocation circuit in a processor-based system is provided, in which a determined total PU power limit budget is allocated to the PU subsystem to constrain its power consumption based on multiple time-based power limits of the processor-based system. Figure 5A and Figure 5B yes Figure 3 A schematic diagram of an example of a power estimator and budget allocation circuit in a power limiter circuit; Figure 6 This is a power consumption graph illustrating how power consumption changes over time, below and above the corresponding time-based power limits for processor-based systems, to illustrate the concept of generating a power limit budget based on the current power consumption tracked within a time window to use power credits to offset power debits within the time window, thereby avoiding the need to unnecessarily limit the power limit budget based on the highest instantaneous power consumption within the time window. Figure 7 This is an example Figure 5A and Figure 5B A flowchart of an exemplary process of the PU subsystem power limiter circuit in the example process is provided. This exemplary process generates a PU subsystem power limit budget based on the current power consumption in the tracking time window to use power credits to offset power debits within the time window, thereby avoiding the need to unnecessarily limit the PU subsystem power limit budget based on the highest instantaneous power consumption within the time window. Figure 8 It can be used as Figure 3 A schematic diagram of an exemplary PU power budget management circuit is provided as a part of the power limiter circuit in the diagram, wherein the PU power budget management circuit is configured to allocate a determined total PU subsystem power limit budget to different PUs in the PU subsystem to optimize their respective performance; Figure 9 This is a schematic diagram of an exemplary PU power constraint circuit, which is configured based on... Figure 3 and Figure 8The PU power budget management circuit in the system allocates the PU power limit budget to the PUs in the PU subsystem from the total PU subsystem power limit budget to constrain the power consumption of the corresponding PUs; Figure 10 This is a block diagram of an exemplary processor-based system including power limiter circuitry, which includes, but is not limited to, power limiter circuitry. Figure 1 , Figure 3 , Figures 5A to 5B and Figure 8 The power limiter circuit in the circuit is configured to (but is not limited to) [the following]. Figure 4 and Figure 7 The process involves allocating the total PU power limit budget to the PU subsystems to constrain their power consumption, based on multiple time-based power limits for the processor-based system; and Figure 11 This is a block diagram of an exemplary wireless communication device including a radio frequency (RF) component, which may include a processor-based system that includes a power limiter circuit, including but not limited to... Figure 1 , Figure 3 , Figures 5A to 5B and Figure 8 The power limiter circuit in the circuit is configured to (but is not limited to) [the following]. Figure 4 and Figure 7 In the process, the total PU power limit budget is allocated to the PU subsystem to constrain its power consumption based on multiple time-based power limits of the processor-based system. Detailed Implementation

[0022] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] The aspects disclosed herein include power constraints in processor-based systems based on allocating power budgets to different subsystems according to multiple time-based power limits. A processor-based system has multiple power-consuming subsystems, each containing circuitry that consumes power from the processor-based system's power supply based on its operational requirements. For example, a processor-based system may include a processing unit (PU) subsystem comprising one or more PUs, each of which requests and consumes power based on a workload being performed (which may vary over time). As an example, a PU subsystem having one or more PUs, along with non-PU devices (e.g., memory), may be included within a system-on-a-chip (SoC). A processor-based system may also have other non-PU power-consuming subsystems (such as memory) and power management circuitry that requires power to store data and provide read access to and persistently maintain such data, the power management circuitry being used to deliver power and control the temperature of the processor-based system. Processor-based systems may have power limits based on subsystem performance limits, thermal limits, and / or skin temperature limits, necessitating that the overall power consumption in the processor-based system be limited in a manner that optimizes the performance of the subsystems within the processor-based system. Furthermore, these power limits may have different time constants within which power consumption is limited, such as from the millisecond (ms) to the second (s) level. Therefore, it may be necessary to limit power consumption differently within different time constants or windows based on multiple time-based power limits specified for the processor-based system. Otherwise, for example, the power consumption of a processor-based system may remain within the desired limits over a longer duration but violate the power limits over a shorter duration, which could still negatively impact processor and / or battery performance.

[0024] In this regard, in the exemplary aspects disclosed herein, a processor-based system includes power limiter circuitry to limit the overall power consumption of the processor-based system within different time-based power limits, while attempting to still achieve optimized performance of the PU subsystem. The power limiter circuitry is configured to manage multiple different time-based (e.g., time constant) power limits for the processor-based system and is configured to allocate corresponding power limit budgets based on these multiple time-based power limits to constrain the power consumption of different subsystems. For example, the processor-based system may have multiple different time-based power limits for different time constants, such as burst power limits over shorter time durations (e.g., milliseconds) and average power consumption over longer time durations (e.g., seconds). In this regard, the power limiter circuitry is configured to compare the multiple time-based power limits assigned to the processor-based system with the current power consumption of multiple subsystems within the processor-based system to generate corresponding power limit budgets for constraining the power consumption of the subsystems.

[0025] In one example, time-based power limits that are compared with the current power consumption to generate corresponding power limit budgets are each converted to a common (e.g., the shortest) duration time window of the most time-constrained power limit. This allows the power limiter circuitry to compare each of the generated power limit budgets based on different time-based power limits over the common time window, so as to constrain power consumption based on the determined most constrained power limit budget. In this way, the time-based power limits that generate the most power-constrained power limit budget can be used to limit power consumption in a processor-based system to avoid or reduce the likelihood of violating any of the multiple time-based power limits.

[0026] In this way, the power limit budget of a processor-based system can be optimized dynamically and continuously based on multiple time-based power limits to constrain power consumption within the system. Therefore, the performance of the processor-based system can be optimized in real time within multiple time-based power limits while remaining within the system's thermal and / or skin temperature limits. Limiting power consumption in the processor-based system also allows for the sustainable achievement of the desired overall workload performance of the PU subsystem, as heat and temperature can degrade workload performance. Limiting power consumption in the processor-based system also extends battery life, as temperature can negatively impact battery performance and power supply capacity.

[0027] In this regard, Figure 1This is a block diagram of an exemplary processor-based system 100, which includes a PU subsystem 102 having multiple processing units (PUs) 104(1)-104(P), a non-PU device 106, and a power limiter circuit 108. As discussed in more detail below, the power limiter circuit 108 is configured to constrain and limit the overall power consumption of the processor-based system 100 and its PU subsystem 102 within different time-based power limits, while attempting to still achieve optimized performance of the PU subsystem 102. Before discussing exemplary aspects of how the power limiter circuit 108 limits the overall power consumption of the processor-based system 100 and its PU subsystem 102 within different time-based power limits, exemplary elements and circuitry in the processor-based system 100 are now described first.

[0028] In this regard, refer to Figure 1 The processor-based system 100 in this example includes an integrated circuit (IC) chip 110, which in this example is a system-on-a-chip (SoC) 112. In this example, the SoC 112 includes four (4) PUs 104(1)-104(4). In this example, these PUs are a first central PU (CPU) 114, a second CPU 116, a graphics PU (GPU) 118, and a neural PU (NPU) 120. Each of the PUs 104(1)-104(4) is configured to execute instructions to perform a corresponding workload. Therefore, the PUs 104(1)-104(4) consume power to operate. In this example, the SoC 112 includes a shared memory system 122 that can be accessed by each of the PUs 104(1)-104(4) to store and retrieve data for executing instructions. As an example, the shared memory system 122 may be a cache memory, such as a last-level cache memory. In this example, the shared memory system 122 has a shared memory 124 (e.g., double data rate (DDR) memory) that is typically accessible by each of the PUs 104(1)-104(4). The shared memory system 122 may also have a memory management unit (MMU) configured to manage access to the shared memory 124. The shared memory system 122 may also have statically configured memory regions for the respective PUs 104(1)-104(4) and the multimedia system 126, which is also included in the SoC 112.

[0029] Continue to refer to Figure 1The processor-based system 100 also includes other devices external to the SoC 112 and its PUs 104(1)-104(4) that provide supporting functions, including powering the SoC 112 and its PUs 104(1)-104(4) for operation. These other devices are non-PU power consumption devices 128 external to the SoC 112 and its PUs 104(1)-104(4) and are also electrical devices that consume power themselves. In this example, the processor-based system 100 includes a battery charging circuit 130, which is configured to charge a battery 132. If the processor-based system 100 is not connected to a fixed power source, the battery 132 is provided to power the processor-based system 100. In this way, the processor-based system 100 is configured to operate on battery power as a cordless device, such as in a mobile device. Figure 1 As shown, the processor-based system 100 includes a power management IC (PMIC) 134 configured to manage power supply to the SoC 112 and other components of the processor-based system 100, such as a fan 136 for cooling. The PMIC 134 manages a battery charging circuit 130 to charge a battery 132 when the processor-based system 100 is connected to a power source. The PMIC 134 also manages the discharge of the battery 132 to provide power when the processor-based system 100 is not connected to a power source. In this example, the processor-based system 100 also includes a pre-buck power supply circuit 138 configured to power the SoC 112 for peak current demands.

[0030] In the processor-based system 100, each of the PUs 104(1)-104(P) requests and consumes power based on its workload, which may vary over time. As an example, a PU subsystem 102 with its PUs 104(1)-104(P) and non-PU devices such as interface circuitry 140 may be included within the SoC 112. The processor-based system 100 may also have other non-PU power subsystems (such as a shared memory system 122) that require power to store data and provide read access to and persistent maintenance of such data. The processor-based system 100 may also have non-PU power management circuitry (e.g., battery charging circuitry 130, battery 132, PMIC 134, fan 136, and pre-buck power supply circuitry 138) for delivering power and controlling the temperature of the processor-based system 100. The processor-based system 100 may have power limits based on subsystem 102 performance limits, thermal limits, and / or skin temperature limits, such that the overall power consumption in the processor-based system 100 needs to be limited, but in a manner that optimizes the performance of the PU subsystem 102 in the processor-based system 100. Furthermore, these power limits may have different time constants within which power consumption is limited, such as from the millisecond (ms) to the second (s) level. Therefore, it may be necessary to limit power consumption differently within different time constants or windows based on multiple time-based power limits specified for the processor-based system 100 and / or its PU subsystem 102. Otherwise, for example, the power consumption of the processor-based system 100 may still be within the desired limits over a longer duration but violate the power limits over a shorter duration, which may still negatively impact processor and / or battery performance.

[0031] For example, Figure 2 Table 200 illustrates exemplary time-based power limits 202(1)-202(7), which may be... Figure 1 The expected power consumption limit of the processor-based system 100 in the example. Figure 2As shown, a first time-based power limit 202(1) of the processor-based system 100 can be used for sudden changes in current flow rate (referred to as "di / dt" events) that may cause, for example, a voltage drop. This time-based power limit 202(1) is for a time duration with a resolution in nanoseconds (ns) (e.g., between 1 ns and 10 ns). A second time-based power limit 202(2) of the processor-based system 100 can be used for peak current in the distribution network (PDN) of the processor-based system 100 over a time duration between 10 ns and 100 ns. A third time-based power limit 202(3) of the processor-based system 100 can be used for peak current in the voltage regulator over a time duration in the microsecond (μs) range (e.g., between 0.5 μs and 1.0 μs or between 10 μs and 100 μs). A fourth time-based power limit 202(4) of the processor-based system 100 can be used for peak current in the circuit board over a time duration between 2.5 μs and 5.0 μs. The fifth time-based power limit 202(5) of the processor-based system 100 is for the peak current of the battery 132 over a time duration of 20 μs to 100 μs to maintain the health of the battery 132. The sixth time-based power limit 202(6) of the processor-based system 100 is for the peak current of the pre-buck power supply circuit 138 over a time duration of 10 μs to 100 μs. The seventh time-based power limit 202(7) of the processor-based system 100 is for the thermal design power limit of the continuous current level over a longer time duration, such as 0.5 milliseconds (ms) to 60 seconds (s).

[0032] like Figure 2 As shown, the processor-based system 100 may also have time-based temperature limits 204(1)-204(2). For example, the first time-based temperature limit 204(1) of the processor-based system 100 may be a junction temperature limit over a time duration of 0.1 ms to 100 ms to control excess heat generated and / or maintain the processor-based system 100. The second time-based temperature limit 204(2) of the processor-based system 100 may be a plate temperature limit over a time duration of 1 s to 60 s to maintain the processor-based system 100 within a skin temperature limit.

[0033] In this regard, such as Figure 1 As shown in the processor-based system 100 and discussed in more detail below by example, the processor-based system 100 includes a power limiter circuit 108 configured to allocate a determined total PU power limit budget to the PU subsystem 102 to constrain its power consumption based on a plurality of time-based power limits of the processor-based system 100. Figure 1In the example processor-based system 100, power limiter circuitry 108 includes a power estimator and budget allocation circuitry 142 configured to execute instructions to generate a power budget allocation for the processor-based system 100 and the PU subsystem 102 to constrain its power consumption. As discussed in more detail below, power limiter circuitry 108 is configured to generate a total PU subsystem power limit budget 144 based on managing multiple power limits, so that the power consumption in the PU subsystem 102 is constrained by the total PU subsystem power limit budget 144. Furthermore, in this example, as discussed in more detail below, the SoC 112 also includes a PU power budget management circuit 146, which is configured to further allocate the total PU subsystem power limit budget 144 to the corresponding PU power limit budgets 148(1)-148(4), 148(P) for each PU 104(1)-104(4), 104(P), which are used to constrain the power consumption of each PU 104(1)-104(4), 104(P). For example, the PU power budget management circuit 146 may be configured to allocate the total PU subsystem power limit budget 144 to the respective PU power limit budgets 148(1)-148(4), 148(P) based on the relative workload of the PUs 104(1)-104(4), 104(P). For example, this allows the performance of PUs 104(1)-104(4), 104(P) to be optimized according to their workload and relative to their power requirements, while remaining within the overall constraint of the total PU subsystem power limit budget of 144.

[0034] Figure 3 yes Figure 1 A schematic diagram of the PU subsystem 102 in the processor-based system 100 illustrates additional exemplary details. Figure 3 As shown, the power limiter circuit 108 includes a PU power estimator and budget allocation circuit 142, which is configured to generate a total PU subsystem power limit budget 144 to constrain the power consumption of the PU subsystem 102 based on multiple time-based power limits. Furthermore, as... Figure 3As shown, the power limiter circuit 108 includes a PU power budget management circuit 146 configured to allocate individual PU power limit budgets 148(1)-148(4) from the total PU subsystem power limit budget 144 to constrain the power consumption of individual PUs 104(1)-104(4) in the SoC 112. In this example, as discussed below, the individual PU power limit budgets 148(1)-148(4) are individual PU burst power limit budgets 148(1)-148(4) used by PUs 104(1)-104(4) to constrain the burst power consumption of PUs 104(1)-104(4). For example, the burst power limit can be a power limit within a burst power time limit, which, as a non-limiting example, is such as fifteen (15) ms or less. In this example, for convenience, the power limiter circuit 108 and its PU power estimator and budget allocation circuit 142 and PU power budget management circuit 146 are provided as part of the SoC 112 containing PU subsystem 102 and PU 104(1)-104(4), but this is not required.

[0035] like Figure 3 As shown, the power estimator and budget allocation circuit 142 of the power limiter circuit 108 is configured to receive power telemetry data 300 from devices in the processor-based system 100, which indicates the current power consumption in the processor-based system 100. As discussed below, the power estimator and budget allocation circuit 142 uses the power telemetry data 300 to determine the current power consumption of the processor-based system 100, such that the power estimator and budget allocation circuit 142 can generate system power limit budgets for system devices in the processor-based system 100 and generate PU subsystem power limit budgets for constraining the power consumption of PUs 104(1)-104(4). The power estimator and budget allocation circuit 142 is configured to generate these system power limit budgets and PU subsystem power limit budgets based on whether the current power consumption of the processor-based system 100 exceeds a system power limit. For example, as previously discussed, there may be system power limits for the power consumption of the processor-based system 100 based on performance, thermal limits, and / or skin temperature limits.

[0036] For example, the power estimator and budget allocation circuit 142 is configured to receive battery and charging power consumption 302 (1) from the battery charging circuit 130. When connected to a power source, the battery charging circuit 130 is configured to charge the battery 132. Figure 1In this example, the battery charging circuit 130 is configured to provide a battery and charging power consumption 302(1) to the power estimator and budget allocation circuit 142 once every ten (10) ms. The power estimator and budget allocation circuit 142 is also configured to receive a pre-buck power consumption 302(2) from a pre-buck power supply circuit 138, which indicates burst power used to provide burst power in response to burst power demands of the processor-based system 100. In this example, the pre-buck power supply circuit 138 is configured to provide a pre-buck power consumption 302(2) once every ten (10) ms. The power estimator and budget allocation circuit 142 is also configured to receive a system power consumption 302(3) from a PMIC 134, which indicates system power provided to power the processor-based system 100. In this example, the PMIC 134 is configured to provide a system power consumption 302(3) once every ten (10) ms.

[0037] The power estimator and budget allocation circuit 142 is also configured to receive the current power consumption of the PU 302(4)(1)-304(4)(4), which indicates the current power consumption in PUs 104(1)-104(4). For example, the PU subsystem power monitoring circuit (digital power monitoring (DPM) circuit) 304(1)-304(4) may be associated with the corresponding PU 104(1)-104(4) to measure the current power consumption of the PU 302(4)(1)-304(4)(4) in its corresponding PU 104(1)-104(4). The power monitoring circuits 304(1)-304(4) may each be configured to provide, for example, the current power consumption of the PU 302(4)(1)-304(4)(4) in its corresponding PU 104(1)-104(4) once every 200 μs. This enables the power estimator and budget allocation circuit 142 to determine whether the current power consumption 302(4)(1)-304(4)(4) of the PUs 104(1)-104(4) exceeds their respective PU power limit budgets 148(1)-148(4), and if so, to adjust their PU power limit budgets 148(1)-148(4) to maintain the overall system time-based power limit 308 and / or the PU subsystem time-based power limit 310. The power estimator and budget allocation circuit 142 is also configured to receive the current power consumption 302(5), which indicates the current power consumption in the shared memory system 122 and the multimedia system 126 in the PU subsystem 102. For example, system power monitoring circuits (DPM) 306(1), 306(2) may be associated with the respective shared memory system 122 and multimedia system 126 to measure the current power consumption in their respective shared memory system 122 and multimedia system 126, and provide such current power consumption as current power consumption 302(5), 302(6). Power monitoring circuits 306(1), 306(2) may also be configured to generate interrupt request IRQs to instruct the power estimator and budget allocation circuit 142 to poll the current power consumption 302(5), 302(6). Thus, in this way, in this example, the power estimator and budget allocation circuit 142 may use the current power consumption 302(4)(1)-304(4)(4) and the current power consumption 302(5), 306(6) to estimate the current power consumption 306P of the PU subsystem in the PU subsystem 102.

[0038] The power estimator and budget allocation circuit 142 is configured to determine the current power consumption of the processor-based system 100 and the PU subsystems 102 and PUs 104(1)-104(4) using the current power consumption 302(1)-302(6). In this example, the power limiter circuit 108 and its power estimator and budget allocation circuit 142 are configured using one or more system time-based power limits 308 and one or more PU subsystem time-based power limits 310. For example, as an example, the system time-based power limit 308 may include... Figure 2 The time-based power limits 202(1)-202(5), 202(7) are included. The system time-based power limit 308 may be a power limit for power consumption over a longer time duration (such as greater than or equal to one (1) second). As another example, the time-based power limit 310 of the PU subsystem may include Figure 2 The time-based power limit 202(6) is used in the system. The time-based power limit 310 of the PU subsystem can be a power limit for power consumption over a short time duration (such as less than or equal to fifteen (15) ms). The PU power estimator and budget allocation circuit 142 uses the system time-based power limit 308 and the PU subsystem time-based power limit 310 to allocate power budget limits for PUs 104(1)-104(4) in the processor-based system 100 and the PU subsystem 102.

[0039] In this regard, as an example, see reference Figure 4 In the exemplary process 400, the power estimator and budget allocation circuit 142 is configured to compare the current power consumption 302P of the PU subsystem 102, which indicates the current power consumption in the PU subsystem 102 (e.g., from the current power consumption 302(4)(1)-304(4)(4), 302(5)-302(6)), with the time-based power limit of each of the one or more PU subsystem time-based power limits 310. Figure 4 (See box 402 in the image). This allows the power estimator and budget allocation circuit 142 to determine whether the current power consumption in the PU subsystem 102 exceeds the corresponding PU subsystem time-based power limit 310. The power estimator and budget allocation circuit 142 is also configured to compare the current system power consumption 302(1)-302(3) indicating the current power consumption in the processor-based system 100 with each of the system time-based power limits 308. Figure 4 (See box 404 in the diagram). This allows the power estimator and budget allocation circuit 142 to determine whether the current power consumption in the processor-based system 100 exceeds the corresponding system time-based power limit 308.

[0040] Continue to refer to Figure 4The power estimator and budget allocation circuit 142 are then configured to generate one or more first PU subsystem power limit budgets 312 based on a comparison between the current power consumption of the PU subsystem in PU subsystem 102 and the time-based power limit of each PU subsystem in PU subsystem time-based power limit 310. Figure 4 (See box 406 in the diagram). For example, the power estimator and budget allocation circuit 142 is configured to generate a separate first PU subsystem power limit budget 312 for each PU subsystem based on a comparison of the current power consumption of the PU subsystem with a time-based power limit 310 for each PU subsystem. The power estimator and budget allocation circuit 142 is also configured to generate one or more second PU subsystem power limit budgets 314 based on a comparison of the current system power consumption in the processor-based system 100 with each system time-based power limit in the system time-based power limit 308. Figure 4 (Box 408 in the diagram). For example, the power estimator and budget allocation circuit 142 may be allocated based on a power limit budget that is allocated to one or more other non-PU devices 106 (in the diagram). Figure 1 The remaining power budget is then used to generate one or more second PU subsystem power limit budgets 314. For example, the power estimator and budget allocation circuit 142 are configured to generate a separate second PU subsystem power limit budget 314 for each system time-based power limit 308 based on a comparison between the current power consumption of the system and each system time-based power limit 308.

[0041] The power estimator and budget allocation circuit 142 are then configured to generate a total PU subsystem power limit budget 144 based on the lower power limit budget among one or more first PU subsystem power limit budgets 312 and one or more second PU subsystem power limit budgets 314. Figure 4 (See box 410 in the text). This is because, as discussed in more detail below, it may be expected that the power estimator and budget allocation circuit 142 will use the most constrained power limit budget among the first PU subsystem power limit budget 312 and the second PU subsystem power limit budget 314 to generate the total PU subsystem power limit budget 144. This ensures that the power consumption in PU subsystem 102 does not cause the processor-based system 100 to exceed its total power limit (taking into account the power consumption of other non-PU devices outside PU subsystem 102), or exceed the PU subsystem-specific time-based power limit of PU subsystem 102. By selecting the most constrained power limit budget among the first PU subsystem power limit budget 312 and the second PU subsystem power limit budget 314 to generate the total PU subsystem power limit budget 144, PU subsystem 102 can be operated such that its current power consumption does not exceed the total PU subsystem power limit budget 144. Figure 4(Box 412 in the middle). Figure 4 The process 400 can be executed continuously in a loop, such that the total PU subsystem power limit budget 144 is continuously updated according to the resolution of the received power telemetry data 300. In this way, taking into account the power budget available to provide power to the PU subsystem 102 and the processor-based system 100, the total PU subsystem power limit budget 144 can vary and increase or decrease within possible ranges while keeping the PU subsystem 102 within the power consumption constraints of the time-based power limits 308, 310.

[0042] Then, as Figure 3 As shown, the PU power budget management circuit 146 in the power limiter circuit 108 is configured to receive the total PU subsystem power limit budget 144 to establish a corresponding PU power limit budget 148(1)-148(4), 148(P) for each PU 104(1)-104(4), 104(P). The PU power budget management circuit 146 is configured to transmit the PU power limit budgets 148(1)-148(4), 148(P) to the corresponding PUs 104(1)-104(4), 104(P) so that the PUs 104(1)-104(4), 104(P) can constrain their power consumption according to the corresponding PU power limit budgets 148(1)-148(4), 148(P). For example, the PU power budget management circuit 146 may provide an updated PU power limit budget 148(1)-148(4), 148(P) to the corresponding PUs 104(1)-104(4), 104(P) every fifteen (15) ms. The timing resolution of providing the updated PU power limit budget 148(1)-148(4), 148(P) to the corresponding PUs 104(1)-104(4) should ideally (but not necessarily) be based on the minimum time limit of the PU subsystem time-based power limit 310, so that PUs 104(1)-104(4) can constrain their power consumption within the most stringent PU subsystem time-based power limit 310, thereby avoiding or reducing power consumption exceeding the PU subsystem time-based power limit 310. In this example, the PU power budget management circuit 146 can provide updated PU power limit budgets 148(1)-148(4), 148(P) as PU burst power limit budgets 148(1)-148(4), 148(P) for constraining burst power consumption.

[0043] Continue to refer to Figure 3In this example, the PU power budget management circuit 146 is configured to allocate PU power limit budgets 148(1)-148(4) from the total PU subsystem power limit budget 144 to each PU 104(1)-104(4). This causes the current power consumption 302(4)(1)-302(4)(4) of the corresponding PU 104(1)-104(4) to be constrained within its corresponding PU power limit budget 148(1)-148(4). This is to maintain the current power consumption of PU subsystem 102 within the PU subsystem time-based power limit 310, and to maintain the overall current power consumption of processor-based system 100 within the system time-based power limit 308. Figure 3 As shown, each of PUs 104(1)-104(4) is configured to use its respective received PU power limit budget 148(1)-148(4) to set the operating point (operating frequency and / or operating voltage) of the Dynamic Voltage and Frequency Scaling (DVFS) circuits 316(1)-316(4) to control its respective current power consumption 302(4)(1)-302(4)(4). For example, each of PUs 104(1)-104(4) may be configured to use its respective received PU power limit budget 148(1)-148(4) to reset the operating point (operating frequency and / or operating voltage) of its respective DVFS circuits 316(1)-316(4) every fifteen (15) ms to control the current burst power consumption 302(4)(1)-302(4)(4). In this example, PUs 104(1)-104(4) can also each be configured to periodically (e.g., every 10) use their respective received pre-step PU power limit budgets 348(1)-348(4) generated by the power limiter circuit 108. s) Reset the operating point (e.g., operating frequency and / or operating voltage) of its corresponding circuits 318(1)-318(4) to control pre-buck power consumption.

[0044] Figure 5A and Figure 5B yes Figure 3 A schematic diagram of an example of the power estimator and budget allocation circuit 142 of the power limiter circuit 108 is provided to illustrate and discuss further exemplary details regarding how to provide a total PU subsystem power limit budget 144 to constrain the power consumption of the PU subsystem 102. Figure 5A It is shown how to generate multiple second PU subsystem power limit budgets 314(1)-314(4) based on corresponding different system time-based power limits 308(1)-308(4). Figure 5BThis demonstrates how to generate multiple first PU subsystem power budgets 312(1)-312(3) based on the time-based power limits 310(1)-310(3) of the corresponding different PU subsystems. Figure 5A and Figure 5B As shown, in this example, the power estimator and budget allocation circuit 142 includes a PU subsystem power budget selection circuit 500, which is configured to receive each of the first PU subsystem power limit budgets 312(1)-312(3) generated based on different PU subsystem time-based power limits 310(1)-310(3), and each of the second PU subsystem power limit budgets 314(1)-314(4) generated based on different system time-based power limits 308(1)-308(4). The PU subsystem power budget selection circuit 500 is configured to select the lower power budget from the first PU subsystem power limit budgets 312(1)-312(3) and the second PU subsystem power limit budgets 314(1)-314(4) as the total PU subsystem power limit budget 144 to constrain the power consumption of PU subsystem 102 and its PUs 104(1)-104(4) (see [link to relevant documentation]). Figure 3 ).

[0045] In this regard, such as Figure 5AAs shown, the power estimator and budget allocation circuit 142 is configured to receive the current power consumption 302(1) of the battery and charging as an indication of the current system power consumption 502 in the processor-based system 100. The current system power consumption 502 is provided to a plurality of filter circuits 504(1)-504(4), which are provided for each of the system time-based power limits 308(1)-308(4). This allows a second PU subsystem power limit budget 314(1)-314(4) to be generated for different system time-based power limits 308(1)-308(4). Each of the filter circuits 504(1)-504(4) is configured to sample the current system power consumption 502 within the time limit of its corresponding system time-based power limit 308(1)-308(4) to generate a corresponding sampled current system power consumption 506(1)-506(4) compatible with the time limit of the corresponding system time-based power limit 308(1)-308(4). In this example, the power estimator and budget allocation circuit 142 also includes system comparator circuits 508(1)-508(4), each of which is configured to receive the corresponding system time-based power limit 308(1) and the corresponding sampled current system power consumption 506(1)-506(4). System comparator circuits 508(1)-508(4) are each configured to compare the corresponding sampled current system power consumption 506(1)-506(4) with the corresponding system time-based power limit 308(1)-308(4) and provide the corresponding system power budget allocation circuits 512(1)-512(4) with the corresponding power consumption difference 510(1)-510(4) indicating the comparison.

[0046] System power budget allocation circuits 512(1)-512(4) are each configured to generate corresponding system burst power limit budgets 514(1)-514(4) based on a comparison between the corresponding sampled current system power consumption 506(1)-506(4) and the corresponding system time-based power limits 308(1)-308(4). In this example, the system burst power limit budgets 514(1)-514(4) are burst power limit budgets. System power budget allocation circuits 512(1)-512(4) are each configured to convert the system burst power limit budgets 514(1)-514(4) into burst power limit budgets such that these budgets can be used to generate a total PU subsystem power limit budget 144 based on the most constrained burst power limit in the processor-based system 100, as previously discussed. Then, as Figure 5AAs shown, system power budget allocation circuits 516(1)-516(4) are provided, each of which is configured to receive a corresponding system burst power limit budget 514(1)-514(4). The system power budget allocation circuits 516(1)-516(4) are configured to determine system burst power limit budgets 518(1)-518(4) from the corresponding system burst power limit budgets 514(1)-514(4) for other non-PU devices 106 (e.g., models (MDMs)) in the processor-based system 100 that require power to operate the processor-based system 100. The system power budget allocation circuits 516(1)-516(4) are also configured to determine a second PU subsystem power limit budget 314(1)-314(4) from the corresponding system burst power limit budgets 514(1)-514(4) of the PU subsystem 102, which in this example is the second PU subsystem burst power limit budget 314(1)-314(4). The system power budget allocation circuits 516(1)-516(4) can be configured to prioritize non-PU device 106 or PU subsystem 102 when allocating system burst power limit budgets 514(1)-514(4) to system burst power limit budgets 518(1)-518(4) and the second PU subsystem burst power limit budgets 314(1)-314(4).

[0047] Continue to refer to Figure 5AThe power estimator and budget allocation circuit 142 may optionally include PU subsystem burst power budget circuits 520(1)-520(3), each of which is configured to receive the current power consumption 302P of the PU subsystem to determine whether the second PU subsystem burst power limit budget 314(1)-314(4) exceeds the current power consumption 302P of the PU subsystem. If the current power consumption 302P of the PU subsystem does not exceed the corresponding second PU subsystem burst power limit budget 314(1)-314(4), the corresponding PU subsystem burst power budget circuit 520(1)-520(3) may maintain or increase the corresponding second PU subsystem burst power limit budget 314(1)-314(4). If the current power consumption 302P of the PU subsystem exceeds the corresponding second PU subsystem burst power limit budget 314(1)-314(4), then the corresponding PU subsystem burst power budget circuit 520(1)-520(3) can reduce the corresponding second PU subsystem burst power limit budget 314(1)-314(4). This additional optional function can be provided as an additional safety and accuracy measure when generating the second PU subsystem burst power limit budget 314(1)-314(4), since these second PU subsystem burst power limit budgets are initially generated based on the current power consumption 302(1) of the system. The final second PU subsystem burst power limit budgets 314(1)-314(4) are provided to the PU subsystem power budget selection circuit 500 to select the lower power limit budget from the second PU subsystem burst power limit budgets 314(1)-314(4) and the first PU subsystem burst power limit budgets 312(1)-312(3) generated by the power estimator and budget allocation circuit 142, such as Figure 5B As shown, this will now be described.

[0048] like Figure 5BAs shown, the power estimator and budget allocation circuit 142 is configured to receive the current power consumption 302P of the PU subsystem as an indication of the current power consumption of the PU subsystem 102. The current power consumption 302P of the PU subsystem is provided to a filter circuit 524(1) for a first PU subsystem time-based power limit 310(3). The filter circuit 524(1) is configured to sample the current power consumption 302P of the PU subsystem within the time limit of its corresponding PU subsystem time-based power limit 310(3) to generate a sampled current power consumption 526(1) of the PU subsystem that is compatible with the time limit of the corresponding PU subsystem time-based power limit 310(3). In this example, the power estimator and budget allocation circuit 142 also includes a PU subsystem comparator circuit 528(1) configured to receive the PU subsystem time-based power limit 310(3) and the corresponding sampled current power consumption 526(1). The PU subsystem comparator circuit 528(1) is configured to compare the sampled current power consumption 526(1) of the PU subsystem with the time-based power limit 310(3) of the PU subsystem, and provide a power consumption difference 530(1) indicating the comparison to the first PU subsystem power budget allocation circuit 532(3). The first PU subsystem power budget allocation circuit 532(3) is configured to generate a corresponding PU subsystem burst power limit budget 312(3) based on the comparison between the corresponding sampled current power consumption 526(1) of the PU subsystem and the time-based power limit 310(3) of the PU subsystem. In this example, the system burst power limit budget 312(3) is a burst power limit budget. The first PU subsystem power budget allocation circuit 532(3) is configured to convert the PU subsystem burst power limit budget 312(3) into a burst power limit budget such that the budget can be used to generate a total PU subsystem power limit budget 144 based on the most constrained burst power limit in the processor-based system 100, as previously discussed.

[0049] Note that in this example, the PU subsystem comparator circuit 528(1) is configured to compare the sampled current power consumption 526(1) of the PU subsystem with the minimum of either the time-based power limit 310(3) of the PU subsystem or the second PU subsystem burst power limit budget 314(4), because in this example, the second PU subsystem burst power limit budget 314(4) is not coupled to the PU subsystem power budget selection circuit 500. In this example, as discussed in more detail below, the second PU subsystem burst power limit budget 314(4) is provided to the PU power budget management circuit 146 for allocating the total PU subsystem power limit budget 144.

[0050] Continue to refer to Figure 5BThe time-based power limits 310(1) and 310(2) of the first PU subsystem are provided to the corresponding first PU subsystem power budget allocation circuits 532(1) and 532(2). The first PU subsystem power budget allocation circuits 532(1) and 532(2) are configured to generate corresponding PU subsystem burst power limit budgets 312(1) and 312(2) based on a comparison between the current power consumption 302P of the PU subsystem and the corresponding time-based power limits 310(1) and 310(2) of the PU subsystem. In this example, the PU subsystem burst power limit budgets 312(1) and 312(1) are burst power limit budgets. The first PU subsystem power budget allocation circuits 532(1) and 532(2) are each configured to convert the corresponding PU subsystem burst power limit budgets 312(1) and 312(2) into corresponding burst power limit budgets, such that these budgets can be used to generate the total PU subsystem power limit budget 144 based on the most constrained burst power limit in the processor-based system 100, as previously discussed.

[0051] The final first PU subsystem burst power limit budget 312(1)-312(3) is provided to the PU subsystem power budget selection circuit 500. The PU subsystem power budget selection circuit 500 is configured to select the first PU subsystem burst power limit budget 312(1)-312(3) generated by the power estimator and budget allocation circuit 142 (e.g., ...). Figure 5B (as shown) and the second PU subsystem burst power limit budget 314(1)-314(4) generated by the power estimator and budget allocation circuit 142 (as shown) Figure 5A As shown, a lower power limit budget is selected to provide the total PU subsystem power limit budget 144. As discussed above, the total PU subsystem power limit budget 144 is determined by... Figure 3 The PU power budget management circuit 146 is used to allocate power limit budgets 148(1)-148(4) for each PU to constrain the power consumption of PUs 104(1)-104(4) in the PU subsystem 102.

[0052] Figure 5A and Figure 5BThe power estimator and budget allocation circuit 142 in the first PU subsystem power budget allocation circuit 532(1)-532(3) and the second PU subsystem power budget allocation circuit 512(1)-512(3) can also be configured to generate their corresponding first PU subsystem power limit budgets 312(1)-312(3) and second PU subsystem power limit budgets 314(1)-314(3) based on the current power consumption credit and debit scheme, to further optimize the corresponding first PU subsystem power limit budgets 312(1)-312(3) and second PU subsystem power limit budgets 314(1)-314(3). This is in Figure 6 The power consumption curve in Figure 600 is shown as an example. Figure 6 The power consumption curve 600 illustrates the change of current power consumption (POWER) over time (TIME), below and above the corresponding time-based burst power limit budgets 602(1), 602(2) of the processor-based system 100. As an example, the time-based burst power limit budgets 602(1), 602(2) can be any of the system time-based power limits 308(1)-308(4) or the PU subsystem time-based power limits 310(1)-310(3). The power consumption curve 600 shows the current power consumption (POWER) within the time limit or burst time window 604 between time t0 and time t3.

[0053] like Figure 6 As shown, between time t0 and time t1, the current power consumption P1 is lower than the expected power limit budget 602(1). The current power consumption P1 is also the average power consumption P at this time. AVG Since the current power consumption P1 is below the burst power limit budget 602(1), power credit is essentially achieved, whereby the current power consumption can increase beyond the burst power limit budget 602(1) after time t1, and still result in an average power consumption P within the burst time window 604. AVG It is within the expected power limit budget 602(1). In this example, power credit and debit are the sum of the excess and under-limit portions of the current power consumption relative to the burst power limit budget 602(1). As this example shows, if the current power consumption (POWER) subsequently increases to the current power consumption P2 at time t2, the average power consumption P within the burst time window 604 is... AVG The power consumption will begin to increase, but will not immediately exceed the burst power limit budget 602(1). Therefore, the burst power limit budget can be temporarily increased to the maximum burst power limit budget 602(2) to allow the PU subsystem 102 to consume more average power consumption P within the burst time window 604. AVG To improve performance. Then, as shown at time t2, after the current power consumption is already at power P2, with the average power consumption P...AVG The expected burst power limit budget 602(1) is approaching the burst time window 604, and the average power consumption P AVG This results in a debiting effect on previous power credits. Therefore, the burst power limit budget may temporarily decrease to burst power limit budget 602(3), while still providing a power debit higher than burst power limit budget 602(1) because the average power consumption P AVG The expected burst power limit budget 602 (1) is still not exceeded. However, at time t3, the average power consumption P in the burst time window 604 is... AVG This equals the expected burst power limit budget 602(1), which means that the previous power credit between time t0 and t1 has been completely exhausted and a debit has been generated. Therefore, the power limit budget can be reduced back to the original burst power limit budget 602(1).

[0054] In this way, using Figure 6 The power credit and debit scheme shown, the power budget allocation circuits 532(1)-532(3) and 512(1)-512(3) can further optimize the total PU subsystem power limit budget 144 to limit the power consumption of the PU subsystem 102 when the generated total PU subsystem power limit budget 144 is not completely exhausted at a given burst time window. For example, refer to Figure 5A The system power budget allocation circuits 512(1)-512(3) can be configured to track the difference between the corresponding system burst power limit budgets 514(1)-514(3) and the corresponding sampled system current power consumption 506(1)-506(3). The system power budget allocation circuits 512(1)-512(3) can be configured to adjust the corresponding system burst power limit budgets 514(1)-514(3) based on the difference between the corresponding system burst power limit budgets 514(1)-514(3) and the corresponding sampled system current power consumption 506(1)-506(3). The system power budget allocation circuits 512(1)-512(3) can be configured to increase the corresponding system burst power limit budget 514(1)-514(3) when the corresponding system burst power limit budget 514(1)-514(3) is less than the corresponding sampled current system power consumption 506(1)-506(3) or its average value. The system power budget allocation circuits 512(1)-512(3) can also be configured to decrease the corresponding system burst power limit budget 514(1)-514(3) when the corresponding system burst power limit budget 514(1)-514(3) is greater than the corresponding sampled current system power consumption 506(1)-506(3) or its average value.

[0055] In addition, using Figure 6The power credit and debit scheme shown is for reference. Figure 5B The PU subsystem power budget allocation circuits 532(1)-532(3) can be configured to track the difference between the corresponding PU subsystem burst power limit 310(1)-310(3) and the corresponding current power consumption 302P, 526(1). The PU subsystem power budget allocation circuits 532(1)-532(3) can be configured to adjust the corresponding PU subsystem burst power limit budget 312(1)-312(3) based on the difference between the corresponding PU subsystem burst power limit budget 312(1)-312(3) and the corresponding PU subsystem current power consumption 302P, 526(1). The PU subsystem power budget allocation circuits 532(1)-532(3) can be configured to increase the corresponding PU subsystem burst power limit budget 312(1)-312(3) when the corresponding PU subsystem burst power limit budget 312(1)-312(3) is less than the corresponding PU subsystem current power consumption 302P, 526(1) or their average value. The PU subsystem power budget allocation circuits 532(1)-532(3) can also be configured to decrease the corresponding PU subsystem burst power limit budget 312(1)-312(3) when the corresponding system burst power limit budget 312(1)-312(3) is greater than the corresponding PU subsystem current power consumption 302P, 526(1) or their average value.

[0056] Figure 7 This is a flowchart illustrating exemplary process 700. Figure 5A and Figure 5B Any of the power budget allocation circuits 532(1)-532(3) and 512(1)-512(3) in the PU power budget management circuit 146 can perform this process to track the current power consumption in a burst time window to use power credits to offset the power debits within that time window, thereby avoiding the need to unnecessarily limit the first PU subsystem power limit budget 312(1)-312(3) and / or the second PU subsystem power limit budget 314(1)-314(3) generated. Process 700 is discussed with respect to the PU subsystem power budget allocation circuit 532(1), but can be performed by any of the power budget allocation circuits 532(1)-532(3) and 512(1)-512(3). In this regard, as Figure 7 As shown, the first step in process 700 is to determine whether the power budget credit (PL1Crdt) is available based on the power credit. Figure 7Box 702 in the middle). If not, this is an error or violation. In this case, the instantaneous burst power limit budget (IntSpcBrstTrgt) used to set the current burst power limit budget is reduced by multiplying the power budget credit (PL1Crdt) by a negative multiplier value and then adding the product to the original PU subsystem burst power limit budget 312(1). Figure 7 (Box 704 in the middle).

[0057] If in Figure 7 If an initial power budget credit (PL1Crdt) is available in box 702, then the PU subsystem power budget allocation circuit 532(1) calculates the second higher PU subsystem burst power limit budget 312(1)(2) by adding the first lower PU subsystem burst power limit budget 312(1)(1) to the power budget credit (PL1Crdt) and multiplying it by the multiplier value. Figure 7 (Box 706 in the middle). PU subsystem power budget allocation circuit 532(1) then determines whether the second PU subsystem power limit budget 312(1)(2) exceeds the second burst power limit budget (PL2T threshold) ( Figure 7 (See box 708 in the table). If it does not exceed the limit, the instantaneous burst power limit budget (IntSpcBrstTrgt) is set to the lower first PU subsystem burst power limit budget 312(1)(1). Figure 7 (See box 710 in the middle). If the second PU subsystem power limit budget 312(1)(2) exceeds the second burst power limit, then this is a burst power demand case, in which the instantaneous burst power limit budget (IntSpcBrstTrgt) is then set to the higher second PU subsystem power limit budget 312(1)(2). Figure 7 (in box 712). Then, since it is determined in box 702 that there is available power credit, the PU subsystem power budget allocation circuit 532(1) determines whether the second PU subsystem burst power limit budget 312(1)(2) exceeds the maximum allowable burst power limit budget 312(1)(3). Figure 7 (in box 714), and if exceeded, the PU subsystem burst power limit budget 312(1) is set to the maximum burst power limit budget 312(1)(3). Figure 7 (See box 716 in the table). If the burst power limit budget 312(1)(2) of the second PU subsystem does not exceed the maximum allowable burst power limit budget 312(1)(3), then the burst power limit budget 312(1) of the PU subsystem is set to the instantaneous burst power limit budget 312(1)(2) (IntSpcBrstTrgt) to exhaust the power credit ( Figure 7 (Box 718 in the middle).

[0058] Figure 8 It is possible Figure 3 , Figure 5A and Figure 5B A schematic diagram of an exemplary PU power budget management circuit 146 provided in the power limiter circuit 108. As described above regarding... Figure 3 , Figure 5A and Figure 5B The PU power budget management circuit 146 is configured to allocate the total PU subsystem power limit budget 144 determined by the power estimator and the budget allocation circuit 142 to the different PUs 104(1)-104(P) in the PU subsystem 102 to optimize their respective performance.

[0059] In this regard, such as Figure 8 As shown, in this example, the PU power budget management circuit 146 includes a comparator circuit 802 configured to generate an adjusted total PU subsystem power limit budget 144(1) based on whether the sampled current power consumption 526(1) of the PU subsystem differs from the total PU subsystem power limit budget 144. For example, if the total PU subsystem power limit budget 144 is less than the sampled current power consumption 526(1), the total PU subsystem power limit budget 144 may be increased in the adjusted total PU subsystem power limit budget 144(1). If the total PU subsystem power limit budget 144 is greater than the sampled current power consumption 526(1), the total PU subsystem power limit budget 144 may be decreased in the adjusted total PU subsystem power limit budget 144(1). In this example, the PU power budget management circuit 146 includes a proportional-integral-derivative (PID) circuit 804 to smooth the adjusted total PU subsystem power limit budget 144(1) to provide a new total PU subsystem power limit budget 144(2) to be allocated to PUs 104(1)-104(P).

[0060] Continue to refer to Figure 8The PU power budget management circuit 146 also includes a minimum value circuit 806 configured to provide a final total PU subsystem power limit budget 144(3) as the lower of a new total PU subsystem power limit budget 144(2) and a PU subsystem burst power limit budget 312(3). This ensures that the final total PU subsystem power limit budget 144(3) does not exceed a third PU subsystem burst power limit budget 312(3), which can be provided as a final total PU subsystem power limit budget 144(3) with a minimum time duration or limit. The PU power budget management circuit 146 also includes a PU budget allocation circuit 808 configured to allocate PU power limit budgets 148(1)-148(P) to the corresponding PUs 104(1)-104(P) to constrain their power consumption. The PU budget allocation circuit 808 can be configured to allocate or split the final total PU subsystem power limit budget 144(3) into PU power limit budgets 148(1)-148(P) based on power priority cues 810(1)-810(P) provided from the respective PUs 104(1)-104(P). The PU budget allocation circuit 808 can also be configured to allocate or split the final total PU subsystem power limit budget 144(3) into PU power limit budgets 148(1)-148(P) based on power cues 812(1)-812(P) provided from the respective PUs 104(1)-104(P), which may be based on the workload performed by the respective PUs 104(1)-104(P). The PU budget allocation circuit 808 can also be configured to allocate or split the final total PU subsystem power limit budget 144(3) into PU power limit budgets 148(1)-148(P) based on the requested or maximum permissible power limit budgets 814(1)-814(4) provided by the respective PUs 104(1)-104(P). In this regard, if the power limit budgets are available, the PU budget allocation circuit 808 can be configured to provide the respective PU power limit budgets 148(1)-148(P) to the respective PUs 104(1)-104(4) according to the requests of each PU.

[0061] Figure 9 This is a schematic diagram of an exemplary PU power constraint circuit 900, which may be provided in any of PUs 104(1)-104(P) to be based on... Figure 3 and Figure 8The PU power budget management circuit 146 allocates a PU power limit budget 148 (10-148(P)) to constrain the power consumption of the corresponding PUs 104(1)-104(P). The PU power constraint circuit 900 is described as being included in or provided to the PU 104(1) to constrain its power consumption, but it should be noted that the PU power constraint 900 may be included in any of the PUs 104(1)-104(P).

[0062] In this regard, such as Figure 9 As shown, the PU power constraint circuit 900 receives the current PU power consumption 302(4)(1) of PU 104(1). The PU power constraint circuit 900 includes an averaging circuit 902 that averages the current PU power consumption 302(4)(1) within a burst window to provide a current burst power consumption 904(1). The PU power constraint circuit 900 includes a PID circuit 906 that smooths the current burst power consumption 904(1) to a desired power consumption level 905 to meet the PU burst power limit budget 148(1) of PU 104(1). The PU power constraint circuit 900 also includes a DVFS strategy circuit 907 that is configured to set an operating point 918 for operating PU 104(1) based on the desired power consumption level 905. The set operating point 918 is communicated to a frequency circuit 908 that is configured to set the operating frequency f of PU 104(1) based on the set operating point 918. The desired operating point 918 is also communicated to a voltage regulator circuit 910, which is configured to set the operating voltage V of PU 104(1) based on the desired operating point 918. The operating frequency f and the operating voltage V are provided to a power estimator circuit 912, which is configured to generate an estimated power consumption 914 of PU 104(1) relative to the desired operating point 918. A desired power calculation circuit 916 is configured to, based on whether the estimated power consumption 914 of PU 104(1) based on the set operating point 918 is greater than or less than the power consumption at the set operating point 918, provide... Figure 8 The PU power budget management circuit 146 in the middle provides the expected maximum allowable burst power limit budget 814(1).

[0063] The processor-based system including power limiter circuitry can be provided in an IC package provided in any processor-based device or in an IC package integrated into any processor-based device, the power limiter circuitry including but not limited to... Figure 1 , Figure 3 , Figures 5A to 5B and Figure 8 The power limiter circuit 108 is configured to (but is not limited to) [the following]. Figure 4 and Figure 7In processes 400 and 700, and in accordance with any aspect disclosed herein, a total PU power limit budget is allocated to the PU subsystem to constrain its power consumption based on multiple time-based power limits of the processor-based system. Examples not intended to be limiting include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0064] In this regard, Figure 10 An example of a processor-based system 1000 is illustrated. The processor-based system 1000 may include a power limiter circuit 1002, including but not limited to... Figure 1 , Figure 3 , Figures 5A to 5B and Figure 8 The power limiter circuit 108 is configured to (but is not limited to) [the following]. Figure 4 and Figure 7 In processes 400 and 700, and in accordance with any aspect disclosed herein, a total PU power limit budget is allocated to the PU subsystem to constrain its power consumption based on multiple time-based power limits of the processor-based system. In this example, the processor-based system 1000 may be configured as IC 1004 and as a system-on-a-chip (SoC) 1006. The processor-based system 1000 includes a PU 1008, which includes one or more processors 1010. As an example, the multiple processors may include a CPU, a GPU, and an NPU, similar to... Figure 1The processor-based system 100 includes CPUs 114 and 116, a GPU 118, and an NPU 120. A PU 1008 may have a shared memory 1012 (e.g., a shared cache memory) coupled to the PU 1008 for fast access to temporary data storage. The PU 1008 is coupled to a system bus 1014 and can couple master and slave devices included in the processor-based system 1000 to each other. As is well known, the PU 1008 communicates with these other devices by exchanging address, control, and data information via the system bus 1014. For example, the PU 1008 may communicate a bus transaction request to a memory controller 1016, which is an example of a slave device. Although in Figure 10 Not illustrated, but multiple system buses 1014 may be provided, each of which constitutes a different structure.

[0065] Other master and slave devices can be connected to system bus 1014. For example... Figure 10 As illustrated, these devices may include a memory system 1020, one or more input devices 1022, one or more output devices 1024, one or more network interface devices 1026, and one or more display controllers 1028, the memory system including a memory controller 1016 and a memory array 1018. Input devices 1022 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 1024 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 1026 may be any device configured to allow the exchange of data to and from network 1030. Network 1030 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth, etc. ™ Networks and the Internet. The network interface device 1026 can be configured to support any type of communication protocol desired.

[0066] PU 1008 can also be configured to access display controller 1028 via system bus 1014 to control information transmitted to one or more displays 1032. Display controller 1028 transmits information to be displayed to display 1032 via one or more video processors 1034, which process the information to be displayed into a format suitable for display 1032. Display controller 1028 and video processor 1034 may be included in the same or different ICs, and as an example, may be included in the same IC 1004 containing PU 1008. Display 1032 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0067] Figure 11 An exemplary wireless communication device 1100 is illustrated, which includes radio frequency (RF) components and power limiter circuits 1102(1), 1102(2), such as Figure 1 , Figure 3 , Figures 5A to 5B and Figure 8 The power limiter circuit 108 is configured to (but is not limited to) [the following]. Figure 4 and Figure 7 In processes 400 and 700, and in accordance with any aspect disclosed herein, a total PU power limit budget is allocated to the PU subsystem to constrain its power consumption based on multiple time-based power limits of the processor-based system. As an example, wireless communication device 1100 may include any of the devices mentioned above or be provided in any of the devices mentioned above. Figure 11 As shown, the wireless communication device 1100 includes a transceiver 1104 and a data processor 1106, each of which may include its own power limiter circuits 1102(1) and 1102(2). The data processor 1106 may include memory for storing data and program code. The transceiver 1104 includes a transmitter 1108 and a receiver 1110 supporting bidirectional communication. Generally, the wireless communication device 1100 may include any number of transmitters 1108 and / or receivers 1110 for any number of communication systems and frequency bands. All or part of the transceiver 1104 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0068] The transmitter 1108 or receiver 1110 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband. For example, for receiver 1110, the signal is converted from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 11 In the wireless communication device 1100, the transmitter 1108 and the receiver 1110 are implemented using a direct frequency conversion architecture.

[0069] In the transmission path, data processor 1106 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1108. In the exemplary wireless communication device 1100, data processor 1106 includes digital-to-analog converters (DACs) 1112(1) and 1112(2) to convert the digital signals generated by data processor 1106 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0070] Within transmitter 1108, low-pass filters 1114(1) and 1114(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1116(1) and 1116(2) amplify the signals from low-pass filters 1114(1) and 1114(2), respectively, and provide I and Q baseband signals. Upconverter 1118 uses mixers 1120(1) and 1120(2) to upconvert the I and Q baseband signals from transmit (TX) local oscillator (LO) signal generator 1122 to provide upconverted signal 1124. Filter 1126 filters the upconverted signal 1124 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1128 amplifies the up-converted signal 1124 from filter 1126 to obtain the desired output power level and provide a transmit RF signal. The transmit RF signal is routed through duplexer or switch 1130 and transmitted via antenna 1132.

[0071] In the receiving path, antenna 1132 receives signals transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1130 and provided to low-noise amplifier (LNA) 1134. Duplexer or switch 1130 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1134 and filtered by filter 1136 to obtain the desired RF input signal. Downconversion mixers 1138(1) and 1138(2) mix the output of filter 1136 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1140 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1142(1) and 1142(2) and further filtered by low-pass filters 1144(1) and 1144(2) to obtain I and Q analog input signals, which are provided to data processor 1106. In this example, data processor 1106 includes analog-to-digital converters (ADCs) 1146(1) and 1146(2) to convert the analog input signals into digital signals to be further processed by data processor 1106.

[0072] exist Figure 11 In the wireless communication device 1100, a TX LO signal generator 1122 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1140 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1148 receives timing information from a data processor 1106 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1122. Similarly, an RX PLL circuit 1150 receives timing information from a data processor 1106 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1140.

[0073] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device or processing unit, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0074] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0075] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0076] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0077] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0078] Specific implementation examples are described in the following numbered clauses: 1. A power limiter circuit for limiting power consumption in a processor-based system, the processor-based system including a processing unit (PU) subsystem, the processing unit (PU) subsystem including one or more PUs, the power limiter circuit being configured to: (a) The current power consumption of the PU subsystem, which indicates the first current power consumption in the PU subsystem, is compared with the time-based power limit of each of one or more time-based power limits for the PU subsystem; (b) The system current power consumption, which indicates the second current power consumption in the processor-based system, is compared with each of one or more system time-based power limits; (c) Generate one or more first PU subsystem power limit budgets based on the comparison between the current power consumption of the PU subsystem and the time-based power limits of the one or more PU subsystems; (d) Generate one or more second PU subsystem power limit budgets based on the comparison between the current power consumption of the system in the processor-based system and one or more corresponding system time-based power limits; (e) Generate a total PU subsystem power limit budget based on the lower of the one or more first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets; and (f) Make the power consumption in the PU subsystem subject to the total PU subsystem power limit budget.

[0079] 2. The power limiter circuit according to Clause 1, wherein the power limiter circuit is further configured as follows: Within the time limit of each of the one or more time-based power limits for the PU subsystems, the current power consumption of the PU subsystem is sampled to generate one or more sampled current power consumptions of the PU subsystems; and The power limiter circuit is configured as follows: The current power consumption of the PU subsystem is compared by being configured to perform the following operations: comparing the current power consumption of each of the one or more sampled current power consumptions of the PU subsystem with the corresponding time-based power limit of the one or more PU subsystems; and The power limit budget for the one or more first PU subsystems is generated based on the comparison between the current power consumption of the one or more sampled PU subsystems and the time-based power limits of the corresponding one or more PU subsystems.

[0080] 3. The power limiter circuit according to Clause 2, wherein the power limiter circuit is further configured as follows: The current system power consumption is sampled within a time limit of each of the one or more system time-based power limits to generate one or more sampled current system power consumptions; and The power limiter circuit is configured as follows: The system current power consumption is compared by being configured to perform the following operations: comparing each of the one or more sampled system current power consumptions with the corresponding one or more system time-based power limits; and The power limit budget of the one or more second PU subsystems is generated based on the comparison between the current power consumption of the one or more sampled systems and the corresponding one or more power limits based on system time.

[0081] 4. The power limiter circuit according to any one of clauses 1 to 3, wherein the power limiter circuit is further configured as follows: Based on the burst power time limit, the power limit budget of the one or more first PU subsystems is converted into the corresponding burst power limit budget of the one or more first PU subsystems; Based on the burst power time limit, the power limit budget of the one or more second PU subsystems is converted into the corresponding burst power limit budget of the one or more second PU subsystems; and The power limiter circuit is configured as follows: The total PU subsystem power limit budget is generated based on the lower power limit budget among the one or more first PU subsystem burst power limit budgets and the one or more second PU subsystem burst power limit budgets.

[0082] 5. The power limiter circuit according to any one of clauses 1 to 4, wherein the power limiter circuit is further configured to: The time-based power limits of the one or more PU subsystems are converted into corresponding burst power limits of the one or more PU subsystems within the burst power time limit; The one or more system time-based power limits are converted into one or more corresponding system burst power limits within the burst power time limits; and The power limiter circuit is configured as follows: The current power consumption of the PU subsystem is compared by being configured to perform the following operation: the current burst power consumption of the PU subsystem, which indicates the first current burst power consumption in the PU subsystem, is compared with each of the one or more PU subsystem burst power limits; The current power consumption of the system is compared by being configured to perform the following operation: comparing the current burst power consumption of the system, which indicates a second current burst power consumption in the processor-based system, with each of the one or more system burst power limits; The one or more first PU subsystem power limit budgets are generated by being configured to perform the following operations: generating one or more first PU subsystem burst power limit budgets based on the comparison between the current burst power consumption of the PU subsystem in the PU subsystem and the corresponding one or more PU subsystem burst power limits; The one or more second PU subsystem power limit budgets are generated by being configured to perform the following operations: generating one or more second PU subsystem burst power limit budgets based on the comparison between the current burst power consumption of the system in the processor-based system and the corresponding one or more system burst power limits; The total PU subsystem power limit budget is generated by being configured to perform the following operations: generating the total PU subsystem burst power limit budget based on the lower burst power limit budget among the one or more first PU subsystem burst power limit budgets and the one or more second PU subsystem burst power limit budgets; and The power consumption in the PU subsystem is subject to the total PU subsystem burst power limit budget constraint.

[0083] 6. The power limiter circuit according to Clause 5, wherein the burst power time limit is less than or equal to fifteen (15) milliseconds (ms).

[0084] 7. The power limiter circuit according to any one of Clauses 1 to 6, wherein the power limiter circuit is configured to generate a power limit budget for the one or more second PU subsystems based on a comparison of the current power consumption of the system with the one or more system time-based power limits, the current power consumption of the system including the current power consumption of the battery and battery charger in the processor-based system.

[0085] 8. The power limiter circuit according to any one of clauses 1 to 7, wherein the power limiter circuit is configured to: The power limit budget for the one or more first PU subsystems is generated by being configured to: reduce the power limit budget for the one or more first PU subsystems based on a comparison of the first current power consumption in the PU subsystem being greater than the time-based power limit of the one or more PU subsystems; and The one or more second PU subsystem power limit budgets are generated by being configured to reduce the power limit budgets of the one or more second PU subsystems based on a comparison of the current power consumption of the system in the processor-based system being greater than the one or more system time-based power limits.

[0086] 9. The power limiter circuit according to any one of clauses 1 to 7, wherein the power limiter circuit is configured to: The power limit budget for the one or more first PU subsystems is generated by being configured to: increase the power limit budget for the one or more first PU subsystems based on a comparison of the first current power consumption in the PU subsystem being less than the time-based power limit of the one or more PU subsystems; and The one or more second PU subsystem power limit budgets are generated by being configured to increase the power limit budgets of the one or more second PU subsystems based on a comparison of the current power consumption of the system in the processor-based system being less than the one or more system time-based power limits.

[0087] 10. The power limiter circuit according to any one of clauses 1 to 9, wherein the power limiter circuit is configured to generate the power limit budget of the one or more second PU subsystems by being configured to perform the following operations: The system power limit budget for the processor-based system is generated based on the comparison between the current power consumption of the system in the processor-based system and one or more system time-based power limits. Generate at least one non-PU subsystem power limit budget from the system power limit budget to constrain the power of the non-PU subsystems in the processor-based system; and The power limit budget for the one or more second PU subsystems is generated based on the difference between the system power limit budget and the power limit budget for the at least one non-PU subsystem.

[0088] 11. The power limiter circuit according to Clause 5, wherein the power limiter circuit is further configured to: In the comparison between the current burst power consumption of the PU subsystem and the corresponding burst power limit of one or more PU subsystems within the burst power time limit, the difference between the current burst power of one or more PU subsystems is tracked. The sum of one or more current burst power values ​​of the corresponding one or more PU subsystems is generated by comparing the current burst power consumption of the PU subsystem with the corresponding one or more PU subsystem burst power limits within the burst power time limit; and The burst power limit budget for the one or more first PU subsystems is generated based on the comparison between the current sum of burst power of the one or more PU subsystems and the corresponding burst power limit of the one or more PU subsystems.

[0089] 12. The power limiter circuit according to clause 5 or 11, wherein the power limiter circuit is further configured to: In the comparison between the current burst power consumption of the system and one or more corresponding system burst power limits within the burst power time limit in the processor-based system, one or more current system burst power differences are tracked. In the comparison between the current burst power consumption of the system and one or more corresponding system burst power limits within the burst power time limit in the processor-based system, a sum of one or more system current burst power differences is generated; and The burst power limit budget for the one or more second PU subsystems is generated based on the comparison between the sum of the current burst power of the one or more systems and the corresponding burst power limit of the one or more systems.

[0090] 13. The power limiter circuit according to any one of clauses 1 to 12, wherein the power limiter circuit is configured to: The current power consumption of the PU subsystem is compared with the time-based power limit of each of the multiple time-based power limits for PU subsystems; The power limit budgets for the one or more first PU subsystems are generated by being configured to perform the following operations: generating a plurality of first PU subsystem power limit budgets based on a comparison between the current power consumption of the PU subsystems and the time-based power limit of each of the plurality of PU subsystems; and The total PU subsystem power limit budget is generated based on the lower power limit budget among the plurality of first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets.

[0091] 14. The power limiter circuit according to Clause 13, wherein the time-based power limits of the plurality of PU subsystems include: The first PU subsystem has a time-based power limit, wherein the first PU subsystem has a first time limit of less than or equal to fifteen (15) milliseconds (ms); and The second PU subsystem has a time-based power limit, which has a second time limit greater than or equal to one (1) second.

[0092] 15. The power limiter circuit according to any one of clauses 1 to 14, wherein the power limiter circuit is configured to: The current power consumption of the system is compared with each of a plurality of system time-based power limits; The one or more second PU subsystem power limit budgets are generated by being configured to perform the following operations: generating multiple second PU subsystem power limit budgets based on the comparison of the current power consumption of the system in the processor-based system with the corresponding multiple system time-based power limits; and The total PU subsystem power limit budget is generated based on the lower power limit budget among the one or more first PU subsystem power limit budgets and the plurality of second PU subsystem power limit budgets.

[0093] 16. The power limiter circuit according to Clause 15, wherein the plurality of system time-based power limits include: A first system time-based power limit, wherein the first system time-based power limit has a first time limit of less than or equal to fifteen (15) milliseconds (ms); and The second power limit based on system time has a second time limit greater than or equal to one (1) second.

[0094] 17. The power limiter circuit according to Clause 5, wherein the power limiter circuit is further configured to: The total PU subsystem power limit budget is allocated to each of the one or more PUs comprising multiple PUs; and The power consumption of each of the plurality of PUs is constrained based on the corresponding PU power limit budget allocated to each PU in the plurality of PU power limit budgets.

[0095] 18. The power limiter circuit according to Clause 17, wherein the power limiter circuit is further configured to: generate an adjusted total PU subsystem power limit budget based on a comparison of the current burst power consumption of the PU subsystem with the total PU subsystem power limit; and

[0096] The power limiter circuit is configured to allocate the plurality of PU power limit budgets from the adjusted total PU subsystem power limit budget to each of the plurality of PUs.

[0097] 19. The power limiter circuit according to Clause 17 or 18, wherein the power limiter circuit is further configured to: The current power consumption of the PU subsystem, which indicates the first current power consumption in the PU subsystem, is compared with the second PU subsystem burst power limit. A third PU subsystem burst power limit budget is generated based on the comparison between the current power consumption of the PU subsystem and the burst power limit of the second PU subsystem. The adjusted total PU subsystem power limit budget is generated based on the smaller of the total PU subsystem power limit budget and the third PU subsystem burst power limit budget; and The power limiter circuit is configured as follows: The PU power limit budget is allocated by being configured to perform the following operation: allocating the adjusted total PU subsystem power limit budget from the total PU subsystem power limit budget to each of the plurality of PUs.

[0098] 20. The power limiter circuit according to any one of clauses 17 to 19, wherein the power limiter circuit is configured to allocate the PU power limit budget by being configured to perform the following operation: allocating the PU power limit budget in the total PU subsystem power limit budget to each of the plurality of PUs based on the workload of each PU.

[0099] 21. The power limiter circuit according to any one of clauses 17 to 20, wherein the power limiter circuit is configured to allocate the PU power limit budget by being configured to allocate the PU power limit budget in the total PU subsystem power limit budget to each of the plurality of PUs based on the PU hints of each PU.

[0100] 22. The power limiter circuit according to any one of clauses 17 to 21, wherein the power limiter circuit is further configured to: generate a desired PU power limit budget for each of the plurality of PUs, the desired PU power limit budget indicating the desired power consumption of each PU; and

[0101] The power limiter circuit is configured to allocate the PU power limit budget by performing the following operation: allocating the PU power limit budget in the total PU subsystem power limit budget to each of the plurality of PUs based on the expected PU power limit budget for each PU.

[0102] 23. The power limiter circuit according to any one of clauses 1 to 22, wherein the power limiter circuit further comprises: A power estimator and budget allocation circuit, wherein the power estimator and budget allocation circuit is configured to: The current power consumption of the PU subsystem, which indicates the first current power consumption in the PU subsystem, is compared with the time-based power limit of each of the one or more PU subsystems. The system current power consumption, which indicates the second current power consumption in the processor-based system, is compared with each of the one or more system time-based power limits. The power limit budget of the one or more first PU subsystems is generated based on the comparison between the current power consumption of the PU subsystem and the time-based power limit of the corresponding one or more PU subsystems. The power limit budget for the one or more second PU subsystems is generated based on the comparison between the current power consumption of the system in the processor-based system and one or more corresponding system time-based power limits; and The total PU subsystem power limit budget is generated based on the lower power limit budget among the one or more first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets; and A PU power budget management circuit, wherein the PU power budget management circuit is configured to: The PU power limit budget in the total PU subsystem power limit budget is allocated to each of the one or more PUs that include multiple PUs; and The power consumption of each of the plurality of PUs is constrained based on the corresponding power limit budget allocated to each PU.

[0103] 24. The power limiter circuit according to Clause 23, wherein the power estimator and budget allocation circuitry comprises: One or more PU subsystem comparator circuits, each of the one or more PU subsystem comparator circuits being configured to: compare the current power consumption of the PU subsystem in the PU subsystem with a time-based power limit of the one or more PU subsystems in the PU subsystem time-based power limit; One or more system comparator circuits, each of the one or more system comparator circuits being configured to: compare the current power consumption of the system in the processor-based system with a system time-based power limit among the one or more system time-based power limits; One or more system power budget allocation circuits, each of the one or more system power budget allocation circuits being configured to: generate a second PU subsystem power limit budget in the one or more second PU subsystem power limit budgets based on a comparison between the current power consumption of the system in the processor-based system and a system time-based power limit in the one or more system time-based power limits; and A PU subsystem power budget selection circuit is configured to generate the total PU subsystem power limit budget based on the lower power limit budget among one or more first PU subsystem power limit budgets and one or more second PU subsystem power limit budgets.

[0104] 25. The power limiter circuit according to any one of clauses 1 to 24, wherein the power limiter circuit is configured to continuously repeat (a) to (f).

[0105] 26. The power limiter circuit according to any one of Clauses 1 to 25, wherein the power limiter circuit is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0106] 27. A method for limiting power consumption in a processor-based system, the processor-based system comprising a processing unit (PU) subsystem, the processing unit (PU) subsystem including one or more PUs, the method comprising: (a) The current power consumption of the PU subsystem, which indicates the first current power consumption in the PU subsystem, is compared with the time-based power limit of each of one or more time-based power limits for the PU subsystem; (b) The system current power consumption, which indicates the second current power consumption in the processor-based system, is compared with each of one or more system time-based power limits; (c) Generate one or more first PU subsystem power limit budgets based on the comparison between the current power consumption of the PU subsystem and the time-based power limits of the corresponding one or more PU subsystems; (d) Generate one or more second PU subsystem power limit budgets based on the comparison between the current power consumption of the system in the processor-based system and one or more corresponding system time-based power limits; (e) Generate a total PU subsystem power limit budget based on the lower of the one or more first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets; and (f) Make the power consumption in the PU subsystem subject to the total PU subsystem power limit budget.

[0107] 28. The method according to Clause 27, further comprising: Within the time limit of each of the one or more time-based power limits for the PU subsystems, the current power consumption of the PU subsystem is sampled to generate one or more sampled current power consumptions of the PU subsystems; and in: Comparing the current power consumption of the PU subsystem includes: comparing the current power consumption of each of the one or more sampled current power consumptions of the PU subsystem with the corresponding time-based power limit of the one or more PU subsystems; and Generating the power limit budget for the one or more first PU subsystems includes: generating the power limit budget for the one or more first PU subsystems based on the comparison between the current power consumption of the one or more sampled PU subsystems and the time-based power limits of the corresponding one or more PU subsystems.

[0108] 29. The method according to Clause 28, further comprising: The current system power consumption is sampled within a time limit of each of the one or more system time-based power limits to generate one or more sampled current system power consumptions; and in: Comparing the current system power consumption includes: comparing each of the one or more sampled current system power consumptions with the corresponding one or more system time-based power limits; and Generating the power limit budget for the one or more second PU subsystems includes generating the power limit budget for the one or more second PU subsystems based on the comparison between the current power consumption of the one or more sampled systems and the corresponding one or more power limits based on system time.

[0109] 30. The method according to any one of clauses 27 to 29, wherein the method further comprises: The time-based power limits of the one or more PU subsystems are converted into corresponding burst power limits for the one or more PU subsystems within their respective burst power time limits; and The one or more system time-based power limits are converted into one or more corresponding system burst power limits within the burst power time limits; in: Comparing the current power consumption of the PU subsystem includes: comparing the current burst power consumption of the PU subsystem, which indicates the first current burst power consumption in the PU subsystem, with each of the one or more PU subsystem burst power limits; Comparing the current power consumption of the system includes: comparing the current burst power consumption of the system, which indicates a second current burst power consumption in the processor-based system, with each of the one or more system burst power limits; Generating the one or more first PU subsystem power limit budgets includes: generating one or more first PU subsystem burst power limit budgets based on the comparison between the current burst power consumption of the PU subsystem and the corresponding one or more PU subsystem burst power limits; Generating the power limit budget for the one or more second PU subsystems includes: generating the power limit budget for the one or more second PU subsystems based on the comparison between the current burst power consumption of the system in the processor-based system and the corresponding one or more system burst power limits; Generating the total PU subsystem power limit budget includes: generating the total PU subsystem burst power limit budget based on the lower burst power limit budget among the one or more first PU subsystem burst power limit budgets and the one or more second PU subsystem burst power limit budgets; and Constraining the power consumption in the PU subsystem includes subjecting the power consumption in the PU subsystem to the total PU subsystem burst power limit budget.

[0110] 31. The method according to any one of clauses 27 to 30, wherein generating the power limit budget for the one or more second PU subsystems comprises: The system power limit budget for the processor-based system is generated based on the comparison between the current power consumption of the system in the processor-based system and one or more system time-based power limits. Generate at least one non-PU subsystem power limit budget from the system power limit budget to constrain the power of the non-PU subsystems in the processor-based system; and The power limit budget for the one or more second PU subsystems is generated based on the difference between the system power limit budget and the power limit budget for the at least one non-PU subsystem.

[0111] 32. The method according to clause 30, further comprising: In the comparison between the current burst power consumption of the PU subsystem and the corresponding burst power limit of one or more PU subsystems within the burst power time limit, the difference between the current burst power consumption of one or more PU subsystems is tracked; and The sum of one or more current burst power values ​​of the corresponding one or more PU subsystems is generated by comparing the current burst power consumption of the PU subsystem with the corresponding one or more PU subsystem burst power limits within the burst power time limit; in: Generating the burst power limit budget for the one or more first PU subsystems includes: generating the burst power limit budget for the one or more first PU subsystems based on the comparison between the sum of the current burst power of the one or more PU subsystems and the corresponding burst power limit of the one or more PU subsystems.

[0112] 33. The method according to clause 30, further comprising: The total PU subsystem power limit budget is allocated to each of the one or more PUs comprising multiple PUs; and The power consumption of each of the plurality of PUs is constrained based on the corresponding PU power limit budget allocated to each PU in the plurality of PU power limit budgets.

[0113] 34. The method according to Clause 33, further comprising: generating an adjusted total PU subsystem power limit budget by comparing the current burst power consumption of the PU subsystem with the total PU subsystem power limit budget; and

[0114] The allocation of the multiple PU power limit budgets includes: allocating the multiple PU power limit budgets from the adjusted total PU subsystem power limit budget to each of the multiple PUs.

[0115] 35. A processor-based system, the processor-based system comprising: A processing unit (PU) subsystem, the processing unit (PU) subsystem comprising one or more PUs; A non-PU subsystem, the non-PU subsystem comprising one or more non-PU devices; A PU subsystem power monitoring circuit is configured to monitor the current power consumption of the PU subsystem within the PU subsystem. A system power monitoring circuit, configured to monitor the current power consumption of the processor-based system; One or more PU power constraint circuits, each of the one or more PU power constraint circuits being configured to: constrain a PU in the one or more PUs; and A power limiter circuit, wherein the power limiter circuit is configured to: (a) The current power consumption of the PU subsystem, which indicates the first current power consumption in the PU subsystem, is compared with the time-based power limit of each of one or more time-based power limits for the PU subsystem; (b) The system current power consumption, which indicates a second current power consumption in the processor-based system, is compared with each of one or more system time-based power limits. (c) Generate one or more first PU subsystem power limit budgets based on the comparison between the current power consumption of the PU subsystem and the time-based power limits of the one or more PU subsystems; (d) Generate one or more second PU subsystem power limit budgets based on the comparison between the current power consumption of the system in the processor-based system and the one or more system time-based power limits; (e) Generate a total PU subsystem power limit budget based on the lower of the one or more first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets; and (f) Constrain the power consumption in the PU subsystem to the total PU subsystem power limit budget.

Claims

1. A power limiter circuit for limiting power consumption in a processor-based system, the processor-based system including a processing unit (PU) subsystem, the processing unit (PU) subsystem including one or more PUs, the power limiter circuit being configured to: (a) The current power consumption of the PU subsystem, which indicates the first current power consumption in the PU subsystem, is compared with the time-based power limit of each of one or more time-based power limits for the PU subsystem; (b) The system current power consumption, which indicates the second current power consumption in the processor-based system, is compared with each of one or more system time-based power limits; (c) Generate one or more first PU subsystem power limit budgets based on the comparison between the current power consumption of the PU subsystem and the time-based power limits of the one or more PU subsystems; (d) Generate one or more second PU subsystem power limit budgets based on the comparison between the current power consumption of the system in the processor-based system and one or more corresponding system time-based power limits; (e) Generate a total PU subsystem power limit budget based on the lower of the one or more first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets; and (f) Make the power consumption in the PU subsystem subject to the total PU subsystem power limit budget.

2. The power limiter circuit according to claim 1, wherein the power limiter circuit is further configured as follows: Within the time limit of each of the one or more time-based power limits for the PU subsystems, the current power consumption of the PU subsystem is sampled to generate one or more sampled current power consumptions of the PU subsystems; and The power limiter circuit is configured as follows: The current power consumption of the PU subsystem is compared by being configured to perform the following operations: comparing the current power consumption of each of the one or more sampled current power consumptions of the PU subsystem with the corresponding time-based power limit of the one or more PU subsystems; and The power limit budget for the one or more first PU subsystems is generated based on the comparison between the current power consumption of the one or more sampled PU subsystems and the time-based power limits of the corresponding one or more PU subsystems.

3. The power limiter circuit according to claim 2, wherein the power limiter circuit is further configured as follows: Within the time limit of each of the one or more system time-based power limits, the current system power consumption is sampled to generate one or more sampled current system power consumptions; and The power limiter circuit is configured as follows: The system current power consumption is compared by being configured to perform the following operations: comparing each of the one or more sampled system current power consumptions with the corresponding one or more system time-based power limits; and The power limit budget of the one or more second PU subsystems is generated based on the comparison between the current power consumption of the one or more sampled systems and the corresponding one or more power limits based on system time.

4. The power limiter circuit according to claim 1, wherein the power limiter circuit is further configured as follows: Based on the burst power time limit, the power limit budget of the one or more first PU subsystems is converted into the corresponding burst power limit budget of the one or more first PU subsystems; Based on the burst power time limit, the power limit budget of the one or more second PU subsystems is converted into the corresponding burst power limit budget of the one or more second PU subsystems; and The power limiter circuit is configured as follows: The total PU subsystem power limit budget is generated based on the lower power limit budget among the one or more first PU subsystem burst power limit budgets and the one or more second PU subsystem burst power limit budgets.

5. The power limiter circuit according to claim 1, wherein the power limiter circuit is further configured as follows: The time-based power limits of the one or more PU subsystems are converted into corresponding burst power limits of the one or more PU subsystems within the burst power time limit; The one or more system time-based power limits are converted into one or more corresponding system burst power limits within the burst power time limits; and The power limiter circuit is configured as follows: The current power consumption of the PU subsystem is compared by being configured to perform the following operation: the current burst power consumption of the PU subsystem, which indicates the first current burst power consumption in the PU subsystem, is compared with each of the one or more PU subsystem burst power limits; The current power consumption of the system is compared by being configured to perform the following operation: comparing the current burst power consumption of the system, which indicates the second current burst power consumption of the processor-based system, with each of the one or more system burst power limits; The one or more first PU subsystem power limit budgets are generated by being configured to perform the following operations: generating one or more first PU subsystem burst power limit budgets based on the comparison between the current burst power consumption of the PU subsystem in the PU subsystem and the corresponding one or more PU subsystem burst power limits; The one or more second PU subsystem power limit budgets are generated by being configured to perform the following operations: generating one or more second PU subsystem burst power limit budgets based on the comparison between the current burst power consumption of the system in the processor-based system and the corresponding one or more system burst power limits; The total PU subsystem power limit budget is generated by being configured to perform the following operations: generating the total PU subsystem burst power limit budget based on the lower burst power limit budget among the one or more first PU subsystem burst power limit budgets and the one or more second PU subsystem burst power limit budgets; and The power consumption in the PU subsystem is subject to the total PU subsystem burst power limit budget constraint.

6. The power limiter circuit according to claim 5, wherein the burst power time limit is less than or equal to fifteen (15) milliseconds (ms).

7. The power limiter circuit of claim 1, wherein the power limiter circuit is configured to generate a power limit budget for the one or more second PU subsystems based on a comparison of the current power consumption of the system with the one or more power limits based on system time, wherein the current power consumption of the system includes the current power consumption of the battery and battery charger in the processor-based system.

8. The power limiter circuit according to claim 1, wherein the power limiter circuit is configured as follows: The power limit budget for the one or more first PU subsystems is generated by being configured to: reduce the power limit budget for the one or more first PU subsystems based on a comparison of the first current power consumption in the PU subsystem being greater than the time-based power limit of the one or more PU subsystems; and The one or more second PU subsystem power limit budgets are generated by being configured to reduce the power limit budgets of the one or more second PU subsystems based on a comparison of the current power consumption of the system in the processor-based system being greater than the one or more system time-based power limits.

9. The power limiter circuit according to claim 1, wherein the power limiter circuit is configured as follows: The power limit budget for the one or more first PU subsystems is generated by being configured to: increase the power limit budget for the one or more first PU subsystems based on a comparison of the first current power consumption in the PU subsystem being less than the time-based power limit of the one or more PU subsystems; and The one or more second PU subsystem power limit budgets are generated by being configured to increase the power limit budgets of the one or more second PU subsystems based on a comparison of the current power consumption of the system in the processor-based system being less than the one or more system time-based power limits.

10. The power limiter circuit of claim 1, wherein the power limiter circuit is configured to generate the power limit budget for the one or more second PU subsystems by being configured to perform the following operations: The system power limit budget for the processor-based system is generated based on the comparison between the current power consumption of the system in the processor-based system and one or more system time-based power limits. Generate at least one non-PU subsystem power limit budget from the system power limit budget to constrain the power of the non-PU subsystems in the processor-based system; and The power limit budget for the one or more second PU subsystems is generated based on the difference between the system power limit budget and the power limit budget for the at least one non-PU subsystem.

11. The power limiter circuit according to claim 5, wherein the power limiter circuit is further configured to: In the comparison between the current burst power consumption of the PU subsystem and the corresponding burst power limit of one or more PU subsystems within the burst power time limit, the difference between the current burst power of one or more PU subsystems is tracked. The sum of one or more current burst power values ​​of the corresponding one or more PU subsystems is generated by comparing the current burst power consumption of the PU subsystem with the corresponding one or more PU subsystem burst power limits within the burst power time limit; and The burst power limit budget for the one or more first PU subsystems is generated based on the comparison between the current sum of burst power of the one or more PU subsystems and the corresponding burst power limit of the one or more PU subsystems.

12. The power limiter circuit according to claim 5, wherein the power limiter circuit is further configured to: In the comparison between the current burst power consumption of the system and one or more corresponding system burst power limits within the burst power time limit in the processor-based system, one or more current system burst power differences are tracked. In the comparison between the current burst power consumption of the system and one or more corresponding system burst power limits within the burst power time limit in the processor-based system, a sum of one or more system current burst power differences is generated; and The burst power limit budget for the one or more second PU subsystems is generated based on the comparison between the sum of the current burst power of the one or more systems and the corresponding burst power limit of the one or more systems.

13. The power limiter circuit according to claim 1, wherein the power limiter circuit is configured as follows: The current power consumption of the PU subsystem is compared with the time-based power limit of each of the multiple time-based power limits for PU subsystems; The power limit budgets for the one or more first PU subsystems are generated by being configured to perform the following operations: generating a plurality of first PU subsystem power limit budgets based on a comparison between the current power consumption of the PU subsystems and the time-based power limit of each of the plurality of PU subsystems; and The total PU subsystem power limit budget is generated based on the lower power limit budget among the plurality of first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets.

14. The power limiter circuit of claim 13, wherein the time-based power limits of the plurality of PU subsystems include: The first PU subsystem has a time-based power limit, which has a first time limit of less than or equal to fifteen (15) milliseconds (ms). and The second PU subsystem has a time-based power limit, which has a second time limit greater than or equal to one (1) second.

15. The power limiter circuit according to claim 1, wherein the power limiter circuit is configured to: The current power consumption of the system is compared with each of a plurality of system time-based power limits; The one or more second PU subsystem power limit budgets are generated by being configured to perform the following operations: generating multiple second PU subsystem power limit budgets based on the comparison of the current power consumption of the system in the processor-based system with the corresponding multiple system time-based power limits; and The total PU subsystem power limit budget is generated based on the lower power limit budget among the one or more first PU subsystem power limit budgets and the plurality of second PU subsystem power limit budgets.

16. The power limiter circuit of claim 15, wherein the plurality of system time-based power limits include: A first system time-based power limit, wherein the first system time-based power limit has a first time limit of less than or equal to fifteen (15) milliseconds (ms); and The second power limit based on system time has a second time limit greater than or equal to one (1) second.

17. The power limiter circuit according to claim 5, wherein the power limiter circuit is further configured to: The total PU subsystem power limit budget is allocated to each of the one or more PUs comprising multiple PUs; and The power consumption of each of the plurality of PUs is constrained based on the corresponding PU power limit budget allocated to each PU in the plurality of PU power limit budgets.

18. The power limiter circuit of claim 17, further configured to: generate an adjusted total PU subsystem power limit budget based on a comparison between the current burst power consumption of the PU subsystem and the total PU subsystem power limit; and The power limiter circuit is configured to allocate the plurality of PU power limit budgets from the adjusted total PU subsystem power limit budget to each of the plurality of PUs.

19. The power limiter circuit of claim 17, wherein the power limiter circuit is further configured to: The current power consumption of the PU subsystem, which indicates the first current power consumption in the PU subsystem, is compared with the second PU subsystem burst power limit. A third PU subsystem burst power limit budget is generated based on the comparison between the current power consumption of the PU subsystem and the burst power limit of the second PU subsystem. The adjusted total PU subsystem power limit budget is generated based on the smaller of the total PU subsystem power limit budget and the third PU subsystem burst power limit budget; and The power limiter circuit is configured as follows: The PU power limit budget is allocated by being configured to perform the following operation: allocating the adjusted total PU subsystem power limit budget from the total PU subsystem power limit budget to each of the plurality of PUs.

20. The power limiter circuit of claim 17, wherein the power limiter circuit is configured to allocate the PU power limit budget by being configured to perform the following operation: allocating the PU power limit budget in the total PU subsystem power limit budget to each of the plurality of PUs based on the workload of each PU.

21. The power limiter circuit of claim 17, wherein the power limiter circuit is configured to allocate the PU power limit budget by being configured to perform the following operation: allocating the PU power limit budget in the total PU subsystem power limit budget to each of the plurality of PUs based on the PU hints of each PU.

22. The power limiter circuit of claim 17, further configured to: generate a desired PU power limit budget for each of the plurality of PUs, the desired PU power limit budget indicating the desired power consumption of each PU; and The power limiter circuit is configured to allocate the PU power limit budget by performing the following operation: allocating the PU power limit budget in the total PU subsystem power limit budget to each of the plurality of PUs based on the expected PU power limit budget for each PU.

23. The power limiter circuit according to claim 1, wherein the power limiter circuit further comprises: A power estimator and budget allocation circuit, wherein the power estimator and budget allocation circuit is configured to: The current power consumption of the PU subsystem, which indicates the first current power consumption in the PU subsystem, is compared with the time-based power limit of each of the one or more PU subsystems. The system current power consumption, which indicates the second current power consumption in the processor-based system, is compared with each of the one or more system time-based power limits. The power limit budget of the one or more first PU subsystems is generated based on the comparison between the current power consumption of the PU subsystem and the time-based power limit of the corresponding one or more PU subsystems. The power limit budget for the one or more second PU subsystems is generated based on the comparison between the current power consumption of the system in the processor-based system and one or more corresponding system time-based power limits; and The total PU subsystem power limit budget is generated based on the lower power limit budget among the one or more first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets; and A PU power budget management circuit, wherein the PU power budget management circuit is configured to: The PU power limit budget in the total PU subsystem power limit budget is allocated to each of the one or more PUs that include multiple PUs; and The power consumption of each of the plurality of PUs is constrained based on the corresponding PU power limit budget allocated to each PU.

24. The power limiter circuit of claim 23, wherein the power estimator and budget allocation circuit comprises: One or more PU subsystem comparator circuits, each of the one or more PU subsystem comparator circuits being configured to: compare the current power consumption of the PU subsystem in the PU subsystem with a time-based power limit of the one or more PU subsystems in the PU subsystem time-based power limit; One or more system comparator circuits, each of the one or more system comparator circuits being configured to: compare the current power consumption of the system in the processor-based system with a system time-based power limit among the one or more system time-based power limits; One or more system power budget allocation circuits, each of the one or more system power budget allocation circuits being configured to: generate a second PU subsystem power limit budget in the one or more second PU subsystem power limit budgets based on a comparison between the current power consumption of the system in the processor-based system and the power limit based on the system time in the one or more system time-based power limits; and A PU subsystem power budget selection circuit is configured to generate the total PU subsystem power limit budget based on the lower power limit budget among one or more first PU subsystem power limit budgets and one or more second PU subsystem power limit budgets.

25. The power limiter circuit of claim 1, wherein the power limiter circuit is configured to continuously repeat (a) to (f).

26. The power limiter circuit of claim 1, wherein the power limiter circuit is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

27. A method for limiting power consumption in a processor-based system, the processor-based system comprising a processing unit (PU) subsystem, the processing unit (PU) subsystem including one or more PUs, the method comprising: (a) The current power consumption of the PU subsystem, which indicates the first current power consumption in the PU subsystem, is compared with the time-based power limit of each of one or more time-based power limits for the PU subsystem; (b) The system current power consumption, which indicates the second current power consumption in the processor-based system, is compared with each of one or more system time-based power limits; (c) Generate one or more first PU subsystem power limit budgets based on the comparison between the current power consumption of the PU subsystem and the time-based power limits of the corresponding one or more PU subsystems; (d) Generate one or more second PU subsystem power limit budgets based on the comparison between the current power consumption of the system in the processor-based system and one or more corresponding system time-based power limits; (e) Generate a total PU subsystem power limit budget based on the lower of the one or more first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets; and (f) Make the power consumption in the PU subsystem subject to the total PU subsystem power limit budget.

28. The method of claim 27, further comprising: Within the time limit of each of the one or more time-based power limits for the PU subsystems, the current power consumption of the PU subsystem is sampled to generate one or more sampled current power consumptions of the PU subsystems; and in: Comparing the current power consumption of the PU subsystem includes: comparing the current power consumption of each of the one or more sampled current power consumptions of the PU subsystem with the time-based power limit of the corresponding one or more PU subsystems; and Generating the power limit budget for the one or more first PU subsystems includes: generating the power limit budget for the one or more first PU subsystems based on the comparison between the current power consumption of the one or more sampled PU subsystems and the time-based power limits of the corresponding one or more PU subsystems.

29. The method according to claim 28, further comprising: The current power consumption of the system is sampled within the time limit of each of the one or more system time-based power limits to generate one or more sampled current power consumptions of the system. and in: Comparing the current system power consumption includes: comparing each of the one or more sampled current system power consumptions with the corresponding one or more system time-based power limits; and Generating the power limit budget for the one or more second PU subsystems includes generating the power limit budget for the one or more second PU subsystems based on the comparison between the current power consumption of the one or more sampled systems and the corresponding one or more power limits based on system time.

30. The method of claim 27, further comprising: The time-based power limits of the one or more PU subsystems are converted into corresponding burst power limits for the one or more PU subsystems within their respective burst power time limits; and The one or more system time-based power limits are converted into one or more corresponding system burst power limits within the burst power time limits; in: Comparing the current power consumption of the PU subsystem includes: comparing the current burst power consumption of the PU subsystem, which indicates the first current burst power consumption in the PU subsystem, with each of the one or more PU subsystem burst power limits; Comparing the current power consumption of the system includes: comparing the current burst power consumption of the system, which indicates a second current burst power consumption in the processor-based system, with each of the one or more system burst power limits; Generating the one or more first PU subsystem power limit budgets includes: generating one or more first PU subsystem burst power limit budgets based on the comparison between the current burst power consumption of the PU subsystem and the corresponding one or more PU subsystem burst power limits; Generating the power limit budget for the one or more second PU subsystems includes: generating the power limit budget for the one or more second PU subsystems based on the comparison between the current burst power consumption of the system in the processor-based system and the corresponding one or more system burst power limits; Generating the total PU subsystem power limit budget includes: generating the total PU subsystem burst power limit budget based on the lower burst power limit budget among the one or more first PU subsystem burst power limit budgets and the one or more second PU subsystem burst power limit budgets; and Constraining the power consumption in the PU subsystem includes subjecting the power consumption in the PU subsystem to the total PU subsystem burst power limit budget.

31. The method of claim 27, wherein generating the power limit budget for the one or more second PU subsystems comprises: The system power limit budget for the processor-based system is generated based on the comparison between the current power consumption of the system in the processor-based system and one or more system time-based power limits. Generate at least one non-PU subsystem power limit budget from the system power limit budget to constrain the power of the non-PU subsystems in the processor-based system; and The power limit budget for the one or more second PU subsystems is generated based on the difference between the system power limit budget and the power limit budget for the at least one non-PU subsystem.

32. The method according to claim 30, further comprising: In the comparison between the current burst power consumption of the PU subsystem and the corresponding burst power limit of one or more PU subsystems within the burst power time limit, the difference between the current burst power consumption of one or more PU subsystems is tracked; and The sum of one or more current burst power values ​​of the corresponding one or more PU subsystems is generated by comparing the current burst power consumption of the PU subsystem with the corresponding one or more PU subsystem burst power limits within the burst power time limit; in: Generating the burst power limit budget for the one or more first PU subsystems includes: generating the burst power limit budget for the one or more first PU subsystems based on the comparison between the sum of the current burst power of the one or more PU subsystems and the corresponding burst power limit of the one or more PU subsystems.

33. The method according to claim 30, further comprising: The total PU subsystem power limit budget is allocated to each of the one or more PUs comprising multiple PUs; and The power consumption of each of the plurality of PUs is constrained based on the corresponding PU power limit budget allocated to each PU in the plurality of PU power limit budgets.

34. The method according to claim 33, further comprising: An adjusted total PU subsystem power limit budget is generated by comparing the current burst power consumption of the PU subsystem with the total PU subsystem power limit budget. and The allocation of the multiple PU power limit budgets includes: allocating the multiple PU power limit budgets from the adjusted total PU subsystem power limit budget to each of the multiple PUs.

35. A processor-based system, the processor-based system comprising: A processing unit (PU) subsystem, the processing unit (PU) subsystem comprising one or more PUs; A non-PU subsystem, the non-PU subsystem comprising one or more non-PU devices; A PU subsystem power monitoring circuit is configured to monitor the current power consumption of the PU subsystem within the PU subsystem. A system power monitoring circuit, configured to monitor the current power consumption of the processor-based system; One or more PU power constraint circuits, each of the one or more PU power constraint circuits being configured to: constrain a PU in the one or more PUs; and A power limiter circuit, wherein the power limiter circuit is configured to: (a) The current power consumption of the PU subsystem, which indicates the first current power consumption in the PU subsystem, is compared with the time-based power limit of each of one or more time-based power limits for the PU subsystem; (b) The system current power consumption, which indicates a second current power consumption in the processor-based system, is compared with each of one or more system time-based power limits. (c) Generate one or more first PU subsystem power limit budgets based on the comparison between the current power consumption of the PU subsystem and the time-based power limits of the one or more PU subsystems; (d) Generate one or more second PU subsystem power limit budgets based on the comparison between the current power consumption of the system in the processor-based system and the one or more system time-based power limits; (e) Generate a total PU subsystem power limit budget based on the lower of the one or more first PU subsystem power limit budgets and the one or more second PU subsystem power limit budgets; and (f) Constrain the power consumption in the PU subsystem to the total PU subsystem power limit budget.

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