Pixel circuit, pixel driving method and display device

Abstract

The invention provides a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a light-emitting element, a driving circuit and a compensation control circuit. The pixel circuit further comprises a first energy storage circuit. The first energy storage circuit controls the potential of the first end of the first energy storage circuit according to the first bias voltage signal; the first bias voltage signal is a variable voltage signal; and / or the pixel circuit further comprises a second energy storage circuit; the compensation control circuit comprises a first compensation circuit and a second compensation circuit; the second energy storage circuit controls the potential of the first end of the second energy storage circuit according to the second bias voltage signal; the second bias voltage signal is a variable voltage signal. The driving transistor can be subjected to fixed bias, and the threshold voltage of the driving transistor is recovered, so that the brightness uniformity can be well maintained under each frequency.

Description

Pixel circuit, pixel driving method and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a pixel circuit, a pixel driving method and a display device. BACKGROUND

[0002] With the increase of resolution and frequency of the display device, the driving power consumption of the screen is further improved. In order to reduce the driving power consumption, the display screen needs to be reduced in frequency. However, the randomness of the driving frequency will cause the output of the thin film transistor to be random, resulting in a flashing screen phenomenon when the frequency changes.

[0003] SUMMARY

[0004] In one aspect, the pixel circuit comprises a light emitting element, a driving circuit and a compensation control circuit.

[0005] The control end of the driving circuit is electrically connected with the first node, the first end of the driving circuit is electrically connected with the second node, and the second end of the driving circuit is electrically connected with the third node. The driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node.

[0006] The compensation control circuit is electrically connected with the compensation control end, the first node and the third node respectively, and is used for controlling the communication or disconnection between the first node and the third node under the control of a compensation control signal provided by the compensation control end.

[0007] The pixel circuit further comprises a first energy storage circuit. The first end of the first energy storage circuit is electrically connected with the second node or the third node, and the second end of the first energy storage circuit is electrically connected with a first bias voltage end. The first energy storage circuit is used for controlling the potential of the first end of the first energy storage circuit according to a first bias voltage signal provided by the first bias voltage end. The first bias voltage signal is a variable voltage signal; and / or,

[0008] The pixel circuit further comprises a second energy storage circuit; the compensation control circuit comprises a first compensation circuit and a second compensation circuit; the first compensation circuit is electrically connected with the compensation control end, the first node and an intermediate node respectively, and is used for controlling the first node and the intermediate node to be connected or disconnected under the control of a compensation control signal provided by the compensation control end; the second compensation circuit is electrically connected with the compensation control end, the intermediate node and the third node respectively, and is used for controlling the intermediate node and the third node to be connected or disconnected under the control of a compensation control signal provided by the compensation control end; a first end of the second energy storage circuit is electrically connected with the intermediate node, and a second end of the second energy storage circuit is electrically connected with a second bias voltage end, and the second energy storage circuit is used for controlling the potential of the first end of the second energy storage circuit according to a second bias voltage signal provided by the second bias voltage end; the second bias voltage signal is a variable voltage signal.

[0009] Optionally, the pixel circuit further comprises a data writing circuit, a third energy storage circuit and a first initialization circuit.

[0010] The data writing circuit is electrically connected with a writing control end, a data line and the second node respectively, and is used for controlling the data line and the second node to be connected or disconnected under the control of a writing control signal provided by the writing control end;

[0011] The third energy storage circuit is electrically connected with the first node, and is used for maintaining the potential of the first node;

[0012] The first initialization circuit is electrically connected with a reset control end and a first initial voltage end respectively, and is further electrically connected with the first node or the third node, and is used for controlling a first initial voltage provided by the first initial voltage end to be written into the first node or the third node under the control of a reset control signal provided by the reset control end.

[0013] Optionally, the pixel circuit further comprises a fourth energy storage circuit, a fifth energy storage circuit, a data writing circuit, a first control circuit, a second control circuit and a sixth energy storage circuit.

[0014] A first end of the fourth energy storage circuit is electrically connected with the first node, a second end of the fourth energy storage circuit is electrically connected with a first control node, a first end of the fifth energy storage circuit is electrically connected with the first control node, and a second end of the fifth energy storage circuit is electrically connected with a writing node, and the fourth energy storage circuit and the fifth energy storage circuit are used for storing electric energy;

[0015] The data writing circuit is electrically connected with a writing control end, a data line and the writing node respectively, and is configured to control the data line and the writing node to be in communication or disconnected under the control of a writing control signal provided by the writing control end.

[0016] The first control circuit is electrically connected with a turn-on / off control end, the first control node and the second control node respectively, and is configured to control the first control node and the second control node to be in communication or disconnected under the control of a turn-on / off control signal provided by the turn-on / off control end.

[0017] The second control circuit is electrically connected with the turn-on / off control end, the second control node and a second voltage end respectively, and is configured to control the second control node and the second voltage end to be in communication or disconnected under the control of the turn-on / off control signal.

[0018] The first end of the sixth energy storage circuit is electrically connected with the second control node, and the second end of the sixth energy storage circuit is electrically connected with a third bias voltage end, and the sixth energy storage circuit is configured to control the electric potential of the second control node according to a third bias voltage signal provided by the third bias voltage end; the third bias voltage signal is a variable voltage signal.

[0019] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a setting circuit.

[0020] The setting circuit is electrically connected with a setting control end, a setting voltage end and the writing node respectively, and is configured to control the setting voltage end and the writing node to be in communication or disconnected under the control of a setting control signal provided by the setting control end.

[0021] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a first light-emitting control circuit, a second light-emitting control circuit and a second initialization circuit.

[0022] The first light-emitting control circuit is electrically connected with a first light-emitting control end, a power voltage end and the second node respectively, and is configured to control the power voltage end and the second node to be in communication or disconnected under the control of a first light-emitting control signal provided by the first light-emitting control end.

[0023] The second light-emitting control circuit is electrically connected with a second light-emitting control end, the third node and the first pole of the light-emitting element respectively, and is configured to control the third node and the first pole of the light-emitting element to be in communication or disconnected under the control of a second light-emitting control signal provided by the second light-emitting control end.

[0024] The second initialization circuit is electrically connected with the initial control end, the second initial voltage end and the first electrode of the light emitting element respectively, and is configured to control the second initial voltage end to be connected or disconnected with the first electrode of the light emitting element under the control of an initial control signal provided by the initial control end.

[0025] The second electrode of the light emitting element is electrically connected with the first voltage end.

[0026] Optionally, the first bias voltage end is configured to change the potential of the first end of the first energy storage circuit by providing a first bias voltage signal in a bias stage, so that a driving transistor included in the driving circuit is in a bias state.

[0027] The display period of the pixel circuit includes a bias stage, a data writing stage and a light emitting stage which are independent of each other.

[0028] Optionally, the second bias voltage end is configured to change the potential of the first end of the second energy storage circuit by providing a second bias voltage signal in the bias stage, so as to reduce the leakage current of the first node.

[0029] The display period of the pixel circuit includes a bias stage, a data writing stage and a light emitting stage which are independent of each other.

[0030] The first compensation circuit is configured to control the first node to be disconnected with the intermediate node under the control of the compensation control signal in the bias stage.

[0031] The second compensation circuit is configured to control the intermediate node to be disconnected with the third node under the control of the compensation control signal in the bias stage.

[0032] Optionally, the third bias voltage end is configured to change the potential of the second control node by providing a third bias voltage signal in a bias voltage stage, so as to reduce the leakage current of the first control node.

[0033] The display period of the pixel circuit includes a bias voltage stage and a light emitting stage which are independent of each other.

[0034] The first control circuit is configured to control the first control node to be disconnected with the second control node under the control of the on-off control signal in the bias voltage stage.

[0035] The second control circuit is configured to control the second control node to be disconnected with the second voltage end under the control of the on-off control signal in the bias voltage stage.

[0036] Optionally, the driving circuit includes a driving transistor, and the first energy storage circuit includes a first capacitor.

[0037] The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node.

[0038] The first end of the first capacitor is electrically connected with the second node or the third node, and the second end of the first capacitor is electrically connected with the first bias voltage end.

[0039] Optionally, the first compensation circuit comprises a first transistor, the second compensation circuit comprises a second transistor, and the second energy storage circuit comprises a second capacitor.

[0040] The gate of the first transistor is electrically connected with the compensation control end, the first pole of the first transistor is electrically connected with the first node, and the second pole of the first transistor is electrically connected with the intermediate node.

[0041] The gate of the second transistor is electrically connected with the compensation control end, the first pole of the second transistor is electrically connected with the intermediate node, and the second pole of the second transistor is electrically connected with the third node.

[0042] The first end of the second capacitor is electrically connected with the intermediate node, and the second end of the second capacitor is electrically connected with the second bias voltage end.

[0043] Optionally, the compensation control circuit comprises a first transistor.

[0044] The gate of the first transistor is electrically connected with the compensation control end, the first pole of the first transistor is electrically connected with the first node, and the second pole of the first transistor is electrically connected with the third node.

[0045] Optionally, the data writing circuit comprises a third transistor, the third energy storage circuit comprises a third capacitor, and the first initialization circuit comprises a fourth transistor.

[0046] The gate of the third transistor is electrically connected with the writing control end, the first pole of the third transistor is electrically connected with the data line, and the second pole of the third transistor is electrically connected with the second node.

[0047] The first end of the third capacitor is electrically connected with the first node, and the second end of the third capacitor is electrically connected with a direct current voltage end.

[0048] The gate of the fourth transistor is electrically connected with a reset control end, the first pole of the fourth transistor is electrically connected with the first initial voltage end, and the second pole of the fourth transistor is electrically connected with the first node or the third node.

[0049] Optionally, the first light-emitting control circuit comprises a fifth transistor, the second light-emitting control circuit comprises a sixth transistor, and the second initialization circuit comprises a seventh transistor;

[0050] The gate of the fifth transistor is electrically connected with the light-emitting control end, the first pole of the fifth transistor is electrically connected with the power voltage end, and the second pole of the fifth transistor is electrically connected with the second node.

[0051] The gate of the sixth transistor is electrically connected with the light-emitting control end, the first pole of the sixth transistor is electrically connected with the third node, and the second pole of the sixth transistor is electrically connected with the first pole of the light-emitting element.

[0052] The gate of the seventh transistor is electrically connected with the initialization control end, the first pole of the seventh transistor is electrically connected with the second initialization voltage end, and the second pole of the seventh transistor is electrically connected with the first pole of the light-emitting element.

[0053] Optionally, the fourth energy storage circuit comprises a fourth capacitor, the fifth energy storage circuit comprises a fifth capacitor, the data writing circuit comprises a third transistor, the first control circuit comprises an eighth transistor, the second control circuit comprises a ninth transistor, and the sixth energy storage circuit comprises a sixth capacitor.

[0054] The first end of the fourth capacitor is electrically connected with the first node, the second end of the fourth capacitor is electrically connected with the first control node, the first end of the fifth capacitor is electrically connected with the first control node, and the second end of the fifth capacitor is electrically connected with the writing node.

[0055] The gate of the third transistor is electrically connected with the writing control end, the first pole of the third transistor is electrically connected with the data line, and the second pole of the third transistor is electrically connected with the writing node.

[0056] The gate of the eighth transistor is electrically connected with the on-off control end, the first pole of the eighth transistor is electrically connected with the first control node, and the second pole of the eighth transistor is electrically connected with the second control node.

[0057] The gate of the ninth transistor is electrically connected with the on-off control end, the first pole of the ninth transistor is electrically connected with the second control node, and the second pole of the ninth transistor is electrically connected with the second voltage end.

[0058] The first end of the sixth capacitor is electrically connected with the second control node, and the second end of the sixth capacitor is electrically connected with the third bias voltage end.

[0059] Optionally, the setting circuit comprises a tenth transistor.

[0060] The gate of the tenth transistor is electrically connected with the set control end, the first pole of the tenth transistor is electrically connected with the set voltage end, and the second pole of the tenth transistor is electrically connected with the write node.

[0061] In a second aspect, the pixel driving method is applied to the pixel circuit, and a display period includes a bias stage and a light emitting stage arranged in sequence.

[0062] In the bias stage, the potential of the first terminal of the first energy storage circuit is changed by the first bias voltage signal, so that the driving transistor included in the driving circuit is in a bias state; and / or, in the bias stage, the potential of the first terminal of the second energy storage circuit is changed by the second bias voltage signal, so as to reduce the leakage current of the first node.

[0063] In the light emitting stage, the driving circuit generates a driving current for driving the light emitting element.

[0064] Optionally, the pixel circuit further includes a data writing circuit; the data writing circuit is electrically connected with the write control end, the data line and the second node respectively; the display period further includes a data writing stage arranged before the light emitting stage, and the data writing stage is independent of the bias stage; and the pixel driving method includes:

[0065] In the data writing stage, the data writing circuit writes the data voltage provided by the data line into the second node under the control of the write control signal.

[0066] In the bias stage, the compensation control circuit controls the disconnection between the first node and the third node under the control of the compensation control signal.

[0067] Optionally, the pixel circuit further includes a fourth energy storage circuit, a fifth energy storage circuit, a data writing circuit, a first control circuit, a second control circuit and a sixth energy storage circuit; the display period further includes a bias voltage stage; the bias voltage stage is arranged before the light emitting stage; and the pixel driving method includes:

[0068] In the bias voltage stage, the potential of the second control node is changed by providing a third bias voltage signal, so as to reduce the leakage current of the first control node; the first control circuit controls the disconnection between the first control node and the second control node under the control of a switch control signal; and the second control circuit controls the disconnection between the second control node and the second voltage end under the control of the switch control signal.

[0069] Optionally, the display period is a refresh frame, and a holding frame includes a holding bias stage and a holding light emitting stage arranged in sequence; and the pixel driving method further includes:

[0070] In the holding bias stage, the potential of the first terminal of the first energy storage circuit is changed by the first bias voltage signal, so that the driving transistor is in a bias state; and / or, in the holding bias stage, the potential of the first terminal of the second energy storage circuit is changed by the second bias voltage signal, so as to reduce the leakage current of the first node;

[0071] In the holding bias stage, the compensation control circuit controls the disconnection between the first node and the third node under the control of the compensation control signal.

[0072] In the holding light-emitting stage, the driving circuit generates a driving current for driving the light-emitting element.

[0073] Optionally, the pixel circuit further comprises a data writing circuit; the data writing circuit is electrically connected with the writing control end, the data line and the second node respectively; and the pixel driving method further comprises:

[0074] In the holding bias stage, the data writing circuit controls the disconnection between the data line and the second node under the control of the writing control signal.

[0075] Optionally, the pixel circuit further comprises a fourth energy storage circuit, a fifth energy storage circuit, a data writing circuit, a first control circuit, a second control circuit and a sixth energy storage circuit; the holding frame further comprises a holding bias stage arranged before the holding light-emitting stage; and the pixel driving method further comprises:

[0076] In the holding bias stage, the potential of the second control node is changed by providing a third bias voltage signal, so as to reduce the leakage current of the first control node; the first control circuit controls the disconnection between the first control node and the second control node under the control of the on-off control signal; and the second control circuit controls the disconnection between the second control node and the second voltage terminal under the control of the on-off control signal.

[0077] In a third aspect, the embodiments of the present disclosure provide a display device comprising the pixel circuit. BRIEF DESCRIPTION OF DRAWINGS

[0078] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] FIG. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0082] FIG. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] FIG. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0084] FIG. 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0085] FIG. 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0086] FIG. 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0087] FIG. 10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0088] FIG. 11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0089] FIG. 12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0090] FIG. 13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0091] FIG. 14 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0092] FIG. 15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0093] FIG. 16A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0094] FIG. 16B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0095] FIG. 17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0096] FIG. 18 is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 17;

[0097] FIG. 19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0098] FIG. 20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0099] FIG. 21 is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 20;

[0100] FIG. 22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0101] FIG. 23 is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 22;

[0102] FIG. 24 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0103] FIG. 25 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0104] FIG. 26 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0105] FIG. 27 is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 26;

[0106] FIG. 28 is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 26. DETAILED DESCRIPTION

[0107] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the protection scope of the present disclosure.

[0108] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as the first pole and the other is referred to as the second pole.

[0109] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0110] The pixel circuit according to the embodiments of the present disclosure includes a light emitting element, a driving circuit and a compensation control circuit.

[0111] The control end of the driving circuit is electrically connected with the first node, the first end of the driving circuit is electrically connected with the second node, and the second end of the driving circuit is electrically connected with the third node. The driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node.

[0112] The compensation control circuit is electrically connected with the compensation control end, the first node and the third node respectively, and is configured to control the communication or disconnection between the first node and the third node under the control of a compensation control signal provided by the compensation control end.

[0113] The pixel circuit further comprises a first energy storage circuit; a first end of the first energy storage circuit is electrically connected with the second node or the third node, a second end of the first energy storage circuit is electrically connected with a first bias voltage terminal, and the first energy storage circuit is configured to control the potential of the first end of the first energy storage circuit according to a first bias voltage signal provided by the first bias voltage terminal; the first bias voltage signal is a variable voltage signal; and / or,

[0114] The pixel circuit further comprises a second energy storage circuit; the compensation control circuit comprises a first compensation circuit and a second compensation circuit; the first compensation circuit is electrically connected with a compensation control terminal, the first node and an intermediate node respectively, and is configured to control the communication or disconnection between the first node and the intermediate node under the control of a compensation control signal provided by the compensation control terminal; the second compensation circuit is electrically connected with the compensation control terminal, the intermediate node and the third node respectively, and is configured to control the communication or disconnection between the intermediate node and the third node under the control of the compensation control signal provided by the compensation control terminal; a first end of the second energy storage circuit is electrically connected with the intermediate node, and a second end of the second energy storage circuit is electrically connected with a second bias voltage terminal, and the second energy storage circuit is configured to control the potential of the first end of the second energy storage circuit according to a second bias voltage signal provided by the second bias voltage terminal; the second bias voltage signal is a variable voltage signal.

[0115] In the pixel circuit according to at least one of the embodiments of the present disclosure, the pixel circuit can comprise a first energy storage circuit, the source / drain of the driving transistor in the driving circuit can be biased in a capacitive jump mode of the first energy storage circuit, and variable refresh frequency adjustment of the pixel can be achieved.

[0116] In the pixel circuit according to at least one of the embodiments of the present disclosure, the pixel circuit can further comprise a second energy storage circuit, the compensation control circuit can comprise a first compensation circuit and a second compensation circuit connected in series with each other, the first compensation circuit and the second compensation circuit are electrically connected with each other through an intermediate node, a first end of the second energy storage circuit is electrically connected with the intermediate node, and a second end of the second energy storage circuit is electrically connected with a second bias voltage terminal; when the voltage value of a second bias voltage signal provided by the second bias voltage terminal changes, the potential of the intermediate node changes, so as to reduce the difference between the potential of the first node and the potential of the intermediate node, and reduce the leakage current of the first node.

[0117] In the biasing phase, the first compensation circuit controls the disconnection between the first node and the intermediate node under the control of the compensation control signal; and the second compensation circuit controls the disconnection between the intermediate node and the third node under the control of the compensation control signal.

[0118] In the related art, as the resolution and frequency of the display device increase, the driving power consumption of the display screen further increases. In order to reduce the driving power consumption, the display screen needs to be subjected to noise reduction processing. However, the randomness of the driving frequency can cause the output of the thin film transistor to be random, resulting in a flashing screen phenomenon when the frequency changes. Based on the above problems, at least one embodiment of the present disclosure adopts a first energy storage circuit, a first end of the first energy storage circuit is electrically connected to a first end of the driving circuit or a second end of the driving circuit, and a second end of the first energy storage circuit is electrically connected to a first bias voltage end for providing a first bias voltage signal. When the voltage value of the first bias voltage signal provided by the first bias voltage end changes, the potential of the first end of the driving circuit or the potential of the second end of the driving circuit changes accordingly, the driving transistor can be fixedly biased, the threshold voltage of the driving transistor is restored, and the display panel can well maintain the brightness uniformity at each frequency.

[0119] In at least one embodiment of the present disclosure, the first bias voltage signal and the second bias voltage signal can be provided by a GOA (Gate On Array, gate driving circuit disposed on an array substrate) circuit.

[0120] In at least one embodiment of the present disclosure, the first bias voltage end is configured to, in a biasing phase, change the potential of the first end of the first energy storage circuit by providing the first bias voltage signal, so that a driving transistor included in the driving circuit is in a biasing state.

[0121] The display period of the pixel circuit includes a biasing phase, a data writing phase and a light emitting phase which are independent of each other.

[0122] In specific implementation, at least part of time in a time period other than the data writing phase and the light emitting phase included in the display period, the potential of the first end of the first energy storage circuit is changed by providing the first bias voltage signal, so that the driving transistor included in the driving circuit is in a biasing state.

[0123] In at least one embodiment of the present disclosure, the second bias voltage end is configured to, in a biasing phase, change the potential of the first end of the second energy storage circuit by providing the second bias voltage signal, so as to reduce the leakage current of the first node.

[0124] The display period of the pixel circuit includes a biasing phase, a data writing phase and a light emitting phase which are independent of each other.

[0125] The first compensation circuit is configured to, in the biasing phase, control the first node and the intermediate node to be disconnected under the control of the compensation control signal.

[0126] The second compensation circuit is configured to control the disconnection between the intermediate node and the third node under the control of the compensation control signal in the bias stage.

[0127] In a specific implementation, the difference between the potential of the first node and the potential of the intermediate node is reduced by providing a second bias voltage signal in at least part of the time period included in the display period other than the data writing stage and the light emitting stage, so as to reduce the leakage of the first node.

[0128] In at least one embodiment of the present disclosure, the transistors included in the pixel circuit can be LTPS (low temperature polysilicon) transistors, and the active layer material of the transistors can be made of LTPS material; in a specific implementation, the driving transistor included in the driving circuit can be a p-type transistor, and the transistors included in the pixel circuit other than the driving transistor can be p-type transistors or n-type transistors.

[0129] As shown in FIG. 1, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element, a driving circuit 10, a first energy storage circuit 11, and a compensation control circuit 31.

[0130] The control end of the driving circuit 10 is electrically connected with the first node N1, the first end of the driving circuit 10 is electrically connected with the second node N2, and the second end of the driving circuit 10 is electrically connected with the third node N3; the driving circuit 10 generates a driving current for driving the light emitting element under the control of the potential of the first node N1.

[0131] The first end of the first energy storage circuit 11 is electrically connected with the second node N2, and the second end of the first energy storage circuit 11 is electrically connected with a first bias voltage end VB1; the first energy storage circuit 11 is configured to control the potential of the first end of the first energy storage circuit 11 according to a first bias voltage signal provided by the first bias voltage end VB1.

[0132] The compensation control circuit 31 is electrically connected with a compensation control end SC, the first node N1, and the third node N3, respectively, and is configured to control the communication or disconnection between the first node N1 and the third node N3 under the control of a compensation control signal provided by the compensation control end SC.

[0133] At least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure works in a display period including a first bias stage and a light emitting stage arranged in sequence.

[0134] In the first bias stage, the potential of the second node N2 is changed by the first bias voltage signal, so that the driving transistor included in the driving circuit 10 is in a bias state.

[0135] In the light emitting stage, the driving circuit 10 generates a driving current for driving the light emitting element E1.

[0136] As shown in FIG. 2, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element, a driving circuit 10, a first energy storage circuit 11, and a compensation control circuit 31.

[0137] The control end of the driving circuit 10 is electrically connected with the first node N1, the first end of the driving circuit 10 is electrically connected with the second node N2, the second end of the driving circuit 10 is electrically connected with the third node N3, and the driving circuit 10 generates a driving current for driving the light emitting element under the control of the potential of the first node N1.

[0138] The first end of the first energy storage circuit 11 is electrically connected with the third node N3, and the second end of the first energy storage circuit 11 is electrically connected with a first bias voltage end VB1. The first energy storage circuit 11 is configured to control the potential of the first end of the first energy storage circuit 11 according to a first bias voltage signal provided by the first bias voltage end VB1.

[0139] The compensation control circuit 31 is electrically connected with a compensation control end SC, the first node N1, and the third node N3, respectively. The compensation control circuit 31 is configured to control the communication or disconnection between the first node N1 and the third node N3 under the control of a compensation control signal provided by the compensation control end SC.

[0140] At least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure works in a display period including a first bias stage and a light emitting stage arranged in sequence.

[0141] In the first bias stage, the potential of the third node N3 is changed by the first bias voltage signal, so that the driving transistor included in the driving circuit 10 is in a bias state.

[0142] In the light emitting stage, the driving circuit 10 generates a driving current for driving the light emitting element E1.

[0143] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit, a third energy storage circuit, and a first initialization circuit.

[0144] The data writing circuit is electrically connected with a writing control end, a data line, and the second node, respectively. The data writing circuit is configured to control the communication or disconnection between the data line and the second node under the control of a writing control signal provided by the writing control end.

[0145] The third energy storage circuit is electrically connected with the first node, and is configured to maintain the potential of the first node.

[0146] The first initialization circuit is electrically connected with the reset control end and the first initial voltage end respectively, and is also electrically connected with the first node or the third node. The first initialization circuit is used for writing the first initial voltage provided by the first initial voltage end into the first node or the third node under the control of the reset control signal provided by the reset control end.

[0147] As shown in FIG. 3, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1,

[0148] The pixel circuit provided in at least one embodiment of the present disclosure further includes a data writing circuit 32, a third energy storage circuit 33 and a first initialization circuit 34.

[0149] The data writing circuit 32 is electrically connected with a writing control end SW, a data line DL and the second node N2 respectively, and is used for controlling the data line DL to be in communication or disconnected with the second node N2 under the control of the writing control signal provided by the writing control end SW.

[0150] The third energy storage circuit 33 is electrically connected with the first node N1, and is used for maintaining the potential of the first node N1.

[0151] The first initialization circuit 34 is electrically connected with a reset control end R1 and a first initial voltage end I1 respectively, and is also electrically connected with the first node N1. The first initialization circuit 34 is used for writing the first initial voltage Vinit1 provided by the first initial voltage end I1 into the first node N1 under the control of the reset control signal provided by the reset control end R1.

[0152] Optionally, when the transistors included in the compensation control circuit and the transistors included in the data writing circuit are all p-type transistors or are all n-type transistors, the compensation control end and the writing control end can both be a scanning end, and the scanning end can be an nth row gate driving end. The reset control end R1 can be an (n-1)th row gate driving end.

[0153] In at least one embodiment of the pixel circuit shown in FIG. 3, the display period includes a reset stage and a data writing stage arranged before the first bias stage. The reset stage and the data writing stage are arranged in sequence.

[0154] In the reset stage, the first initialization circuit 34 writes the first initial voltage Vinit1 into the first node N1 under the control of the reset control signal, so as to initialize the potential of the first node N1. Thus, at the beginning of the data writing stage, the driving transistor included in the driving circuit 10 can be turned on.

[0155] In the data writing stage, the data writing circuit 32 writes the data voltage Vdata provided by the data line DL into the second node N2 under the control of a writing control signal, and the compensation control circuit 31 controls the communication between the first node N1 and the third node N3 under the control of a compensation control signal.

[0156] At least one embodiment of the pixel circuit shown in FIG. 3 of the present disclosure, when in operation, the display period can further include a second bias stage; the second bias stage is arranged before the reset stage; or, the second bias stage is arranged between the reset stage and the data writing stage.

[0157] In the second bias stage, the potential of the first terminal of the first energy storage circuit 11 is changed by a first bias voltage signal, so that the driving transistor included in the driving circuit 10 is in a bias state, to improve the hysteresis phenomenon of the driving transistor.

[0158] As shown in FIG. 4, based on at least one embodiment of the pixel circuit shown in FIG. 1,

[0159] The pixel circuit of at least one embodiment of the present disclosure further includes a data writing circuit 32, a third energy storage circuit 33, and a first initialization circuit 34.

[0160] The data writing circuit 32 is electrically connected with a writing control end SW, a data line DL, and the second node N2, respectively, and is configured to control the communication or disconnection between the data line DL and the second node N2 under the control of a writing control signal provided by the writing control end SW.

[0161] The third energy storage circuit 33 is electrically connected with the first node N1, and is configured to maintain the potential of the first node N1.

[0162] The first initialization circuit 34 is electrically connected with a reset control end R1 and a first initial voltage end I1, respectively, and is further electrically connected with the third node N3. The first initialization circuit 34 is configured to write a first initial voltage Vinit1 provided by the first initial voltage end I1 into the third node N3 under the control of a reset control signal provided by the reset control end R1.

[0163] At least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure, when in operation, the display period includes a reset stage and a data writing stage arranged before the first bias stage; the reset stage and the data writing stage are arranged in sequence.

[0164] In the reset stage, the first initialization circuit 34 writes the first initial voltage Vinit1 into the third node N3 under the control of a reset control signal, and the compensation control circuit 31 controls the communication between the first node N1 and the third node N3 under the control of a compensation control signal, so as to initialize the potential of the first node N1, so that the driving transistor included in the driving circuit 10 can be turned on at the beginning of the data writing stage.

[0165] In the data writing stage, the data writing circuit 32 writes the data voltage Vdata provided by the data line DL into the second node N2 under the control of a writing control signal, and the compensation control circuit 31 controls the communication between the first node N1 and the third node N3 under the control of a compensation control signal.

[0166] At least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure works, and the display period can further include a second bias stage; the second bias stage is arranged before the reset stage; or, the second bias stage is arranged between the reset stage and the data writing stage.

[0167] In the second bias stage, the potential of the first terminal of the first energy storage circuit 11 is changed by the first bias voltage signal, so that the driving transistor included in the driving circuit 10 is in a bias state, so as to improve the hysteresis phenomenon of the driving transistor.

[0168] As shown in FIG. 5, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit of at least one embodiment of the present disclosure further includes a data writing circuit 32, a third energy storage circuit 33 and a first initialization circuit 34.

[0169] The data writing circuit 32 is electrically connected with a writing control end SW, a data line DL and the second node N2 respectively, and is used for controlling the communication or disconnection between the data line DL and the second node N2 under the control of a writing control signal provided by the writing control end SW.

[0170] The third energy storage circuit 33 is electrically connected with the first node N1, and is used for maintaining the potential of the first node N1.

[0171] The first initialization circuit 34 is electrically connected with a reset control end R1 and a first initial voltage end I1 respectively, and is further electrically connected with the first node N1. The first initialization circuit 34 is used for writing the first initial voltage Vinit1 provided by the first initial voltage end I1 into the first node N1 under the control of a reset control signal provided by the reset control end R1.

[0172] Optionally, when the transistors included in the compensation control and the transistors included in the data write circuit are both p-type transistors or both n-type transistors, the compensation control end and the write control end can both be scan ends, the scan ends can be nth row gate driving ends, and the reset control end R1 can be an (n-1)th row gate driving end.

[0173] At least one embodiment of the pixel circuit shown in FIG. 5 of the present disclosure, when in operation, the display period includes a reset phase and a data write phase arranged before the first bias phase; the reset phase and the data write phase are arranged in sequence;

[0174] In the reset phase, the first initialization circuit 34 writes the first initial voltage Vinit1 into the first node N1 under the control of the reset control signal, to initialize the potential of the first node N1, so that the driving transistor included in the driving circuit 10 can be turned on at the beginning of the data write phase;

[0175] In the data write phase, the data write circuit 32 writes the data voltage Vdata provided by the data line DL into the second node N2 under the control of the write control signal, and the compensation control circuit 31 controls the communication between the first node N1 and the third node N3 under the control of the compensation control signal.

[0176] At least one embodiment of the pixel circuit shown in FIG. 5 of the present disclosure, when in operation, the display period can further include a second bias phase; the second bias phase is arranged before the reset phase; or, the second bias phase is arranged between the reset phase and the data write phase;

[0177] In the second bias phase, the potential of the first terminal of the first energy storage circuit 11 is changed by the first bias voltage signal, so that the driving transistor included in the driving circuit 10 is in a bias state, to improve the hysteresis phenomenon of the driving transistor.

[0178] As shown in FIG. 6, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit of at least one embodiment of the present disclosure further includes a data write circuit 32, a third energy storage circuit 33, and a first initialization circuit 34;

[0179] The data write circuit 32 is electrically connected with a write control end SW, a data line DL, and the second node N2, for controlling the communication or disconnection between the data line DL and the second node N2 under the control of the write control signal provided by the write control end SW;

[0180] The third energy storage circuit 33 is electrically connected with the first node N1, for maintaining the potential of the first node N1;

[0181] The first initialization circuit 34 is electrically connected with the reset control end R1 and the first initial voltage end I1 respectively, and is also electrically connected with the third node N3. The first initialization circuit 34 is used for writing the first initial voltage Vinit1 provided by the first initial voltage end I1 into the third node N3 under the control of the reset control signal provided by the reset control end R1.

[0182] At least one embodiment of the pixel circuit shown in FIG. 6 of the present disclosure, when working, the display period includes a reset stage and a data writing stage arranged before the first bias stage; the reset stage and the data writing stage are arranged in sequence;

[0183] In the reset stage, the first initialization circuit 34 writes the first initial voltage Vinit1 into the third node N3 under the control of the reset control signal, and the compensation control circuit 31 controls the communication between the first node N1 and the third node N3 under the control of the compensation control signal, so as to initialize the potential of the first node N1, so that the drive transistor included in the drive circuit 10 can be turned on at the beginning of the data writing stage;

[0184] In the data writing stage, the data writing circuit 32 writes the data voltage Vdata provided by the data line DL into the second node N2 under the control of the writing control signal, and the compensation control circuit 31 controls the communication between the first node N1 and the third node N3 under the control of the compensation control signal.

[0185] At least one embodiment of the pixel circuit shown in FIG. 6 of the present disclosure, when working, the display period can also include a second bias stage; the second bias stage is arranged before the reset stage; or, the second bias stage is arranged between the reset stage and the data writing stage;

[0186] In the second bias stage, the potential of the first end of the first energy storage circuit 11 is changed by the first bias voltage signal, so that the drive transistor included in the drive circuit 10 is in a bias state, so as to improve the hysteresis phenomenon of the drive transistor.

[0187] The pixel circuit in at least one embodiment of the present disclosure further includes a first light-emitting control circuit, a second light-emitting control circuit and a second initialization circuit;

[0188] The first light-emitting control circuit is electrically connected with the first light-emitting control end, the power voltage end and the second node respectively, and is used for controlling the communication or disconnection between the power voltage end and the second node under the control of the first light-emitting control signal provided by the first light-emitting control end;

[0189] The second light-emitting control circuit is electrically connected with the second light-emitting control terminal, the third node and the first electrode of the light-emitting element respectively, and is configured to control the third node and the first electrode of the light-emitting element to be in communication or disconnected under the control of a second light-emitting control signal provided by the second light-emitting control terminal.

[0190] The second initialization circuit is electrically connected with the initial control terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is configured to control the second initial voltage terminal and the first electrode of the light-emitting element to be in communication or disconnected under the control of an initial control signal provided by the initial control terminal.

[0191] The second electrode of the light-emitting element is electrically connected with the first voltage terminal.

[0192] In a specific implementation, the pixel circuit can include a first light-emitting control circuit, a second light-emitting control circuit and a second initialization circuit; the first light-emitting control circuit and the second light-emitting control circuit perform light-emitting control, and the second initialization circuit writes a second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of an initial control signal, to clear the residual charges in the first electrode of the light-emitting element.

[0193] Optionally, the first light-emitting control terminal and the second light-emitting control terminal can be the same light-emitting control terminal.

[0194] As shown in FIG. 7, on the basis of at least one embodiment of the pixel circuit shown in FIG. 3, the pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit 71, a second light-emitting control circuit 72 and a second initialization circuit 73.

[0195] The first light-emitting control circuit 71 is electrically connected with the light-emitting control terminal EM, the power voltage terminal VDD and the second node N2 respectively, and is configured to control the power voltage terminal VDD and the second node N2 to be in communication or disconnected under the control of a light-emitting control signal provided by the light-emitting control terminal EM.

[0196] The second light-emitting control circuit 72 is electrically connected with the light-emitting control terminal EM, the third node N3 and the first electrode of the light-emitting element E1 respectively, and is configured to control the third node N3 and the first electrode of the light-emitting element E1 to be in communication or disconnected under the control of the light-emitting control signal.

[0197] The second initialization circuit 73 is electrically connected with the initial control terminal HRST, the second initial voltage terminal I2 and the first electrode of the light-emitting element E1 respectively, and is configured to control the second initial voltage terminal I2 and the first electrode of the light-emitting element E1 to be in communication or disconnected under the control of an initial control signal provided by the initial control terminal HRST; the second initial voltage terminal I2 is configured to provide a second initial voltage Vinit2.

[0198] The second electrode of the light emitting element E1 is electrically connected with the first voltage terminal V1.

[0199] Optionally, the first voltage terminal can be a low voltage terminal.

[0200] As shown in FIG. 8, on the basis of at least one embodiment of the pixel circuit shown in FIG. 4, the pixel circuit according to at least one embodiment of the present disclosure further comprises a first light emitting control circuit 71, a second light emitting control circuit 72 and a second initialization circuit 73.

[0201] The first light emitting control circuit 71 is electrically connected with the light emitting control terminal EM, the power voltage terminal VDD and the second node N2 respectively, and is configured to control the power voltage terminal VDD and the second node N2 to be connected or disconnected under the control of a light emitting control signal provided by the light emitting control terminal EM.

[0202] The second light emitting control circuit 72 is electrically connected with the light emitting control terminal EM, the third node N3 and the first electrode of the light emitting element E1 respectively, and is configured to control the third node N3 and the first electrode of the light emitting element E1 to be connected or disconnected under the control of the light emitting control signal.

[0203] The second initialization circuit 73 is electrically connected with an initial control terminal HRST, a second initial voltage terminal I2 and the first electrode of the light emitting element E1 respectively, and is configured to control the second initial voltage terminal I2 and the first electrode of the light emitting element E1 to be connected or disconnected under the control of an initial control signal provided by the initial control terminal HRST; the second initial voltage terminal I2 is configured to provide a second initial voltage Vinit2.

[0204] The second electrode of the light emitting element E1 is electrically connected with the first voltage terminal V1.

[0205] As shown in FIG. 9, on the basis of at least one embodiment of the pixel circuit shown in FIG. 5, the pixel circuit according to at least one embodiment of the present disclosure further comprises a first light emitting control circuit 71, a second light emitting control circuit 72 and a second initialization circuit 73.

[0206] The first light emitting control circuit 71 is electrically connected with the light emitting control terminal EM, the power voltage terminal VDD and the second node N2 respectively, and is configured to control the power voltage terminal VDD and the second node N2 to be connected or disconnected under the control of a light emitting control signal provided by the light emitting control terminal EM.

[0207] The second light-emitting control circuit 72 is electrically connected with the light-emitting control end EM, the third node N3 and the first electrode of the light-emitting element E1 respectively, and is configured to control the communication or disconnection between the third node N3 and the first electrode of the light-emitting element E1 under the control of the light-emitting control signal.

[0208] The second initialization circuit 73 is electrically connected with the initial control end HRST, the second initial voltage end I2 and the first electrode of the light-emitting element E1 respectively, and is configured to control the communication or disconnection between the second initial voltage end I2 and the first electrode of the light-emitting element E1 under the control of the initial control signal provided by the initial control end HRST; the second initial voltage end I2 is configured to provide a second initial voltage Vinit2.

[0209] The second electrode of the light-emitting element E1 is electrically connected with the first voltage end V1.

[0210] As shown in FIG. 10, on the basis of at least one embodiment of the pixel circuit shown in FIG. 6, the pixel circuit provided in at least one embodiment of the present disclosure further includes a first light-emitting control circuit 71, a second light-emitting control circuit 72 and a second initialization circuit 73.

[0211] The first light-emitting control circuit 71 is electrically connected with the light-emitting control end EM, the power voltage end VDD and the second node N2 respectively, and is configured to control the communication or disconnection between the power voltage end VDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control end EM.

[0212] The second light-emitting control circuit 72 is electrically connected with the light-emitting control end EM, the third node N3 and the first electrode of the light-emitting element E1 respectively, and is configured to control the communication or disconnection between the third node N3 and the first electrode of the light-emitting element E1 under the control of the light-emitting control signal.

[0213] The second initialization circuit 73 is electrically connected with the initial control end HRST, the second initial voltage end I2 and the first electrode of the light-emitting element E1 respectively, and is configured to control the communication or disconnection between the second initial voltage end I2 and the first electrode of the light-emitting element E1 under the control of the initial control signal provided by the initial control end HRST; the second initial voltage end I2 is configured to provide a second initial voltage Vinit2.

[0214] The second electrode of the light-emitting element E1 is electrically connected with the first voltage end V1.

[0215] As shown in FIG. 11, on the basis of at least one embodiment of the pixel circuit shown in FIG. 7, the pixel circuit provided in at least one embodiment of the present disclosure further includes a second energy storage circuit 110; the compensation control circuit includes a first compensation circuit 111 and a second compensation circuit 112;

[0216] The first compensation circuit 111 is electrically connected with the compensation control end SC, the first node N1 and the intermediate node NZ respectively, and is configured to control the first node N1 and the intermediate node NZ to be connected or disconnected under the control of a compensation control signal provided by the compensation control end SC.

[0217] The second compensation circuit 112 is electrically connected with the compensation control end SC, the intermediate node NZ and the third node N3 respectively, and is configured to control the intermediate node NZ and the third node N3 to be connected or disconnected under the control of a compensation control signal provided by the compensation control end SC.

[0218] The first end of the second energy storage circuit 110 is electrically connected with the intermediate node NZ, and the second end of the second energy storage circuit 110 is electrically connected with the second bias voltage end VB2. The second energy storage circuit is configured to control the potential of the first end of the second energy storage circuit 110 according to a second bias voltage signal provided by the second bias voltage end VB2.

[0219] In at least one embodiment of the pixel circuit shown in FIG. 11, in the data writing stage, the first compensation circuit 111 controls the first node N1 and the intermediate node NZ to be connected under the control of a compensation control signal, and the second compensation circuit 112 controls the intermediate node NZ and the third node N3 to be connected under the control of the compensation control signal.

[0220] In the first bias stage and the second bias stage, the potential of the first end of the second energy storage circuit 110 is changed by the second bias voltage signal provided by the second bias voltage end VB2, so that the absolute value of the difference between the potential of the first node N1 and the potential of the intermediate node NZ is reduced, the difference between the potential of the first node and the potential of the intermediate node is reduced, and the leakage current of the first node N1 is reduced.

[0221] In the first bias stage and the second bias stage, the second initialization circuit 73 controls the second initialization voltage Vinit2 provided by the second initialization voltage end I2 to be written into the first electrode of the light emitting element E1 under the control of an initial control signal, and clears the residual charge in the first electrode of the light emitting element E1.

[0222] As shown in FIG. 12, based on at least one embodiment of the pixel circuit shown in FIG. 8, the pixel circuit according to at least one embodiment of the present disclosure further comprises a second energy storage circuit 110, and the compensation control circuit comprises a first compensation circuit 111 and a second compensation circuit 112.

[0223] The first compensation circuit 111 is electrically connected with the compensation control end SC, the first node N1 and the intermediate node NZ respectively, and is configured to control the first node N1 and the intermediate node NZ to be connected or disconnected under the control of a compensation control signal provided by the compensation control end SC.

[0224] The second compensation circuit 112 is electrically connected with the compensation control end SC, the intermediate node NZ and the third node N3 respectively, and is configured to control the intermediate node NZ and the third node N3 to be connected or disconnected under the control of a compensation control signal provided by the compensation control end SC.

[0225] The first end of the second energy storage circuit 110 is electrically connected with the intermediate node NZ, and the second end of the second energy storage circuit 110 is electrically connected with the second bias voltage end VB2. The second energy storage circuit is configured to control the potential of the first end of the second energy storage circuit 110 according to a second bias voltage signal provided by the second bias voltage end VB2.

[0226] At least one embodiment of the pixel circuit shown in FIG. 12 is in operation. In the data writing stage, the first compensation circuit 111 controls the first node N1 and the intermediate node NZ to be connected under the control of a compensation control signal; and the second compensation circuit 112 controls the intermediate node NZ and the third node N3 to be connected under the control of the compensation control signal.

[0227] In the first bias stage and the second bias stage, the potential of the first end of the second energy storage circuit 110 is changed by the second bias voltage signal provided by the second bias voltage end VB2, so that the absolute value of the difference between the potential of the first node N1 and the potential of the intermediate node NZ is reduced, the difference between the potential of the first node and the potential of the intermediate node is reduced, and the drain current of the first node N1 is reduced.

[0228] In the first bias stage and the second bias stage, the second initialization circuit 73 controls the second initialization voltage Vinit2 provided by the second initialization voltage end I2 to be written into the first electrode of the light emitting element E1 under the control of an initial control signal, and clears the residual charge in the first electrode of the light emitting element E1.

[0229] As shown in FIG. 13, on the basis of at least one embodiment of the pixel circuit shown in FIG. 9, the pixel circuit according to at least one embodiment of the present disclosure further comprises a second energy storage circuit 110; and the compensation control circuit comprises a first compensation circuit 111 and a second compensation circuit 112.

[0230] The first compensation circuit 111 is electrically connected with the compensation control end SC, the first node N1 and the intermediate node NZ respectively, and is configured to control the first node N1 and the intermediate node NZ to be connected or disconnected under the control of a compensation control signal provided by the compensation control end SC.

[0231] The second compensation circuit 112 is electrically connected with the compensation control end SC, the intermediate node NZ and the third node N3 respectively, and is configured to control the intermediate node NZ and the third node N3 to be connected or disconnected under the control of a compensation control signal provided by the compensation control end SC.

[0232] The first end of the second energy storage circuit 110 is electrically connected with the intermediate node NZ, and the second end of the second energy storage circuit 110 is electrically connected with the second bias voltage end VB2. The second energy storage circuit is configured to control the potential of the first end of the second energy storage circuit 110 according to a second bias voltage signal provided by the second bias voltage end VB2.

[0233] In at least one embodiment of the pixel circuit shown in FIG. 13, in the data writing stage, the first compensation circuit 111 controls the first node N1 and the intermediate node NZ to be connected under the control of a compensation control signal; and the second compensation circuit 112 controls the intermediate node NZ and the third node N3 to be connected under the control of the compensation control signal.

[0234] In the first bias stage and the second bias stage, the potential of the first end of the second energy storage circuit 110 is changed by the second bias voltage signal provided by the second bias voltage end VB2, so that the absolute value of the difference between the potential of the first node N1 and the potential of the intermediate node NZ is reduced, the difference between the potential of the first node and the potential of the intermediate node is reduced, and the drain current of the first node N1 is reduced.

[0235] In the first bias stage and the second bias stage, the second initialization circuit 73 controls the second initialization voltage Vinit2 provided by the second initialization voltage end I2 to be written into the first electrode of the light emitting element E1 under the control of an initial control signal, and clears the residual charge in the first electrode of the light emitting element E1.

[0236] As shown in FIG. 14, on the basis of at least one embodiment of the pixel circuit shown in FIG. 10, the pixel circuit according to at least one embodiment of the present disclosure further comprises a second energy storage circuit 110; and the compensation control circuit comprises a first compensation circuit 111 and a second compensation circuit 112.

[0237] The first compensation circuit 111 is electrically connected with the compensation control end SC, the first node N1 and the intermediate node NZ respectively, and is configured to control the first node N1 and the intermediate node NZ to be connected or disconnected under the control of a compensation control signal provided by the compensation control end SC.

[0238] The second compensation circuit 112 is electrically connected with the compensation control end SC, the intermediate node NZ and the third node N3 respectively, and is configured to control the intermediate node NZ and the third node N3 to be connected or disconnected under the control of a compensation control signal provided by the compensation control end SC.

[0239] The first end of the second energy storage circuit 110 is electrically connected with the intermediate node NZ, and the second end of the second energy storage circuit 110 is electrically connected with the second bias voltage end VB2. The second energy storage circuit is configured to control the potential of the first end of the second energy storage circuit 110 according to a second bias voltage signal provided by the second bias voltage end VB2.

[0240] In at least one embodiment of the pixel circuit shown in FIG. 14, in the data writing stage, the first compensation circuit 111 controls the first node N1 and the intermediate node NZ to be connected under the control of a compensation control signal, and the second compensation circuit 112 controls the intermediate node NZ and the third node N3 to be connected under the control of the compensation control signal.

[0241] In the first bias stage and the second bias stage, the potential of the first end of the second energy storage circuit 110 is changed by the second bias voltage signal provided by the second bias voltage end VB2, so that the absolute value of the difference between the potential of the first node N1 and the potential of the intermediate node NZ is reduced, the difference between the potential of the first node and the potential of the intermediate node is reduced, and the drain current of the first node N1 is reduced.

[0242] In the first bias stage and the second bias stage, the second initialization circuit 73 controls the second initialization voltage Vinit2 provided by the second initialization voltage end I2 to be written into the first electrode of the light emitting element E1 under the control of an initial control signal, and clears the residual charge in the first electrode of the light emitting element E1.

[0243] In at least one embodiment of the present disclosure, when the display panel performs low-frequency display, the display period is a refresh frame, and the maintaining frame includes a maintaining bias stage.

[0244] In the maintaining bias stage, the second initialization circuit writes a second initial voltage into the first electrode of the light emitting element under the control of an initial control signal, clears the residual charge of the first electrode of the light emitting element, changes the potential of the first terminal of the first energy storage circuit through a first bias voltage signal, so that the driving transistor is in a bias state, restores the threshold voltage of the driving transistor, and improves the hysteresis phenomenon of the driving transistor; the potential of the first terminal of the second energy storage circuit 110 is changed through a second bias voltage signal provided by a second bias voltage terminal VB2, so that the absolute value of the difference between the potential of the first node N1 and the potential of the intermediate node NZ is reduced, the difference between the potential of the first node and the potential of the intermediate node is reduced, and the leakage current of the first node N1 is reduced; in this way, when the display panel displays at a low frequency, it is beneficial to maintain the potential of N1 and improve the hysteresis phenomenon of the driving transistor, the brightness uniformity can be well maintained when displaying at a low frequency, and variable refresh frequency adjustment of the pixel can be realized.

[0245] As shown in FIG. 15, the pixel circuit includes a driving circuit 10, a compensation control circuit, and a second energy storage circuit 110 according to at least one embodiment of the present disclosure; the compensation control circuit includes a first compensation circuit 111 and a second compensation circuit 112;

[0246] The control end of the driving circuit 10 is electrically connected with the first node N1, the first end of the driving circuit 10 is electrically connected with the second node N2, and the second end of the driving circuit 10 is electrically connected with the third node N3; the driving circuit 10 generates a driving current for driving the light emitting element under the control of the potential of the first node N1;

[0247] The first compensation circuit 111 is electrically connected with a compensation control end SC, the first node N1, and an intermediate node NZ respectively, and is used for controlling the communication or disconnection between the first node N1 and the intermediate node NZ under the control of a compensation control signal provided by the compensation control end SC;

[0248] The second compensation circuit 112 is electrically connected with the compensation control end SC, the intermediate node NZ, and the third node N3 respectively, and is used for controlling the communication or disconnection between the intermediate node NZ and the third node N3 under the control of a compensation control signal provided by the compensation control end SC;

[0249] The first end of the second energy storage circuit 110 is electrically connected with the intermediate node NZ, and the second end of the second energy storage circuit 110 is electrically connected with a second bias voltage terminal VB2; the second energy storage circuit is used for controlling the potential of the first end of the second energy storage circuit 110 according to a second bias voltage signal provided by the second bias voltage terminal VB2.

[0250] At least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure works as follows. In a biasing phase, the first compensation circuit 111 is controlled by a compensation control signal to control the disconnection between the first node N1 and the intermediate node NZ; the second compensation circuit 112 is controlled by the compensation control signal to control the disconnection between the intermediate node NZ and the third node N3; and a second bias voltage signal provided by a second bias voltage terminal VB2 changes the potential of the first end of the second energy storage circuit 110, so as to reduce the absolute value of the difference between the potential of the first node N1 and the potential of the intermediate node NZ, thereby reducing the difference between the potential of the first node and the potential of the intermediate node, and reducing the leakage current of the first node N1.

[0251] The pixel circuit in at least one embodiment of the present disclosure further includes a fourth energy storage circuit, a fifth energy storage circuit, a data writing circuit, a first control circuit, a second control circuit, and a sixth energy storage circuit.

[0252] The first end of the fourth energy storage circuit is electrically connected with the first node, the second end of the fourth energy storage circuit is electrically connected with a first control node, the first end of the fifth energy storage circuit is electrically connected with the first control node, and the second end of the fifth energy storage circuit is electrically connected with a writing node. The fourth energy storage circuit and the fifth energy storage circuit are used for storing electric energy.

[0253] The data writing circuit is electrically connected with a writing control terminal, a data line, and the writing node respectively, and is used for controlling the communication or disconnection between the data line and the writing node under the control of a writing control signal provided by the writing control terminal.

[0254] The first control circuit is electrically connected with a pass-through control terminal, the first control node, and a second control node respectively, and is used for controlling the communication or disconnection between the first control node and the second control node under the control of a pass-through control signal provided by the pass-through control terminal.

[0255] The second control circuit is electrically connected with the pass-through control terminal, the second control node, and a second voltage terminal respectively, and is used for controlling the communication or disconnection between the second control node and the second voltage terminal under the control of the pass-through control signal.

[0256] The first end of the sixth energy storage circuit is electrically connected with the second control node, and the second end of the sixth energy storage circuit is electrically connected with a third bias voltage terminal. The sixth energy storage circuit is used for controlling the potential of the second control node according to a third bias voltage signal provided by the third bias voltage terminal. The third bias voltage signal is a variable voltage signal.

[0257] In at least one embodiment of the present disclosure, the pass-through control terminal and the compensation control terminal can be the same control terminal.

[0258] Optionally, the second voltage terminal can be a power voltage terminal.

[0259] In at least one embodiment of the present disclosure, the third bias voltage terminal is configured to change the potential of the second control node by providing a third bias voltage signal in a biasing phase, so as to reduce the leakage current of the first control node.

[0260] The display period of the pixel circuit comprises a biasing phase and a light-emitting phase which are independent of each other.

[0261] The first control circuit is configured to control the disconnection between the first control node and the second control node under the control of the on-off control signal in the biasing phase.

[0262] The second control circuit is configured to control the disconnection between the second control node and the second voltage terminal under the control of the on-off control signal in the biasing phase.

[0263] In a specific implementation, the potential of the second control node can be changed by providing a third bias voltage signal in at least part of the time period other than the light-emitting phase in the display period, so as to reduce the leakage current of the first control node.

[0264] The pixel circuit according to at least one embodiment of the present disclosure can further comprise a setting circuit.

[0265] The setting circuit is electrically connected to a setting control terminal, a setting voltage terminal and the write-in node, and is configured to control the communication or disconnection between the setting voltage terminal and the write-in node under the control of a setting control signal provided by the setting control terminal.

[0266] In a specific implementation, the pixel circuit can further comprise a setting circuit, which can write a setting voltage provided by the setting voltage terminal into the write-in node under the control of a setting control signal, so that the data voltage can be written into the first node in the form of voltage jump of the capacitor.

[0267] Optionally, the setting control terminal and the first light-emitting control terminal can be the same control terminal.

[0268] As shown in FIG. 16A, on the basis of at least one embodiment of the pixel circuit shown in FIG. 15, the pixel circuit according to at least one embodiment of the present disclosure further comprises a fourth energy storage circuit 161, a fifth energy storage circuit 162, a data write-in circuit 32, a first control circuit 163, a second control circuit 164 and a sixth energy storage circuit 165.

[0269] The first end of the fourth energy storage circuit 161 is electrically connected with the first node N1, the second end of the fourth energy storage circuit 161 is electrically connected with the first control node NC1, the first end of the fifth energy storage circuit 162 is electrically connected with the first control node NC1, and the second end of the fifth energy storage circuit 162 is electrically connected with the write node NW, and the fourth energy storage circuit 161 and the fifth energy storage circuit 162 are used for storing electric energy.

[0270] The data write circuit 32 is electrically connected with the write control end SW, the data line DL and the write node NW respectively, and is used for controlling the data line DL and the write node NW to be connected or disconnected under the control of the write control signal provided by the write control end SW.

[0271] The first control circuit 163 is electrically connected with the on-off control end AZ, the first control node NC1 and the second control node NC2 respectively, and is used for controlling the first control node NC1 and the second control node NC2 to be connected or disconnected under the control of the on-off control signal provided by the on-off control end AZ.

[0272] The second control circuit 164 is electrically connected with the on-off control end AZ, the second control node NC2 and the second voltage end V2 respectively, and is used for controlling the second control node NC2 and the second voltage end V2 to be connected or disconnected under the control of the on-off control signal.

[0273] The first end of the sixth energy storage circuit 165 is electrically connected with the second control node NC2, and the second end of the sixth energy storage circuit 165 is electrically connected with the third bias voltage end VB3, and the sixth energy storage circuit 165 is used for controlling the potential of the second control node NC2 according to the third bias voltage signal provided by the third bias voltage end VB3, and the third bias voltage signal is a variable voltage signal.

[0274] In at least one embodiment of the present disclosure, the third bias voltage signal can be provided by a GOA (Gate On Array, gate drive circuit arranged on an array substrate) circuit.

[0275] The pixel circuit in at least one embodiment of the present disclosure further comprises a setting circuit 166.

[0276] The setting circuit 166 is electrically connected with the setting control end SZ, the setting voltage end VZ and the write node NW respectively, and is used for controlling the setting voltage end VZ and the write node NW to be connected or disconnected under the control of the setting control signal provided by the setting control end SZ.

[0277] Optionally, the setting voltage end VZ can be a first reference voltage end.

[0278] As shown in FIG. 16B, on the basis of at least one embodiment of the pixel circuit shown in FIG. 16A, the pixel circuit provided by at least one embodiment of the present disclosure further includes a first light-emitting control circuit 71, a second light-emitting control circuit 72, and a second initialization circuit 73.

[0279] The first light-emitting control circuit 71 is electrically connected with a first light-emitting control terminal EM1, a power voltage terminal VDD, and the second node N2 respectively, and is configured to control the power voltage terminal VDD and the second node N2 to be connected or disconnected under the control of a first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0280] The second light-emitting control circuit 72 is electrically connected with a second light-emitting control terminal EM2, the third node N3, and a first electrode of the light-emitting element E1 respectively, and is configured to control the third node N3 and the first electrode of the light-emitting element E1 to be connected or disconnected under the control of a second light-emitting control signal provided by the second light-emitting control terminal EM2; a second electrode of the light-emitting element E1 is electrically connected with a first voltage terminal V1.

[0281] The second initialization circuit 73 is electrically connected with an initial control terminal HRST, a second initial voltage terminal I2, and the first electrode of the light-emitting element E1 respectively, and is configured to control the second initial voltage terminal I2 and the first electrode of the light-emitting element E1 to be connected or disconnected under the control of an initial control signal provided by the initial control terminal HRST; the second initial voltage terminal I2 is configured to provide a second initial voltage Vinit2.

[0282] The pixel circuit provided by at least one embodiment of the present disclosure further includes a first initialization circuit 34.

[0283] The first initialization circuit 34 is electrically connected with a reset control terminal R1 and a first initial voltage terminal I1 respectively, and is further electrically connected with the third node N3; the first initialization circuit 34 is configured to control a first initial voltage Vinit1 provided by the first initial voltage terminal I1 to be written into the third node N3 under the control of a reset control signal provided by the reset control terminal R1.

[0284] The pixel circuit provided by at least one embodiment of the present disclosure further includes a third initialization circuit 167.

[0285] The third initialization circuit 167 is electrically connected with an initial control terminal HRST, a second reference voltage terminal REF2, and the second node N2 respectively, and is configured to control the second reference voltage terminal REF2 and the second node N2 to be connected or disconnected under the control of an initial control signal provided by the initial control terminal HRST.

[0286] Optionally, the driving circuit comprises a driving transistor, and the first energy storage circuit comprises a first capacitor;

[0287] The gate of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node.

[0288] The first end of the first capacitor is electrically connected with the second node or the third node, and the second end of the first capacitor is electrically connected with a first bias voltage terminal.

[0289] Optionally, the first compensation circuit comprises a first transistor, the second compensation circuit comprises a second transistor, and the second energy storage circuit comprises a second capacitor.

[0290] The gate of the first transistor is electrically connected with the compensation control terminal, the first electrode of the first transistor is electrically connected with the first node, and the second electrode of the first transistor is electrically connected with the intermediate node.

[0291] The gate of the second transistor is electrically connected with the compensation control terminal, the first electrode of the second transistor is electrically connected with the intermediate node, and the second electrode of the second transistor is electrically connected with the third node.

[0292] The first end of the second capacitor is electrically connected with the intermediate node, and the second end of the second capacitor is electrically connected with a second bias voltage terminal.

[0293] Optionally, the compensation control circuit comprises a first transistor.

[0294] The gate of the first transistor is electrically connected with the compensation control terminal, the first electrode of the first transistor is electrically connected with the first node, and the second electrode of the first transistor is electrically connected with the third node.

[0295] Optionally, the data writing circuit comprises a third transistor, the third energy storage circuit comprises a third capacitor, and the first initialization circuit comprises a fourth transistor.

[0296] The gate of the third transistor is electrically connected with the writing control terminal, the first electrode of the third transistor is electrically connected with the data line, and the second electrode of the third transistor is electrically connected with the second node.

[0297] The first end of the third capacitor is electrically connected with the first node, and the second end of the third capacitor is electrically connected with a direct current voltage terminal.

[0298] The gate of the fourth transistor is electrically connected with a reset control terminal, the first electrode of the fourth transistor is electrically connected with the first initialization voltage terminal, and the second electrode of the fourth transistor is electrically connected with the first node or the third node.

[0299] Optionally, the first light-emitting control circuit comprises a fifth transistor, the second light-emitting control circuit comprises a sixth transistor, and the second initialization circuit comprises a seventh transistor.

[0300] The gate of the fifth transistor is electrically connected with the light-emitting control end, the first pole of the fifth transistor is electrically connected with the power voltage end, and the second pole of the fifth transistor is electrically connected with the second node.

[0301] The gate of the sixth transistor is electrically connected with the light-emitting control end, the first pole of the sixth transistor is electrically connected with the third node, and the second pole of the sixth transistor is electrically connected with the first pole of the light-emitting element.

[0302] The gate of the seventh transistor is electrically connected with the initialization control end, the first pole of the seventh transistor is electrically connected with the second initialization voltage end, and the second pole of the seventh transistor is electrically connected with the first pole of the light-emitting element.

[0303] Optionally, the direct current voltage end can be a power voltage end.

[0304] Optionally, the fourth energy storage circuit comprises a fourth capacitor, the fifth energy storage circuit comprises a fifth capacitor, the data writing circuit comprises a third transistor, the first control circuit comprises an eighth transistor, the second control circuit comprises a ninth transistor, and the sixth energy storage circuit comprises a sixth capacitor.

[0305] The first end of the fourth capacitor is electrically connected with the first node, the second end of the fourth capacitor is electrically connected with a first control node, the first end of the fifth capacitor is electrically connected with the first control node, and the second end of the fifth capacitor is electrically connected with a writing node.

[0306] The gate of the third transistor is electrically connected with a writing control end, the first pole of the third transistor is electrically connected with a data line, and the second pole of the third transistor is electrically connected with the writing node.

[0307] The gate of the eighth transistor is electrically connected with the on-off control end, the first pole of the eighth transistor is electrically connected with the first control node, and the second pole of the eighth transistor is electrically connected with the second control node.

[0308] The gate of the ninth transistor is electrically connected with the on-off control end, the first pole of the ninth transistor is electrically connected with the second control node, and the second pole of the ninth transistor is electrically connected with a second voltage end.

[0309] The first end of the sixth capacitor is electrically connected with the second control node, and the second end of the sixth capacitor is electrically connected with a third bias voltage end.

[0310] Optionally, the setting circuit comprises a tenth transistor;

[0311] The gate of the tenth transistor is electrically connected with the setting control end, the first pole of the tenth transistor is electrically connected with the setting voltage end, and the second pole of the tenth transistor is electrically connected with the writing node.

[0312] As shown in FIG. 17, on the basis of at least one embodiment of the pixel circuit shown in FIG. 7, the driving circuit comprises a driving transistor T0, and the first energy storage circuit comprises a first capacitor C1; and the light emitting element is an organic light emitting diode O1.

[0313] The gate of the driving transistor T0 is electrically connected with the first node N1, the source of the driving transistor T0 is electrically connected with the second node N2, and the drain of the driving transistor T0 is electrically connected with the third node N3.

[0314] The first end of the first capacitor C1 is electrically connected with the second node N2, and the second end of the first capacitor C1 is electrically connected with a first bias voltage end VB1.

[0315] The compensation control circuit comprises a first transistor T1.

[0316] The gate of the first transistor T1 is electrically connected with the scanning end GT, the source of the first transistor T1 is electrically connected with the first node N1, and the drain of the first transistor T1 is electrically connected with the third node N3.

[0317] The data writing circuit comprises a third transistor T3, the third energy storage circuit comprises a third capacitor C3, and the first initialization circuit comprises a fourth transistor T4.

[0318] The gate of the third transistor T3 is electrically connected with the scanning end GT, the source of the third transistor T3 is electrically connected with the data line DL, and the drain of the third transistor T3 is electrically connected with the second node N2.

[0319] The first end of the third capacitor C3 is electrically connected with the first node N1, and the second end of the third capacitor C3 is electrically connected with a power voltage end VDD.

[0320] The gate of the fourth transistor T4 is electrically connected with a reset control end R1, the source of the fourth transistor T4 is electrically connected with the first initial voltage end I1, and the drain of the fourth transistor T4 is electrically connected with the first node N1.

[0321] The first light emitting control circuit comprises a fifth transistor T5, the second light emitting control circuit comprises a sixth transistor T6, and the second initialization circuit comprises a seventh transistor T7.

[0322] The gate of the fifth transistor T5 is electrically connected with the light-emitting control end EM, the source of the fifth transistor T5 is electrically connected with the power voltage end VDD, and the drain of the fifth transistor T5 is electrically connected with the second node N2;

[0323] The gate of the sixth transistor T6 is electrically connected with the light-emitting control end EM, the source of the sixth transistor T6 is electrically connected with the third node N3, and the drain of the sixth transistor T6 is electrically connected with the anode of O1;

[0324] The gate of the seventh transistor T7 is electrically connected with the initial control end HRST, the source of the seventh transistor T7 is electrically connected with the second initial voltage end I2, and the drain of the seventh transistor T7 is electrically connected with the anode of O1;

[0325] The cathode of O1 is electrically connected with the low voltage end VSS.

[0326] In at least one embodiment of the pixel circuit shown in FIG. 17, all the transistors are p-type transistors.

[0327] In at least one embodiment of the pixel circuit shown in FIG. 17, the write control end and the compensation control end are both scanning ends GT.

[0328] In at least one embodiment of the present disclosure, the voltage value of the first bias voltage signal provided by VB1 can be greater than or equal to -10V and less than or equal to 10V.

[0329] As shown in FIG. 18, in at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure, when working, the refresh frame can include the second bias stage S1, the reset stage S2, the data writing stage S3, the first bias stage S4 and the light-emitting stage S5 arranged in sequence;

[0330] In the second bias stage S1, HRST provides a low voltage signal, I2 provides the second initial voltage Vinit2 to the anode of O1, and the residual charge of the anode of O1 is cleared; VB1 pulls up the potential of N2, so that T0 is in a bias state;

[0331] In the reset stage S2, R1 provides a low voltage signal, HRST provides a high voltage signal, GT provides a high voltage signal, T4 is opened, and I1 provides the first initial voltage Vinit1 to N1, so that T0 can be turned on at the beginning of the data writing stage S3;

[0332] In the data writing stage S3, R1 provides a high voltage signal, GT provides a low voltage signal, T1 and T3 are opened, DL provides the data voltage Vdata to N2, and N1 is connected with N3;

[0333] At the beginning of the data writing stage S3, T0 is turned on, C3 is charged by Vdata to change the potential of the gate of T0 until T0 is turned off, at this time, the potential of N1 is Vdata+Vth, Vth is the threshold voltage of T0;

[0334] In the first biasing stage S4, HRST provides a low voltage signal, I2 provides the second initial voltage Vinit2 to the anode of O1 to clear the residual charge of the anode of O1; VB1 pulls up the potential of N2 so that T0 is in a biasing state;

[0335] In the light emitting stage S5, EM provides a low voltage signal, T5 and T6 are turned on, and T0 drives O1 to emit light.

[0336] At least one embodiment of the pixel circuit shown in FIG. 17 can control T0 to be in a fixed biasing state in the first biasing stage and the second biasing stage in each refresh frame, restore the threshold voltage of T0, improve the hysteresis of T0, clear the residual charge of the anode of O1, and improve the brightness uniformity of O1.

[0337] At least one embodiment of the pixel circuit shown in FIG. 17 can further have a biasing stage between S3 and S4, and voltage biasing can be performed in the time period other than the data writing stage S3 and the light emitting stage S5 included in the refresh frame.

[0338] In FIG. 18, the holding frame can include a first holding biasing stage S11 and a second holding biasing stage S12; the holding frame can further include a holding light emitting stage S10 arranged after the second holding biasing stage S12;

[0339] In the first holding biasing stage S11 and the second holding biasing stage S12, HRST provides a low voltage signal, I2 provides the second initial voltage Vinit2 to the anode of O1 to clear the residual charge of the anode of O1; VB1 pulls up the potential of N2 so that T0 is in a biasing state;

[0340] In the holding light emitting stage S10, EM provides a low voltage signal, T5 and T6 are turned on, and T0 drives O1 to emit light.

[0341] At least one embodiment of the pixel circuit shown in FIG. 17 can control T0 to be in a fixed biasing state in the first holding biasing stage and the second holding biasing stage in each holding frame, restore the threshold voltage of T0, improve the hysteresis of T0, clear the residual charge of the anode of O1, and improve the brightness uniformity of O1 in low frequency display.

[0342] At least one embodiment of the pixel circuit shown in FIG. 17 can also have the voltage value of the first bias voltage signal provided by VB1 decrease during the first bias stage, the second bias stage, the first holding bias stage, and the second holding bias stage.

[0343] As shown in FIG. 19, on the basis of at least one embodiment of the pixel circuit shown in FIG. 9, the driving circuit includes a driving transistor T0, and the first energy storage circuit includes a first capacitor C1; and the light emitting element is an organic light emitting diode O1.

[0344] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3.

[0345] The first end of the first capacitor C1 is electrically connected to the third node N3, and the second end of the first capacitor C1 is electrically connected to the first bias voltage terminal VB1.

[0346] The compensation control circuit includes a first transistor T1.

[0347] The gate of the first transistor T1 is electrically connected to the scan terminal GT, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the third node N3.

[0348] The data writing circuit includes a third transistor T3, the third energy storage circuit includes a third capacitor C3, and the first initialization circuit includes a fourth transistor T4.

[0349] The gate of the third transistor T3 is electrically connected to the scan terminal GT, the source of the third transistor T3 is electrically connected to the data line DL, and the drain of the third transistor T3 is electrically connected to the second node N2.

[0350] The first end of the third capacitor C3 is electrically connected to the first node N1, and the second end of the third capacitor C3 is electrically connected to the power voltage terminal VDD.

[0351] The gate of the fourth transistor T4 is electrically connected to the reset control terminal R1, the source of the fourth transistor T4 is electrically connected to the first initial voltage terminal I1, and the drain of the fourth transistor T4 is electrically connected to the first node N1.

[0352] The first light emitting control circuit includes a fifth transistor T5, the second light emitting control circuit includes a sixth transistor T6, and the second initialization circuit includes a seventh transistor T7.

[0353] The gate of the fifth transistor T5 is electrically connected with the light-emitting control end EM, the source of the fifth transistor T5 is electrically connected with the power voltage end VDD, and the drain of the fifth transistor T5 is electrically connected with the second node N2.

[0354] The gate of the sixth transistor T6 is electrically connected with the light-emitting control end EM, the source of the sixth transistor T6 is electrically connected with the third node N3, and the drain of the sixth transistor T6 is electrically connected with the anode of O1.

[0355] The gate of the seventh transistor T7 is electrically connected with the initial control end HRST, the source of the seventh transistor T7 is electrically connected with the second initial voltage end I2, and the drain of the seventh transistor T7 is electrically connected with the anode of O1.

[0356] The cathode of O1 is electrically connected with the low voltage end VSS.

[0357] In at least one embodiment of the pixel circuit shown in FIG. 19, all the transistors are p-type transistors.

[0358] In at least one embodiment of the pixel circuit shown in FIG. 19, the write control end and the compensation control end are both scan ends GT.

[0359] As shown in FIG. 18, in at least one embodiment of the pixel circuit shown in FIG. 19, during operation, a refresh frame can include a second bias stage S1, a reset stage S2, a data write stage S3, a first bias stage S4 and a light-emitting stage S5 arranged in sequence.

[0360] In the second bias stage S1, HRST provides a low voltage signal, I2 provides a second initial voltage Vinit2 to the anode of O1, and residual charges at the anode of O1 are cleared; VB1 pulls up the potential of N3, so that T0 is in a bias state.

[0361] In the reset stage S2, R1 provides a low voltage signal, HRST provides a high voltage signal, GT provides a high voltage signal, T4 is turned on, and I1 provides a first initial voltage Vinit1 to N1, so that T0 can be turned on at the beginning of the data write stage S3.

[0362] In the data write stage S3, R1 provides a high voltage signal, GT provides a low voltage signal, T1 and T3 are turned on, DL provides a data voltage Vdata to N2, and N1 is connected with N3.

[0363] At the beginning of the data write stage S3, T0 is turned on, Vdata charges C3 to change the potential of the gate of T0, until T0 is turned off, at which time the potential of N1 is Vdata+Vth, and Vth is the threshold voltage of T0.

[0364] In the first biasing stage S4, the HRST provides a low voltage signal, the I2 provides the second initial voltage Vinit2 to the anode of the O1, and the residual charge at the anode of the O1 is cleared; the VB1 pulls up the potential of the N3, so that the T0 is in a biasing state.

[0365] In the light emitting stage S5, the EM provides a low voltage signal, the T5 and the T6 are turned on, and the T0 drives the O1 to emit light.

[0366] At least one embodiment of the pixel circuit shown in FIG. 19 is in operation, in each refresh frame, the T0 can be controlled to be in a fixed biasing state in the refresh period and the refresh stage, the threshold voltage of the T0 is recovered, the hysteresis phenomenon of the T0 is improved, the residual charge at the anode of the O1 is cleared, and the brightness uniformity of the O1 is improved.

[0367] At least one embodiment of the pixel circuit shown in FIG. 20 is in operation, in the period other than the data writing stage S3 and the light emitting stage S5 included in the refresh frame, voltage biasing can be performed.

[0368] In FIG. 18, the holding frame can include a first holding biasing stage S11 and a second holding biasing stage S12.

[0369] In the first holding biasing stage S11 and the second holding biasing stage S12, the HRST provides a low voltage signal, the I2 provides the second initial voltage Vinit2 to the anode of the O1, and the residual charge at the anode of the O1 is cleared; the VB1 pulls up the potential of the N3, so that the T0 is in a biasing state.

[0370] At least one embodiment of the pixel circuit shown in FIG. 19 is in operation, in each refresh frame, the T0 can be controlled to be in a fixed biasing state in the refresh period and the refresh stage, the threshold voltage of the T0 is recovered, the hysteresis phenomenon of the T0 is improved, the residual charge at the anode of the O1 is cleared, and the brightness uniformity of the O1 is improved.

[0371] At least one embodiment of the pixel circuit shown in FIG. 19 is in operation, in the first biasing stage, the second biasing stage, the first holding biasing stage, and the second holding biasing stage, the voltage value of the first biasing voltage signal provided by the VB1 can also be lowered.

[0372] As shown in FIG. 20, on the basis of at least one embodiment of the pixel circuit shown in FIG. 11, the driving circuit includes the driving transistor T0, the first energy storage circuit includes the first capacitor C1; and the light emitting element is the organic light emitting diode O1.

[0373] The gate of the driving transistor T0 is electrically connected with the first node N1, the source of the driving transistor T0 is electrically connected with the second node N2, and the drain of the driving transistor T0 is electrically connected with the third node N3;

[0374] The first end of the first capacitor C1 is electrically connected with the second node N2, and the second end of the first capacitor C1 is electrically connected with the first bias voltage terminal VB1;

[0375] The first compensation circuit comprises a first transistor T1, the second compensation circuit comprises a second transistor T2, and the second energy storage circuit comprises a second capacitor C2;

[0376] The gate of the first transistor T1 is electrically connected with the scan terminal GT, the source of the first transistor T1 is electrically connected with the first node N1, and the drain of the first transistor T1 is electrically connected with the intermediate node NZ;

[0377] The gate of the second transistor T2 is electrically connected with the scan terminal GT, the source of the second transistor T2 is electrically connected with the intermediate node NZ, and the drain of the second transistor T2 is electrically connected with the third node N3;

[0378] The first end of the second capacitor C2 is electrically connected with the intermediate node NZ, and the second end of the second capacitor C2 is electrically connected with the second bias voltage terminal VB2;

[0379] The data writing circuit comprises a third transistor T3, the third energy storage circuit comprises a third capacitor C3, and the first initialization circuit comprises a fourth transistor T4;

[0380] The gate of the third transistor T3 is electrically connected with the scan terminal GT, the source of the third transistor T3 is electrically connected with the data line DL, and the drain of the third transistor T3 is electrically connected with the second node N2;

[0381] The first end of the third capacitor C3 is electrically connected with the first node N1, and the second end of the third capacitor C3 is electrically connected with the power voltage terminal VDD;

[0382] The gate of the fourth transistor T4 is electrically connected with the reset control terminal R1, the source of the fourth transistor T4 is electrically connected with the first initial voltage terminal I1, and the drain of the fourth transistor T4 is electrically connected with the first node N1;

[0383] The first light-emitting control circuit comprises a fifth transistor T5, the second light-emitting control circuit comprises a sixth transistor T6, and the second initialization circuit comprises a seventh transistor T7;

[0384] The gate of the fifth transistor T5 is electrically connected with the light-emitting control end EM, the source of the fifth transistor T5 is electrically connected with the power voltage end VDD, and the drain of the fifth transistor T5 is electrically connected with the second node N2.

[0385] The gate of the sixth transistor T6 is electrically connected with the light-emitting control end EM, the source of the sixth transistor T6 is electrically connected with the third node N3, and the drain of the sixth transistor T6 is electrically connected with the anode of O1; the cathode of O1 is electrically connected with the low voltage end VSS.

[0386] The gate of the seventh transistor T7 is electrically connected with the initial control end HRST, the source of the seventh transistor T7 is electrically connected with the second initial voltage end I2, and the drain of the seventh transistor T7 is electrically connected with the anode of O1.

[0387] In at least one embodiment of the pixel circuit shown in FIG. 20, all the transistors are p-type transistors.

[0388] In at least one embodiment of the pixel circuit shown in FIG. 20, the write control end and the compensation control end are both scanning ends GT.

[0389] In at least one embodiment of the present disclosure, the voltage value of the second bias voltage signal provided by VB2 can be greater than or equal to -7V and less than or equal to 7V.

[0390] As shown in FIG. 21, in at least one embodiment of the pixel circuit shown in FIG. 20 of the present disclosure, when working, the refresh frame can include the second bias stage S1, the reset stage S2, the data writing stage S3, the first bias stage S4 and the light-emitting stage S5 arranged in sequence;

[0391] In the second bias stage S1, HRST provides a low voltage signal, T7 is turned on, I2 provides the second initial voltage Vinit2 to the anode of O1 to clear the residual charge of the anode of O1; the first bias voltage signal provided by VB1 pulls up the potential of N2, so that T0 is in a bias state; VB2 pulls up the potential of NZ to reduce the potential difference between N1 and NZ and reduce the leakage of N1;

[0392] In the reset stage S2, R1 provides a low voltage signal, T4 is turned on, and I1 provides the first initial voltage Vinit1 to N1, so that T0 can be turned on at the beginning of the data writing stage S3;

[0393] In the data writing stage S3, GT provides a low voltage signal, T1, T2 and T3 are turned on, DL provides the data voltage Vdata to N2, and N1 and N3 are connected;

[0394] At the beginning of the data writing stage S3, T0 is turned on, C3 is charged through Vdata, the potential of N1 is changed, until T0 is turned off, at this time, the potential of N1 is Vdata+Vth, wherein Vth is the threshold voltage of T0;

[0395] In the first bias stage S4, HRST provides a low voltage signal, T7 is turned on, I2 provides the second initial voltage Vinit2 to the anode of O1, and the residual charge of the anode of O1 is cleared; the first bias voltage signal provided by VB1 pulls up the potential of N2, so that T0 is in a bias state; VB2 pulls up the potential of NZ, so as to reduce the potential difference between N1 and NZ and the leakage of N1;

[0396] In the light emitting stage S5, EM provides a low voltage signal, T5 and T6 are turned on, and T0 drives O1 to emit light.

[0397] At least one embodiment of the pixel circuit shown in FIG. 20 works as follows: in each holding frame, in the holding bias stage, T0 can be controlled to be in a fixed bias state, the threshold voltage of T0 is recovered, the hysteresis of T0 is improved, and the residual charge of the anode of O1 is cleared, so that the brightness uniformity of O1 can be improved when low-frequency display is performed.

[0398] At least one embodiment of the pixel circuit shown in FIG. 20 works as follows: in the first bias stage, the second bias stage and the holding bias stage, the voltage value of the first bias voltage signal provided by VB1 can also be reduced.

[0399] As shown in FIG. 22, at least one embodiment of the pixel circuit shown in FIG. 8 is based on the following,

[0400] The driving circuit comprises a driving transistor T0, and the first energy storage circuit comprises a first capacitor C1; and the light emitting element is an organic light emitting diode O1;

[0401] The gate of the driving transistor T0 is electrically connected with the first node N1, the source of the driving transistor T0 is electrically connected with the second node N2, and the drain of the driving transistor T0 is electrically connected with the third node N3;

[0402] The first end of the first capacitor C1 is electrically connected with the second node N2, and the second end of the first capacitor C1 is electrically connected with a first bias voltage terminal VB1;

[0403] The compensation control circuit comprises a first transistor T1;

[0404] The gate of the first transistor T1 is electrically connected with a compensation control terminal SC, the source of the first transistor T1 is electrically connected with the first node N1, and the drain of the first transistor T1 is electrically connected with the third node N3.

[0405] The data writing circuit comprises a third transistor T3, the third energy storage circuit comprises a third capacitor C3, and the first initialization circuit comprises a fourth transistor T4.

[0406] The gate of the third transistor T3 is electrically connected with the writing control end SW, the source of the third transistor T3 is electrically connected with the data line DL, and the drain of the third transistor T3 is electrically connected with the second node N2.

[0407] The first end of the third capacitor C3 is electrically connected with the first node N1, and the second end of the third capacitor C3 is electrically connected with the power voltage end VDD.

[0408] The gate of the fourth transistor T4 is electrically connected with the reset control end R1, the source of the fourth transistor T4 is electrically connected with the first initial voltage end I1, and the drain of the fourth transistor T4 is electrically connected with the third node N3.

[0409] The first light-emitting control circuit comprises a fifth transistor T5, the second light-emitting control circuit comprises a sixth transistor T6, and the second initialization circuit comprises a seventh transistor T7.

[0410] The gate of the fifth transistor T5 is electrically connected with the light-emitting control end EM, the source of the fifth transistor T5 is electrically connected with the power voltage end VDD, and the drain of the fifth transistor T5 is electrically connected with the second node N2.

[0411] The gate of the sixth transistor T6 is electrically connected with the light-emitting control end EM, the source of the sixth transistor T6 is electrically connected with the third node N3, and the drain of the sixth transistor T6 is electrically connected with the anode of O1.

[0412] The gate of the seventh transistor T7 is electrically connected with the initial control end HRST, the source of the seventh transistor T7 is electrically connected with the second initial voltage end I2, and the drain of the seventh transistor T7 is electrically connected with the anode of O1.

[0413] The cathode of O1 is electrically connected with the low voltage end VSS.

[0414] At least one embodiment of the pixel circuit shown in FIG. 22 of the present disclosure is an LTPO pixel circuit, T1 is an n-type transistor, and the other transistors except T1 are p-type transistors.

[0415] As shown in FIG. 23, at least one embodiment of the pixel circuit shown in FIG. 22 of the present disclosure works, and the refresh frame can comprise the second bias stage S1, the reset stage S2, the data writing stage S3, the first bias stage S4 and the light-emitting stage S5 arranged in sequence.

[0416] In the second biasing stage S1, the HRST provides a low voltage signal, the I2 provides the second initial voltage Vinit2 to the anode of the O1, to clear the residual charge of the anode of the O1; the VB1 pulls up the potential of the N2, so that the T0 is in a biasing state;

[0417] In the reset stage S2, the R1 provides a low voltage signal, the HRST provides a high voltage signal, the SC provides a high voltage signal, the SW provides a high voltage signal, the T4 and the T1 are opened, the I1 provides the first initial voltage Vinit1 to the N1, so that the T0 can be turned on at the beginning of the data writing stage S3;

[0418] In the data writing stage S3, the R1 provides a high voltage signal, the SC provides a high voltage signal, the SW provides a low voltage signal, the T1 and the T3 are opened, the DL provides the data voltage Vdata to the N2, the N1 is communicated with the N3;

[0419] At the beginning of the data writing stage S3, the T0 is turned on, the C3 is charged by the Vdata to change the potential of the gate of the T0, until the T0 is turned off, at this time, the potential of the N1 is Vdata+Vth, and the Vth is the threshold voltage of the T0;

[0420] In the first biasing stage S4, the HRST provides a low voltage signal, the I2 provides the second initial voltage Vinit2 to the anode of the O1, to clear the residual charge of the anode of the O1; the VB1 pulls up the potential of the N2, so that the T0 is in a biasing state;

[0421] In the light emitting stage S5, the EM provides a low voltage signal, the T5 and the T6 are opened, and the T0 drives the O1 to emit light.

[0422] At least one embodiment of the pixel circuit shown in FIG. 22 can control the T0 to be in a fixed biasing state in the refresh time period and the refresh stage, restore the threshold voltage of the T0, improve the hysteresis phenomenon of the T0, clear the residual charge of the anode of the O1, and improve the brightness uniformity of the O1 in each refresh frame.

[0423] At least one embodiment of the pixel circuit shown in FIG. 22 can further have a biasing stage between the reset stage S2 and the data writing stage S3 in operation; and the voltage biasing can be performed in the time period other than the data writing stage and the light emitting stage included in the refresh frame.

[0424] In FIG. 22, the holding frame can include the first holding biasing stage S11 and the second holding biasing stage S12;

[0425] In the first holding bias stage S11 and the second holding bias stage S12, the HRST provides a low voltage signal, I2 provides the second initial voltage Vinit2 to the anode of O1, and the residual charge of the anode of O1 is cleared; VB1 pulls up the potential of N2, so that T0 is in a bias state.

[0426] At least one embodiment of the pixel circuit shown in FIG. 22 works as follows: in each holding frame, T0 can be controlled to be in a fixed bias state in the first holding bias stage and the second holding bias stage, the threshold voltage of T0 is recovered, the hysteresis phenomenon of T0 is improved, and the residual charge of the anode of O1 is cleared, so that the brightness uniformity of O1 can be improved when low-frequency display is performed.

[0427] At least one embodiment of the pixel circuit shown in FIG. 22 works as follows: in the first bias stage, the second bias stage, the first holding bias stage, and the second holding bias stage, the voltage value of the first bias voltage signal provided by VB1 can also be lowered.

[0428] At least one embodiment of the pixel circuit shown in FIG. 24 is different from at least one embodiment of the pixel circuit shown in FIG. 22 as follows: the first end of C1 is electrically connected to the third node N3, the potential of N3 is changed by the first bias voltage signal provided by VB1, so that T0 is in a bias state.

[0429] At least one embodiment of the pixel circuit shown in FIG. 25 is different from at least one embodiment of the pixel circuit shown in FIG. 20 as follows: C1 is not included.

[0430] As shown in FIG. 26, on the basis of at least one embodiment of the pixel circuit shown in FIG. 16B, the driving circuit includes a driving transistor T0; and the light-emitting element is an organic light-emitting diode O1.

[0431] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3.

[0432] The first compensation circuit includes a first transistor T1, and the second compensation circuit includes a second transistor T2; and the second energy storage circuit includes a second capacitor C2.

[0433] The gate of the first transistor T1 is electrically connected to the on-off control end AZ, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the intermediate node NZ.

[0434] A gate of the second transistor T2 is electrically connected with the on-off control end AZ, a source of the second transistor T2 is electrically connected with the intermediate node NZ, and a drain of the second transistor T2 is electrically connected with the third node N3;

[0435] A first end of the second capacitor C2 is electrically connected with the intermediate node NZ, and a second end of the second capacitor C2 is electrically connected with the third bias voltage end VB3;

[0436] The first initialization circuit comprises a fourth transistor T4;

[0437] A gate of the fourth transistor T4 is electrically connected with the reset control end R1, a source of the fourth transistor T4 is electrically connected with the first initial voltage end I1, and a drain of the fourth transistor T4 is electrically connected with the third node N3;

[0438] The first light-emitting control circuit comprises a fifth transistor T5, the second light-emitting control circuit comprises a sixth transistor T6, and the second initialization circuit comprises a seventh transistor T7;

[0439] A gate of the fifth transistor T5 is electrically connected with the first light-emitting control end EM1, a source of the fifth transistor T5 is electrically connected with the power voltage end VDD, and a drain of the fifth transistor T5 is electrically connected with the second node N2;

[0440] A gate of the sixth transistor T6 is electrically connected with the second light-emitting control end EM2, a source of the sixth transistor T6 is electrically connected with the third node N3, and a drain of the sixth transistor T6 is electrically connected with an anode of O1; a cathode of O1 is electrically connected with the low voltage end VSS;

[0441] A gate of the seventh transistor T7 is electrically connected with the initial control end HRST, a source of the seventh transistor T7 is electrically connected with the second initial voltage end I2, and a drain of the seventh transistor T7 is electrically connected with the anode of O1;

[0442] The fourth energy storage circuit comprises a fourth capacitor C4, the fifth energy storage circuit comprises a fifth capacitor C5, the data writing circuit comprises a third transistor T3, the first control circuit comprises an eighth transistor T8, the second control circuit comprises a ninth transistor T9, and the sixth energy storage circuit comprises a sixth capacitor C6;

[0443] A first end of the fourth capacitor C4 is electrically connected with the first node N1, a second end of the fourth capacitor C4 is electrically connected with the first control node NC1, a first end of the fifth capacitor N5 is electrically connected with the first control node NC1, and a second end of the fifth capacitor C5 is electrically connected with the writing node NW;

[0444] The gate of the third transistor T3 is electrically connected with the scan terminal GT, the source of the third transistor T3 is electrically connected with the data line DL, and the drain of the third transistor T3 is electrically connected with the write node NW.

[0445] The gate of the eighth transistor T8 is electrically connected with the on-off control terminal AZ, the source of the eighth transistor T8 is electrically connected with the first control node NC1, and the drain of the eighth transistor T8 is electrically connected with the second control node NC2.

[0446] The gate of the ninth transistor T9 is electrically connected with the on-off control terminal AZ, the source of the ninth transistor T9 is electrically connected with the second control node NC2, and the drain of the ninth transistor T9 is electrically connected with the power voltage terminal VDD.

[0447] The first end of the sixth capacitor C6 is electrically connected with the second control node NC2, and the second end of the sixth capacitor C6 is electrically connected with the third bias voltage terminal VB3.

[0448] The setting circuit comprises a tenth transistor T10.

[0449] The gate of the tenth transistor T10 is electrically connected with the first light-emitting control terminal EM1, the source of the tenth transistor T10 is electrically connected with the first reference voltage terminal REF1, and the drain of the tenth transistor T10 is electrically connected with the write node NW.

[0450] The third initialization circuit comprises an eleventh transistor T11.

[0451] The gate of T11 is electrically connected with HRST, the source of T11 is electrically connected with the second reference voltage terminal REF2, and the drain of T11 is electrically connected with the second node N2.

[0452] In at least one embodiment of the pixel circuit shown in FIG. 26, all transistors are p-type transistors.

[0453] In at least one embodiment of the pixel circuit shown in FIG. 26, the compensation control terminal and the on-off control terminal are the same control terminal, the setting control terminal and the first light-emitting control terminal are the same control terminal, the write control terminal is the scan terminal, the setting voltage terminal is the first reference voltage terminal, and the second bias voltage terminal and the third bias voltage terminal are the same bias voltage terminal.

[0454] As shown in FIG. 27, in at least one embodiment of the pixel circuit shown in FIG. 26 of the present disclosure, during operation, a refresh frame comprises a first setting stage S01, a second setting stage S02, a compensation stage S03, a data writing stage S3, a bias stage S0, a third setting stage S04 and a light-emitting stage S5 arranged in sequence.

[0455] In the first setting stage S01, EM1 provides a high voltage signal, EM2 provides a high voltage signal, AZ provides a low voltage signal, HRST provides a low voltage signal, R1 provides a high voltage signal, GT provides a high voltage signal, T7 and T11 are opened, I2 provides a second initial voltage Vinit2 to the anode of O1, and the residual charge of the anode of O1 is cleared; REF2 provides a second reference voltage Vref2 to N2, and the hysteresis of T0 is improved;

[0456] In the second setting stage S02, EM1 provides a high voltage signal, EM2 provides a high voltage signal, AZ provides a low voltage signal, HRST provides a high voltage signal, R1 provides a low voltage signal, GT provides a high voltage signal, T1 and T2 are opened, and I1 provides a first initial voltage Vinit1 to N1, so that T0 can be turned on at the beginning of the compensation stage S03;

[0457] In the compensation stage S03, EM1 provides a low voltage signal, EM2 provides a high voltage signal, AZ provides a low voltage signal, HRST provides a high voltage signal, R1 provides a high voltage signal, GT provides a high voltage signal, T5 is opened, T10 is opened, and T1 and T2 are opened;

[0458] At the beginning of the compensation stage S03, T0 is opened, the power voltage signal provided by VDD charges C4 and C5, changes the potential of N1, until the potential of N1 becomes Vdd+Vth, and T0 is turned off, wherein Vdd is the voltage value of the power voltage signal provided by VDD, and Vth is the threshold voltage of T0;

[0459] In the data writing stage S3, EM1 provides a high voltage signal, EM2 provides a high voltage signal, AZ provides a low voltage signal, HRST provides a high voltage signal, R1 provides a high voltage signal, GT provides a low voltage signal, T3 is opened, and DL provides a data voltage Vdata to NW;

[0460] In the bias stage S0, the voltage value of the third bias voltage signal provided by VB3 is reduced, so as to reduce the voltage difference between NZ and N1, reduce the leakage of N1, reduce the voltage difference between NC1 and NC2, and reduce the leakage of N2;

[0461] In the bias stage S0, AZ provides a high voltage signal, and T1, T2, T8 and T9 are turned off;

[0462] In the bias stage S0, EM1 provides a low voltage signal, T10 is opened, REF1 writes a first reference voltage Vref1 to NW, so as to write Vdata to N1;

[0463] In the third setting stage S04, EM1 provides a high voltage signal, EM2 provides a high voltage signal, AZ provides a high voltage signal, HRST provides a low voltage signal, R1 provides a high voltage signal, GT provides a high voltage signal, T7 and T11 are opened, I2 provides the second initial voltage Vinit2 to the anode of O1 to clear the residual charge of the anode of O1; REF2 provides the second reference voltage Vref2 to N2 to improve the hysteresis of T0;

[0464] In the light emitting stage S5, EM1 provides a low voltage signal, EM2 provides a low voltage signal, AZ provides a high voltage signal, HRST provides a high voltage signal, R1 provides a high voltage signal, GT provides a high voltage signal, T5 and T6 are opened, and T0 drives O1 to emit light.

[0465] At least one embodiment of the pixel circuit shown in FIG. 26 of the present disclosure, when in operation, during the time period of the refresh frame except the light emitting stage S5, when AZ provides a high voltage signal, a biasing stage can be set to perform voltage biasing.

[0466] As shown in FIG. 28, at least one embodiment of the pixel circuit shown in FIG. 26 of the present disclosure, when in operation, the holding frame can include a holding biasing stage S20, a holding reset stage S21 and a holding light emitting stage S10 set in sequence;

[0467] In the holding biasing stage S20, EM1 provides a high voltage signal, EM2 provides a high voltage signal, AZ provides a high voltage signal, HRST provides a high voltage signal, R1 provides a high voltage signal, GT provides a high voltage signal, and the voltage value of the third biasing voltage signal provided by VB3 is decreased to reduce the voltage difference between NZ and N1, reduce the leakage of N1, reduce the voltage difference between NC1 and NC2, and reduce the leakage of N2;

[0468] In the holding reset stage S21, EM1 provides a high voltage signal, EM2 provides a high voltage signal, AZ provides a high voltage signal, HRST provides a low voltage signal, R1 provides a high voltage signal, GT provides a high voltage signal, T7 and T11 are opened, I2 provides the second initial voltage Vinit2 to the anode of O1 to clear the residual charge of the anode of O1; REF2 provides the second reference voltage Vref2 to N2 to improve the hysteresis of T0;

[0469] In the holding light emitting stage S10, EM1 provides a low voltage signal, EM2 provides a low voltage signal, AZ provides a high voltage signal, HRST provides a high voltage signal, R1 provides a high voltage signal, GT provides a high voltage signal, T5 and T6 are opened, and T0 drives O1 to emit light.

[0470] The pixel driving method provided by the embodiments of the present disclosure is applied to the pixel circuit described above, and a display period includes a bias stage and a light emitting stage arranged in sequence; the pixel driving method includes:

[0471] In the bias stage, the potential of the first terminal of the first energy storage circuit is changed by a first bias voltage signal, so that the driving transistor included in the driving circuit is in a bias state; and / or, in the bias stage, the potential of the first terminal of the second energy storage circuit is changed by a second bias voltage signal, so as to reduce the leakage current of the first node;

[0472] In the light emitting stage, the driving circuit generates a driving current for driving the light emitting element.

[0473] In at least one embodiment of the present disclosure, the pixel circuit further includes a data writing circuit; the data writing circuit is electrically connected with a writing control terminal, a data line and the second node respectively; the display period further includes a data writing stage arranged before the light emitting stage, and the data writing stage is independent of the bias stage; the pixel driving method includes:

[0474] In the data writing stage, the data writing circuit writes a data voltage provided by the data line into the second node under the control of a writing control signal;

[0475] In the bias stage, the compensation control circuit controls the disconnection between the first node and the third node under the control of a compensation control signal.

[0476] In specific implementation, the bias stage can be arranged at a time other than the data writing stage and the light emitting stage included in the display period, so as to perform voltage biasing, and in the bias stage, the compensation control circuit controls the disconnection between the first node and the third node under the control of a compensation control signal.

[0477] Optionally, the pixel circuit further includes a fourth energy storage circuit, a fifth energy storage circuit, a data writing circuit, a first control circuit, a second control circuit and a sixth energy storage circuit; the display period further includes a bias voltage stage; the bias voltage stage is arranged before the light emitting stage; the pixel driving method includes:

[0478] In the bias voltage stage, the potential of the second control node is changed by providing a third bias voltage signal, so as to reduce the leakage current of the first control node; the first control circuit controls the disconnection between the first control node and the second control node under the control of a pass-through control signal; the second control circuit controls the disconnection between the second control node and the second voltage terminal under the control of the pass-through control signal.

[0479] In a specific implementation, the display period includes a time period other than the light emitting stage, when the first control circuit controls the first control node to be disconnected from the second control node under the control of the on-off control signal, and the second control circuit controls the second control node to be disconnected from the second voltage terminal under the control of the on-off control signal, a bias voltage stage is set, in which the potential of the second control node is changed by providing a third bias voltage signal to reduce the leakage current of the first control node.

[0480] In at least one embodiment of the present disclosure, the display period is a refresh frame, and the holding frame includes a holding bias stage and a holding light emitting stage arranged in sequence; the pixel driving method further includes:

[0481] In the holding bias stage, the potential of the first terminal of the first energy storage circuit is changed by the first bias voltage signal so that the drive transistor is in a bias state; and / or, in the holding bias stage, the potential of the first terminal of the second energy storage circuit is changed by the second bias voltage signal to reduce the leakage current of the first node;

[0482] In the holding bias stage, the compensation control circuit controls the first node to be disconnected from the third node under the control of the compensation control signal;

[0483] In the holding light emitting stage, the drive circuit generates a drive current to drive the light emitting element.

[0484] In a specific implementation, the holding frame can include a holding bias stage and a holding light emitting stage arranged in sequence, in the holding bias stage, the potential of the first terminal of the first energy storage circuit is changed by the first bias voltage signal so that the drive transistor is in a bias state; and / or, the potential of the first terminal of the second energy storage circuit is changed by the second bias voltage signal to reduce the leakage current of the first node.

[0485] Optionally, the pixel circuit further includes a data writing circuit; the data writing circuit is electrically connected with the writing control terminal, the data line and the second node respectively; the pixel driving method further includes:

[0486] In the holding bias stage, the data writing circuit controls the data line to be disconnected from the second node under the control of the writing control signal.

[0487] In at least one embodiment of the present disclosure, the pixel circuit further includes a fourth energy storage circuit, a fifth energy storage circuit, a data writing circuit, a first control circuit, a second control circuit and a sixth energy storage circuit; the holding frame further includes a holding bias voltage stage arranged before the holding light emitting stage; the pixel driving method further includes:

[0488] In the holding bias stage, the potential of the second control node is changed by providing a third bias voltage signal to reduce the leakage current of the first control node; the first control circuit controls the disconnection between the first control node and the second control node under the control of the on-off control signal; and the second control circuit controls the disconnection between the second control node and the second voltage terminal under the control of the on-off control signal.

[0489] In a specific implementation, the holding frame includes a holding bias stage and a holding light-emitting stage arranged in sequence, in the holding bias stage, the potential of the second control node is changed by providing a third bias voltage signal to reduce the leakage current of the first control node; and in the holding bias stage, the first control circuit controls the disconnection between the first control node and the second control node under the control of the on-off control signal; and the second control circuit controls the disconnection between the second control node and the second voltage terminal under the control of the on-off control signal.

[0490] The display device includes the pixel circuit.

[0491] The above describes the preferred embodiments of the present disclosure, and it should be pointed out that for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should be considered as the protection scope of the present disclosure.

Claims

1. A pixel circuit, comprising a light emitting element, a driving circuit and a compensation control circuit; a control terminal of the driving circuit is electrically connected with a first node, a first terminal of the driving circuit is electrically connected with a second node, a second terminal of the driving circuit is electrically connected with a third node, and the driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node; the compensation control circuit is electrically connected with a compensation control terminal, the first node and the third node respectively, and is configured to control the communication or disconnection between the first node and the third node under the control of a compensation control signal provided by the compensation control terminal; the pixel circuit further comprises a first energy storage circuit, a first terminal of the first energy storage circuit is electrically connected with the second node or the third node, a second terminal of the first energy storage circuit is electrically connected with a first bias voltage terminal, and the first energy storage circuit is configured to control the potential of the first terminal of the first energy storage circuit according to a first bias voltage signal provided by the first bias voltage terminal, wherein the first bias voltage signal is a variable voltage signal; and / or, the pixel circuit further comprises a second energy storage circuit, the compensation control circuit comprises a first compensation circuit and a second compensation circuit, the first compensation circuit is electrically connected with the compensation control terminal, the first node and an intermediate node respectively, and is configured to control the communication or disconnection between the first node and the intermediate node under the control of the compensation control signal provided by the compensation control terminal, the second compensation circuit is electrically connected with the compensation control terminal, the intermediate node and the third node respectively, and is configured to control the communication or disconnection between the intermediate node and the third node under the control of the compensation control signal provided by the compensation control terminal, a first terminal of the second energy storage circuit is electrically connected with the intermediate node, and a second terminal of the second energy storage circuit is electrically connected with a second bias voltage terminal, and the second energy storage circuit is configured to control the potential of the first terminal of the second energy storage circuit according to a second bias voltage signal provided by the second bias voltage terminal; the second bias voltage signal is a variable voltage signal.

2. The pixel circuit of claim 1, wherein, further comprising a data writing circuit, a third energy storage circuit and a first initialization circuit; the data writing circuit is electrically connected with a writing control terminal, a data line and the second node respectively, and is configured to control the communication or disconnection between the data line and the second node under the control of a writing control signal provided by the writing control terminal; the third energy storage circuit is electrically connected with the first node, and is configured to maintain the potential of the first node; the first initialization circuit is electrically connected with a reset control terminal and a first initial voltage terminal respectively, and is further electrically connected with the first node or the third node, and is configured to control the writing of a first initial voltage provided by the first initial voltage terminal into the first node or the third node under the control of a reset control signal provided by the reset control terminal.

3. The pixel circuit of claim 1, wherein, further comprising a fourth energy storage circuit, a fifth energy storage circuit, a data writing circuit, a first control circuit, a second control circuit and a sixth energy storage circuit. a first end of the fourth energy storage circuit is electrically connected with the first node, a second end of the fourth energy storage circuit is electrically connected with the first control node, a first end of the fifth energy storage circuit is electrically connected with the first control node, a second end of the fifth energy storage circuit is electrically connected with the write node, and the fourth energy storage circuit and the fifth energy storage circuit are used for storing electric energy; the data write circuit is electrically connected with the write control end, the data line and the write node respectively, and is used for controlling the data line to be in communication or disconnection with the write node under the control of a write control signal provided by the write control end; the first control circuit is electrically connected with the on-off control end, the first control node and the second control node respectively, and is used for controlling the first control node to be in communication or disconnection with the second control node under the control of an on-off control signal provided by the on-off control end; the second control circuit is electrically connected with the on-off control end, the second control node and the second voltage end respectively, and is used for controlling the second control node to be in communication or disconnection with the second voltage end under the control of the on-off control signal; a first end of the sixth energy storage circuit is electrically connected with the second control node, and a second end of the sixth energy storage circuit is electrically connected with a third bias voltage end, the sixth energy storage circuit being used for controlling the electric potential of the second control node according to a third bias voltage signal provided by the third bias voltage end; the third bias voltage signal is a variable voltage signal. a setting circuit is further included; 4. The pixel circuit of claim 3, wherein, the setting circuit is electrically connected with the setting control end, the setting voltage end and the write node respectively, and is used for controlling the setting voltage end to be in communication or disconnection with the write node under the control of a setting control signal provided by the setting control end. a first light emitting control circuit, a second light emitting control circuit and a second initialization circuit are further included; 5. The pixel circuit of claim 1, wherein, the first light emitting control circuit is electrically connected with the first light emitting control end, the power voltage end and the second node respectively, and is used for controlling the power voltage end to be in communication or disconnection with the second node under the control of a first light emitting control signal provided by the first light emitting control end; the second light emitting control circuit is electrically connected with the second light emitting control end, the third node and the first pole of the light emitting element respectively, and is used for controlling the third node to be in communication or disconnection with the first pole of the light emitting element under the control of a second light emitting control signal provided by the second light emitting control end; the second initialization circuit is electrically connected with the initial control end, the second initial voltage end and the first pole of the light emitting element respectively, and is used for controlling the second initial voltage end to be in communication or disconnection with the first pole of the light emitting element under the control of an initial control signal provided by the initial control end; the second pole of the light emitting element is electrically connected with the first voltage end.

6. The pixel circuit according to any one of claims 1 to 5, wherein the first bias voltage end is used for changing the electric potential of the first end of the first energy storage circuit by providing a first bias voltage signal in a bias stage, so that a drive transistor included in the drive circuit is in a bias state. ​ The display period of the pixel circuit comprises a bias stage, a data writing stage and a light emitting stage which are independent of each other.

7. The pixel circuit of any one of claims 1 to 5, wherein, The second bias voltage terminal is configured to change the potential of the first end of the second energy storage circuit by providing a second bias voltage signal in the bias stage, so as to reduce the leakage current of the first node. The display period of the pixel circuit comprises a bias stage, a data writing stage and a light emitting stage which are independent of each other. The first compensation circuit is configured to control the disconnection between the first node and the intermediate node under the control of the compensation control signal in the bias stage. The second compensation circuit is configured to control the disconnection between the intermediate node and the third node under the control of the compensation control signal in the bias stage.

8. The pixel circuit of claim 3, wherein, The third bias voltage terminal is configured to change the potential of the second control node by providing a third bias voltage signal in the bias stage, so as to reduce the leakage current of the first control node. The display period of the pixel circuit comprises a bias stage and a light emitting stage which are independent of each other. The first control circuit is configured to control the disconnection between the first control node and the second control node under the control of the on-off control signal in the bias stage. The second control circuit is configured to control the disconnection between the second control node and the second voltage terminal under the control of the on-off control signal in the bias stage.

9. The pixel circuit of claim 1, wherein, The driving circuit comprises a driving transistor, and the first energy storage circuit comprises a first capacitor. The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node. The first end of the first capacitor is electrically connected with the second node or the third node, and the second end of the first capacitor is electrically connected with the first bias voltage terminal.

10. The pixel circuit of claim 1, wherein, The first compensation circuit comprises a first transistor, the second compensation circuit comprises a second transistor, and the second energy storage circuit comprises a second capacitor. The gate of the first transistor is electrically connected with the compensation control terminal, the first pole of the first transistor is electrically connected with the first node, and the second pole of the first transistor is electrically connected with the intermediate node. The gate of the second transistor is electrically connected with the compensation control terminal, the first pole of the second transistor is electrically connected with the intermediate node, and the second pole of the second transistor is electrically connected with the third node. The first end of the second capacitor is electrically connected with the intermediate node, and the second end of the second capacitor is electrically connected with the second bias voltage terminal.

11. The pixel circuit of claim 1, wherein, The compensation control circuit comprises a first transistor. The gate of the first transistor is electrically connected with the compensation control terminal, the first pole of the first transistor is electrically connected with the first node, and the second pole of the first transistor is electrically connected with the third node.

12. The pixel circuit of claim 2, wherein, The data writing circuit comprises a third transistor, the third energy storage circuit comprises a third capacitor, and the first initialization circuit comprises a fourth transistor. The gate of the third transistor is electrically connected with the writing control terminal, the first pole of the third transistor is electrically connected with the data line, and the second pole of the third transistor is electrically connected with the second node. A first end of the third capacitor is electrically connected with the first node, and a second end of the third capacitor is electrically connected with a direct current voltage terminal; A gate of the fourth transistor is electrically connected with a reset control terminal, a first pole of the fourth transistor is electrically connected with the first initial voltage terminal, and a second pole of the fourth transistor is electrically connected with the first node or the third node.

13. The pixel circuit of claim 5, wherein, The first light-emitting control circuit comprises a fifth transistor, the second light-emitting control circuit comprises a sixth transistor, and the second initialization circuit comprises a seventh transistor; A gate of the fifth transistor is electrically connected with the light-emitting control terminal, a first pole of the fifth transistor is electrically connected with the power voltage terminal, and a second pole of the fifth transistor is electrically connected with the second node; A gate of the sixth transistor is electrically connected with the light-emitting control terminal, a first pole of the sixth transistor is electrically connected with the third node, and a second pole of the sixth transistor is electrically connected with the first pole of the light-emitting element; A gate of the seventh transistor is electrically connected with an initial control terminal, a first pole of the seventh transistor is electrically connected with the second initial voltage terminal, and a second pole of the seventh transistor is electrically connected with the first pole of the light-emitting element.

14. The pixel circuit of claim 3, wherein, The fourth energy storage circuit comprises a fourth capacitor, the fifth energy storage circuit comprises a fifth capacitor, the data writing circuit comprises a third transistor, the first control circuit comprises an eighth transistor, the second control circuit comprises a ninth transistor, and the sixth energy storage circuit comprises a sixth capacitor; A first end of the fourth capacitor is electrically connected with the first node, a second end of the fourth capacitor is electrically connected with a first control node, a first end of the fifth capacitor is electrically connected with the first control node, and a second end of the fifth capacitor is electrically connected with a writing node; A gate of the third transistor is electrically connected with a writing control terminal, a first pole of the third transistor is electrically connected with a data line, and a second pole of the third transistor is electrically connected with the writing node; A gate of the eighth transistor is electrically connected with the on-off control terminal, a first pole of the eighth transistor is electrically connected with the first control node, and a second pole of the eighth transistor is electrically connected with the second control node; A gate of the ninth transistor is electrically connected with the on-off control terminal, a first pole of the ninth transistor is electrically connected with the second control node, and a second pole of the ninth transistor is electrically connected with a second voltage terminal; A first end of the sixth capacitor is electrically connected with the second control node, and a second end of the sixth capacitor is electrically connected with a third bias voltage terminal.

15. The pixel circuit of claim 4, wherein, The setting circuit comprises a tenth transistor; A gate of the tenth transistor is electrically connected with the setting control terminal, a first pole of the tenth transistor is electrically connected with the setting voltage terminal, and a second pole of the tenth transistor is electrically connected with the writing node.

16. A pixel driving method applied to the pixel circuit according to any one of claims 1 to 15, wherein a display period comprises a bias stage and a light-emitting stage arranged in sequence; and the pixel driving method comprises: In the bias stage, the potential of the first terminal of the first energy storage circuit is changed by a first bias voltage signal, so that the driving transistor included in the driving circuit is in a bias state; In the bias stage, the potential of the first terminal of the second energy storage circuit is changed by a second bias voltage signal, so as to reduce the leakage current of the first node; In the light emitting stage, the driving circuit generates a driving current for driving the light emitting element.

17. The pixel driving method of claim 16, wherein, The pixel circuit further comprises a data writing circuit; the data writing circuit is electrically connected with a writing control terminal, a data line and the second node respectively; the display period further comprises a data writing stage arranged before the light emitting stage, and the data writing stage is independent of the bias stage; the pixel driving method comprises: In the data writing stage, the data writing circuit writes a data voltage provided by the data line into the second node under the control of a writing control signal; In the bias stage, the compensation control circuit controls the disconnection between the first node and the third node under the control of a compensation control signal.

18. The pixel driving method of claim 16, wherein, The pixel circuit further comprises a fourth energy storage circuit, a fifth energy storage circuit, a data writing circuit, a first control circuit, a second control circuit and a sixth energy storage circuit; the display period further comprises a bias stage; The bias stage is arranged before the light emitting stage; The pixel driving method comprises: In the bias stage, the potential of the second control node is changed by providing a third bias voltage signal, so as to reduce the leakage current of the first control node; the first control circuit controls the disconnection between the first control node and the second control node under the control of a pass-through control signal; the second control circuit controls the disconnection between the second control node and the second voltage terminal under the control of the pass-through control signal.

19. The pixel driving method according to any one of claims 16 to 18, wherein, The display period is a refresh frame, and the holding frame comprises a holding bias stage and a holding light emitting stage arranged in sequence; the pixel driving method further comprises: In the holding bias stage, the potential of the first terminal of the first energy storage circuit is changed by a first bias voltage signal, so that the driving transistor is in a bias state; and / or, in the holding bias stage, the potential of the first terminal of the second energy storage circuit is changed by a second bias voltage signal, so as to reduce the leakage current of the first node; In the holding bias stage, the compensation control circuit controls the disconnection between the first node and the third node under the control of a compensation control signal; In the holding light emitting stage, the driving circuit generates a driving current for driving the light emitting element.

20. The pixel driving method of claim 19, wherein, The pixel circuit further comprises a data writing circuit; the data writing circuit is electrically connected with a writing control terminal, a data line and the second node respectively; the pixel driving method further comprises: In the holding bias stage, the data writing circuit controls the disconnection between the data line and the second node under the control of a writing control signal.

21. The pixel driving method of claim 19, wherein, The pixel circuit further comprises a fourth energy storage circuit, a fifth energy storage circuit, a data writing circuit, a first control circuit, a second control circuit and a sixth energy storage circuit; the holding frame further comprises a holding bias stage arranged before the holding light emitting stage; the pixel driving method further comprises: In the holding bias stage, the potential of the second control node is changed by providing a third bias voltage signal to reduce the leakage current of the first control node; the first control circuit controls the disconnection between the first control node and the second control node under the control of a switch control signal; and the second control circuit controls the disconnection between the second control node and the second voltage terminal under the control of the switch control signal.

22. A display device comprising the pixel circuit according to any one of claims 1 to 15.

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