Stacked cft device and corresponding manufacturing method
By employing an independent dielectric wall design and a fully all-around gate structure in CFET devices, the problem of reduced design flexibility and suboptimal performance caused by dielectric walls in traditional CFET devices is solved, thereby reducing parasitic capacitance and improving power performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2023-09-21
- Publication Date
- 2026-04-17
AI Technical Summary
In traditional CFET devices, the stacked structure of forked transistors reduces design flexibility due to the dielectric walls between adjacent transistor stacks, and the top and bottom transistors share the same dielectric wall, resulting in suboptimal performance.
By employing an independent dielectric wall design, the channels of nMOS and pMOS transistors are separated. By shortening the extension length of the gate structure on the channel side, a fully encircling gate structure is formed, reducing parasitic capacitance.
The reduced output gate-to-drain capacitance improves the power performance of CFET devices and enhances design-related parasitic capacitance optimization.
Smart Images
Figure CN121890278A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to transistors, and more particularly to a stacked complementary field-effect transistor (CFET) device. Furthermore, this invention also provides a method for manufacturing a stacked CFET device. Background Technology
[0002] CFETs are considered the most promising candidate for future semiconductor device scaling. A CFET comprises an n-type transistor (nMOS) and a p-type transistor with opposite polarity (pMOS). A CFET can also include both n-channel and p-channel FETs. For example, nMOS transistors can be stacked on top of pMOS transistors (or vice versa) to form a stacked CFET.
[0003] Before the widespread adoption of CFETs, there may be technology nodes relying on fork-plate transistors. The metal gate of a fork-plate transistor may have a very small or even zero extension length at the edge of the transistor channel. Research on fork-plate architectures primarily aims to achieve further size scaling, as these architectures can increase the channel active area within given cell height constraints.
[0004] Existing research has proposed using forked transistors as the bottom and top transistors in stacked CFETs. The main driving force behind this approach is to further achieve device miniaturization. However, conventional CFETs composed of forked transistors have dielectric walls between adjacent transistor stacks, which reduces design flexibility because the basic structure of the transistors needs to be composed of four (instead of two) separate transistors. Furthermore, in conventional forked-based CFETs, the top and bottom transistors share a dielectric wall, which, while simplifying the fabrication process, may lead to suboptimal performance. Summary of the Invention
[0005] In view of the foregoing, the present invention aims to provide an improved CFET device, i.e., a device using at least one CFET. The objective is, for example, to minimize parasitic capacitance in the CFET device and thus improve its power performance. Specifically, the objective is to reduce the output gate-to-drain capacitance (also known as Miller capacitance). Another objective is to achieve design-related optimization of the CFET device, particularly the reduction of design-related parasitic capacitance.
[0006] These and other objectives are achieved by the technical solutions of the invention as described in the independent claims. Advantageous implementation methods are further described in the dependent claims.
[0007] A first aspect of the present invention provides a CFET device comprising: an nMOS transistor including a first channel and a first gate structure surrounding the first channel; a pMOS transistor including a second channel and a second gate structure surrounding the second channel, wherein the nMOS transistor and the pMOS transistor are stacked on top of each other (in any order) along a first axis; and a first dielectric wall disposed on a first side of the nMOS transistor and the pMOS transistor along a second axis perpendicular to the first axis, wherein the first dielectric wall is adjacent to the first channel but spaced apart from the second channel along the second axis by a portion of the second gate structure, the portion being disposed between the second channel and the first dielectric wall.
[0008] Each transistor's channel can be one of several channels. Each transistor's channel can also consist of several "sub-channels," such as several nanosheets. These sub-channels can be stacked along a first direction and separated from each other by a gate structure composed of a gate dielectric and a gate metal. The first dielectric wall may be misaligned with the edge of the first channel. The same applies to the second dielectric wall, which may also be misaligned with the edge of the second channel. Therefore, the first and second gate structures can completely or partially surround the first and second channels, respectively. In this way, the first gate structure and the second gate structure can form a gate-all-round (GAA) structure.
[0009] The first axis (i.e., the stacking direction of the two transistors) is perpendicular to the channel direction, which is defined by the direction of the current flowing through the channel between the drain and source of the transistor using a CFET device. Additionally, the second axis is perpendicular to the channel direction.
[0010] Because the first dielectric wall is adjacent to the first channel, no portion of the first gate structure is disposed between the first dielectric wall and the first channel along the second axis. That is, the first gate structure does not extend beyond the first channel along the second axis to the first side. This minimized extension length of the first gate structure results in a smaller gate-to-source / drain (S / D) parasitic capacitance of the nMOS transistor in this case compared to a longer extension length. It is worth noting that in the CFET device of the first aspect, the nMOS and pMOS transistors can also be interchanged and stacked in a different order.
[0011] In an implementation of the first aspect, the CFET device further includes: a second dielectric wall disposed along the second axis on a second side of the nMOS transistor and the pMOS transistor, wherein the second side is opposite to the first side of the nMOS transistor and the pMOS transistor, the second dielectric wall is adjacent to the second channel, but is spaced apart from the first channel along the second axis by a portion of the first gate structure, the portion being disposed between the first channel and the second dielectric wall.
[0012] Because the second dielectric wall is adjacent to the second channel, no portion of the second gate structure is disposed between the second dielectric wall and the second channel along the second axis. That is, the second gate structure does not extend beyond the second channel along the second axis to the second side. This minimized extension length of the second gate structure results in a smaller gate-to-S / D parasitic capacitance of the pMOS transistor in this case compared to a longer extension length.
[0013] It is worth noting that for one or two transistors, completely eliminating the extension length of both gate structures to either side of a CFET device is practically impractical, as the corresponding gate structures might otherwise lose control of the respective channel. However, for each transistor, the extension length of one gate structure to one side can be eliminated to reduce capacitance as described above and achieve better device performance. The setting of the remaining gate structure extension length can be design-dependent.
[0014] In one implementation of the first aspect, the first channel has a first width along the second axis, and the second channel has a second width along the second axis, wherein the first width and the second width are the same as or different; and / or one or both edges of the first channel and the second channel are aligned along the first axis, wherein the edges define the first width and the second width, respectively.
[0015] However, the channels of nMOS and pMOS transistors can also be configured to be offset from other channels along the second axis, but overlap each other along the second axis.
[0016] In one implementation of the first aspect, the first side surface of the first gate structure is offset from the first side surface of the second gate structure along the second axis.
[0017] The side surface of the gate structure can be a sidewall, which can be formed from the material of the gate structure and interface with other materials used in CFET devices.
[0018] In one implementation of the first aspect, the second side surface of the first gate structure is offset from the second side surface of the second gate structure along the second axis.
[0019] In one implementation of the first aspect, both the first gate structure and the second gate structure include a gate dielectric surrounding a respective first channel or second channel, and a gate metal surrounding the gate dielectric and the first channel or second channel.
[0020] In an implementation of the first aspect, the CFET device further includes: a first power rail disposed above the nMOS transistor and the pMOS transistor along the first axis and connected to the source of the nMOS transistor through at least one first metal via; and a second power rail disposed above the nMOS transistor and the pMOS transistor along the first axis and connected to the source of the pMOS transistor through at least one second metal via, wherein a portion of the second dielectric wall is disposed between the first power rail and the source of the pMOS transistor.
[0021] The second dielectric wall ensures that there is no electrical short circuit between the first metal via and the source of the pMOS transistor.
[0022] In one implementation of the first aspect, the distance between the second channel and the first dielectric wall along the second axis is in the range of 5 nm to 20 nm; and / or the distance between the first channel and the second dielectric wall along the second axis is in the range of 5 nm to 20 nm.
[0023] It is worth noting that the distance between the second channel and the second dielectric wall, and between the first channel and the first dielectric wall, can be 0 nm or very close to 0 nm.
[0024] In one implementation of the first aspect, the first channel is formed by one or more first nanosheets; the second channel is formed by one or more second nanosheets.
[0025] In one implementation of the first aspect, the nMOS transistor and the pMOS transistor are forked transistors, and at least the first dielectric wall is a forked isolation wall.
[0026] Therefore, the CFET device of the present invention enjoys the benefits of a forked transistor.
[0027] In one implementation of the first aspect, the nMOS transistor and the pMOS transistor together form a CFET.
[0028] A second aspect of the present invention provides a method for fabricating a CFET device, the method comprising: forming a first channel of an nMOS transistor; forming a second channel of a pMOS transistor, wherein the first channel of the nMOS transistor and the second channel of the pMOS transistor are stacked along a first axis; forming a first dielectric wall on a first side of the first channel and the second channel along a second axis perpendicular to the first axis, wherein the first dielectric wall is formed adjacent to the first channel but spaced apart from the second channel along the second axis; forming a first gate structure of the nMOS transistor and a second gate structure of the pMOS transistor, wherein the first gate structure and the second gate structure surround the first channel and the second channel respectively, and a portion of the second gate structure is disposed between the second channel and the first dielectric wall.
[0029] In one implementation of the second aspect, the method further includes: forming a second dielectric wall along the second axis on a second side of the first channel and the second channel, wherein the second side is opposite to the first side of the first channel and the second channel; the second dielectric wall is formed adjacent to the second channel but spaced apart from the first channel along the second axis, and when the first gate structure and the second gate structure are formed, a portion of the first gate structure is disposed between the first channel and the second dielectric wall.
[0030] In one implementation of the second aspect, the first channel is formed to have a first width along the second axis, and the second channel is formed to have a second width along the second axis, wherein the first width and the second width are the same or different; and / or one or both edges of the first channel and the second channel are aligned along the first axis when the channels are formed, wherein the edges define the first width and the second width, respectively.
[0031] In one implementation of the second aspect, the first side surface of the first gate structure is offset from the first side surface of the second gate structure along the second axis.
[0032] In one implementation of the second aspect, the second side surface of the first gate structure is offset from the second side surface of the second gate structure along the second axis.
[0033] In one implementation of the second aspect, both the first gate structure and the second gate structure include a gate dielectric surrounding a respective first channel or second channel, and a gate metal surrounding the gate dielectric and the first channel or second channel.
[0034] In an implementation of the second aspect, the method further includes: forming a first power rail above the nMOS transistor and the pMOS transistor along the first axis, and connecting the first power rail to the source of the nMOS transistor through at least one first metal via; forming a second power rail above the nMOS transistor and the pMOS transistor along the first axis, and connecting the second power rail to the source of the pMOS transistor through at least one second metal via, wherein a portion of the second dielectric wall is disposed between the first power rail and the source of the pMOS transistor.
[0035] In one implementation of the second aspect, the distance between the second channel and the first dielectric wall along the second axis is in the range of 5 nm to 20 nm; and / or the distance between the first channel and the second dielectric wall along the second axis is in the range of 5 nm to 20 nm.
[0036] In one implementation of the second aspect, the first channel is formed by forming one or more first nanosheets; the second channel is formed by forming one or more second nanosheets.
[0037] In one implementation of the second aspect, the nMOS transistor and the pMOS transistor are forked transistors, and at least the first dielectric wall is a forked isolation wall.
[0038] In one implementation of the first aspect, the nMOS transistor and the pMOS transistor together form a CFET.
[0039] The second aspect and its implementation method achieve the same advantages as described above for the CFET device with respect to the first aspect and its corresponding implementation.
[0040] In summary, based on the above aspects and implementation methods, this invention proposes reducing the extension length of the gate structure to decrease parasitic capacitance. It also envisions creating separate dielectric walls for the top and bottom transistors of the CFET device. Attached Figure Description
[0041] The following detailed description of specific embodiments, in conjunction with the accompanying drawings, will illustrate the above aspects and various implementations, as shown in the drawings: Figure 1 A cross-sectional view of the CFET device according to the present invention is shown.
[0042] Figure 2 A cross-sectional view of an exemplary CFET device according to the present invention is shown.
[0043] Figure 3A cross-sectional view of an exemplary CFET device according to the present invention is shown.
[0044] Figure 4 A cross-sectional view of an exemplary CFET device according to the present invention is shown.
[0045] Figure 5 A cross-sectional view of an exemplary CFET device according to the present invention is shown.
[0046] Figure 6 A top view of an exemplary CFET device according to the present invention is shown.
[0047] Figure 7 A flowchart of a method for manufacturing a CFET device according to the present invention is shown. Detailed Implementation
[0048] Figure 1 A CFET device 100 according to the present invention is shown. The CFET device 100 can be a nanosheet-based or fork-based CFET device. The CFET device 100 can be any kind of device based on CFET technology.
[0049] CFET device 100 includes an n-type transistor 101 and a p-type transistor 104 with opposite polarity. The n-type transistor is an nMOS, and the p-type transistor is a pMOS. The nMOS transistor 101 and the pMOS transistor 104 constitute the CFET. The nMOS transistor 101 and the pMOS transistor 104 are stacked on top of each other along a first axis 107. Figure 1 In this example, pMOS transistors (also referred to here as top-layer transistors) are stacked on top of nMOS transistors (also referred to here as bottom-layer transistors) along the first axis, but this stacking order can also be reversed.
[0050] The nMOS transistor 101 includes a first channel 102 and a first gate structure 103 surrounding the first channel 102. The first channel 102 is an n-channel. The first channel 102 may include multiple sub-channels, such as multiple stacked nanosheets. The pMOS transistor 104 includes a second channel 105 and a second gate structure 106 surrounding the second channel 105. The second channel 105 is a p-channel. The second channel 105 may also include multiple sub-channels, such as multiple stacked nanosheets. Channels 102 and 105 may include a semiconductor material (such as silicon), which may be n-type doped and p-type doped for different channels, respectively. Gate structures 103 and 106 may each include a gate metal and a suitable gate dielectric, both surrounding their respective channels 102 and 105. The gate dielectric may be an oxide, such as silicon oxide and / or hafnium oxide. The gate metals of the nMOS transistor 101 and the pMOS transistor 104 may be different, for example, they may have different work functions. Metals used in conventional devices can be used.
[0051] The CFET device 100 also includes a first dielectric wall 108, which is disposed on a first side of both the nMOS transistor 101 and the pMOS transistor 104, the first side being relative to a second axis 109, the second axis 109 being perpendicular to the first axis 107. Figure 1 In the example, the first side is the left side. The first and second axes 107 and 109 can be axes in a conventional coordinate system as shown. The first dielectric wall 108 can include a dielectric material, such as an oxide or a high-k material.
[0052] like Figure 1 As further shown, the wall of the first dielectric 108 is adjacent to the first channel 102, that is, directly adjacent to the first channel 102, but spaced apart from the second channel 105 along the second axis 109. This space is formed by a portion of the second gate structure 106, which is disposed between the second channel 105 and the first dielectric wall 108. It can be seen that there is no portion of the first gate structure 103 between the first channel 102 and the dielectric wall 108 along the second axis 109.
[0053] Please note that a portion of the CFET device 100 (located in) Figure 1 (on the right side) not in Figure 1 As shown, specifically, the first gate structure 103 and the second gate structure 106 are located on the second side of the nMOS transistor 101 and the pMOS transistor 104. Different implementation methods can be used here, and some of them are described below.
[0054] Figure 2 A CFET device 100 according to the present invention is shown, the CFET device 100 being in Figure 1It is built based on the CFET device 100 shown. Figure 1 and Figure 2 The same elements in the same array are marked with the same label, and this can be achieved similarly.
[0055] like Figure 2 As shown, the CFET device 100 may further include a second dielectric wall 201 disposed along a second axis 109 on a second side of the nMOS transistor 101 and the pMOS transistor 104. In the figure, for example, the second side is the right side. The second side is opposite to the first side of the nMOS transistor 101 and the pMOS transistor 104 relative to the second axis 109.
[0056] The second dielectric wall 201 is adjacent to the second channel 105, that is, directly adjacent to the second channel 105, but spaced apart from the first channel 102 along the second axis 109. This space is formed by a portion of the first gate structure 103, which is disposed between the first channel 102 and the second dielectric wall 201 along the second axis 109.
[0057] Due to the arrangement of the first dielectric wall 108 and the second dielectric wall 201, it is possible to... Figure 2 It can be seen that the first side surface 203 of the first gate structure 103 is offset from the first side surface 106 of the second gate structure 106 along the second axis. Similarly, the second side surface 204 of the first gate structure 103 is offset from the second side surface 205 of the second gate structure 106 along the second axis 109.
[0058] exist Figure 2 In the first channel 102 and the second channel 105, each includes multiple sub-channels (for example, two sub-channels are shown for each channel 102 and 105, but more sub-channels or only one sub-channel may exist), and these sub-channels are disposed above each other along the first direction 107. These sub-channels may be nanosheets, as shown, and are isolated by their respective gate structures 103 and 106. Furthermore, the first channel 102 and the second channel 105 (as shown...) Figure 1 (as shown) or all of its sub-channels (such as Figure 2 One or both edges (left and / or right edges) of the channels 102 and 205 (as shown) may be aligned along the first axis 107. The edges of the channels 102 and 205 define their respective widths. The first channel 102 may have a first width, and the second channel 105 may have a second width. If the channels 102 and 105 include multiple sub-channels, each sub-channel may have either a first width or a second width. However, the sub-channels of a channel 102 or 105 may also differ in width. Furthermore, the first width and the second width may be the same or different.
[0059] Figure 2A substrate structure (such as a substrate) is also shown, on which stacked transistors 101 and 104 are disposed. The substrate structure may include a silicon fin substrate disposed between shallow trench isolation (STI) 202.
[0060] Figure 3 A CFET device 100 according to the present invention is shown, the CFET device 100 being in Figure 1 It is built based on the CFET device 100 shown. Figure 1 and Figure 3 The same elements in the same array are marked with the same label, and this can be achieved similarly.
[0061] and Figure 2 Compared to the CFET device 100 shown, Figure 3 The architecture of the CFET device 100 shown is mirrored with respect to the first axis 107. That is, the first side is now the right side of the nMOS transistor 101 and pMOS transistor 104, and the second side is now the left side. It is worth noting that in this invention, the first and second sides can also be interchanged. Additionally, the nMOS transistor 101 and pMOS transistor 104 can also be interchanged, i.e., in... Figure 1 , Figure 2 and Figure 3 In the CFET device 100 shown, the nMOS transistor 101 can be located above the pMOS transistor 104. The first and second sides along the second axis 109 can correspond to the "north" and "south" sides of the CFET device 100, an orientation commonly used in conventional devices, which will be explained further later.
[0062] Figure 4 A CFET device 100 is shown, which is related to... Figure 1 The CFET devices are similar to the 100, but differ in one aspect. However, Figure 4 and Figure 1 The same elements in the same array are marked with the same label, and this can be achieved similarly.
[0063] With Figure 1 The CFET device 100 shown is different. Figure 4 The first gate structure 103 and the second gate structure 106 of the CFET device 100 shown have shortened extension lengths on the same side. That is, in Figure 4In this configuration, the second dielectric wall 201 is adjacent to the first channel 102 and the second channel 105. The first dielectric wall 108 is spaced apart from the second channel 105 by a portion of the second gate structure 106 along the second axis 109, this portion being disposed between the second channel 105 and the first dielectric wall 108. It is also spaced apart from the first channel 102 by a portion of the first gate structure 103 along the second axis 109, this portion being disposed between the first channel 102 and the second dielectric wall 201. It is worth noting that another possible configuration also exists: the first dielectric wall 108 is adjacent to both channels 102 and 105, while the second dielectric wall 201 is spaced apart from both channels 102 and 105 by portions of the corresponding gate structures 103 and 106.
[0064] Figure 5 Some CFET devices 100 described in this invention are compared with a reference CFET device. Figure 5 In the middle, "North" (N) indicates the first side, and "South" (S) indicates the second side.
[0065] Figure 5 (a) shows a reference CFET device. Figure 5 (c) shows the relationship with Figure 2 The device shown is similar to the CFET device 100. Figure 5 (d) shows the relationship with Figure 3 The device shown is similar to the CFET device 100. Figure 5 (d) shows the relationship with Figure 4 The device shown is similar to the CFET device 100. Figure 5 (b) shows the above description Figure 4 A mirrored CFET device. In this invention, the first distance along the second axis 109 between the second channel 105 and the first dielectric wall 108 can be in the range of 5 nm to 20 nm. The second distance along the second axis 109 between the first channel 102 and the second dielectric wall 201 can be in the range of 5 nm to 20 nm. Typically, any extension length of the gate structures 103, 106 along the second axis beyond their respective channels 102, 105 (to the first side or the second side) can be in the range of 5 nm to 20 nm. Figure 5 In the example, the first and second distances are approximately 10 nm. If gate structures 103 and 106 are adjacent to the channel, this distance is... Figure 5 The value is 0 nm. TS, BS, BN, and TN represent the distances from "top south", "bottom south", "bottom north", and "top north", which refer to the extension length (i.e., the corresponding distance) of the gate structures 103 and 106 of the bottom transistor or top transistor (pMOS 104 or nMOS 101, respectively) on the first and second sides.
[0066] A reference CFET device is a regular undoped GAA transistor whose gate structure extends to both sides (i.e., the north and south sides) around the channel. In the CFET device 100 of the present invention, the CFET device 100 can be a forked transistor device, with gate structures 103 and 106 extending only to one side of the CFET device 100, i.e., the north or south side. With the CFET device 100 of the present invention, the extension length of the gate structure of the top and bottom transistors can be shortened according to design requirements. Essentially, there are four possible combinations, such as... Figure 5 (as well as Figure 2 , Figure 3 and Figure 4 As shown in the diagram. All these combinations will achieve a certain degree of reduction in parasitic capacitance.
[0067] Figure 6 A top view of a CFET-based inverter is shown, which is an example of a CFET device 100 according to the present invention. Figure 6 The same elements as those in the aforementioned figures are labeled again using the same numbers.
[0068] Figure 6 Specifically, the inverter may further include a first power rail 601 and a second power rail 603 (VSS and VDD, etc.). Power rails 601 and 603 are disposed along a first axis 107 above nMOS transistor 101 and pMOS transistor 104. Note that in Figure 6 In this configuration, nMOS transistor 101 is positioned on top of pMOS transistor 104.
[0069] The first power rail 601 is connected to the source 606 of the nMOS transistor 101 through at least one first metal via 607. The second power rail 603 is connected to the source 606' of the pMOS transistor 104 through at least one second metal via 604. The output of the inverter is formed by connecting the two drains 605 and 605' of transistors 101 and 104 through at least one third metal via 602. The dielectric wall 201 limits the extension length of the gate structure of the bottom transistor 104, and the dielectric wall 108 limits the extension length of the gate structure of the top transistor 101. Furthermore, a portion of the dielectric wall 201 is disposed between the first power rail 601 and the source 606'. The dielectric wall 201 helps to prevent a short circuit between the via 607 and the source 606' of the pMOS transistor 104.
[0070] Figure 7A method 700 for manufacturing a CFET device 100 according to the present invention is shown, for example, manufacturing the CFET device 100 shown in any of the foregoing figures. Method 700 includes step 701: forming a first channel 102 of an nMOS transistor 101. Method 700 further includes step 702: forming a second channel 105 of a pMOS transistor 104. The first channel 102 of the nMOS transistor 101 and the second channel 105 of the pMOS transistor 104 are stacked along a first axis 107. Method 700 further includes step 703: forming a first dielectric wall 108 on a first side of the first channel 102 and the second channel 105 along a second axis 109 perpendicular to the first axis 107. The first dielectric wall 108 is formed adjacent to the first channel 102 but spaced apart from the second channel 105 along the second axis 109. Method 700 further includes step 704: forming a first gate structure 103 of nMOS transistor 101 and a second gate structure 106 of pMOS transistor 104, wherein the first gate structure 103 and the second gate structure 106 surround the first channel 102 and the second channel 105 respectively, and a portion of the second gate structure 106 is disposed between the second channel 105 and the first dielectric wall 108.
[0071] The technical solution of this invention offers the advantage of reducing gate-to-S / D parasitic capacitance, thanks to the shortened extension length of the gate structure beyond the sides of channels 102 and 105, respectively. Furthermore, this technical solution allows for adjustment of the positions of the first dielectric wall 108 and the second dielectric wall 201 according to design requirements, and can reduce Miller capacitance.
[0072] The CFET device 100 of this invention can be applied to any application scenario that requires transistors. Transistors are a component of all integrated circuits, whether for mobile devices or high-performance computing applications. CFET is considered one of the ultimate solutions for driving the scaling of logic technology.
[0073] This invention has been described in conjunction with various embodiments as examples and implementations. However, based on a study of the drawings, the invention, and the independent claims, those skilled in the art will understand and implement other variations when practicing the claimed subject matter. In the claims and the description, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" does not exclude a plurality. A single element or other unit can perform the function of several entities or items described in the claims. Listing certain measures in dissimilar dependent claims does not imply that combinations of these measures cannot be used in advantageous implementations.
Claims
1. A complementary field-effect transistor (CFET) device (100), characterized in that, include: The nMOS transistor (101) includes a first channel (102) and a first gate structure (103) surrounding the first channel (102). pMOS transistor (104) includes a second channel (105) and a second gate structure (106) surrounding the second channel (105). The nMOS transistor (101) and the pMOS transistor (104) are stacked on top of each other along the first axis (107); A first dielectric wall (108) is disposed on the first side of the nMOS transistor (101) and the pMOS transistor (104) along a second axis (109) perpendicular to the first axis (107). The first dielectric wall (108) is adjacent to the first channel (102), but is spaced apart from the second channel (105) by a portion of the second gate structure (106) along the second axis (109), the portion being disposed between the second channel (105) and the first dielectric wall (108).
2. The CFET device (100) according to claim 1, characterized in that, Also includes: A second dielectric wall (201) is disposed along the second axis (109) on the second side of the nMOS transistor (101) and the pMOS transistor (104), wherein the second side is opposite to the first side of the nMOS transistor (101) and the pMOS transistor (104). The second dielectric wall (201) is adjacent to the second channel (105), but is spaced apart from the first channel (102) by a portion of the first gate structure (103) along the second axis (109), the portion being disposed between the first channel (102) and the second dielectric wall (201).
3. The CFET device (100) according to claim 1 or 2, characterized in that, The first channel (102) has a first width along the second axis (109), and the second channel (105) has a second width along the second axis (109), wherein, The first width may be the same as or different from the second width; and / or One or both edges of the first channel (102) and the second channel (105) are aligned along the first axis (107), wherein the edges define the first width and the second width, respectively.
4. The CFET device (100) according to any one of claims 1 to 3, characterized in that, The first side surface (203) of the first gate structure (103) is offset from the first side surface (206) of the second gate structure (106) along the second axis (109).
5. The CFET device (100) according to any one of claims 1 to 4, characterized in that, The second side surface (204) of the first gate structure (103) is offset from the second side surface (205) of the second gate structure (106) along the second axis (109).
6. The CFET device (100) according to any one of claims 1 to 5, characterized in that, Both the first gate structure (103) and the second gate structure (106) include a gate dielectric surrounding the respective first channel 102 or second channel 105, and a gate metal surrounding the gate dielectric and the first channel (102) or the second channel (105).
7. The CFET device (100) according to any one of claims 2 to 6, characterized in that, Also includes: A first power rail (601) is disposed above the nMOS transistor (101) and the pMOS transistor (104) along the first axis (107) and is connected to the source (606) of the nMOS transistor (101) through at least one first metal via (607). A second power rail (603) is disposed above the nMOS transistor (101) and the pMOS transistor (104) along the first axis (107), and is connected to the source (606') of the pMOS transistor (104) through at least one second metal via (604), wherein, A portion of the second dielectric wall (201) is disposed between the first power rail (601) and the source (606) of the nMOS transistor (101).
8. The CFET device (100) according to any one of claims 1 to 7, characterized in that, The distance between the second channel (105) and the first dielectric wall (108) along the second axis (109) is in the range of 5 nm to 20 nm; and / or The distance between the first channel (102) and the second dielectric wall (201) along the second axis (109) is in the range of 5 nm to 20 nm.
9. The CFET device (100) according to any one of claims 1 to 7, characterized in that, The first channel (102) is formed by one or more first nanosheets; The second channel (105) is formed by one or more second nanosheets.
10. The CFET device (100) according to any one of claims 1 to 9, characterized in that, The nMOS transistor and the pMOS transistor are forked transistors, and at least the first dielectric wall (108) is a forked isolation wall.
11. The CFET device (100) according to any one of claims 1 to 10, characterized in that, The nMOS transistor (101) and the pMOS transistor (104) together form a CFET.
12. A method (700) for fabricating a complementary field-effect transistor (CFET) device (100), characterized in that, The method (700) includes: The first channel (102) forming the (701) nMOS transistor (101) is the first channel (102); The second channel (105) forming the (702) pMOS transistor (104) is the second channel (105), wherein, The first channel (102) of the nMOS transistor (101) and the second channel (105) of the pMOS transistor (104) are stacked along the first axis (107); Along a second axis (109) perpendicular to the first axis (107), a first dielectric wall (108) is formed (703) on the first side of the first channel (102) and the second channel (105), wherein, The first dielectric wall (108) is formed adjacent to the first channel (102), but is spaced apart from the second channel (105) along the second axis (109); Forming (704) the first gate structure (103) of the nMOS transistor (101) and the second gate structure (106) of the pMOS transistor (104), wherein, The first gate structure (103) and the second gate structure (106) surround the first channel (102) and the second channel (105) respectively, and a portion of the second gate structure (106) is disposed between the second channel (105) and the first dielectric wall (108).