Photoetching overlay structure, optical adapter plate and manufacturing method thereof

Abstract

The invention relates to a photoetching overlay structure, an optical adapter plate and a manufacturing method of the photoetching overlay structure, and relates to the technical field of optoelectronic integration and semiconductor manufacturing, and the photoetching overlay structure comprises a first photoetching pattern area, a second photoetching pattern area, an overlapping overlay area and a heat insulation splicing conical structure, the first photoetching pattern area comprises a first waveguide pattern with first size precision; the second photoetching pattern area comprises a second waveguide pattern with second size precision, and the second size precision is lower than the first size precision; an overlapping and overlay area is configured at the junction of the first photoetching pattern area and the second photoetching pattern area, and in the overlapping and overlay area, the second waveguide pattern partially covers the tail end of the first waveguide pattern in space; the width of the heat insulation splicing conical structure linearly changes in the light transmission direction, and at least part of the heat insulation splicing conical structure is formed in the overlapping and overlay area. According to the invention, low-cost cross-scale processing and manufacturing are realized.

Description

Technical Field

[0001] This application relates to the fields of optoelectronic integration and semiconductor manufacturing technology, and in particular to a photolithography overlay structure, an optical adapter plate and its manufacturing method. Background Technology

[0002] With the explosive growth in demand for artificial intelligence (AI), high-performance computing (HPC), and data centers, the requirements for chip computing power and I / O (input / output) bandwidth have shown an exponential upward trend. Traditional electronic interconnect technologies, due to their inherent RC latency, huge power consumption, and "memory wall" and "I / O wall" problems, are increasingly becoming bottlenecks for further improving system performance. Against this backdrop, silicon photonics technology introduces optical interconnects to the chip scale, using optical signals for data transmission. With its inherent advantages of high bandwidth, low latency, and low power consumption, it is regarded as one of the key paths to break through the aforementioned bottlenecks, extend Moore's Law, and even surpass Moore's Law.

[0003] However, the current mainstream two-dimensional planar integration solutions for silicon photonics chips and electronic chips face many fundamental challenges when facing ultra-large-scale, high-density interconnection applications.

[0004] First, there is a trade-off between integration density and performance. To achieve high bandwidth, a large number of optical waveguides and grating couplers need to be integrated, which requires optical adapters to have high-density nanoscale fine structures. Typically, this requires expensive and time-consuming high-resolution lithography technologies such as electron beam lithography (EBL), which severely restricts production costs and capacity, making it difficult to meet the needs of large-scale mass production.

[0005] Secondly, there is a lack of cross-scale processing capability. Optical adapters contain features at both the nanoscale and microscale. A single photolithography technique is insufficient to efficiently and economically process feature sizes spanning orders of magnitude simultaneously. For example, while stepper lithography offers high precision for fabricating micron-scale structures, it severely wastes its resolution advantage and has a very limited field of view, making it difficult to form ultra-large-area patterns in a single exposure. On the other hand, while contact lithography is low-cost and offers a large field of view, its resolution is lower, making it difficult to process fine nanoscale structures.

[0006] Current technologies struggle to achieve high-precision stitching between different lithography processes. For instance, precisely aligning the stepper lithography region used for fabricating nanostructures with the contact lithography region used for fabricating microstructures remains a challenging problem. Stitching errors directly lead to optical path misalignment, introducing significant insertion loss and causing system failure.

[0007] Therefore, there is an urgent need for an optical adapter plate and its manufacturing method that can balance processing costs and precision, solve cross-scale processing problems, and effectively accommodate splicing errors in hybrid lithography processes. Summary of the Invention

[0008] The purpose of this application is to provide a photolithography overlay structure, an optical adapter plate, and a manufacturing method, aiming to solve the technical problems of difficult cross-scale processing, excessively high requirements for large-area splicing alignment accuracy in hybrid photolithography processes, and high manufacturing costs in the prior art.

[0009] Firstly, the photolithography overlay structure based on hybrid photolithography provided in this application adopts the following technical solution: A photolithographic overlay structure based on hybrid photolithography, used to form a continuous optical waveguide transmission link on a substrate, comprising: The first photolithographic patterning area contains a first waveguide pattern with a first dimensional accuracy; The second lithographic patterning area includes a second waveguide pattern with a second dimensional accuracy, which is lower than the first dimensional accuracy. An overlapping etched region is disposed at the boundary between the first lithographic pattern area and the second lithographic pattern area. In the overlapping etched region, the second waveguide pattern partially covers the end of the first waveguide pattern in space. The thermally insulated conical structure has a width that varies linearly along the light transmission direction and is at least partially formed within the overlapping etched area. It is used to absorb the etched deviation between the first feature size accuracy and the second size accuracy to achieve thermally insulated transmission of optical signals.

[0010] Furthermore, the width of the thermally insulated conical structure varies from the starting end to the ending end, from the starting end width W1 to the ending end width W2, where W1 > W2; and W2 and W1 satisfy the relationship: (W2 W1) / 2≥ΔL, where ΔL is the maximum overlay deviation of the contact lithography process relative to the step lithography process.

[0011] Furthermore, the overlay offset is 2–3 μm.

[0012] Furthermore, the length from the starting end to the ending end is configured to satisfy the adiabatic evolution condition of the optical signal; wherein, the length is much larger than the width difference between the starting end and the ending end, and the linearly gradient length is 480 to 520 μm, so that the optical signal maintains low-loss transmission when passing through the adiabatic splicing conical structure.

[0013] Furthermore, the first dimensional accuracy is at the nanometer level, and the first photolithographic pattern area is used to etch nanometer-level fine structures; the second dimensional accuracy is at the micrometer level, and the second photolithographic pattern area is used to etch micrometer-level fine structures.

[0014] Secondly, the ultra-large optical adapter board based on heterogeneous integration provided in this application adopts the following technical solution: An ultra-large optical adapter plate based on heterogeneous integration, employing the aforementioned photolithography overlay structure, the optical adapter plate comprising: A substrate layer on which a cladding layer is grown; Three silicon nitride waveguide layers are disposed sequentially and spaced apart from top to bottom within the cladding layer. The three silicon nitride waveguide layers include: The middle waveguide layer and the bottom waveguide layer together constitute the optical routing layer, which is used for the transmission and distribution of optical signals; The top waveguide layer, which is thinner than the middle and bottom waveguide layers, is configured as the optical coupling interface between the chip and the adapter board. The three-layer silicon nitride waveguide layer is provided with a double-segment thermally insulating conical structure. The width of the double-segment thermally insulating conical structure is linearly narrowed along the length direction of the silicon nitride waveguide layer, so that adjacent waveguide layers are vertically interconnected through the double-segment thermally insulating conical structure to realize mode field conversion of optical signals.

[0015] Furthermore, the thickness of the top waveguide layer is set to 90nm to 110nm, and the thickness of the middle waveguide layer and the bottom waveguide layer are both set to 380nm to 420nm. The top waveguide is a low-confinement waveguide for low-loss transmission; the middle waveguide and the bottom waveguide are high-confinement waveguides for setting up wavelength division multiplexing (WDM) or power dividers.

[0016] Furthermore, the dual-segment adiabatic conical structure includes a first adiabatic segment and a second adiabatic segment, wherein the narrowing rate of the first adiabatic segment is lower than that of the second adiabatic segment, and adjacent waveguide layers are vertically coupled at least through the first adiabatic segment.

[0017] Thirdly, the manufacturing method of an ultra-large optical adapter plate based on heterogeneous integration provided in this application adopts the following technical solution: A method for manufacturing an ultra-large optical adapter plate based on heterogeneous integration, used to prepare the aforementioned adapter plate, the manufacturing method comprising the following steps: S100, providing a substrate with a silicon nitride thin film deposited on it; S200: Pattern the underlying silicon nitride film to form an underlying waveguide layer and alignment marks; S300: Deposit a first spacer layer and a middle silicon nitride thin film; pattern the middle silicon nitride thin film based on the alignment marks to form a middle waveguide layer; S400, deposit the second spacer layer and the top silicon nitride film. Based on the alignment mark, use a hybrid lithography process combining step lithography and contact lithography to pattern the top silicon nitride film to form the top waveguide layer. S500, metallization process is carried out to complete the manufacturing of optical adapter board; The hybrid lithography process in S400 includes: Step lithography stage: The silicon nitride thin film is exposed, developed and etched using step lithography to form the main fine structure, and an overlapping area is reserved at the splicing point with the subsequent contact lithography. Contact lithography stage: After step lithography and etching are completed, contact lithography is applied to the wafer. The contact lithography process is used for alignment, overlay, exposure and development, so that the contact lithography pattern covers the end of the main fine structure in the overlapping area. After confirming the splicing effect, etching is performed to obtain a complete silicon nitride waveguide pattern. The thermally insulating conical structure is formed within the overlapping area.

[0018] Furthermore, the metallization process in S500 includes: Spin-coat the primer and anneal it, then coat it with DUV photoresist; Based on the alignment marks, step lithography is used for exposure and development to form a lithographic morphology with undercut features; Metal electrodes are formed by depositing metal through electron beam evaporation and then peeling them off by soaking in a hot water bath with N-methylpyrrolidone.

[0019] In summary, this application includes at least one of the following beneficial technical effects: 1. High yield and robustness of splicing: A mask splicing tolerance scheme based on overlapping overprinted areas and thermal tape is proposed, which relaxes the extreme requirements for photolithography alignment accuracy and changes the process difficulty from "must be perfectly aligned" to "can still work within the expected offset", which greatly improves the manufacturing yield and process robustness, laying the foundation for the actual mass production of large-area optical adapter boards.

[0020] 2. High-density and high-performance integration: Through a "thin-thick" three-layer silicon nitride stacked architecture, the functions of the coupling layer and the routing layer are separated and optimized. The thin layer specializes in efficient and low-loss inter-chip coupling, while the thick layer focuses on low-loss, high-density optical signal transmission and processing, thereby achieving optimal performance at the system level.

[0021] 3. Low-cost cross-scale manufacturing: Innovatively combining high-precision stepper lithography and low-cost contact lithography, maximizing the advantages of each process. Using expensive high-resolution lithography only where it is most needed, while employing economical lithography in other areas, significantly reduces manufacturing costs for large-scale production, while perfectly solving the challenge of one-time processing of nanoscale and microscale structures. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the photolithographic overlay structure and splicing principle of this application; Figure 2 This is a schematic diagram of the interlayer coupling relationship between different waveguide layers in this application.

[0024] Figure 3 This is a cross-sectional structural diagram of the optical adapter plate of this application; Figure 4 These are planar and three-dimensional schematic diagrams of the interlayer vertical coupling structure of this application; In the figure, 100 is the first lithographic pattern area; 200 is the second lithographic pattern area; 300 is the overlapping lithographic region; 500 is the substrate layer; 510 is the cladding layer; 610 is the bottom waveguide layer; 620 is the middle waveguide layer; 630 is the top waveguide layer; 700 is the dual-segment thermally insulating conical structure; 710 is the first thermally insulating segment; and 720 is the second thermally insulating segment. Detailed Implementation

[0025] The technical solution of this application will now be clearly and completely described with reference to the accompanying drawings. The following embodiments are exemplary and are only used to explain this application, and should not be construed as limiting this application. In the following description, the same reference numerals are used to denote the same or equivalent elements, and repeated descriptions are omitted.

[0026] In the description of this application, it should be understood that the terms "upper", "lower", "inner", "outer", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this application is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this application and to simplify the description, and are not intended to indicate or imply that the equipment or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0027] Furthermore, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] It should also be further understood that the term “and / or” as used in this application refers to any combination of one or more of the listed items, as well as all possible combinations.

[0029] Example 1: This embodiment details a photolithography overlay structure based on hybrid lithography. This structure is mainly used to form a continuous optical waveguide transmission link on a substrate to solve the splicing alignment error problem caused by the mixed use of stepper lithography and contact lithography.

[0030] Reference Figure 1 The photolithographic overlay structure includes a first photolithographic pattern area 100, a second photolithographic pattern area 200, and an overlapping overlay area 300 located at the junction of the two.

[0031] The first lithographic patterned region 100 includes a first waveguide pattern with a first dimensional accuracy. In a specific embodiment, this region is defined by a stepper lithography process, possessing nanometer-scale processing capabilities.

[0032] For example, the first waveguide pattern within the first photolithographic patterning area 100 is used to form a nanoscale fine structure with a feature size as small as 150 nm. Specifically, it may include a multimode interference coupler, a waveguide cross, an interlayer coupler, etc.

[0033] The second lithographic patterning region 200 includes a second waveguide pattern with a second dimensional accuracy. The second dimensional accuracy is lower than the first dimensional accuracy. In one specific embodiment, this region is defined by a contact lithography process, providing micron-level processing capability.

[0034] For example, the second waveguide pattern within the second photolithographic patterning area 200 includes a micron-level fine structure, which may specifically include a multimode transmission waveguide with a width greater than 8 μm, a docking slot for assisting physical coupling of optical fibers, and a mechanical alignment structure for assisting positioning during packaging.

[0035] It should be noted that the first dimensional accuracy and the second dimensional accuracy in this application only indicate the difference in accuracy during the photolithography process and do not limit the specific photolithography scheme. The step-step lithography and contact lithography in this embodiment are only examples. For example, in another specific scheme, the first dimensional accuracy can also adopt other nanometer-level precision photolithography processes.

[0036] Furthermore, the photolithography overlay structure has an overlapping overlay region 300 and an internal heat-insulating conical structure 310 formed on a photomask.

[0037] The overlapping area 300 is located at the boundary between the first lithographic pattern area 100 and the second lithographic pattern area 200. Within this area, the second waveguide pattern formed by exposure partially covers the end of the first waveguide pattern in space, ensuring that the two remain in contact even if there is displacement.

[0038] Structurally, the thermally insulating conical structure is at least partially formed within the overlapping etched region 300, and its width varies linearly along the light transmission direction. This structure can absorb the etched deviation between the first dimensional accuracy and the second dimensional accuracy.

[0039] Specifically, the width of the thermally insulated conical structure changes from the starting end to the ending end, from the starting end width W1 to the ending end width W2, where W1 > W2; and W2 and W1 satisfy the relationship: (W2 W1) / 2≥ΔL, where ΔL is the maximum overlay deviation of the contact lithography process relative to the step lithography process.

[0040] For example, the width of the starting end in the first lithographic pattern area (100) is 2μm to 4μm, and the width of the ending end in the second lithographic pattern area (200) is 7μm to 10μm. This width gradient design across the two lithographic pattern areas ensures that the ending end can still effectively enclose the optical path corresponding to the starting end when there is a deviation in lithographic alignment.

[0041] For example, the linearly gradient length from the starting end to the ending end is set to 480–520 μm, such as 500 μm. This length is sufficient to ensure the adiabatic evolution of the optical mode field during the width change process, avoiding radiation loss.

[0042] The fault tolerance principle is as follows: Because the first photolithographic pattern area 100 and the second photolithographic pattern area 200 use different photolithographic processes, alignment is difficult during splicing. See Figure 1The diagram illustrates three scenarios for cross-size stitching. Ideally, the first lithographic pattern area 100 and the second lithographic pattern area 200 are perfectly aligned. However, in practice, due to differences in dimensional accuracy, longitudinal and horizontal misalignment commonly occurs during mask stitching.

[0043] In this embodiment, the width of the terminating end of the thermally insulating tapered structure is 7μm to 10μm, and the width of the starting end is 2μm to 4μm. When the contact lithography process produces an overlay offset within a preset range relative to the step lithography process (e.g., the offset is within 3μm), the terminating end with a larger width can still completely cover the optical path area where the starting end is located, thereby compensating for the alignment error caused by process deviation and maintaining the continuity of the optical signal.

[0044] The heat-insulated splicing conical structure design of the photomask relaxes the alignment accuracy requirements to the micrometer level, changing the process difficulty from "must be perfectly aligned" to "can still work within the expected offset", which greatly improves the manufacturing yield and process robustness, laying the foundation for the actual mass production of large-area optical adapters.

[0045] See also Figure 1 This exhibit demonstrates the actual pattern formed when the photomask shifts, showcasing how photolithographic overlay structures enable the fabrication of feature sizes spanning orders of magnitude from nanometers to micrometers. Its mask's fault-tolerant Taper design fundamentally overcomes the challenge of high-precision overlay between different photolithography processes, shifting the success rate from relying on "extremely high-precision alignment" to relying on "design tolerance." This significantly improves production yield and process robustness, providing a feasible technical path for the mass production of large-area, high-performance optical adapters.

[0046] In this embodiment, the overlay offset is 2–3 μm, which is the offset range mentioned above that "it can still work within the expected offset range". That is, the maximum overlay deviation is 3 μm.

[0047] Example 2: Reference Figures 2-4 This embodiment discloses an ultra-large optical adapter board based on heterogeneous integration, which applies the photolithography overlay structure described in Embodiment 1, achieving a balance between high density and large area.

[0048] Reference Figure 3 The optical adapter includes a substrate layer 500 and three silicon nitride waveguide layers stacked thereon.

[0049] The substrate 500 is typically a silicon substrate, on which a cladding 510 is grown to provide a low-refractive-index optical confinement environment. Three silicon nitride waveguide layers are sequentially spaced within the cladding 510 from top to bottom. The layers are isolated from each other by silicon dioxide spacers (not shown in the figure).

[0050] The three-layer silicon nitride waveguide layer is divided into two parts in terms of function and structure: The middle waveguide layer 620 and the bottom waveguide layer 610 (optical routing layer): together they constitute the optical routing layer, used for high-density transmission and distribution of optical signals. In order to achieve high-density transmission, the thickness of the middle waveguide layer 620 and the bottom waveguide layer 610 is set to 380nm~420nm.

[0051] Due to their thickness, the middle waveguide layer 620 and the bottom waveguide layer 610 are highly confined waveguides, tightly trapping the optical field within the waveguide core. For example, the middle and bottom waveguides are used to house wavelength division multiplexing (WDM) units (such as AWGs) or power dividers (such as nMIs) to achieve large-area interconnects.

[0052] The thicknesses of the middle waveguide layer 620 and the bottom waveguide layer 610 can be the same or different, and their thicknesses can be set to 380nm, 400nm, or 420nm, as long as the thickness range is met. In a specific embodiment, the thicknesses of the middle waveguide layer 620 and the bottom waveguide layer 610 are the same to facilitate processing, and the thickness of the middle waveguide layer 620 and the bottom waveguide layer 610 is set to 400nm.

[0053] Top waveguide layer 630 (optical coupling interface): The thickness of this layer is less than that of the middle waveguide layer and the bottom waveguide layer. The thickness of the top waveguide layer 630 is set to 90nm~110nm.

[0054] Due to its thinness, the top waveguide layer 630 is a low-confined waveguide with a large and divergent optical mode field, and is configured as the optical coupling interface between the chip and the adapter board. This design facilitates low-loss transmission and mode field matching with external lasers or optical fibers. The thickness of the top waveguide layer 630 can be set to 90 nm, 100 nm, or 110 nm, as long as the thickness falls within a certain range. For example, the thickness of the top waveguide layer 630 is set to 100 nm.

[0055] To achieve interconnection between the three waveguide layers, the three silicon nitride waveguide layers are provided with a double-segment thermally insulating conical structure 700. (Refer to...) Figure 2 and Figure 4 This structure is used to realize mode-field conversion and vertical interconnection of optical signals. The dual-segment thermally adiabatic conical structure 700 is configured such that its width linearly narrows along the length of the silicon nitride waveguide layer to reduce the ability to confine the optical field and force the optical field to "escape" into the adjacent waveguide layer.

[0056] Specifically, the dual-segment thermally adiabatic conical structure 700 includes a first thermally adiabatic segment 710 and a second thermally adiabatic segment 720. The narrowing rate of the first thermally adiabatic segment 710 is set lower than that of the second thermally adiabatic segment 720. Adjacent waveguide layers are vertically coupled at least through the first thermally adiabatic segment 710.

[0057] Ideally, adjacent waveguides are coupled through the first insulating section 710. When the vertical coupling deviates, adjacent waveguides are coupled through the first insulating section 710 and the second insulating section 720. The setting of the second insulating section 720 makes the light pass through the adjacent waveguides more smoothly and reduces the insertion loss.

[0058] The above scheme will be further explained below with specific examples.

[0059] See Figure 2 It demonstrates the vertical coupling between the bottom waveguide layer 610 and the middle waveguide layer 620, as well as the vertical coupling between the middle waveguide layer 620 and the top waveguide layer 630.

[0060] The bottom waveguide layer 610 and the middle waveguide layer 620 employ a dimensionally symmetrical vertical coupling structure. The first adiabatic segment 710 has a large length-to-width ratio, with an initial width ranging from 0.1 μm to 0.18 μm, achieving adiabatic mode evolution to 0.3 μm to 0.4 μm within a gradually increasing length of 400 μm to 500 μm. The subsequent second adiabatic segment 720 is used for rapid mode field matching, with its width increasing from a shorter length of 50 μm to 120 μm to over 1.0 μm. This symmetrical structure ensures that optical signals are transmitted between the bottom and middle layers with extremely low loss (e.g., less than 0.15 dB within a 100 nm bandwidth).

[0061] The first insulating section 710 of the middle waveguide layer 620 has an initial width of 0.18μm to 0.25μm, which widens to 0.45μm to 0.55μm through a linearly tapered region with a length of 350μm to 450μm; the second insulating section 720 has an initial width of 0.45μm to 0.55μm, which widens to 0.9μm to 1.2μm through a linearly tapered region with a length of 35μm to 50μm. The first insulating section 710 of the top waveguide layer 630 has an initial width of 1.25μm to 1.45μm, which widens to 1.6μm to 1.8μm through a linearly tapered region of 350μm to 450μm in length; its second insulating section 720 has an initial width of 1.6μm to 1.8μm, which widens to 2.5μm to 3.2μm through a linearly tapered region of 35μm to 50μm in length.

[0062] Further, see Figure 4 It demonstrates the vertical coupling of the optical adapter plate to the optical core through the top waveguide layer 630.

[0063] Example 3: This embodiment discloses a manufacturing method for an ultra-large optical adapter plate based on heterogeneous integration. The manufacturing method emphasizes a process flow of first stepping, then contacting, and overlapping overlay etching. The manufacturing method includes the following steps: S100, providing a substrate with an underlying silicon nitride thin film deposited.

[0064] The manufacturing process of optical adapters is based on silicon substrate wafers with pre-deposited cladding and underlying silicon nitride films. The process flow begins with wafer cleaning, followed by partial cladding growth via thermal oxidation or PECVD, and then deposition of the underlying silicon nitride film via LPCVD.

[0065] S200: Pattern the underlying silicon nitride thin film to form the underlying waveguide layer 610 and alignment marks.

[0066] Although this layer pattern does not require precise alignment, in this step, the first layer pattern is defined and globally universal alignment marks are etched out for use in subsequent photolithography alignment.

[0067] Specifically, the waveguide and alignment mark pattern of the bottom silicon nitride thin film is split into five 22nm×22nm or 17nm×26nm DUV photomasks. The pattern is then formed on the wafer by sequential exposure and splicing of multiple masks, and finally transferred to the bottom waveguide layer 610 by ICP dielectric etching.

[0068] S300: Deposit a first spacer layer and a middle silicon nitride thin film; pattern the middle silicon nitride thin film based on the alignment marks to form a middle waveguide layer 620.

[0069] The pattern of the middle silicon nitride thin film is also split into multiple masks, and multiple rounds of alignment and exposure are performed with the help of alignment marks etched on the bottom waveguide layer 610 to combine the complete pattern at precise positions. The pattern transfer is then completed by ICP etching.

[0070] S400, deposit the second spacer layer and the top silicon nitride thin film. Based on the alignment mark, use a hybrid lithography process combining step lithography and contact lithography to pattern the top silicon nitride thin film to form the top waveguide layer 630.

[0071] The hybrid lithography process specifically includes: Stepper lithography stage: High-precision DUV stepper lithography is employed. Based on alignment marks, the silicon nitride thin film is exposed, developed, and etched. During this stage, the main fine structure is formed, and an overlap area is reserved at the junction with subsequent contact lithography.

[0072] Contact lithography stage: Contact photoresist is applied to the wafer after step-through lithography and etching. Alignment (based on the same alignment mark), overlay, exposure, and development are then performed using contact lithography.

[0073] At this stage, the contact lithography pattern physically covers the ends of the fine structure of the main body within the overlapping area. After confirming the stitching effect, a second etching is performed to obtain a complete, physically connected silicon nitride waveguide pattern.

[0074] It should be noted that the spacer layer is not shown in the figure.

[0075] Simultaneously, before depositing the bottom, middle, and top silicon nitride films in sequence, a corresponding lower cladding layer is deposited. After the bottom, middle, and top silicon nitride films, a corresponding upper cladding layer is deposited to coat the silicon nitride films and planarize the optical adapter plate. That is, the deposition is carried out in batches to form a complete cladding layer covering three layers of silicon nitride films.

[0076] In addition, after any silicon nitride waveguide layer is etched, the wafer needs to be cleaned, the aforementioned cladding cake is deposited and annealed, and then polished by CMP.

[0077] The S500 undergoes a metallization process to complete the manufacturing of the optical adapter plate.

[0078] Because the wafer has significant warping due to multiple depositions and heat treatments, contact lithography cannot meet the requirements of overlay accuracy for metal patterning. Therefore, DUV lithography is still used for metal layer patterning. The pattern position is ensured by aligning the alignment marks of the bottom waveguide layer 610.

[0079] The metallization process specifically includes the following steps: Spin-coating the primer and annealing, then coating with DUV photoresist for exposure and development, forming a photolithographic morphology with undercut characteristics.

[0080] Based on the alignment marks, DUV step lithography is used for exposure and development.

[0081] Metal electrodes are formed by depositing metal through electron beam evaporation and then peeling them off by soaking in a hot water bath with N-methylpyrrolidone.

[0082] The wafers are cleaned, and the adapter board processing is complete.

[0083] The embodiments described in this specific implementation are preferred embodiments of this application and are not intended to limit the scope of protection of this application. Identical components are represented by the same reference numerals. Therefore, all equivalent changes made to the structure, shape, and principle of this application should be covered within the scope of protection of this application.

Claims

1. A photolithographic overlay structure based on hybrid photolithography, used to form a continuous optical waveguide transmission link on a substrate, characterized in that, include: The first photolithographic patterning area contains a first waveguide pattern with a first dimensional accuracy; The second lithographic patterning area includes a second waveguide pattern with a second dimensional accuracy, which is lower than the first dimensional accuracy. An overlapping etched region is disposed at the boundary between the first lithographic pattern area and the second lithographic pattern area. In the overlapping etched region, the second waveguide pattern partially covers the end of the first waveguide pattern in space. The thermally insulated conical structure has a width that varies linearly along the light transmission direction and is at least partially formed within the overlapping etched area. It is used to absorb the etched deviation between the first feature size accuracy and the second size accuracy to achieve thermally insulated transmission of optical signals.

2. The photolithographic overlay structure based on hybrid photolithography according to claim 1, characterized in that, The width of the insulated conical structure changes from the starting end (W1) to the ending end (W2), where W1 > W2; and W2 and W1 satisfy the following relationship: (W2 W1) / 2≥ΔL, where ΔL is the maximum overlay deviation of the contact lithography process relative to the step lithography process.

3. The photolithographic overlay structure based on hybrid photolithography according to claim 2, characterized in that, The overlay offset is 2–3 μm.

4. The photolithographic overlay structure based on hybrid photolithography according to claim 2, characterized in that, The length from the starting end to the ending end is configured to satisfy the adiabatic evolution condition of the optical signal; wherein the length is much larger than the width difference between the starting end and the ending end, and the linearly gradient length is 480 to 520 μm, so that the optical signal maintains low-loss transmission when passing through the adiabatic splicing conical structure.

5. The photolithographic overlay structure based on hybrid photolithography according to claim 1, characterized in that, The first dimensional accuracy is at the nanometer level, and the first photolithographic pattern area is used to etch nanometer-level fine structures; the second dimensional accuracy is at the micrometer level, and the second photolithographic pattern area is used to etch micrometer-level fine structures.

6. A super-large optical adapter board based on heterogeneous integration, characterized in that, The application has the photolithography overlay structure according to any one of claims 1-5, wherein the optical adapter plate comprises: A substrate layer on which a cladding layer is grown; Three silicon nitride waveguide layers are disposed sequentially and spaced apart from top to bottom within the cladding layer. The three silicon nitride waveguide layers include: The middle waveguide layer and the bottom waveguide layer together constitute the optical routing layer, which is used for the transmission and distribution of optical signals; The top waveguide layer, which is thinner than the middle and bottom waveguide layers, is configured as the optical coupling interface between the chip and the adapter board. The three-layer silicon nitride waveguide layer is provided with a double-segment thermally insulating conical structure. The width of the double-segment thermally insulating conical structure is linearly narrowed along the length direction of the silicon nitride waveguide layer, so that adjacent waveguide layers are vertically interconnected through the double-segment thermally insulating conical structure to realize mode field conversion of optical signals.

7. The ultra-large optical adapter board based on heterogeneous integration according to claim 6, characterized in that, The thickness of the top waveguide layer is set to 90nm to 110nm, and the thickness of the middle waveguide layer and the bottom waveguide layer are both set to 380nm to 420nm. The top waveguide is a low-confinement waveguide for low-loss transmission; the middle waveguide and the bottom waveguide are high-confinement waveguides for setting up wavelength division multiplexing (WDM) or power dividers.

8. The ultra-large optical adapter board based on heterogeneous integration according to claim 6, characterized in that, The dual-segment adiabatic conical structure includes a first adiabatic segment and a second adiabatic segment. The narrowing rate of the first adiabatic segment is lower than that of the second adiabatic segment. Adjacent waveguide layers are vertically coupled at least through the first adiabatic segment.

9. A method for manufacturing an ultra-large optical adapter plate based on heterogeneous integration, characterized in that, The manufacturing method for preparing the adapter plate according to any one of claims 6-8 includes the following steps: S100, providing a substrate with a deposited silicon nitride thin film; S200: Pattern the underlying silicon nitride film to form an underlying waveguide layer and alignment marks; S300: Deposit a first spacer layer and a middle silicon nitride thin film; pattern the middle silicon nitride thin film based on the alignment marks to form a middle waveguide layer; S400, deposit the second spacer layer and the top silicon nitride film. Based on the alignment mark, use a hybrid lithography process combining step lithography and contact lithography to pattern the top silicon nitride film to form the top waveguide layer. S500, metallization process is carried out to complete the manufacturing of optical adapter board; The hybrid lithography process in S400 includes: Step lithography stage: The silicon nitride thin film is exposed, developed and etched using step lithography to form the main fine structure, and an overlapping area is reserved at the splicing point with the subsequent contact lithography. Contact lithography stage: After step lithography and etching are completed, contact lithography is applied to the wafer. The contact lithography process is used for alignment, overlay, exposure and development, so that the contact lithography pattern covers the end of the main fine structure in the overlapping area. After confirming the splicing effect, etching is performed to obtain a complete silicon nitride waveguide pattern. The thermally insulating conical structure is formed within the overlapping area.

10. A method for manufacturing an ultra-large optical adapter plate based on heterogeneous integration according to claim 9, characterized in that, The metallization process in S500 includes: Spin-coat the primer and anneal it, then coat it with DUV photoresist; Based on the alignment marks, step lithography is used for exposure and development to form a lithographic morphology with undercut features; Metal electrodes are formed by depositing metal through electron beam evaporation and then peeling them off by soaking in a hot water bath with N-methylpyrrolidone.

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