MCU dynamic power consumption adjusting method and system based on load prediction

Abstract

The invention discloses an MCU dynamic power consumption adjustment method and system based on load prediction, and relates to the technical field of power consumption adjustment, and the method comprises the steps: firstly obtaining an original event record containing an interrupt vector number and a timestamp, carrying out the deep filtering and feature extraction of an event stream, and constructing a state vector representing a system operation mode at a current moment; then, a sparse Markov chain model is introduced to carry out probability prediction on the state vector, the most likely system state at the next moment is deduced, and CPU main frequency and bus / peripheral frequency requirements are independently analyzed through a double-track mapping mechanism; and then, in combination with a global hardware constraint condition, arbitration and energy efficiency optimization solution are performed on the two types of frequency requirements, and a precise regulation and control instruction containing target voltage and frequency is generated. In this way, double-track collaborative precise regulation and control of CPU calculation and peripheral communication loads can be achieved, and therefore the operation stability and the energy utilization efficiency of an MCU system under complex working conditions are greatly improved.

Description

Technical Field

[0001] This application relates to the field of power consumption regulation technology, and more specifically, to a method and system for dynamic power consumption regulation of MCU based on load prediction. Background Technology

[0002] With the rapid development of embedded applications such as the Internet of Things (IoT), automotive electronics, and smart wearables, microcontrollers (MCUs) have become the core of modern electronic systems. In these applications, systems not only need to handle increasingly complex computing tasks to provide stronger performance, but also face stringent power consumption and heat dissipation limitations. Low-power design is particularly crucial in battery-powered portable devices. To balance the trade-off between performance and power consumption, Dynamic Voltage and Frequency Scaling (DVFS) technology has emerged. It allows the MCU to dynamically adjust its core voltage and operating frequency based on the real-time workload, thus entering a deep power-saving state under low loads and responding quickly under high loads to ensure system performance and optimize energy efficiency. However, the effectiveness of DVFS technology highly depends on accurate prediction of future loads. If the prediction is lagging or inaccurate, it will lead to substandard system performance or unsatisfactory energy-saving effects.

[0003] To address these issues, most existing technologies rely on monitoring and predicting the utilization of the central processing unit (CPU). These methods build predictive models by monitoring CPU activity, such as recording idle time, tracking task switching frequencies, or analyzing historical instruction sequences, and then inferring the computational demands of the next moment, thereby guiding adjustments to frequency and voltage. However, these CPU-centric predictive methods have an inherent cognitive blind spot: they struggle to comprehensively depict the true load of the entire MCU system. In modern, complex MCU architectures, large data throughput and high-frequency communication tasks are not directly handled by the CPU but are delegated to autonomous units such as direct memory access (DMA) controllers or high-speed serial peripherals (e.g., SPI, I2C). When the CPU is relatively idle, but the DMA is performing intensive data transfers or peripherals are engaged in high-speed communication, the system's bus and memory subsystems are actually under immense pressure. At this point, the prediction model based on CPU utilization will incorrectly judge that the system is in a low-load state and make a decision to reduce the clock frequency of the system bus or peripherals. This misjudgment is very likely to cause serious functional failures such as first-in-first-out (FIFO) queue overflow or loss of communication data packets on the data transmission link, thereby seriously affecting the stability and reliability of the system.

[0004] Therefore, there is an urgent need for an optimized method and system for dynamic power consumption regulation of MCUs based on load prediction. Summary of the Invention

[0005] This application is made in order to solve the above-mentioned technical problems.

[0006] According to one aspect of this application, a method for dynamic power consumption regulation of an MCU based on load prediction is provided, comprising:

[0007] Obtain the original event record, which includes the original interrupt vector number, the timestamp when entering the interrupt, and the timestamp when exiting the interrupt;

[0008] The original event records are filtered and feature extracted to obtain the state vector at the current moment. The state vector at the current moment includes the discretized interrupt ID and the quantized time level.

[0009] The next state is predicted based on a sparse Markov chain from the current state vector to obtain the most likely state vector at the next moment.

[0010] A dual-track load demand mapping is performed on the most likely state vector for the next predicted moment to obtain the CPU clock frequency and bus / peripheral frequency required for the prediction.

[0011] Global constraint arbitration and energy efficiency optimization are performed on the predicted CPU clock frequency and the predicted bus / peripheral frequency to obtain control instructions containing the target voltage and target frequency.

[0012] According to another aspect of this application, a MCU dynamic power consumption regulation system based on load prediction is provided, comprising:

[0013] The event log acquisition module is used to acquire the original event log, which includes the original interrupt vector number, the timestamp when entering the interrupt, and the timestamp when exiting the interrupt;

[0014] The filtering and feature extraction module is used to filter and extract features from the original event records to obtain the current state vector, which includes the discretized interrupt ID and the quantized time level.

[0015] The next state prediction module is used to predict the next state of the current state vector based on a sparse Markov chain to obtain the predicted most likely state vector for the next moment.

[0016] The dual-track load demand mapping module is used to perform dual-track load demand mapping on the most likely state vector in the next predicted moment to obtain the CPU frequency and bus / peripheral frequency required for prediction.

[0017] The constraint arbitration and optimization module is used to perform global constraint arbitration and energy efficiency optimization on the predicted required CPU clock frequency and the predicted required bus / peripheral frequency to obtain control instructions containing target voltage and target frequency.

[0018] Compared with existing technologies, this application provides a method and system for dynamic power consumption regulation of MCUs based on load prediction. First, it acquires raw event records including interrupt vector numbers and timestamps, and performs deep filtering and feature extraction on the event stream to construct a state vector representing the system's current operating mode. Then, a sparse Markov chain model is introduced to probabilistically predict the state vector, inferring the most likely system state at the next moment, and independently resolves the CPU clock frequency and bus / peripheral frequency requirements through a dual-track mapping mechanism. Furthermore, combined with global hardware constraints, arbitration and energy efficiency optimization are performed on the two types of frequency requirements to generate precise control instructions containing target voltage and frequency. This enables precise dual-track coordinated control of CPU computing and peripheral communication loads, thereby significantly improving the operational stability and energy efficiency of the MCU system under complex operating conditions. Attached Figure Description

[0019] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0020] Figure 1 This is a flowchart of a MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application.

[0021] Figure 2 This is a data flow diagram of a load prediction-based MCU dynamic power consumption adjustment method according to an embodiment of this application.

[0022] Figure 3 This is a flowchart of sub-step S2 of the MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application.

[0023] Figure 4 This is a flowchart of sub-step S3 of the MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application.

[0024] Figure 5 This is a flowchart of sub-step S4 of the MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application.

[0025] Figure 6 This is a flowchart of sub-step S41 of the MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application.

[0026] Figure 7This is a flowchart of sub-step S42 of the MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application.

[0027] Figure 8 This is a block diagram of a load prediction-based MCU dynamic power consumption adjustment system according to an embodiment of this application. Detailed Implementation

[0028] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0029] To address the problems mentioned above in the background technology, this application proposes a method for dynamic power consumption adjustment of MCUs based on load prediction. Figure 1 This is a flowchart of a MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application. Figure 2 This is a data flow diagram of a MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application. Figure 1 and Figure 2 As shown, the MCU dynamic power consumption adjustment method based on load prediction includes the following steps: S1, acquiring original event records, which include the original interrupt vector number, the timestamp when entering the interrupt, and the timestamp when exiting the interrupt; S2, filtering and extracting features from the original event records to obtain the current state vector, which includes the discretized interrupt ID and the quantized time level; S3, predicting the next state based on a sparse Markov chain from the current state vector to obtain the most likely state vector for the next moment; S4, performing dual-track load demand mapping on the most likely state vector for the next moment to obtain the CPU clock frequency and the bus / peripheral frequency required for prediction; S5, performing global constraint arbitration and energy efficiency optimization on the CPU clock frequency and the bus / peripheral frequency required for prediction to obtain control instructions containing the target voltage and target frequency.

[0030] In the aforementioned MCU dynamic power consumption adjustment method based on load prediction, step S1 involves acquiring raw event records, which include the raw interrupt vector number, the timestamp when entering the interrupt, and the timestamp when exiting the interrupt. It should be understood that since MCU dynamic power consumption adjustment requires accurate load prediction, and the type, frequency, and duration of interrupt events directly reflect load changes, this application acquires raw event records such as interrupt vector numbers and interrupt entry / exit timestamps to comprehensively characterize interrupt behavior, establish a mapping relationship between interrupts and load, and provide accurate data input for the load prediction model. This allows the load prediction results to better match the actual operating load of the MCU, making the dynamic power consumption adjustment strategy more targeted, minimizing unnecessary power consumption, and improving energy utilization efficiency while ensuring the system's real-time response performance.

[0031] Specifically, in one possible embodiment, step S1 is implemented as follows: First, the interrupt controller is configured to enable the interrupt vector number capture function and set the detection method for the interrupt trigger signal to ensure that the corresponding interrupt vector number can be accurately identified when an interrupt occurs. Then, the system's high-precision timer is initialized, the timing accuracy is set to meet the timestamp recording requirements, and the timer is linked with the interrupt controller. When an external event triggers an interrupt, the interrupt controller captures the interrupt vector number and simultaneously triggers the timer to record the current time as the timestamp for entering the interrupt. When the interrupt service routine finishes execution and issues an exit signal, the timer again records the current time as the timestamp for exiting the interrupt. Finally, the data transmission module stores the interrupt vector number, the timestamps for entering and exiting the interrupt, in a preset data format in a designated storage area of ​​the on-chip RAM for subsequent use by the load prediction module.

[0032] In the aforementioned MCU dynamic power consumption adjustment method based on load prediction, step S2 involves filtering the event stream and extracting features from the original event records to obtain the current state vector. The current state vector includes a discretized interrupt ID and a quantized time level. It should be understood that because the original event records contain a large number of non-business-related noise interrupts, such as system tick interrupts, and the data is scattered (i.e., vector numbers and timestamps exist independently), they cannot directly provide structured input for the load prediction model, easily leading to prediction bias. Therefore, this application further filters the original event records to remove useless data and extracts interrupt identifiers and time interval features to convert them into state vectors, thereby constructing a structured input that meets the requirements of the prediction model. This reduces the interference of invalid data on the prediction process, while allowing the state vector to accurately reflect the type and timing characteristics of the system load, providing a reliable basis for subsequent predictions based on sparse Markov chains, and improving the accuracy and efficiency of load prediction.

[0033] In particular, in one specific embodiment, Figure 3 This is a flowchart of sub-step S2 of the MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application. Figure 3 As shown, step S2 includes: S21, filtering the original event record based on the interrupt filter mask to determine whether to filter the original event record; S22, in response to the original event record not being marked in the interrupt filter mask, calculating the time interval from the last valid interrupt trigger based on the timestamp when entering the interrupt and the timestamp when exiting the interrupt; S23, quantizing the time interval from the last valid interrupt trigger to obtain the quantized time level; S24, setting the original interrupt vector number as the discretized interrupt ID.

[0034] Specifically, step S21 involves filtering the original event records based on an interrupt filter mask to determine whether to filter them. It should be understood that since the original event records contain interrupts that do not reflect the service load, such as periodic timer interrupts, directly participating in subsequent processing would consume MCU computing resources and distort load assessment, affecting the accuracy of power consumption regulation. Therefore, this application further uses an interrupt filter mask as a screening criterion, determining whether to retain event records by comparing the matching relationship between interrupt identifiers and the mask, thereby filtering out valid interrupts that are only related to the service load. This avoids invalid interrupt data from entering the subsequent processing flow, reduces redundant computational consumption of the MCU, and ensures that subsequent load analysis is based only on real service load data, improving the adaptability of the power consumption regulation strategy to the actual load.

[0035] Specifically, in one possible embodiment, step S21 is implemented as follows: First, the interrupt filtering mask is stored in the MCU's Flash memory in bit field form, where each bit corresponds to an interrupt vector number. A bit value of 1 indicates that the interrupt needs to be filtered, and a bit value of 0 indicates that it needs to be retained. After the original event record is generated, the interrupt vector number is extracted from the record and converted into the bit index corresponding to the mask. Then, the bit value of the bit index in the mask is determined by a bitwise AND operation. If the result is 1, the original event record is directly deleted from the RAM cache; if the result is 0, the record is marked as valid and passed to the feature extraction stage to ensure that subsequent processing only targets service-related interrupts.

[0036] Specifically, in step S22, in response to the original event record not being marked in the interrupt filter mask, the time interval between the entry and exit timestamps of the interrupt is calculated based on the timestamps of entering and exiting the interrupt. It should be understood that relying solely on interrupt identifiers cannot fully reflect the temporal characteristics of the load, while the time interval of interrupt triggers directly reflects the intensity of the service load; for example, short intervals correspond to high load frequency, and long intervals correspond to low load frequency. The lack of this information would prevent load prediction from capturing dynamic change patterns. Therefore, after confirming the validity of the event record, this application uses the difference between the timestamps of entering and exiting the interrupt to calculate the time interval, thereby supplementing the temporal dimension information of the load. This allows the subsequently generated state vector to simultaneously include load type and frequency characteristics, enabling the sparse Markov chain-based prediction model to more comprehensively grasp the system load change trend, significantly improving the foresight and accuracy of the next state prediction, and providing a more realistic decision-making basis for power consumption adjustment.

[0037] Specifically, in one possible embodiment, step S22 is implemented as follows: First, a dedicated storage unit is allocated in the MCU's general-purpose register to store the entry timestamp of the last valid interrupt. When it is detected that the current original event record is not marked by a filter mask, the entry timestamp of the interrupt is read from the record. Then, a subtraction operation is performed by the MCU's arithmetic logic unit, subtracting the previous timestamp in the storage unit from the current entry timestamp to obtain the time interval. Subsequently, the current entry timestamp is overwritten with the original value in the storage unit to prepare for the calculation of the interval of the next valid interrupt. Finally, the calculated time interval is temporarily stored in the temporary data area of ​​RAM, awaiting subsequent quantization processing.

[0038] Specifically, step S23 involves quantizing the time interval since the last valid interrupt trigger to obtain a quantized time level. It should be understood that, due to the significant differences in the numerical range of interrupt time intervals across different business scenarios, continuous numerical values ​​increase the computational complexity of the MCU and are difficult to combine with discrete interrupt IDs to form a suitable feature combination, which does not meet the computational resource requirements of low-power MCUs. Therefore, this application further converts continuous time intervals into discrete quantized levels based on a preset time level threshold, thereby simplifying the processing difficulty of time features. This significantly reduces the computational power consumption of the MCU in the feature processing stage, while simultaneously enabling the time level and discrete interrupt ID to form a unified structured feature, perfectly adapting to the input format of the subsequent load prediction model, effectively improving feature processing efficiency and the running speed of the prediction model, and ensuring the real-time performance of power consumption adjustment.

[0039] Specifically, in one possible embodiment, step S23 is implemented as follows: First, three sets of time thresholds are pre-stored in the MCU's Flash memory. These thresholds are set based on the statistical distribution of typical business scenarios. For example, the short interval threshold is set to 100 microseconds, and the medium-to-long interval boundary threshold is set to 1 millisecond, corresponding to quantization levels 0 (short), 1 (medium), and 2 (long), respectively. Then, after reading the time interval from the temporary data area, the comparator module is called to compare it with the preset thresholds one by one. If the time interval is less than or equal to 100us, the quantization level is determined to be 0, representing high-frequency burst load; if it is greater than 100us and less than or equal to 1ms, the quantization level is determined to be 1; if it is greater than 1ms, the quantization level is determined to be 2, representing sparse background load. Subsequently, the quantization level is written into the state vector to construct the buffer area and associated with the discretized interrupt ID, preparing for subsequent vector combination.

[0040] Specifically, in step S24, the original interrupt vector number is set as the discretized interrupt ID. It should be understood that since the original interrupt vector number may have a non-continuous distribution and an excessively large numerical range, directly using it as a feature would consume a lot of storage resources and increase the difficulty of subsequent state retrieval and matching, which is detrimental to the efficient processing of the MCU. Therefore, this application further standardizes the original interrupt vector number, mapping it to a continuous discretized interrupt ID, thereby optimizing the storage and retrieval efficiency of the feature. This significantly reduces the numerical range of the interrupt identifier, decreases storage resource consumption, and allows subsequent state vectors to be quickly located in the state transition matrix of the sparse Markov chain, significantly improving the efficiency of state retrieval and prediction, and ensuring that the MCU can still efficiently complete load prediction and power consumption adjustment in low-power mode.

[0041] Specifically, in one possible embodiment, step S24 is implemented as follows: First, a mapping table between the original interrupt vector number and the discretized ID is established in the MCU's Flash memory. Each entry in the table contains the original vector number and the corresponding consecutive integer ID (incrementing from 0). After obtaining the original interrupt vector number, a lookup function is called to retrieve a matching entry in the mapping table. If the retrieval is successful, the corresponding discretized ID is directly extracted; if the retrieval fails, i.e., a new interrupt type is encountered, an entry is automatically added to the end of the mapping table, and the current maximum ID value plus 1 is assigned as the discretized ID of the interrupt. Finally, the discretized ID is written into the state vector construction buffer and combined with the quantization time level to form a complete state vector.

[0042] In the aforementioned MCU dynamic power consumption adjustment method based on load prediction, step S3 involves predicting the next state of the current state vector using a sparse Markov chain to obtain the most likely state vector for the next moment. In a specific example of this application, step S3 includes: based on the state transition probability matrix, retrieving and predicting the next state probability distribution of the current state to obtain the most likely state vector for the next moment. It should be understood that relying solely on the current state vector cannot detect load change trends in advance. Traditional prediction models (such as fully connected networks) require significant computing and storage resources, making them unsuitable for low-resource scenarios of MCUs, resulting in delayed power consumption adjustment. Therefore, this application further uses the state transition probability matrix of a sparse Markov chain to predict the next state by retrieving the probability distribution corresponding to the current state, thereby obtaining load trends in advance with low resource consumption. This provides a forward-looking basis for dynamic power consumption adjustment, avoiding adjustment lag. Simultaneously, the sparse matrix significantly reduces storage usage, adapts to the hardware resource limitations of MCUs, and ensures the real-time performance and reliability of the prediction process.

[0043] In particular, in one specific embodiment, Figure 4 This is a flowchart of sub-step S3 of the MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application. Figure 4 As shown, step S3 includes: S31, using the current state vector as the row index, querying the state transition probability matrix to obtain a temporary probability distribution list; S32, performing maximum likelihood estimation on the temporary probability distribution list to obtain the most likely state vector for the predicted next time step.

[0044] Specifically, in step S31, the current state vector is used as the row index to query the state transition probability matrix to obtain a temporary probability distribution list. It should be understood that since the state transition probability matrix stores the transition relationships between all states, performing a full traversal of the matrix to retrieve the probability distribution corresponding to the current state would consume too much MCU computation time, failing to meet the real-time requirements of power consumption adjustment. Therefore, this application further uses the current state vector as the row index to directly locate the corresponding row data in the matrix, thereby quickly extracting all possible next states and their corresponding probabilities for that state. This significantly shortens the probability distribution retrieval time, ensures the real-time performance of the prediction process, lays the foundation for quickly determining the optimal next state, adapts to the MCU's real-time power consumption adjustment requirements, and avoids unnecessary computational waste.

[0045] Specifically, in one possible embodiment, step S31 is implemented as follows: First, the sparse state transition probability matrix is ​​stored in the MCU's SRAM in CSR format, which includes a row pointer array, a column index array, and a probability value array. When the current state vector is obtained, it is converted into a row index integer. The two consecutive values ​​corresponding to that index in the row pointer array are read and used as the start and end addresses of the current row data in the column index array and the probability value array, respectively. Then, from the start address to the end address, the next state vector identifier in the column index array and the corresponding probability in the probability value array are read sequentially. Finally, the read next state vector-probability pairs are stored sequentially in an on-chip FIFO cache to form a temporary probability distribution list, ensuring that subsequent processing can directly call the list without repeated retrieval.

[0046] Specifically, step S32 involves performing maximum likelihood estimation on the temporary probability distribution list to select the most likely state vector for the predicted next moment. It should be understood that since the temporary probability distribution list contains multiple possible next states and their corresponding probabilities, failing to explicitly select the most likely state will lead to a lack of definite target load basis for subsequent power consumption adjustment, causing confusion in the adjustment strategy and affecting the balance between power consumption and performance. Therefore, this application further performs maximum likelihood estimation on the temporary probability distribution list, selecting the state with the highest probability as the prediction result to determine the most reliable load state for the next moment. This provides a clear target direction for dynamic power consumption adjustment, ensuring that the adjustment strategy accurately matches the load requirements of the next stage, effectively balancing the MCU's operating performance and power consumption, and avoiding over-adjustment or under-adjustment due to target ambiguity.

[0047] Specifically, in one possible embodiment, step S32 is implemented as follows: First, two temporary registers are initialized to store the current maximum probability value (initialized to 0) and the corresponding next state vector (initialized to empty), respectively. Then, the MCU's arithmetic logic unit (ALU) is started, sequentially reading each next state vector-probability pair from the temporary probability distribution list. The read probability value is then compared with the current maximum probability value. If the read probability value is greater, the maximum probability value is updated to the read value, and the corresponding next state vector is written to the state register. If the probability values ​​are equal, the state vector with higher priority is selected according to a preset service interruption priority rule. After traversal, the finally determined next state vector is stored in a dedicated prediction result register for direct reading by the dual-track load demand mapping module to initiate the subsequent load demand parsing process.

[0048] It is understandable that the MCU operating environment changes dynamically, and the load transfer mode adjusts in real time according to the application scenario. The offline-built state transition probability matrix cannot adapt to this dynamic change and must be continuously updated online to incorporate new state transition information. Furthermore, considering the significant differences in the consequences of different prediction errors in MCU power management, prediction errors for high-load or high-bandwidth demand events may lead to serious problems such as system lag and functional failure, while prediction errors for low-load events only cause slight power waste. A fixed forgetting factor cannot adapt to these differentiated needs and will reduce the relevance and efficiency of model learning. Therefore, preferably, this application further updates the state transition probability matrix online based on a dynamically adaptive forgetting factor after observing the actual state transition. Specifically, when updating the state transition probability matrix, the forgetting factor is a variable dynamically related to the criticality or risk of the predicted event, and the criticality / risk of the event can be quantified by its requirements for system performance (CPU computing power) and functionality (bus bandwidth). That is, the forgetting factor... The value of can depend on the consequences of prediction errors. If the model makes a prediction error that causes high-load or high-bandwidth events to go unprepared, resulting in system lag or malfunction, then the model should remember this error more deeply, meaning it should adjust more quickly. Conversely, if the prediction error involves two insignificant low-load events, the model can be more forgiving and doesn't need to adjust drastically to maintain stability.

[0049] This is because the consequences of different prediction errors are asymmetrical in MCU power management. High-risk errors (conservative predictions) predict low-load events, but high-load events (such as JPEG decoding) actually occur, resulting in insufficient CPU frequency, severe task timeouts, and a precipitous drop in user experience. Low-risk errors (aggressive predictions), on the other hand, predict a high-load event, but a low-load event actually occurs, resulting in a temporarily higher frequency and slightly wasted power, but without affecting system functionality and performance. Therefore, the model should be more sensitive to high-risk errors, and when such errors occur, the forgetting factor should be adjusted accordingly. The weights should be reduced so that the weights of newly observed (but unpredicted) true transfer paths can be rapidly increased, allowing the model to quickly correct its errors.

[0050] Meanwhile, to improve model stability and convergence speed, a larger forgetting factor is used for routine events with similar load demands and frequent transitions between them. This can prevent the model from fluctuating drastically due to random noise, maintaining model stability, while using a smaller forgetting factor for critical, high-load events. This allows the model to quickly learn the correct transition pattern with a small number of observation samples, accelerating convergence to the optimal strategy.

[0051] Here, we first need to define the criticality metric for the event, that is, we need a function to quantify the criticality of the event represented by any state vector. As mentioned above, this criticality metric can be a weighted combination of its computational and bandwidth requirements. Here, when calculating the CPU clock speed and bus / peripheral frequency required for prediction, we need to divide them by the maximum CPU frequency and the maximum bus / peripheral frequency supported by the MCU, respectively, for normalization.

[0052] Then, the value of the forgetting factor is associated with the critical difference between the predicted event corresponding to the most likely state vector in the next time step and the actual event corresponding to the actual state; the criticality of the event is quantified by the computational load requirement and / or transmission bandwidth requirement of the event. That is, when a state transition occurs... → The model's prediction is At that time, it is necessary to calculate the actual events that occurred. With predicted events Key differences between For example, it could be the normalized L2 norm of the difference vector between the corresponding event state vectors, and the forgetting factor could be:

[0053]

[0054] in, This is set as an upper limit for the forgetting factor (e.g., 0.99) to ensure model stability when key differences are very small. This is set as the lower bound for the forgetting factor (e.g., 0.50), used for situations where key differences are extremely large, to ensure the model learns quickly. The absolute difference between the predicted event and the actual event's criticality, and normalized to the range [0,1], for example, by the maximum value; The forgetting factor is used to determine the relative importance of the predicted and actual events. A smaller forgetting factor is used when the critical difference between the predicted and actual events is greater, thus accelerating the learning and correction of the state transition probability matrix; conversely, a larger forgetting factor is used when the critical difference between the predicted and actual events is smaller, thus maintaining the stability of the state transition probability matrix.

[0055] In this way, by dynamically and adaptively improving the forgetting factor, the business requirements of higher levels (reflected in load requirements) can be correlated with the learning rate of the underlying model, making the online learning process more intelligent and efficient. This allows for a more refined power consumption and performance trade-off in complex and ever-changing embedded environments. Specifically, because the system can learn to recognize critical task switching patterns from low to high load more quickly, it can significantly reduce performance bottlenecks caused by insufficient frequency preparation through faster critical path learning. Simultaneously, the system is less sensitive to random fluctuations in routine, non-critical tasks, resulting in more stable overall model predictions, avoiding unnecessary power consumption jitter, and exhibiting greater robustness. Moreover, by focusing learning resources on critical areas, the system can ensure performance in critical tasks while avoiding over-adjustment on non-critical paths, thus achieving better overall power consumption performance.

[0056] In the aforementioned MCU dynamic power consumption adjustment method based on load prediction, step S4 involves performing a dual-track load demand mapping on the predicted most likely state vector for the next moment to obtain the predicted CPU clock frequency and the predicted bus / peripheral frequency. It should be understood that since the predicted state vector only represents the abstract characteristics of the system load, it cannot directly provide hardware-executable frequency parameters for power consumption adjustment. Furthermore, the CPU computation load and bus / peripheral transmission load requirements of the MCU are independent, and a single frequency adjustment cannot accommodate both, easily leading to insufficient performance or wasted power. Therefore, this application further implements a dual-track mapping on the predicted state vector, separately resolving the CPU clock frequency that meets computational requirements and the bus / peripheral frequency that meets transmission requirements, thereby obtaining the specific parameters required for hardware adjustment. This allows power consumption adjustment to simultaneously adapt to both computational and transmission load requirements, avoiding functional failures caused by a single adjustment, such as communication packet loss due to insufficient bus frequency, while simultaneously achieving precise matching between CPU and bus frequencies, maximizing the MCU's energy efficiency ratio.

[0057] In particular, in one specific embodiment, Figure 5 This is a flowchart of sub-step S4 of the MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application. Figure 5 As shown, step S4 includes: S41, performing a computational load demand mapping based on the predicted event on the most likely state vector in the next predicted moment to obtain the CPU clock frequency required for the prediction; S42, performing a transmission bandwidth demand mapping based on the predicted event on the most likely state vector in the next predicted moment to obtain the bus / peripheral frequency required for the prediction.

[0058] Specifically, in step S41, the most likely state vector for the next predicted moment is mapped to the computational load requirement based on the predicted event to obtain the CPU clock frequency required for the prediction. It should be understood that since the CPU computational load varies significantly depending on the predicted event (e.g., JPEG decoding requires high computational power, while simple I / O interrupts require low computational power), if the CPU runs at a fixed clock frequency, it will suffer from insufficient performance under high load and wasted power under low load, failing to adapt to dynamic load requirements. Therefore, this application further maps the matching CPU computational power requirement to a load configuration table based on the event type corresponding to the predicted state vector, thereby determining the required clock frequency to ensure that the CPU clock frequency accurately matches the computational load. This ensures that the CPU operates at the minimum necessary clock frequency while meeting the current computational requirements, avoiding power consumption losses caused by computational redundancy, and preventing task lag caused by insufficient clock frequency, thus ensuring a balance between real-time performance and low power consumption for the MCU in computationally intensive scenarios.

[0059] In particular, in one specific embodiment, Figure 6 This is a flowchart of sub-step S41 of the MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application. Figure 6 As shown, step S41 includes: S411, using the predicted state vector most likely to occur in the next moment as an index, querying a preset load profile lookup table to obtain the CPU frequency baseline value; S412, dynamically correcting the CPU frequency baseline value to obtain the CPU frequency required for prediction.

[0060] More specifically, in step S411, the predicted state vector most likely to occur in the next moment is used as an index to query a preset load profile lookup table to obtain the CPU frequency baseline value. It should be understood that since the predicted state vector is directly related to the event type, and the basic computing power requirements of different events are stable (e.g., the basic computing power requirement for analog-to-digital conversion sampling is fixed), real-time calculation of the base frequency would consume microcontroller computing power and fail to meet the real-time power consumption adjustment requirements. Therefore, this application further uses the predicted state vector as an index to directly query the base frequency in the preset load profile lookup table to quickly obtain the CPU frequency baseline value adapted to the event type. This significantly shortens the time required to obtain the base frequency, avoids real-time calculation consuming computing power, and ensures that the baseline value matches the basic requirements of the event type, providing a reliable benchmark for subsequent dynamic correction and adapting to the microcontroller's real-time power consumption adjustment requirements.

[0061] Specifically, in one possible embodiment, step S411 is implemented as follows: First, the load profile lookup table (containing the mapping relationship between state vectors, event types, and CPU clock frequency baselines) is loaded from the microcontroller's flash memory into a dedicated lookup table cache in static random access memory, using a hash table structure to improve query efficiency. Next, the predicted state vector is converted into an integer index, and the storage address of the index in the cache is calculated using a hash function. Then, the lookup table entry corresponding to that address is read, and the CPU clock frequency baseline field is extracted, such as a 24MHz baseline corresponding to analog-to-digital conversion sampling interrupt and an 80MHz baseline corresponding to JPEG decoding. Finally, the baseline value is temporarily stored in an on-chip temporary register to provide initial data for subsequent dynamic correction steps, while simultaneously recording the query timestamp to ensure data timeliness.

[0062] More specifically, step S412 involves dynamically correcting the CPU frequency baseline value to obtain the predicted CPU frequency. It should be understood that since the CPU frequency baseline value is based on a static value preset by offline testing, and the execution time of events in actual operation may deviate due to code iteration and changes in data volume (such as changes in the length of analog-to-digital conversion sampling data), using only the baseline value would lead to a mismatch between the frequency and the actual computing power requirements. Therefore, this application further incorporates the historical execution time of events to dynamically fine-tune the baseline value, thereby adapting the frequency to the computing power fluctuations in actual operation. In a specific example of this application, the CPU frequency baseline value is dynamically corrected using the following formula to obtain the predicted CPU frequency:

[0063]

[0064] in, The historical average execution time This is the baseline value for CPU clock speed. As the baseline execution time, As an adaptive adjustment factor, This refers to the CPU clock speed. In other words, it's based on a preset CPU clock speed baseline value. Based on this, we first calculate the historical average execution time. Compared with the baseline execution time The difference as a percentage of the baseline execution time The proportion is used to obtain the degree of deviation of historical performance from the benchmark, and then this deviation proportion is multiplied by the adaptive adjustment factor. This controls the impact of deviation on the CPU frequency adjustment. The result is then added to 1 to form an adjustment coefficient. Finally, this adjustment coefficient is compared with the CPU frequency baseline value. Multiplying these two components will give you the CPU clock speed that best suits the computational load requirements of the predicted events. The entire computation process, by associating historical execution data with benchmark standards and combining them with an adaptive adjustment mechanism, allows the CPU frequency to dynamically adapt to the actual execution situation. This ensures that the performance required for the computational load is met while avoiding unnecessary power waste caused by excessively high frequencies. In this way, the CPU frequency can be more accurately matched to real-time computing power demands, further improving the energy efficiency ratio of the microcontroller.

[0065] Specifically, in step S42, the predicted state vector for the most likely next moment is mapped to the transmission bandwidth requirement based on the predicted event to obtain the predicted bus / peripheral frequency. It should be understood that the bus / peripheral frequency directly determines the timing stability of direct memory access data movement and serial peripheral interface / integrated circuit bus communication. For example, a 10Mbps serial peripheral interface communication requires a peripheral bus frequency of no less than 20MHz. If the bus frequency is adjusted solely based on the CPU clock frequency, insufficient bus frequency can easily lead to FIFO queue overflow or packet loss, or excessively high frequency resulting in wasted power. Therefore, this application further maps the minimum bus bandwidth requirement to the event type corresponding to the predicted state vector through a load profile lookup table, thereby determining the bus / peripheral frequency to ensure the timing requirements of the transmission subsystem. This ensures that the bus / peripheral operates at the minimum frequency required to meet transmission needs, avoids wasted power due to excessively high frequencies, and prevents transmission failures caused by insufficient frequency, ensuring the communication stability and low-power characteristics of the microcontroller in data-intensive scenarios.

[0066] In particular, in one specific embodiment, Figure 7 This is a flowchart of sub-step S42 of the MCU dynamic power consumption adjustment method based on load prediction according to an embodiment of this application. Figure 7 As shown, step S42 includes: S421, using the predicted state vector most likely to occur in the next moment as an index, querying a preset load profile lookup table to obtain the minimum required bus frequency; S422, applying a hard constraint to the minimum required bus frequency to obtain the predicted bus / peripheral frequency.

[0067] More specifically, in step S421, the predicted state vector most likely to occur in the next moment is used as an index to query a preset load profile lookup table to obtain the minimum required bus frequency. It should be understood that since the predicted state vector has a fixed association with the peripheral / direct memory access type (e.g., a specific vector corresponds to serial peripheral interface communication), and the minimum bus frequency requirement for different peripherals is determined by hardware characteristics (e.g., integrated circuit bus peripherals require a minimum bus frequency of 8MHz), real-time calculation of the minimum bus frequency would consume microcontroller computing power and affect transmission efficiency. Therefore, this application further uses the predicted state vector as an index to directly query the minimum bus frequency in the preset load profile lookup table, thereby quickly obtaining a bus frequency benchmark that matches the peripheral requirements. This significantly shortens the time required to obtain the minimum bus frequency, avoids real-time calculation consuming computing power, and ensures that the query result matches the peripheral hardware requirements, providing a reliable benchmark for subsequent hard constraint verification and guaranteeing the real-time performance of the transmission subsystem.

[0068] Specifically, in one possible embodiment, step S421 is implemented as follows: First, the transmission bandwidth sub-table (containing the mapping relationship between state vector, peripheral type, and minimum bus frequency) of the load profile lookup table is loaded from flash memory into the cache of static random access memory, and stored using an array structure to simplify the indexing logic. Next, the predicted state vector is converted into an array index, such as a vector value of 5 corresponding to array index 5. Then, the array element corresponding to this index is read, and the minimum bus frequency field is extracted, such as the minimum bus frequency of peripheral 1 (serial peripheral interface 1) being 20MHz and peripheral 2 (integrated circuit bus 2) being 8MHz. Finally, the minimum bus frequency is temporarily stored in a bus frequency temporary register, and the peripheral type identifier (e.g., serial peripheral interface 1) is recorded to provide data support for subsequent hard constraint verification steps, ensuring the consistency between the data and the peripheral type.

[0069] More specifically, step S422 involves applying a hard constraint to the minimum required bus frequency to obtain the predicted required bus / peripheral frequency. It should be understood that since the minimum required bus frequency retrieved from the load profile lookup table is based on a typical scenario preset, and the minimum operating frequency of peripheral hardware may increase under some extreme conditions (such as low-temperature environments), directly using the lookup value may result in a frequency lower than the actual minimum frequency required by the peripheral, leading to the peripheral failing to function properly, such as timing errors in serial peripheral interface communication. Therefore, this application further performs a hard constraint verification on the retrieved minimum bus frequency to ensure it is not lower than the minimum operating frequency of the peripheral hardware, thereby meeting the hard operating requirements of the peripheral. This completely avoids peripheral failures caused by insufficient bus frequency, ensures the stability of the transmission subsystem under extreme conditions, and does not increase power consumption excessively, only taking the minimum frequency that meets the hard constraint, balancing stability and low power consumption requirements.

[0070] Specifically, in one possible embodiment, step S422 is implemented as follows: First, the minimum hardware operating frequency of the currently associated peripheral is read from the microcontroller's peripheral configuration register. This value is preset according to the peripheral manual during system initialization, such as the minimum hardware frequency of serial peripheral interface 1 being 16MHz. Next, the minimum required bus frequency (e.g., 20MHz) retrieved from the load profile lookup table is compared with the minimum hardware frequency. If the lookup value is greater than or equal to the minimum hardware frequency, the lookup value is directly used as the predicted required bus / peripheral frequency; if the lookup value is less than the minimum hardware frequency, such as a lookup value of 12MHz and a minimum hardware frequency of 16MHz, the minimum hardware frequency is used as the final frequency. Finally, the determined bus / peripheral frequency is temporarily stored in the data buffer of the global arbitration module as the frequency requirement input on the bus side, avoiding the risk of timing or voltage mismatch caused by unilateral frequency adjustment.

[0071] In the aforementioned MCU dynamic power consumption adjustment method based on load prediction, step S5 involves global constraint arbitration and energy efficiency optimization of the predicted CPU clock frequency and the predicted bus / peripheral frequency to obtain control instructions containing target voltage and target frequency. It should be understood that since the predicted CPU clock frequency and bus / peripheral frequency may conflict—for example, the CPU needs to operate at a low frequency but the bus needs a high frequency to ensure transmission, and the voltage needs to be strictly matched with the frequency—if the voltage is not adjusted synchronously when the frequency increases, it will lead to hardware failure; if the voltage is too high when the frequency decreases, it will waste power. If the original predicted values ​​of both are directly used, it will cause hardware instability or energy efficiency imbalance. Therefore, this application further performs global constraint arbitration on the two types of frequencies to determine a compatible target frequency, and then matches the target voltage with the principle of optimal energy efficiency to generate hardware-executable control instructions. This completely solves the frequency conflict problem, ensures timing coordination between the CPU and the bus / peripheral, and achieves the best balance between system energy efficiency and operational stability through optimal matching of voltage and frequency.

[0072] Specifically, in one possible embodiment, step S5 is implemented as follows: First, the bus control module is invoked to read the microcontroller's bus architecture parameters, such as the division coefficients of the high-speed clock and peripheral bus, and the predicted bus / peripheral frequency is converted into the minimum requirement for the high-speed clock. Next, this requirement is compared with the predicted CPU frequency, and the maximum value of the two is taken as the target frequency, ensuring that both CPU computation and bus transmission requirements are met simultaneously. Then, the operating performance point table (which stores the minimum stable voltage corresponding to different frequencies) is loaded from flash memory, and the matching minimum target voltage is obtained by querying based on the target frequency. Next, the voltage detection module is invoked to verify whether the target voltage is within the hardware support range, such as 1.2V-3.3V; if it exceeds this range, it is adjusted to the nearest valid value. Finally, the target voltage and target frequency are encapsulated into a control instruction in a fixed format of voltage value, frequency value, and effective timing, and written into the control register of the power management module to trigger subsequent hardware adjustment actions.

[0073] In summary, the MCU dynamic power consumption adjustment method based on load prediction, as described in this application, is explained. First, it acquires raw event records including interrupt vector numbers and timestamps, and performs deep filtering and feature extraction on the event stream to construct a state vector representing the system's current operating mode. Then, a sparse Markov chain model is introduced to probabilistically predict the state vector, inferring the most likely system state at the next moment, and independently parses the CPU clock frequency and bus / peripheral frequency requirements through a dual-track mapping mechanism. Furthermore, combined with global hardware constraints, arbitration and energy efficiency optimization are performed on the two types of frequency requirements to generate precise control instructions containing target voltage and frequency. This enables precise dual-track coordinated control of CPU computing and peripheral communication loads, thereby significantly improving the operational stability and energy efficiency of the MCU system under complex operating conditions.

[0074] Figure 8 This is a block diagram of a load-prediction-based dynamic power consumption regulation system for an MCU according to an embodiment of this application. Figure 8As shown, the MCU dynamic power consumption adjustment system 100 based on load prediction according to an embodiment of this application includes: an event record acquisition module 110, used to acquire original event records, the original event records including the original interrupt vector number, the timestamp when entering the interrupt, and the timestamp when exiting the interrupt; a filtering and feature extraction module 120, used to filter and extract features from the original event records to obtain the current state vector, the current state vector including the discretized interrupt ID and the quantized time level; a next state prediction module 130, used to perform next state prediction based on a sparse Markov chain on the current state vector to obtain the predicted most likely state vector at the next moment; a dual-track load demand mapping module 140, used to perform dual-track load demand mapping on the predicted most likely state vector at the next moment to obtain the CPU clock frequency and the bus / peripheral frequency required for prediction; and a constraint arbitration and optimization module 150, used to perform global constraint arbitration and energy efficiency optimization on the predicted CPU clock frequency and the predicted bus / peripheral frequency to obtain control instructions including target voltage and target frequency.

[0075] As described above, the load prediction-based MCU dynamic power consumption adjustment system 100 according to the embodiments of this application can be implemented in various wireless terminals, such as servers with a load prediction-based MCU dynamic power consumption adjustment algorithm. In one possible implementation, the load prediction-based MCU dynamic power consumption adjustment system 100 according to the embodiments of this application can be integrated into the wireless terminal as a software module and / or a hardware module. For example, the load prediction-based MCU dynamic power consumption adjustment system 100 can be a software module in the operating system of the wireless terminal, or it can be an application developed for the wireless terminal; of course, the load prediction-based MCU dynamic power consumption adjustment system 100 can also be one of many hardware modules of the wireless terminal.

[0076] Alternatively, in another example, the load prediction-based MCU dynamic power consumption regulation system 100 and the wireless terminal can also be separate devices, and the load prediction-based MCU dynamic power consumption regulation system 100 can be connected to the wireless terminal via wired and / or wireless networks, and transmit interactive information in accordance with an agreed data format.

[0077] Here, those skilled in the art will understand that the specific operations of each step in the above-described load prediction-based MCU dynamic power consumption regulation system have been referenced above. Figures 1 to 7 The method for dynamic power consumption regulation of MCUs based on load prediction has been described in detail, and therefore its repeated description will be omitted.

Claims

1. A method for dynamic power consumption adjustment of an MCU based on load prediction, characterized in that, include: Obtain the original event record, which includes the original interrupt vector number, the timestamp when entering the interrupt, and the timestamp when exiting the interrupt; The original event records are filtered and feature extracted to obtain the state vector at the current moment. The state vector at the current moment includes the discretized interrupt ID and the quantized time level. The next state is predicted based on a sparse Markov chain from the current state vector to obtain the most likely state vector at the next moment. A dual-track load demand mapping is performed on the most likely state vector for the next predicted moment to obtain the CPU clock frequency and bus / peripheral frequency required for the prediction. Global constraint arbitration and energy efficiency optimization are performed on the predicted CPU clock frequency and the predicted bus / peripheral frequency to obtain control instructions containing the target voltage and target frequency.

2. The MCU dynamic power consumption adjustment method based on load prediction according to claim 1, characterized in that, The original event logs are filtered and feature extracted to obtain the current state vector. The current state vector includes a discretized interrupt ID and a quantized time level, including: The original event records are filtered based on the interruption filter mask to determine whether to filter the original event records. In response to the fact that the original event record is not marked in the interrupt filter mask, the time interval from the last valid interrupt trigger is calculated based on the timestamp when entering the interrupt and the timestamp when exiting the interrupt; The time interval since the last valid interrupt is quantized to obtain the quantized time level; Set the original interrupt vector number to the discretized interrupt ID.

3. The MCU dynamic power consumption adjustment method based on load prediction according to claim 1, characterized in that, The process of predicting the next state of the current state vector based on a sparse Markov chain to obtain the predicted most likely state vector at the next moment includes: based on the state transition probability matrix, retrieving and predicting the next state probability distribution of the current state to obtain the predicted most likely state vector at the next moment.

4. The MCU dynamic power consumption adjustment method based on load prediction according to claim 3, characterized in that, Based on the state transition probability matrix, the current state vector is used to retrieve and predict the next state probability distribution based on the current state to obtain the predicted most likely state vector for the next time step, including: Using the current state vector as the row index, query the state transition probability matrix to obtain a list of temporary probability distributions; The list of temporary probability distributions is selected by maximum likelihood estimation to obtain the most likely state vector for the next time step of the prediction.

5. The MCU dynamic power consumption adjustment method based on load prediction according to claim 1, characterized in that, A dual-track load demand mapping is performed on the most likely state vector for the predicted next time step to obtain the predicted CPU clock speed and the predicted bus / peripheral frequency, including: The most likely state vector at the next predicted moment is mapped to the computational load demand based on the predicted event to obtain the CPU frequency required for the prediction. The most likely state vector for the next predicted moment is mapped to the transmission bandwidth requirement based on the predicted event to obtain the bus / peripheral frequency required for the prediction.

6. The MCU dynamic power consumption adjustment method based on load prediction according to claim 5, characterized in that, The most likely state vector at the predicted next moment is mapped to the computational load demand based on the predicted event to obtain the CPU frequency required for the prediction, including: Using the predicted state vector most likely to occur in the next moment as an index, a lookup table in the pre-set load profile is used to obtain the CPU frequency baseline value. The CPU clock speed baseline value is dynamically corrected using the following formula to obtain the predicted CPU clock speed: in, The historical average execution time This is the baseline value for CPU clock speed. As the baseline execution time, As an adaptive adjustment factor, This refers to the CPU clock speed.

7. The MCU dynamic power consumption adjustment method based on load prediction according to claim 5, characterized in that, The predicted transmission bandwidth requirement is mapped based on the predicted event to the most likely state vector at the next predicted moment to obtain the predicted bus / peripheral frequency, including: Using the predicted state vector of the next moment as an index, a lookup table in the pre-set load profile is used to obtain the minimum required bus frequency. A hard constraint is applied to the minimum required bus frequency to obtain the predicted required bus / peripheral frequency.

8. The MCU dynamic power consumption adjustment method based on load prediction according to claim 3, characterized in that, Also includes: After observing the actual state transition, the state transition probability matrix is ​​updated online based on a dynamically adaptive forgetting factor; The value of the forgetting factor is associated with the critical difference between the predicted event corresponding to the most likely state vector in the next moment and the actual event corresponding to the actual state; the criticality of the event is quantified by the computational load requirement and / or transmission bandwidth requirement of the event.

9. The MCU dynamic power consumption adjustment method based on load prediction according to claim 8, characterized in that, include: The greater the critical difference between the predicted event and the actual event, the smaller the value of the forgetting factor, in order to accelerate the learning and correction of the state transition probability matrix; The smaller the critical difference between the predicted event and the actual event, the larger the value of the forgetting factor, in order to maintain the stability of the state transition probability matrix.

10. A dynamic power consumption regulation system for MCUs based on load prediction, characterized in that, include: The event log acquisition module is used to acquire the original event log, which includes the original interrupt vector number, the timestamp when entering the interrupt, and the timestamp when exiting the interrupt; The filtering and feature extraction module is used to filter and extract features from the original event records to obtain the current state vector, which includes the discretized interrupt ID and the quantized time level. The next state prediction module is used to predict the next state of the current state vector based on a sparse Markov chain to obtain the predicted most likely state vector for the next moment. The dual-track load demand mapping module is used to perform dual-track load demand mapping on the most likely state vector in the next predicted moment to obtain the CPU frequency and bus / peripheral frequency required for prediction. The constraint arbitration and optimization module is used to perform global constraint arbitration and energy efficiency optimization on the predicted required CPU clock frequency and the predicted required bus / peripheral frequency to obtain control instructions containing target voltage and target frequency.

Images