Four-way CoaXPress data receiving and storing system and method based on double NVMe SSD disks

Abstract

The invention provides a four-way CoaXPress data receiving and storing system and method based on double NVMe SSD disks, and belongs to the technical field of remote sensing satellite testing. The invention aims to solve the problems of bandwidth bottleneck, complex system and high load of a host CPU (Central Processing Unit) in the traditional scheme based on the PXIe bus. The system comprises a four-way CoaXPress interface module, an FPGA (Field Programmable Gate Array) main controller, a DDR4 (Double Data Rate 4) cache module and a double NVMe SSD (Non-Volatile Memory Express Solid State Disk) storage The SSD is directly controlled through the FPGA, an RAID 0 mode can be configured, a hardware-level parallel write-in channel is constructed, the aggregation storage bandwidth far exceeds that of a traditional scheme that the storage bandwidth is forwarded to a hard disk through a PXIe bus and a host CPU, and the high-bandwidth data throughput requirement of a four-way CoaXPress interface can be easily met.

Description

Technical Field

[0001] This invention relates to a four-channel CoaXPress data receiving and storage system and method based on dual NVMe SSDs, belonging to the field of remote sensing satellite testing technology. Background Technology

[0002] In recent years, satellite remote sensing technology has been continuously developing towards high-resolution, wide-swath imaging and high-speed data transmission. To effectively simulate the working state of real payloads and data transmission links in ground testing, joint testing is usually conducted using camera data simulation systems. However, with the rapid increase in the amount of remote sensing payload data, especially the widespread application of ultra-high-speed interfaces such as CoaXPress, higher demands are placed on the efficiency and stability of real-time data storage and test analysis.

[0003] The currently widely adopted CoaXPress data persistence solution involves receiving data via an FPGA, buffering it in onboard DDR4 memory, and then transmitting it to the controller chassis for storage processing via the PXIe bus. While this solution meets basic requirements at lower data rates, its limitations become increasingly apparent as CoaXPress transmission rates continue to increase: 1. Excessive reliance on host performance: Real-time high-speed data reception and processing place extremely high demands on the PXIe bandwidth and computing power of the controller chassis, requiring a high-performance host, which significantly increases system hardware costs with increasing data rates; 2. Limited scalability: Existing architectures struggle to support multiple, higher-speed CoaXPress data streams without upgrading the core host, resulting in insufficient overall system scalability. Summary of the Invention

[0004] To address the bandwidth bottlenecks, system complexity, and high host CPU load issues inherent in traditional PXIe bus-based solutions, this invention proposes a four-channel CoaXPress data receiving and storage system and method based on dual NVMe SSDs.

[0005] The technical solution adopted by this invention to solve the above problems is: the four-way CoaXPress data receiving and storage system based on dual NVMe SSDs proposed in this invention includes: The four-channel CoaXPress interface module is used to receive image data streams and transmit them to the FPGA main controller. The FPGA main controller has a built-in NVMe controller IP core. The input of the FPGA main controller is connected to four CoaXPress interface modules, and the output is connected to the input of the DDR4 high-speed cache module. It is responsible for receiving, caching, managing and controlling the storage of image data. DDR4 cache module, used for temporary caching of image data; The dual NVMe SSD storage module is activated by the NVMe controller IP core when the temporary cache amount of the DDR4 cache module reaches the trigger condition. It reads image data from the DDR4 cache module and finally stores it in the dual NVMe SSD storage module. The dual NVMe SSD storage module supports high bandwidth and low latency data writing.

[0006] Furthermore, the four-way CoaXPress interface module includes four branches; The first branch includes BNC connector 1 and CXP receiver chip 1; the second branch includes BNC connector 2 and CXP receiver chip 2; the third branch includes BNC connector 3 and CXP receiver chip 3; and the fourth branch includes BNC connector 4 and CXP receiver chip 4. BNC connectors 1, 2, 3, and 4 are used to receive high-speed image data streams from the CoaXPress camera. CXP receiver chips 1, 2, 3, and 4 are used to convert the image data streams received by the BNC connectors of the corresponding branches and transmit the converted data from each branch to the FPGA main controller.

[0007] Furthermore, the FPGA main controller includes: a data receiving and scheduling module, a working status monitoring module, an NVMe controller IP core, and a disk write control module; The data receiving and scheduling module is used to parse the converted data of the corresponding branch and send it to the DDR4 cache module.

[0008] Furthermore, the DDR4 cache module includes a first DDR4 cache branch, a second DDR4 cache branch, a third DDR4 cache branch, and a fourth DDR4 cache branch; the first DDR4 cache branch is used to temporarily cache the parsed data of the first branch, the second DDR4 cache branch is used to temporarily cache the parsed data of the second branch, the third DDR4 cache branch is used to temporarily cache the parsed data of the third branch, and the fourth DDR4 cache branch is used to temporarily cache the parsed data of the fourth branch.

[0009] Furthermore, the dual NVMe SSD storage module includes M.2 SSD 1 and M.2 SSD 2; M.2 SSD 1 stores parsed data of the first DDR4 cache branch and the second DDR4 cache branch under the modulation of the NVMe controller IP core; M.2 SSD 2 stores parsed data of the third DDR4 cache branch and the fourth DDR4 cache branch under the modulation of the NVMe controller IP core. Both M.2 SSD 1 and M.2 SSD 2 have a BAR register and a Command register. The BAR register is used to specify the address resources of the PCIe configuration space of the corresponding M.2 SSD, and the Command register is used to pass the instructions of the NVMe controller IP core.

[0010] Furthermore, the working status monitoring module is used to monitor the data storage status of the first DDR4 cache branch and the second DDR4 cache branch, and the third DDR4 cache branch and the fourth DDR4 cache branch in the DDR4 cache module. When the total memory of parsed data cached by the first DDR4 cache branch and the second DDR4 cache branch reaches 32MB or the total memory of parsed data cached by the third DDR4 cache branch and the fourth DDR4 cache branch reaches 32MB, the NVMe controller IP core is triggered. After the NVMe controller IP core is triggered, if the parsed data memory of the temporary cache in either the first DDR4 cache branch or the second DDR4 cache branch reaches 32MB, the temporary cache data of the cache branch with 32MB of memory is stored in the M.2 SSD 1 through the disk write control module. If the temporary cache data in both the first DDR4 cache branch and the second DDR4 cache branch reaches 32MB at the same time, the temporary cache data of the first DDR4 cache branch is first stored in the M.2 SSD 1 through the disk write control module, and then the temporary cache data in the second DDR4 cache branch is stored in the M.2 SSD 1. If the parsed data of the temporary cache in either the third or fourth DDR4 cache branch reaches 32MB, then the temporary cache data of the cache branch with 32MB of memory is stored in the M.2 SSD 2 through the disk write control module; if the temporary cache data in both the third and fourth DDR4 cache branches reaches 32MB simultaneously, then the temporary cache data of the third DDR4 cache branch is first stored in the M.2 SSD 2 through the disk write control module, and then the temporary cache data of the fourth DDR4 cache branch is stored in the M.2 SSD 2.

[0011] Furthermore, the FPGA main controller is also connected to a clock module and a power module, and the FPGA main controller is also bidirectionally connected to the PXIe interface. The clock module is used to provide a precise time reference signal for the FPGA main controller; The power module provides stable power to the FPGA main controller, four CoaXPress interface modules, DDR4 high-speed cache module, and dual NVMe SSD storage modules. The PXIe interface is used to receive signals from the disk write control module and transmit the parsed data to the dual NVMe SSD storage modules for storage. The PXIe interface also serves as a peripheral interface to connect to external devices.

[0012] A four-way CoaXPress data receiving and storage method based on dual NVMe SSDs includes: Step 1: Configure the BAR and Command registers of the PCIe configuration space for M.2 SSD 1 and M.2 SSD 2 via the NVMe controller IP core; Step 2: After configuration, initialize the dual NVMe SSD storage modules through the NVMe controller IP core, create an ADMIN queue, submit the ADMIN command, and obtain the relevant parameters of M.2 SSD 1 and M.2 SSD 2; Step 3: After obtaining the relevant parameters, the NVMe controller IP core creates an IO queue; Step 4: The FPGA main controller sends a data receiving command to the four CoaXPress interface modules, and the four CoaXPress interface modules begin to receive image data and perform data conversion; Step 5: The converted data is parsed by the data receiving and scheduling module, and the parsed data of the corresponding branch is received by the DDR4 high-speed cache module; Step 6: When the data in the corresponding cache branch of the DDR4 cache module reaches 32MB, the NVMe controller IP core calls and stores it in the dual NVMe SSD storage module. The NVMe controller IP core generates a write command that conforms to the NVMe protocol according to the parameters called by the user and automatically submits the command to complete the data writing process. Step 7: Repeat step 6 to achieve real-time disk storage of multi-channel data.

[0013] Furthermore, step 6 specifically includes: For the first DDR4 cache branch and the second DDR4 cache branch, whenever the total memory of the parsed data in the temporary cache of one of the cache branches reaches 32MB, the NVMe controller IP core is called to write the parsed data of the temporary cache of the corresponding cache branch to M.2 SSD 1; if the temporary cache data in the first DDR4 cache branch and the second DDR4 cache branch both reach 32MB, the disk write control module first stores the temporary cache data of the first DDR4 cache branch to M.2 SSD 1, and then stores the temporary cache data of the second DDR4 cache branch to M.2 SSD 1. For the third and fourth DDR4 cache branches, whenever the total memory of the parsed data in their temporary cache reaches 32MB, the NVMe controller IP core is called to write the parsed data of their temporary cache to M.2 SSD 2; if the temporary cache data in the third and fourth DDR4 cache branches reaches 32MB at the same time, the disk write control module first stores the temporary cache data of the third DDR4 cache branch to M.2 SSD 2, and then stores the temporary cache data of the fourth DDR4 cache branch to M.2 SSD 2. The NVMe controller IP core generates 64 write commands conforming to the NVMe protocol based on the parameters called by the user. Each command transmits 512KB of data and generates a PRP linked list corresponding to each command. The command is automatically submitted to complete the data write-to-disk process.

[0014] The beneficial effects of this invention are: 1. This invention directly controls dual NVMe SSDs via FPGA and can be configured in RAID 0 mode, constructing a hardware-level parallel write channel. The aggregated storage bandwidth far exceeds the traditional solution of forwarding to the hard drive via PXIe bus and then host CPU, and can easily meet the high bandwidth data throughput requirements of four CoaXPress interfaces.

[0015] 2. This invention effectively frees up host CPU resources and improves overall system efficiency. In traditional solutions, the host CPU is heavily involved in the handling of each frame of data, memory management, and the issuance of storage instructions, resulting in extremely high CPU load. In this invention, the host CPU only needs to perform initialization and stop control at the start and end of data acquisition. Throughout the entire data acquisition and storage process, the host CPU is almost completely uninvolved. This completely frees up host CPU resources, allowing the system to focus on data post-processing, display, or other computational tasks, significantly improving the overall efficiency of the entire computer system.

[0016] 3. This invention offers high flexibility and scalability, with the FPGA-based platform providing exceptional reconfigurability. By updating the internal logic design of the FPGA, it can flexibly adapt to CoaXPress cameras with different data specifications (such as resolution and frame rate) or support the expansion of more CoaXPress interfaces. Furthermore, the control strategies for NVMe SSDs (such as cache trigger thresholds and RAID modes) can also be adjusted through the FPGA logic, providing a level of flexibility unmatched by traditional fixed hardware solutions.

[0017] 4. The data receiving and storage system constructed by this invention has potential cost advantages. Although it uses high-performance FPGA and NVMe SSD, it reduces the performance requirements of the PXIe chassis. From the perspective of the entire system, this invention has a competitive advantage in total cost, providing users with a more cost-effective high-performance data storage solution. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the hardware structure of a four-way CoaXPress data receiving and storage system based on dual NVMe SSDs. Figure 2 This is a schematic diagram illustrating the workflow of a four-way CoaXPress data receiving and storage method based on dual NVMe SSDs. Figure 3 This is a schematic diagram of the workflow of an NVMe controller IP core. Detailed Implementation

[0019] Specific implementation method one: as follows Figure 1 As shown, the hardware structure of the four-way CoaXPress data receiving and storage system based on dual NVMe SSDs described in this embodiment includes: The system consists of four CoaXPress interface modules, an FPGA main controller, a DDR4 cache module, and dual NVMe SSD storage modules. The four CoaXPress interface modules receive image data streams and transmit them to the FPGA main controller. The FPGA main controller has a built-in NVMe controller IP core. Its inputs connect to the four CoaXPress interface modules, and its outputs are bidirectionally connected to the inputs of the DDR4 cache modules, handling image data reception, cache management, and storage control. The DDR4 cache module is used for temporary image data caching. The dual NVMe SSD storage modules support high-bandwidth, low-latency data writing.

[0020] like Figure 1As shown, the four-channel CoaXPress interface module includes four branches. The first branch includes a BNC connector 1 and a CXP receiver chip 1; the second branch includes a BNC connector 2 and a CXP receiver chip 2; the third branch includes a BNC connector 3 and a CXP receiver chip 3; and the fourth branch includes a BNC connector 4 and a CXP receiver chip 4. The BNC connectors 1, 2, 3, and 4 are used to receive high-speed image data streams from the CoaXPress camera. The CXP receiver chips 1, 2, 3, and 4 are used to convert the image data streams received by the BNC connectors of the corresponding branches and transmit the converted data from each branch to the FPGA main controller.

[0021] The FPGA main controller includes a data receiving and scheduling module, a working status monitoring module, an NVMe controller IP core, and a disk write control module. The data receiving and scheduling module parses the converted data from the corresponding branches and sends it to the DDR4 cache module. The working status monitoring module monitors the data storage status of the first and second DDR4 cache branches, and the third and fourth DDR4 cache branches within the DDR4 cache module. When the total memory of the parsed data cached in the first and second DDR4 cache branches reaches 32MB, or the total memory of the parsed data cached in the third and fourth DDR4 cache branches reaches 32MB, the NVMe controller IP core is triggered. After the NVMe controller IP core is triggered, if the temporary cached data memory of either the first or second DDR4 cache branch reaches 32MB, the temporary cached data of the cache branch with 32MB of memory is stored in the M.2 disk through the disk write control module. In SSD 1, if the temporary cache data in both the first and second DDR4 cache branches simultaneously reaches 32MB, the disk write control module first stores the temporary cache data of the first DDR4 cache branch to M.2 SSD 1, and then stores the temporary cache data of the second DDR4 cache branch to M.2 SSD 1. If the parsed data memory of the temporary cache in either the third or fourth DDR4 cache branch reaches 32MB, the temporary cache data of the cache branch with 32MB of memory is stored in M.2 SSD 2 through the disk write control module. If the temporary cache data in both the third and fourth DDR4 cache branches simultaneously reaches 32MB, the disk write control module first stores the temporary cache data of the third DDR4 cache branch to M.2 SSD 2, and then stores the temporary cache data of the fourth DDR4 cache branch to M.2 SSD 2.

[0022] Once the NVMe controller IP core is activated, it can directly read data from the aforementioned DDR4 cache and efficiently write the data to the dual NVMe SSDs via the PCIe bus, following the NVMe protocol.

[0023] The FPGA main controller is also connected to a clock module and a power module, and it is also bidirectionally connected to the PXIe interface. The clock module is used to provide a precise time reference signal for the FPGA main controller. The power module is used to provide stable power to the FPGA main controller, the four CoaXPress interface modules, the DDR4 high-speed cache module, and the dual NVMe SSD storage modules. The PXIe interface is used to receive signals from the disk write control module and transmit the parsed data to the dual NVMe SSD storage modules for storage. The PXIe interface also serves as a peripheral interface to connect to external devices.

[0024] This invention utilizes an FPGA-based platform with exceptional reconfigurability. By updating the internal logic design of the FPGA, it can flexibly adapt to CoaXPress cameras with different data specifications (such as resolution and frame rate) or support expansion of more CoaXPress interfaces. Furthermore, the control strategies for NVMe SSDs (such as cache trigger thresholds and RAID modes) can also be adjusted through the FPGA logic, providing a level of flexibility unmatched by traditional fixed hardware solutions.

[0025] The DDR4 cache module includes a first DDR4 cache branch, a second DDR4 cache branch, a third DDR4 cache branch, and a fourth DDR4 cache branch. The first DDR4 cache branch is used to temporarily cache the parsed data of the first branch, the second DDR4 cache branch is used to temporarily cache the parsed data of the second branch, the third DDR4 cache branch is used to temporarily cache the parsed data of the third branch, and the fourth DDR4 cache branch is used to temporarily cache the parsed data of the fourth branch.

[0026] The dual NVMe SSD storage module includes M.2 SSD 1 and M.2 SSD 2. Under the modulation of the NVMe controller IP core, M.2 SSD 1 stores parsed data of the first DDR4 cache branch and the temporary cache of the second DDR4 cache branch. Under the modulation of the NVMe controller IP core, M.2 SSD 2 stores parsed data of the third DDR4 cache branch and the temporary cache of the fourth DDR4 cache branch. Both M.2 SSD 1 and M.2 SSD 2 are equipped with a BAR register and a Command register. The BAR register is used to specify the address resources of the PCIe configuration space of the corresponding M.2 SSD, and the Command register is used to transmit the instructions of the NVMe controller IP core.

[0027] In summary, the key to the four-channel CoaXPress data receiving and storage system constructed in this invention lies in the optimization of the data path: the four-channel CoaXPress data no longer goes through a PXIe switch to be uploaded to the host memory and then scheduled by the host CPU to be written to the host's SSD. Instead, a "CoaXPress interface" is built inside the FPGA. DDR4 cache The NVMe SSD uses a direct path. This path is entirely controlled by FPGA hardware logic, bypassing the host CPU and operating system, which greatly reduces write latency and data transfer overhead.

[0028] Furthermore, the dual NVMe SSD storage module can be configured in RAID 0 mode and is managed collaboratively by the NVMe controller IP core within the FPGA. Data is written to the two hard drives in parallel, thereby aggregating the write bandwidth. Under the PCIe 3.0*4 link, the maximum storage bandwidth of the dual NVMe disks is 32Gbps, which meets the total bandwidth requirements of the four CoaXPress interfaces.

[0029] Specific Implementation Method Two: Combining Figure 2 and Figure 3 This embodiment will be described as follows: Figure 2 As shown in this embodiment, the four-way CoaXPress data receiving and storage method based on dual NVMe SSDs includes: S1: PCIe configuration space for dual NVMe SSD storage modules; like Figure 3 As shown, the BAR register and Command register of the PCIe configuration space of M.2 SSD 1 and M.2 SSD 2 are configured through the NVMe controller IP core.

[0030] S2: Initialization of dual NVMe SSD storage modules; After configuration, the dual NVMe SSD storage modules are initialized through the NVMe controller IP core, an ADMIN queue is created, the ADMIN command is submitted, and the relevant parameters of M.2 SSD 1 and M.2 SSD 2 are obtained.

[0031] S3: NVMe controller IP core creates an IO queue; The NVMe controller IP core creates an IO queue, waiting to execute subsequent read and write commands.

[0032] S4: A four-channel CoaXPress interface module for data reception and conversion; S5: The FPGA main controller performs data reception and temporary caching for the DDR4 high-speed cache module; The data receiving and scheduling module in the FPGA main controller parses the converted data and transmits the parsed data to the DDR4 cache module. The DDR4 cache module is partitioned to obtain four DDR4 cache branches. Each DDR4 cache branch corresponds to one branch in the CoaXPress interface module for temporary data caching.

[0033] S6: After caching to 32MB, the NVMe controller IP core calls to store the parsed data in the dual NVMe SSD storage modules, and generates a write command conforming to the NVMe protocol based on the parameters called by the user and automatically submits the command; For the first and second DDR4 cache branches, whenever the total memory of the parsed data in the temporary cache of either cache branch reaches 32MB, the NVMe controller IP core is invoked to write the parsed data of the corresponding cache branch's temporary cache to M.2 SSD 1. If the temporary cache data in both the first and second DDR4 cache branches simultaneously reaches 32MB, the disk write control module first stores the temporary cache data of the first DDR4 cache branch to M.2 SSD 1, and then stores the temporary cache data of the second DDR4 cache branch to M.2 SSD 1. For the third and fourth DDR4 cache branches, whenever the total memory of the parsed data in their temporary caches reaches 32MB, the NVMe controller IP core is invoked to write the parsed data of their temporary cache to M.2 SSD 1. In SSD 2, if the temporary cache data in the third and fourth DDR4 cache branches simultaneously reaches 32MB, the disk write control module first stores the temporary cache data of the third DDR4 cache branch to M.2 SSD 2, and then stores the temporary cache data of the fourth DDR4 cache branch to M.2 SSD 2. The NVMe controller IP core generates 64 write commands conforming to the NVMe protocol according to the parameters called by the user. Each command transmits 512KB of data, and generates a PRP linked list corresponding to each command, automatically submitting the commands and completing the data write process.

[0034] S7: Repeat S6 to achieve real-time disk storage and processing of multi-channel data.

[0035] In summary, this invention constructs a hardware-level parallel write channel by directly controlling dual NVMe SSDs (configurable to RAID 0 mode) through FPGA during data transmission and reception. The aggregated storage bandwidth far exceeds that of the traditional solution that forwards data to the hard drive via PXIe bus and then through the host CPU, and can easily meet the high bandwidth data throughput requirements of four CoaXPress interfaces.

[0036] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A four-channel CoaXPress data receiving and storage system based on dual NVMe SSDs, characterized in that, include: A four-channel CoaXPress interface module is used to receive image data streams and transmit the image data streams to the FPGA main controller. The FPGA main controller has a built-in NVMe controller IP core. The input of the FPGA main controller is connected to four CoaXPress interface modules, and the output is bidirectionally connected to the input of the DDR4 high-speed cache module. It is responsible for receiving, caching, managing and controlling the storage of image data. A DDR4 cache module, wherein the DDR4 cache module is used to temporarily cache image data; The dual NVMe SSD storage module is activated by the NVMe controller IP core when the temporary cache amount of the DDR4 cache module reaches the trigger condition. It reads image data from the DDR4 cache module and finally stores it in the dual NVMe SSD storage module. The dual NVMe SSD storage module supports high bandwidth and low latency data writing.

2. The four-channel CoaXPress data receiving and storage system based on dual NVMe SSDs according to claim 1, characterized in that, The four-way CoaXPress interface module includes four branches; The first branch includes BNC connector 1 and CXP receiver chip 1; the second branch includes BNC connector 2 and CXP receiver chip 2; the third branch includes BNC connector 3 and CXP receiver chip 3; and the fourth branch includes BNC connector 4 and CXP receiver chip 4. The BNC connectors 1, 2, 3, and 4 are used to receive high-speed image data streams from the CoaXPress camera. The CXP receiver chips 1, 2, 3, and 4 are used to convert the image data streams received by the BNC connectors of the corresponding branches and transmit the converted data from each branch to the FPGA main controller.

3. The four-channel CoaXPress data receiving and storage system based on dual NVMe SSDs according to claim 1, characterized in that, The FPGA main controller includes: a data receiving and scheduling module, a working status monitoring module, an NVMe controller IP core, and a disk write control module; The data receiving and scheduling module is used to parse the converted data of the corresponding branch and send it to the DDR4 cache module.

4. The four-channel CoaXPress data receiving and storage system based on dual NVMe SSDs according to claim 1, characterized in that, The DDR4 cache module includes a first DDR4 cache branch, a second DDR4 cache branch, a third DDR4 cache branch, and a fourth DDR4 cache branch; the first DDR4 cache branch is used to temporarily cache the parsed data of the first branch, the second DDR4 cache branch is used to temporarily cache the parsed data of the second branch, the third DDR4 cache branch is used to temporarily cache the parsed data of the third branch, and the fourth DDR4 cache branch is used to temporarily cache the parsed data of the fourth branch.

5. The four-channel CoaXPress data receiving and storage system based on dual NVMe SSDs according to claim 1, characterized in that, The dual NVMe SSD storage module includes an M.2 SSD 1 and an M.2 SSD 2; the M.2 SSD 1, under the modulation of the NVMe controller IP core, stores parsed data of the temporary cache of the first DDR4 cache branch and the second DDR4 cache branch; the M.2 SSD 2, under the modulation of the NVMe controller IP core, stores parsed data of the temporary cache of the third DDR4 cache branch and the fourth DDR4 cache branch. Both M.2 SSD 1 and M.2 SSD 2 have a BAR register and a Command register. The BAR register is used to specify the address resources of the PCIe configuration space of the corresponding M.2 SSD, and the Command register is used to pass the instructions of the NVMe controller IP core.

6. The four-channel CoaXPress data receiving and storage system based on dual NVMe SSDs according to claims 3-5, characterized in that, The working status monitoring module is used to monitor the data storage status of the first DDR4 cache branch and the second DDR4 cache branch, and the third DDR4 cache branch and the fourth DDR4 cache branch in the DDR4 cache module. When the parsed data memory cached by any cache branch in the first DDR4 cache branch and the second DDR4 cache branch reaches 32MB, or when the parsed data memory cached by any cache branch in the third DDR4 cache branch and the fourth DDR4 cache branch reaches 32MB, the NVMe controller IP core is triggered. After the NVMe controller IP core is triggered, if the parsed data memory of the temporary cache in either the first DDR4 cache branch or the second DDR4 cache branch reaches 32MB, the temporary cache data of the cache branch with 32MB of memory is stored in the M.2 SSD 1 through the disk write control module. If the temporary cache data in both the first DDR4 cache branch and the second DDR4 cache branch reaches 32MB at the same time, the temporary cache data of the first DDR4 cache branch is first stored in the M.2 SSD 1 through the disk write control module, and then the temporary cache data in the second DDR4 cache branch is stored in the M.2 SSD 1. If the parsed data of the temporary cache in either the third or fourth DDR4 cache branch reaches 32MB, then the temporary cache data of the cache branch with 32MB of memory is stored in the M.2 SSD 2 through the disk write control module; if the temporary cache data in both the third and fourth DDR4 cache branches reaches 32MB simultaneously, then the temporary cache data of the third DDR4 cache branch is first stored in the M.2 SSD 2 through the disk write control module, and then the temporary cache data of the fourth DDR4 cache branch is stored in the M.2 SSD 2.

7. The four-channel CoaXPress data receiving and storage system based on dual NVMe SSDs according to claim 1, characterized in that, The FPGA main controller is also connected to a clock module and a power module, and the FPGA main controller is also bidirectionally connected to the PXIe interface. The clock module is used to provide a precise time reference signal for the FPGA main controller; The power module is used to provide stable power to the FPGA main controller, the four CoaXPress interface modules, the DDR4 high-speed cache module and the dual NVMe SSD storage modules; The PXIe interface is used to receive signals from the disk write control module and transmit the parsed data to the dual NVMe SSD storage modules for storage. The PXIe interface also serves as a peripheral interface to connect to external devices.

8. A four-way CoaXPress data receiving and storage method based on dual NVMe SSDs, applied to the four-way CoaXPress data receiving and storage system based on dual NVMe SSDs as described in any one of claims 1-7, characterized in that, include: Step 1: Configure the BAR and Command registers of the PCIe configuration space for M.2 SSD 1 and M.2 SSD 2 via the NVMe controller IP core; Step 2: After configuration, initialize the dual NVMe SSD storage modules through the NVMe controller IP core, create an ADMIN queue, submit the ADMIN command, and obtain the relevant parameters of M.2 SSD 1 and M.2 SSD 2; Step 3: After obtaining the relevant parameters, the NVMe controller IP core creates an IO queue; Step 4: The FPGA main controller sends a data receiving command to the four CoaXPress interface modules, and the four CoaXPress interface modules begin to receive image data and perform data conversion; Step 5: The converted data is parsed by the data receiving and scheduling module, and the parsed data of the corresponding branch is received by the DDR4 high-speed cache module; Step 6: When the data in the corresponding cache branch of the DDR4 cache module reaches 32MB, the NVMe controller IP core calls and stores it in the dual NVMe SSD storage module. The NVMe controller IP core generates a write command that conforms to the NVMe protocol according to the parameters called by the user and automatically submits the command to complete the data writing process. Step 7: Repeat step 6 to achieve real-time disk storage of multi-channel data.

9. The four-channel CoaXPress data receiving and storage method based on dual NVMe SSDs according to claim 8, characterized in that, Step 6 specifically includes: For the first DDR4 cache branch and the second DDR4 cache branch, whenever the total memory of the parsed data in the temporary cache of one of the cache branches reaches 32MB, the NVMe controller IP core is called to write the parsed data of the temporary cache of the corresponding cache branch to M.2 SSD 1; if the temporary cache data in the first DDR4 cache branch and the second DDR4 cache branch both reach 32MB, the disk write control module first stores the temporary cache data of the first DDR4 cache branch to M.2 SSD 1, and then stores the temporary cache data of the second DDR4 cache branch to M.2 SSD 1. For the third and fourth DDR4 cache branches, whenever the total memory of the parsed data in their temporary cache reaches 32MB, the NVMe controller IP core is called to write the parsed data of their temporary cache to M.2 SSD 2; if the temporary cache data in the third and fourth DDR4 cache branches reaches 32MB at the same time, the disk write control module first stores the temporary cache data of the third DDR4 cache branch to M.2 SSD 2, and then stores the temporary cache data of the fourth DDR4 cache branch to M.2 SSD 2. The NVMe controller IP core generates 64 write commands conforming to the NVMe protocol based on the parameters called by the user. Each command transmits 512KB of data and generates a PRP linked list corresponding to each command. The command is automatically submitted to complete the data write-to-disk process.

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