Chip quantum random number extraction system based on silicon-based integrated photonics

Abstract

The invention provides a chip quantum random number extraction system based on silicon-based integrated photonics. The system adopts a modular design, a rear-end circuit is divided into a core module, a main control module, a data reading module, an auxiliary circuit module and a power supply module, all the modules are optimized cooperatively, and the stability of the system is improved; the system is based on a silicon-based photon integration technology, a quantum entropy source module, a detection module, an acquisition module and a post-processing module are fully integrated in a quantum random number generator chip, high miniaturization is realized, and the size is greatly reduced; in combination with a general SPI communication protocol, the system can adapt to various external devices, is compatible with various operating systems such as Windows and has high compatibility; the system supports the plug-and-play extraction of quantum random numbers, the extracted quantum random number sequence can pass 15 sub-tests in an NIST SP 800-22 statistical test packet and a K-S test of IBM SPSS Statistics, and the method has high randomness and high security, can be widely applied to multiple scenes such as cryptography and information security, and provides an efficient and safe solution for related fields.

Description

Technical Field

[0001] This invention relates to the field of quantum information technology, and in particular to a chip-based quantum random number extraction system based on silicon-based integrated photonics. Background Technology

[0002] In the digital age, information security has become a crucial cornerstone for national security, social stability, and economic development. From encrypted financial transactions and privacy protection in communications to blockchain consensus mechanisms, random numbers, as a fundamental resource in these critical areas, directly determine the system's resistance to attacks. Pseudo-random numbers generated based on deterministic algorithms such as RSA and ECC, while computationally efficient, are inherently periodic and vulnerable to the risks of algorithmic cracking posed by quantum computing. Random numbers generated using classical physical processes such as electronic thermal noise and oscillator jitter, while possessing high randomness, suffer from insufficient measurement precision of noise sources and are susceptible to environmental interference, making them difficult to maintain security under quantum technology attacks. The vulnerability of these two types of random number generation schemes to quantum attack models has seriously threatened the reliability of core cryptographic infrastructure. Therefore, developing more secure and reliable random number generation technologies is key to addressing the information security challenges of the quantum era.

[0003] Quantum random number generators (QRNGs) fundamentally address the security flaws of classical entropy sources by extracting the intrinsic randomness of quantum systems. Their randomness, based on the uncertainty principle and quantum state collapse in quantum mechanics, is unaffected by classical physical environments and cannot be reproduced or predicted by any classical computational methods. They can generate truly random numbers, thus becoming one of the core technologies for ensuring the security of information systems in the "post-quantum era." To adapt to post-quantum cryptography applications, the National Institute of Standards and Technology (NIST) in the United States developed the SP 800-90C standard, mandating the use of quantum-secure entropy sources in core cryptographic modules, further confirming the security and reliability of quantum random numbers. Currently, QRNGs have become a crucial cornerstone for high-security key distribution, digital identity authentication, and national cryptographic infrastructure, playing an irreplaceable role in scenarios such as quantum key distribution, quantum digital signatures, and secure multi-party computation.

[0004] Despite the significant advantages and application potential of QRNG, existing solutions have revealed numerous problems in practical applications. Some QRNG solutions rely on complex optical systems, resulting in bulky and complex devices that are difficult to integrate into miniaturized and portable electronic devices, limiting their large-scale application. Furthermore, the maintenance complexity of discrete devices and the overall upgrade cost further hinder the technology's implementation. The non-standardized interface designs of some QRNG solutions also make them difficult to widely apply in miniaturized scenarios such as mobile communications and IoT terminals. Against this backdrop, silicon-based integrated photonics technology, through CMOS-compatible processes, integrates discrete devices onto a single chip, providing a hardware foundation for the widespread deployment of quantum-safe infrastructure through high integration, small size, and high generation rates. Summary of the Invention

[0005] This section aims to elucidate the core technical features of the present invention and provide a technical overview. It should be noted that, to ensure the clarity and explicitness of the core technical direction, simplified descriptions or partial omissions of certain technical details may be used during the drafting of related technical documents. Such technical simplification is entirely based on the requirements of the technical document's standardized expression, and any adjustment to the technical description does not constitute a substantial limitation on the scope of protection of the present invention.

[0006] To address the shortcomings of existing technologies, this invention proposes a chip-based quantum random number extraction system based on silicon-based integrated photonics, aiming to solve the problem that existing quantum random number generators are limited in their large size and difficult integration, thus restricting their large-scale practical application.

[0007] The technical solution adopted in this invention is as follows: a chip-based quantum random number extraction system based on silicon-based integrated photonics, comprising:

[0008] The silicon-based integrated photonics chip quantum random number extraction system is designed with a functional modular approach, including: a core module, a main control module, a data reading module, an auxiliary circuit module, and a power supply module.

[0009] The core module is connected to the main control module; the main control module is connected to the data reading module, the auxiliary circuit module, and the power supply module; the power supply module is connected to the data reading module and the auxiliary circuit module.

[0010] The core module is responsible for generating high-quality quantum random numbers, the main control module is responsible for extracting and transmitting quantum random numbers, the data reading module is responsible for receiving data transmitted by the core module and interacting with external devices, the auxiliary circuit module is responsible for ensuring the stable operation of the system, performing initialization configuration and providing the clock reference required by the system, and the power supply module is responsible for providing stable voltage to each functional module.

[0011] As a chip-based quantum random number extraction system based on silicon-based integrated photonics as described in this invention, the core module includes: a first filter capacitor group and a QRNG chip;

[0012] The first group of filter capacitors is connected to the QRNG chip to reduce low-frequency ripple and ensure that the power module provides a clean and stable power supply to the QRNG chip, thus ensuring the stable operation of the QRNG chip.

[0013] The QRNG chip includes a quantum entropy source module, a detection module, a sampling module and a post-processing module connected in sequence. Each module is fully integrated into a single chip using silicon-based photonics technology.

[0014] The quantum entropy source module uses photons with random phase, frequency, and emission direction generated by amplifying spontaneous emission noise as the initial random source of the system; the detection module converts the optical signal of the initial random source generated by the quantum entropy source module into an electrical signal and linearly amplifies the converted electrical signal; the sampling module samples the linearly amplified electrical signal from the detection module; the post-processing module performs random distillation on the electrical signal sampled by the sampling module to eliminate the influence of classical noise and statistical bias, and finally outputs a high-quality quantum random number bit stream that conforms to a uniform distribution.

[0015] As a chip-based quantum random number extraction system based on silicon-based integrated photonics as described in this invention, the main control module includes: a second filter capacitor group and an STM32 main control chip;

[0016] The second group of filter capacitors is connected to the STM32 main control chip to reduce low-frequency ripple and ensure that the power module provides a clean and stable power supply to the STM32 main control chip, thus ensuring the stable operation of the extraction process.

[0017] The STM32 main control chip is connected to the QRNG chip and is used to send chip select signals, clock signals and other signals to the QRNG chip, thereby controlling the QRNG chip to generate quantum random numbers.

[0018] As a chip-based quantum random number extraction system based on silicon-based integrated photonics described in this invention, the data reading module includes: a first 220Ω current-limiting resistor, a second 220Ω current-limiting resistor, a USB interface, and a CH340N chip;

[0019] The first 220Ω current-limiting resistor is connected to the CH340N chip and the STM32 main control chip, and the second 220Ω current-limiting resistor is also connected to the CH340N chip and the STM32 main control chip; this achieves current-limiting protection to prevent damage to the CH340N chip and the STM32 main control chip.

[0020] The USB interface is connected to an external device, and the CH340N chip is connected to the STM32 host control chip to receive and send data to the STM32 host control chip. The CH340N chip is also connected to the USB interface to receive and send data to the USB interface, thereby completing data protocol conversion and enabling data transmission with external devices.

[0021] As a chip-based quantum random number extraction system based on silicon-based integrated photonics according to the present invention, the auxiliary circuit module includes: a clock circuit, a reset circuit, and a startup mode selection circuit;

[0022] The clock circuit includes: an 8MHz passive crystal oscillator, a 1MΩ bias resistor, a first 10pF capacitor, and a second 10pF capacitor; the first 10pF capacitor and the second 10pF capacitor are connected in series and then connected in parallel with the 8MHz passive crystal oscillator and the 1MΩ bias resistor to form a complete external clock resonant circuit; the clock circuit is connected to the STM32 main control chip to provide a stable external clock source for the STM32 main control chip;

[0023] The reset circuit includes a button and an RC circuit; the button is connected to the RC circuit to implement a manual reset function; the RC circuit is connected to the STM32 main control chip to implement an automatic reset function.

[0024] The startup mode selection circuit is connected to the STM32 main control chip and is used to switch the system startup mode to meet the startup requirements in different scenarios.

[0025] As a chip-based quantum random number extraction system based on silicon-based integrated photonics as described in this invention, the power supply module includes: a first linear voltage regulator branch, a second linear voltage regulator branch, and a Schottky diode;

[0026] The Schottky diode is connected to the USB interface to obtain a +5V voltage; the Schottky diode is connected to the first linear voltage regulator branch and the second linear voltage regulator branch respectively to cut off reverse current, which can effectively prevent current backflow caused by reverse power connection and avoid damage to internal components.

[0027] The first linear voltage regulator branch includes: a first linear regulator diode, a first front-end filter capacitor group, and a first back-end filter capacitor group; the second linear voltage regulator branch includes: a second linear regulator diode, a second front-end filter capacitor group, and a second front-end filter capacitor group.

[0028] The first front-end filter capacitor group is connected to the first linear regulator diode to filter out noise in the +5V input voltage; the first back-end filter capacitor group is connected to the first linear regulator diode to filter the output +3.3V voltage; the first linear regulator diode is connected to the first filter capacitor group of the core module for decoupling filtering, ultimately providing a stable and clean power supply for the QRNG chip;

[0029] The second front-end filter capacitor group is connected to the second linear regulator diode to filter out noise in the +5V input voltage; the second back-end filter capacitor group is connected to the second linear regulator diode to filter the output +3.3V voltage. The second linear regulator diode is connected to the second filter capacitor group of the main control module for decoupling filtering, ultimately providing a stable and clean power supply to the STM32 chip; the second linear regulator diode is connected to the CH340 chip, the reset circuit, and the startup mode selection circuit to supply power to the CH340 chip, the reset circuit, and the startup mode selection circuit.

[0030] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0031] This invention is based on silicon-based photonic integration technology, which integrates a quantum entropy source module, a detection module, a sampling module and a post-processing module into a microchip to achieve high integration and miniaturization.

[0032] This invention employs CMOS-compatible technology and fully integrated chip design to achieve large-scale chip production, significantly reducing manufacturing costs compared to traditional commercial equipment. This breaks down the high-cost barrier of quantum technology and promotes its industrialization.

[0033] This invention enables the generation and real-time transmission of highly secure and stable quantum random numbers in a very small package. The generated quantum random numbers can pass 15 subtests in the NIST SP 800-22 statistical test package and the KS test of IBM SPSS Statistics, demonstrating high randomness and high security.

[0034] This invention utilizes a modular back-end circuit design, dividing the system into a core module, a main control module, a data reading module, an auxiliary circuit module, and a power supply module based on their functions. Through the collaborative optimization of each module, the system's anti-interference capability is significantly improved, and signal crosstalk is reduced.

[0035] This invention uses a modular circuit design to optimize the data reading interface, achieving compatibility with external device interfaces such as 5G modules and mobile terminals, and solving the core pain point of physical connection compatibility.

[0036] This invention develops a core driver based on the general SPI communication protocol, and combines the cross-platform advantages of the C language, making it compatible with multiple mainstream operating systems such as Windows, Linux, and macOS, thus possessing high compatibility.

[0037] This invention achieves real-time quantum random number extraction at 7 Mbit / s by combining hardware timing control and software algorithm optimization. Attached Figure Description

[0038] To better illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings involved in the description of the embodiments will be briefly introduced below. It should be noted that the following drawings are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without creative effort. Specifically:

[0039] Figure 1 This is a hardware architecture connection diagram of a chip quantum random number extraction system based on silicon-based integrated photonics according to an embodiment of the present invention; Detailed Implementation

[0040] This invention proposes a chip-based quantum random number extraction system based on silicon-based integrated photonics. To make the objectives, technical solutions, and implementation details of this invention clearer, the following will describe the specific implementation of this invention in detail with reference to the accompanying drawings, by illustrating the hardware composition of the system, the serial port connection relationship of each component, and the complete data transmission process, so as to facilitate understanding and implementation by those skilled in the art.

[0041] While numerous specific details are set forth in the following description to facilitate a full understanding of the invention, the invention may also be implemented in other ways than those described herein. Those skilled in the art can make equivalent substitutions or modifications without departing from the spirit and scope of the invention; therefore, the invention is not limited to the specific embodiments disclosed below.

[0042] Example 1

[0043] Figure 1 This is a hardware architecture connection diagram of a silicon-based integrated photonics chip quantum random number extraction system according to an embodiment of the present invention, referring to... Figure 1 This is the first embodiment of the present invention, which provides a chip-based quantum random number extraction system based on silicon-based integrated photonics, comprising:

[0044] Core Module 1: QRNG chip 101, quantum entropy source module 1011, detection module 1012, sampling module 1013, post-processing module 1014, first filter capacitor group 102; Main Control Module 2: STM32 main control chip 201, second filter capacitor group 202; Data Reading Module 3: CH340N chip 301, USB interface 302, first 220Ω current limiting resistor 303, second 220Ω current limiting resistor 304; External Device 305; Auxiliary Circuit Module 4: Clock circuit 401, 8MHz passive crystal oscillator 4011, 1MΩ bias resistor 4012, first 10pF capacitor 4013, second 10pF capacitor... Capacitor 4014, reset circuit 402, button 4021, RC circuit 4022, start mode selection circuit 403, power module 5, first linear regulator branch 501, first linear regulator diode 5011, first front-end filter capacitor group 5012, first rear-end filter capacitor group 5013, second linear regulator branch 502, second linear regulator diode 5021, second front-end filter capacitor group 5022, second rear-end filter capacitor group 5023, Schottky diode 503;

[0045] The core module includes a QRNG chip 101 and a first filter capacitor group 102. The QRNG chip 101 includes a quantum entropy source module 1011, a detection module 1012, a sampling module 1013, and a post-processing module 1014. The main control module 2 includes an STM32 main control chip 201 and a second filter capacitor group 202. The data reading module 3 includes a CH340N chip 301, a USB interface 302, a first 220Ω current-limiting resistor 303, and a second 220Ω current-limiting resistor 304. The auxiliary circuit module 4 includes a clock circuit 401, a reset circuit 402, and a startup mode selection circuit 403. The clock circuit includes an 8MHz passive crystal oscillator 4011, a 1MΩ bias resistor 4012, a first 10pF capacitor 4013, and a second 10pF capacitor 4014. The capacitor 4014; the reset circuit includes a button 4021 and an RC circuit 4022; the power module 5 includes a first linear regulator branch 501, a second linear regulator branch 502, and a Schottky diode 503. The first linear regulator branch 501 includes a first linear regulator 5011, a first front-end filter capacitor group 5012, and a first back-end filter capacitor group 5013. The second linear regulator branch 502 includes a second linear regulator 5021, a second front-end filter capacitor group 5022, and a second front-end filter capacitor group 5023.

[0046] The quantum entropy source module 1011 is connected to the detection module 1012; the detection module 1012 is connected to the sampling module 1013; the sampling module 1013 is connected to the post-processing module 1014; the WAKEUP pin of the QRNG chip 101 is connected to PA9 of the STM32 main control chip 201; the Q_CS pin of the QRNG chip 101 is connected to PB12 of the STM32 main control chip 201; the Q_CLK pin of the QRNG chip 101 is connected to PB13 of the STM32 main control chip 201; the Q_DATA pin of the QRNG chip 101 is connected to PB14 of the STM32 main control chip 201; the VIN pin of the core module 1 is connected to the VOUT pin of the first linear regulator 5011 of the power supply module 5.

[0047] The STM32 main control chip 201 is connected to the second filter capacitor group 202; the PB1 pin of the STM32 main control chip 201 is connected to the VCC pin of the CH340N chip 301; the PB10 pin of the STM32 main control chip 201 is connected to the RXD pin of the CH340N chip 301; the PB11 pin of the STM32 main control chip 201 is connected to the TXD pin of the CH340N chip 301.

[0048] The CH340N chip 301 is connected to the USB interface 302; the VCC pin of the USB interface 302 is connected to the Schottky diode 503; the first 220Ω current-limiting resistor 303 is connected to the RXD pin of the CH340N chip 301 and the PB10 pin of the STM32 chip 201; the second 220Ω current-limiting resistor 304 is connected to the TXD pin of the CH340N chip 301 and the PB11 pin of the STM32 chip 201.

[0049] In the clock circuit 401, the first 10pF capacitor 4013 and the second 10pF capacitor 4014 are connected in series and then in parallel with the 8MHz passive crystal oscillator 4011 and the 1MΩ bias resistor 4012. One end of the parallel connection is connected to the OSC_IN pin of the STM32 main control chip 201, and the other end is connected to the OSC_OUT pin of the STM32 main control chip 201. In the reset circuit 402, the button 4021 is connected to the RC circuit 4022, and the RC circuit 4022 is connected to the NRST pin of the STM32 main control chip 201. The boot mode selection circuit 403 is connected to the BOOT0 and BOOT1 pins of the STM32 main control chip 201.

[0050] The VIN pin of the first linear Zener diode 5011 is connected to the VIN pin of the second linear Zener diode 5021, the Schottky diode 503, and the second front-end filter capacitor group 5022, respectively; the VOUT pin of the second linear Zener diode 5021 is connected to the second filter capacitor group 202 and the VCC pin of the CH340N chip 301 after filtering.

[0051] The core module 1 is responsible for generating high-quality quantum random numbers. Specifically, the quantum entropy source module 1011 generates the initial random number, and the detection module 1012 receives the initial random source optical signal generated by the quantum entropy source module 1011, performs photoelectric conversion and linear amplification on it, and transmits the generated amplified electrical signal to the sampling module 1013. The sampling module 1013 performs a sampling operation on the received amplified electrical signal and inputs the acquired sampling data to the post-processing module 1014. The post-processing module 1014 performs random distillation on the sampling electrical signal output by the sampling module 1013, eliminates classical noise interference and statistical bias through hash-type post-processing, and finally outputs a high-quality quantum random number bit stream conforming to a uniform distribution.

[0052] The STM32 main control chip 201 in the main control module 2 is based on a Cortex-M3 core and communicates with the core module 1 via the SPI communication protocol. Specifically, the PB12 pin of the STM32 main control chip 201 is connected to the Q_CS pin of the QRNG chip 101 to send a chip select signal to the QRNG chip 101; the PB13 pin of the STM32 main control chip 201 is connected to the Q_CLK pin of the QRNG chip 101 to send a clock signal to the QRNG chip 101; the PB14 pin of the STM32 main control chip 201 is connected to the Q_DATA pin of the QRNG chip 101 to receive data from the QRNG chip 101; and the PA9 pin of the STM32 main control chip 201 is connected to the WAKEUP pin of the QRNG chip 101 to select the QRNG chip. The sleep and wake-up states of chip 101 are controlled by the STM32 main control chip 201, which adjusts the PA9 pin level to synchronously control the WAKEUP pin level of QRNG chip 101. The second filter capacitor group 202 in the main control module 2 is used to reduce low-frequency ripple interference to ensure that the power supply module 5 provides a clean and stable power supply to the STM32 main control chip 201.

[0053] The data reading module 3 communicates with the main control module 2 via a serial port interface. The RXD pin of the CH340N chip 301 is connected to the PB10 pin of the STM32 main control chip 201 to receive quantum random numbers extracted by the STM32 main control chip 201 from the core module 1. The TXD pin of the CH340N chip 301 is connected to the PB11 pin of the STM32 main control chip 201 to receive data sent from the external device 305 to the STM32 main control chip 201. The RXD pin of the CH340N chip 301 is connected to a first 220Ω current-limiting resistor 303, and the TXD pin of the CH340N chip 301 is connected to a second 220Ω current-limiting resistor 304, thereby achieving current-limiting protection to prevent damage to the PB10 and PB11 pins of the STM32 main control chip 201.

[0054] The UD+ pin of the CH340N chip 301 is connected to the D+ pin of the USB interface 302, and the UD- pin of the CH340N chip 301 is connected to the D- pin of the USB interface 302, thereby realizing bidirectional conversion between the USB bus communication protocol and the TTL serial port communication protocol; the USB interface 302 is connected to the external device 305, establishing a data transmission channel between the main control module 2 and the external device 305, enabling the main control module 2 to send the extracted quantum random numbers to the external device 305.

[0055] The clock circuit 401 of the auxiliary circuit module 4 uses an 8MHz passive crystal oscillator 4011 as the clock source to provide a stable external clock source for the STM32 main control chip 201. The two ends of the 8MHz passive crystal oscillator 4011 are respectively connected to the OSC_IN pin and OSC_OUT pin of the STM32 main control chip 201; the 1MΩ bias resistor 4012 is connected in parallel across the 8MHz passive crystal oscillator 4011 to provide the oscillation bias condition; the first 10pF capacitor 4013 and the second 10pF capacitor 4014 are respectively connected between the two ends of the 8MHz passive crystal oscillator 4011 and ground, thus forming a complete external clock resonant circuit.

[0056] The reset circuit 402 of the auxiliary circuit module 4 includes an RC circuit 4022 and a button 4021. The RC circuit 4022 is connected to the NRST pin of the STM32 main control chip 201 to realize the automatic reset function. When the system is powered on, the RC circuit 4022 generates a reset signal to the NRST pin, so that the program is restored to the initial state. The button 4021 is connected to the RC circuit 4022 to realize the manual reset function. When the button 4021 is pressed, it can pull the NRST pin of the STM32 main control chip 201 low to a low level, thereby realizing the manual reset.

[0057] The startup mode selection circuit 403 of the auxiliary circuit module 4 is used to switch the system startup mode to meet the startup requirements in different scenarios; by adjusting the level states of the BOOT0 and BOOT1 pins, the startup mode of the STM32 main control chip 201 is selected.

[0058] The power module 5 adopts a dual-path independent power supply architecture to power each module of the system. Its core components include a first linear regulator 5011, a second linear regulator 5021, and a Schottky diode 503. The Schottky diode 503 is connected to the VIN pin of the first linear regulator 5011 and the VIN pin of the second linear regulator 5021, respectively, to cut off reverse current, effectively preventing current backflow caused by reverse power connection and avoiding damage to internal components. The Schottky diode 503 is connected to the VCC pin of the USB interface 302 to obtain a +5V voltage. This +5V input voltage is split and enters the first linear regulator branch 501 and the second linear regulator branch 502 respectively. After being stepped down and regulated by the linear regulator, it outputs a +3.3V operating voltage.

[0059] The first linear regulator branch 501 consists of a first linear regulator 5011, a first front-end filter capacitor group 5012, and a first back-end filter capacitor group 5013. The first front-end filter capacitor group 5012 is connected in parallel to the VIN pin of the first linear regulator 5011 to filter out noise in the +5V input voltage. The first back-end filter capacitor group 5013 is connected in parallel to the VOUT pin of the first linear regulator 5011 to filter the output +3.3V voltage. This +3.3V voltage is then decoupled and filtered by the first filter capacitor group 102, ultimately providing a stable and clean power supply to the VIN pin of the core module 1.

[0060] The second linear regulator branch 502 consists of a second linear regulator 5021, a second front-end filter capacitor group 5022, and a second back-end filter capacitor group 5023. The second front-end filter capacitor group 5022 is connected in parallel to the VIN pin of the second linear regulator 5021 to filter out noise in the +5V input voltage. The second back-end filter capacitor group 5023 is connected in parallel to the VOUT pin of the second linear regulator 5021 to filter the output +3.3V voltage. The filtered +3.3V voltage directly powers the VCC pin of the CH340N chip 301, the reset circuit 402, and the startup mode selection circuit 403. Simultaneously, this +3.3V voltage undergoes final decoupling filtering via the second filter capacitor group 202, providing a stable and clean power supply to the PB1 pin of the STM32 main control chip 201.

[0061] Example 2

[0062] Referring to the following steps, the second embodiment of the present invention describes in detail the complete process of system data transmission, including: instruction receiving stage, device control stage, data acquisition stage, and data verification and transmission.

[0063] S1. Command Reception Phase: After the system powers on, the STM32 main control chip enters the initialization process, completing the following operations: configuring BOOT0 and BOOT1 to boot from main flash memory; initializing peripheral resources, including GPIO, SPI2, USART3, and the interrupt vector table; setting default status parameters to ensure the system is in standby mode. The STM32 main control chip then enters serial port listening mode, waiting for valid control commands to be sent from the outside. The command adopts the standard frame structure [0xAA][command][parameter][0xFF], specifically including: frame header identifier (0xAA), used to identify the start of the command; command field, indicating the operation type such as start acquisition, control wake-up, and chip select setting; parameter field, for passing control parameters, such as acquisition length or control signal value; frame tail identifier (0xFF), used for command end determination. When the command is completely received, the STM32 main control chip will parse the fields and enter the corresponding execution process.

[0064] S2. Device Control Phase: Based on the instruction parsing results, the STM32 master control chip controls the operating state of the QRNG chip, specifically including: wake-up control: if the PB14 pin changes from low to high, a wake-up signal is sent to the QRNG chip to put it into working state; otherwise, it remains in sleep mode to save energy. Chip select control: by controlling the state of the PB12 pin, the chip select signal is pulled low or high to start or stop SPI data communication. Output enable control: if the PA8 pin is high, the QRNG chip starts outputting random data; to ensure data security, the QRNG chip stops outputting when the PA pin is low. Clock control: the STM32 master control chip provides the SCK clock signal to the QRNG chip through the PB13 pin and receives the Q_DATA signal from the QRNG chip through the PB14 pin, thereby achieving effective synchronization.

[0065] S3. Data Acquisition Phase: After the STM32 master control chip receives the data acquisition command, the system begins to continuously read random numbers from the QRNG chip via the SPI interface. The specific acquisition process is as follows: SPI initialization: Configure the SPI bus to working mode 0. The STM32 master control chip, acting as the master device, sends a clock signal, and the QRNG chip, acting as the slave device, returns data. Configure the communication rate: Set the SPI clock division to achieve a stable transmission rate of approximately 281.25 kbps. Data buffering: Store every 1024 bytes received into the internal buffer. Interrupt scheduling or polling: Determine if the preset data volume has been reached. Automatic reloading: Automatically end the current acquisition round and proceed to the next phase after reaching the acquisition limit.

[0066] S4. Data Verification and Transmission Phase: After data acquisition, the system performs data verification and serial port transmission. The specific process is as follows: Data Verification: Redundancy verification or marking checks are performed on each segment of buffered data. If a transmission error is found, an error message such as "read failed" is output through the USART interface; Format Encapsulation: Valid data is encapsulated according to the frame format specified by the application layer, including start bit, data bits, parity bits, etc.; Serial Port Transmission: The encapsulated data is transmitted to the external device through the USART interface at a baud rate of 256000bps; Status Reporting: Each data segment is accompanied by a status flag or end flag to ensure correct parsing by the external device.

[0067] The scope of protection of this technology includes, but is not limited to, the above embodiments. The scope of protection of this technology is defined by the claims. Any substitutions, modifications, or improvements to this technology that are easily conceived by those skilled in the art shall fall within the scope of protection of this technology.

Claims

1. A chip-based quantum random number extraction system based on silicon-based integrated photonics, characterized in that, include: The silicon-based integrated photonics chip quantum random number extraction system is designed with a functional modular approach, including: a core module, a main control module, a data reading module, an auxiliary circuit module, and a power supply module. The core module is connected to the main control module; the main control module is connected to the data reading module, the auxiliary circuit module, and the power supply module; the power supply module is connected to the data reading module and the auxiliary circuit module. The core module is responsible for generating high-quality quantum random numbers, the main control module is responsible for extracting and transmitting quantum random numbers, the data reading module is responsible for receiving data transmitted by the core module and interacting with external devices, the auxiliary circuit module is responsible for ensuring the stable operation of the system, performing initialization configuration and providing the clock reference required by the system, and the power supply module is responsible for providing stable voltage to each functional module.

2. The chip-based quantum random number extraction system based on silicon-based integrated photonics as described in claim 1, characterized in that, The core module includes: a first filter capacitor group and a QRNG chip; The first group of filter capacitors is connected to the QRNG chip to reduce low-frequency ripple and ensure that the power module provides a clean and stable power supply to the QRNG chip, thus ensuring the stable operation of the QRNG chip. The QRNG chip includes a quantum entropy source module, a detection module, a sampling module and a post-processing module connected in sequence. Each module is fully integrated into a single chip using silicon-based photonics technology. The quantum entropy source module uses photons with random phase, frequency, and emission direction generated by amplifying spontaneous emission noise as the initial random source of the system; the detection module converts the optical signal of the initial random source generated by the quantum entropy source module into an electrical signal and linearly amplifies the converted electrical signal; the sampling module samples the linearly amplified electrical signal from the detection module; the post-processing module performs random distillation on the electrical signal sampled by the sampling module to eliminate the influence of classical noise and statistical bias, and finally outputs a high-quality quantum random number bit stream that conforms to a uniform distribution.

3. The chip-based quantum random number extraction system based on silicon-based integrated photonics as described in claim 1, characterized in that, The main control module includes: a second group of filter capacitors and an STM32 main control chip; The second group of filter capacitors is connected to the STM32 main control chip to reduce low-frequency ripple and ensure that the power module provides a clean and stable power supply to the STM32 main control chip, thus ensuring the stable operation of the extraction process. The STM32 main control chip is connected to the QRNG chip and is used to send chip select signals, clock signals and other signals to the QRNG chip, thereby controlling the QRNG chip to generate quantum random numbers.

4. The chip-based quantum random number extraction system based on silicon-based integrated photonics as described in claim 1, characterized in that, The data reading module includes: a first 220Ω current-limiting resistor, a second 220Ω current-limiting resistor, a USB interface, and a CH340N chip; The first 220Ω current-limiting resistor is connected to the CH340N chip and the STM32 main control chip, and the second 220Ω current-limiting resistor is also connected to the CH340N chip and the STM32 main control chip; this achieves current-limiting protection to prevent damage to the CH340N chip and the STM32 main control chip. The USB interface is connected to an external device, and the CH340N chip is connected to the STM32 host control chip to receive and send data to the STM32 host control chip. The CH340N chip is also connected to the USB interface to receive and send data to the USB interface, thereby completing data protocol conversion and enabling data transmission with external devices.

5. The chip-based quantum random number extraction system based on silicon-based integrated photonics as described in claim 1, characterized in that, The auxiliary circuit module includes: a clock circuit, a reset circuit, and a startup mode selection circuit; The clock circuit includes: an 8MHz passive crystal oscillator, a 1MΩ bias resistor, a first 10pF capacitor, and a second 10pF capacitor; the first 10pF capacitor and the second 10pF capacitor are connected in series and then connected in parallel with the 8MHz passive crystal oscillator and the 1MΩ bias resistor to form a complete external clock resonant circuit; the clock circuit is connected to the STM32 main control chip to provide a stable external clock source for the STM32 main control chip; The reset circuit includes a button and an RC circuit; the button is connected to the RC circuit to implement a manual reset function; the RC circuit is connected to the STM32 main control chip to implement an automatic reset function. The startup mode selection circuit is connected to the STM32 main control chip and is used to switch the system startup mode to meet the startup requirements in different scenarios.

6. The chip-based quantum random number extraction system based on silicon-based integrated photonics as described in claim 1, characterized in that, The power module includes: a first linear voltage regulator branch, a second linear voltage regulator branch, and a Schottky diode; The Schottky diode is connected to the USB interface to obtain a +5V voltage; the Schottky diode is connected to the first linear voltage regulator branch and the second linear voltage regulator branch respectively to cut off reverse current, which can effectively prevent current backflow caused by reverse power connection and avoid damage to internal components. The first linear voltage regulator branch includes: a first linear regulator diode, a first front-end filter capacitor group, and a first back-end filter capacitor group; the second linear voltage regulator branch includes: a second linear regulator diode, a second front-end filter capacitor group, and a second front-end filter capacitor group. The first front-end filter capacitor group is connected to the first linear regulator diode to filter out noise in the +5V input voltage; the first back-end filter capacitor group is connected to the first linear regulator diode to filter the output +3.3V voltage; the first linear regulator diode is connected to the first filter capacitor group of the core module for decoupling filtering, ultimately providing a stable and clean power supply for the QRNG chip; The second front-end filter capacitor group is connected to the second linear regulator diode to filter out noise in the +5V input voltage; the second back-end filter capacitor group is connected to the second linear regulator diode to filter the output +3.3V voltage. The second linear regulator diode is connected to the second filter capacitor group of the main control module for decoupling filtering, ultimately providing a stable and clean power supply to the STM32 chip; the second linear regulator diode is connected to the CH340 chip, the reset circuit, and the startup mode selection circuit to supply power to the CH340 chip, the reset circuit, and the startup mode selection circuit.

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