Storage device and method of block recovery in the storage device

Abstract

A storage device includes: a non-volatile memory device including a plurality of memory blocks; and a memory controller including an error check code (ECC) circuit that performs ECC encoding and ECC decoding. The memory controller selects a source block to be a target of block recovery from among the plurality of memory blocks, groups a plurality of word lines into weak word lines and strong word lines based on retention characteristics according to physical locations of the plurality of word lines of the source block; and controlling the non-volatile memory device to perform an external copy-back operation for the weak word line and an internal copy-back operation for the strong word line by the ECC circuit, the external copy-back operation including error correction of the ECC circuit and the internal copy-back operation not including the error correction of the ECC circuit.

Description

Technical Field

[0001] The example embodiments generally relate to semiconductor integrated circuits, and more specifically to storage devices and methods for block reclamation in storage devices. Background Technology

[0002] Memory devices (such as flash memory devices, resistive memory devices, etc.) can store data based on multiple threshold voltage distributions or multiple resistance distributions, where each corresponding threshold voltage distribution or resistance distribution is assigned to a corresponding logic state of the stored data. Data stored by a memory cell can be read by determining whether the memory cell is turned on / off when a predetermined read voltage is applied. During (and / or after) the programming of a memory cell, the expected threshold voltage distribution or resistance distribution of the memory cell may be undesirably distorted due to multiple events or conditions, including, for example, charge leakage, programming interference, read interference, word line and / or bit line coupling, temperature changes, voltage changes, memory cell degradation, etc. For example, the expected threshold voltage distribution or resistance distribution may be shifted and / or widened, causing read errors and resulting in erroneous data read that differs from the stored data. Summary of the Invention

[0003] One aspect is to provide a storage device and a method for block reclamation in the storage device, which can prevent or reduce the occurrence of uncorrectable errors.

[0004] According to one or more example embodiments, a method for block reclamation in a storage device is provided, the storage device including a non-volatile memory device and a memory controller controlling the non-volatile memory device, the method comprising: selecting a source block to be targeted for block reclamation from a plurality of memory blocks included in the non-volatile memory device; grouping the plurality of word lines into weak word lines and strong word lines based on the preservation characteristics of the physical locations of a plurality of word lines of the source block; performing an external copyback operation for the weak word lines, the external copyback operation including error correction; and performing an internal copyback operation for the strong word lines, the internal copyback operation not including the error correction.

[0005] According to another aspect of one or more example embodiments, a storage device is provided, comprising: a non-volatile memory device including a plurality of memory blocks; and a memory controller including ECC circuitry configured to perform Error Check Code (ECC) encoding and ECC decoding. The memory controller is configured to select a source block from the plurality of memory blocks as a target for block reclamation; group the plurality of word lines into weak word lines and strong word lines based on retention characteristics of the physical locations of a plurality of word lines of the source block; and control the non-volatile memory device to perform an external copy-back operation for the weak word lines and an internal copy-back operation by the ECC circuitry for the strong word lines, the external copy-back operation including error correction by the ECC circuitry and the internal copy-back operation not including the error correction by the ECC circuitry.

[0006] According to another aspect of one or more example embodiments, a storage device is provided, comprising: a non-volatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of word lines and a plurality of memory cells, the plurality of memory cells being stacked in a vertical direction and formed in a plurality of channel vias; and a memory controller including ECC circuitry configured to perform ECC encoding and ECC decoding. The memory controller is configured to select a source block from the plurality of memory blocks as a target for block reclamation, group the plurality of word lines into weak word lines and strong word lines based on the height of each word line in the vertical direction of the source block, and control the non-volatile memory device to perform an external copy-back operation for the weak word lines and an internal copy-back operation for the strong word lines, the external copy-back operation including error correction by the ECC circuitry and the internal copy-back operation not including the error correction by the ECC circuitry. The non-volatile memory device is configured to transmit read data read from memory cells connected to weak word lines of the source block to the memory controller during the external copy operation, and not transmit read data read from memory cells connected to strong word lines of the source block to the memory controller during the internal copy operation. Attached Figure Description

[0007] The exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0008] Figure 1 This is a block diagram illustrating a storage device according to an example embodiment.

[0009] Figure 2 This is a flowchart illustrating a method for block reclamation in a storage device according to an example embodiment.

[0010] Figure 3This is a block diagram illustrating an example embodiment of a memory controller included in a memory system according to an example embodiment.

[0011] Figure 4 This is a block diagram illustrating a non-volatile memory device according to an example embodiment.

[0012] Figure 5 This is a block diagram illustrating a storage device according to an example embodiment.

[0013] Figure 6 This illustrates the inclusion of examples according to the embodiment. Figure 4 A block diagram of a memory cell array in a non-volatile memory device.

[0014] Figure 7 This illustrates the inclusion of examples according to the embodiments. Figure 6 The circuit diagram of the equivalent circuit of the memory block in the memory cell array.

[0015] Figure 8 This is a diagram illustrating an example state of a multi-level cell included in a non-volatile memory device according to an example embodiment.

[0016] Figure 9 It shows from Figure 8 A diagram of the degenerate state of the state.

[0017] Figure 10 This is a sequence diagram illustrating an external copy-back operation of a storage device according to an example embodiment.

[0018] Figure 11 This illustrates the basis according to the example embodiment. Figure 10 A diagram of the data flow for the external copy operation.

[0019] Figure 12 This is a sequence diagram illustrating the internal copy-back operation of a storage device according to an example embodiment.

[0020] Figure 13 This illustrates the basis according to the example embodiment. Figure 12 A diagram of the data flow for the internal copy operation.

[0021] Figure 14 This is a diagram illustrating an example structure of a cell string of a non-volatile memory device according to an example embodiment.

[0022] Figure 15 and Figure 16 This is a diagram illustrating the retention characteristics of a block reclamation method in a storage device according to an example embodiment.

[0023] Figure 17This is a diagram illustrating the change retention characteristic information in a block reclamation method in a storage device according to an example embodiment.

[0024] Figure 18 This is a diagram illustrating a programming method in a storage device according to an example embodiment.

[0025] Figure 19 and Figure 20 This is a diagram illustrating the execution sequence of a block reclamation method in a storage device according to an example embodiment.

[0026] Figure 21 This is a diagram illustrating a programming method in a storage device according to an example embodiment.

[0027] Figure 22 This is a circuit diagram illustrating the structure of a memory cell array included in a non-volatile memory device according to an example embodiment.

[0028] Figure 23 This illustrates the relationship between the example embodiment and... Figure 22 The diagram shows the memory block structure corresponding to the memory block.

[0029] Figure 24 This is a cross-sectional view showing a boundary layer included in a non-volatile memory device according to an example embodiment.

[0030] Figure 25 This is a diagram illustrating a memory block included in a non-volatile memory device according to an example embodiment.

[0031] Figure 26 This is a diagram illustrating example retention characteristics and retention characteristic information of a non-volatile memory device according to an example embodiment.

[0032] Figure 27 This is a flowchart illustrating the determination of source blocks in a block reclamation method in a storage device according to an example embodiment.

[0033] Figure 28 This illustrates the relationship between the example embodiment and Figure 27 The graph corresponding to the method for determining source block information.

[0034] Figure 29 This is a flowchart illustrating the determination of source blocks in a block reclamation method in a storage device according to an example embodiment.

[0035] Figure 30 This illustrates the relationship between the example embodiment and... Figure 29 The graph corresponding to the method for determining source block information.

[0036] Figure 31 This is a block diagram illustrating a data center including storage devices according to an example embodiment.

[0037] Figure 32 This is a cross-sectional view showing a non-volatile memory device according to an example embodiment.

[0038] Figure 33 This is a diagram used to describe the manufacturing process of a stacked semiconductor device according to an example embodiment. Detailed Implementation

[0039] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, which illustrate some exemplary embodiments. In the drawings, the same reference numerals consistently denote the same elements. For the sake of brevity, repeated descriptions may be omitted.

[0040] The storage device and block reclamation method according to the example embodiment can effectively prevent or reduce the occurrence of uncorrectable errors and improve the reliability and performance of the storage device by selectively performing external copy-back operations or internal copy-back operations based on the retention characteristics of the physical location of the word line.

[0041] Figure 1 This is a block diagram illustrating a storage device according to an example embodiment, and Figure 2 This is a flowchart illustrating a method for block reclamation in a storage device according to an example embodiment.

[0042] refer to Figure 1 The memory system 10 may include a memory controller (or storage controller) 100 and at least one non-volatile memory device 300. Figure 1 The memory system 10 shown may include a flash memory-based data storage medium, such as a memory card, USB memory, SSD, or the like.

[0043] The non-volatile memory device 300 can perform erase, write, or read operations under the control of the memory controller 100. The non-volatile memory device 300 receives commands CMD (such as read commands and write commands) and addresses ADDR (such as read addresses and write addresses) from the memory controller 100 via input and output lines, and transmits and receives data DATA for read or write operations (or programming operations) with the memory controller 100. The non-volatile memory device 300 can receive control signals CTRL via control lines, and can receive power PWR from the memory controller 100.

[0044] The memory controller 100 can control access to the non-volatile memory device 300 based on a request REQ received from an external host device. The memory controller 100 may include an error check code (ECC) circuit 170 and a recycling manager RCM.

[0045] ECC circuit 170 may include an ECC encoder ENC and an ECC decoder DEC. The ECC encoder ENC performs ECC encoding on write data to be stored in the non-volatile memory device 300 to produce encoded data, i.e., codewords. The ECC decoder DEC performs ECC decoding on read data in codeword form read from the non-volatile memory device 300 to correct errors in the read data.

[0046] The Recycle Manager (RCM) manages and controls block reclamation operations, as described below. The RCM can be implemented in hardware, software, firmware, or a combination thereof.

[0047] refer to Figure 1 and Figure 2 The Recycling Manager (RCM) can select a source block from among multiple memory blocks included in the non-volatile memory device 300 as the target for block recycling (S100). Block recycling refers to moving the data of the source block and storing it in the destination block. Source blocks can be selected in various ways, as will be discussed below. Figures 27 to 30 Describe an example implementation for determining the source block.

[0048] The Reclaim Manager (RCM) can group multiple word lines of a source block into weak word lines and strong word lines based on the retention characteristics of the physical locations of the word lines (S200). Weak word lines represent word lines connected to memory cells with a relatively high probability of error occurrence, while strong word lines represent word lines connected to memory cells with a relatively low probability of error occurrence. The RCM can store the grouping results as retention characteristic information (RTI) and can effectively control block reclamation based on the RTI.

[0049] The following will be a reference Figures 14 to 16 The described information allows for the pre-determining of retention characteristic information RTI based on the physical structure of the non-volatile memory device 300. In an example embodiment, reference will be made below. Figure 17 As described, as the retention characteristics of memory blocks deteriorate, the number of weak word lines can be increased and the number of strong word lines can be decreased.

[0050] The Recycle Manager (RCM) can control the non-volatile memory device 300 to perform an external copy operation, which includes error correction (S300) performed by the ECC circuit 170 on weak word lines of the source block. (See below for reference.) Figure 10 and Figure 11 Describe the external copy-back operation.

[0051] In contrast, the Recycle Manager (RCM) can control the non-volatile memory device 300 to perform an internal copy-back operation, which excludes error correction (S400) for strong word lines by the ECC circuit 170. See below for further details. Figure 12 and Figure 13 Describe the internal copy-back operation.

[0052] In the example embodiment, reference will be made as follows. Figures 10 to 13 The non-volatile memory device 300 can transmit read data read from memory cells connected to weak word lines of the source block to the memory controller 100 during an external copy operation. Conversely, during an internal copy operation, read data read from memory cells connected to strong word lines of the source block may not be transmitted to the memory controller 100. During an external copy operation, the ECC circuit 170 of the memory controller 100 can correct errors in the read data read from memory cells connected to weak word lines of the source block and transmit the corrected data to the non-volatile memory device 300. The non-volatile memory device 300 can write the corrected data to a destination block determined among multiple memory blocks. Conversely, during an internal copy operation, the non-volatile memory device 300 can write read data read from memory cells connected to strong word lines of the source block to the destination block (i.e., without correcting errors in the read data).

[0053] For weak word lines with a relatively high probability of error occurrence, the occurrence of uncorrectable errors can be reduced or prevented by using ECC circuit 170 to correct errors. On the other hand, for strong word lines with a relatively low probability of error occurrence, by omitting the transmission of read data, ECC decoding of read data, ECC encoding of correction data, and transmission of correction data, the operations used to perform block reclamation of storage device 10 can be reduced, and the time used for block reclamation can be reduced.

[0054] By utilizing the above configuration and operation, the storage device 10 and block reclamation method according to the example embodiment can effectively prevent or reduce the occurrence of uncorrectable errors by selectively performing external copy-back operations or internal copy-back operations based on the retention characteristics of the physical location of the word line, and improve the reliability and performance of the storage device 10.

[0055] Figure 3 This is a block diagram illustrating an example embodiment of a memory controller included in a memory system according to an example embodiment.

[0056] refer to Figure 3The memory controller (or storage controller) 100 may include a processor 110, a buffer memory (BUFF) 140, a DRAM controller 130, a host interface (HIF) 120, an error correction code (ECC) circuit 170, a memory interface (MIF) 150, an advanced encryption standard (AES) engine 180, and an internal bus 160 electrically connecting the processor 110, the buffer memory (BUFF) 140, the DRAM controller 130, the host interface (HIF) 120, the error correction code (ECC) circuit 170, the memory interface (MIF) 150, and the advanced encryption standard (AES) engine 180.

[0057] Processor 110 can control the operation of memory controller 100 in response to commands received from an external host device via host interface 120. For example, processor 110 can control the memory system (e.g., Figure 1 The operation of 10) in the above text can be driven by firmware to control the corresponding components. In some example embodiments, the above references Figure 1 and Figure 2 The described recycling manager RCM can be implemented as hardware corresponding to a portion of processor 110. In some example embodiments, the recycling manager RCM can be implemented as software or firmware executed by processor 110.

[0058] The buffer memory 140 can store instructions and data executed and processed by the processor 110. For example, the buffer memory 140 can be implemented as a volatile memory, such as SRAM, DRAM, etc.

[0059] The ECC circuit 170 used for error correction can use error correction codes (such as Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, Turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC)) and coding modulation (such as trellis-coded modulation (TCM), block-coded modulation (BCM), Hamming codes, etc.) to perform ECC encoding and ECC decoding.

[0060] The Host Interface (HIF) 120 can provide a physical connection between the host device and the memory controller 100; that is, the Host Interface 120 can provide an interface with the memory controller 100 in a bus format corresponding to the bus format of the host device. In example embodiments, the bus format of the host device may be SCSI or SAS. In some example embodiments, the bus format of the host device may be USB, Peripheral Component Interconnect High Speed ​​(PCIe), ATA, PATA, SATA, NVMe, etc.

[0061] The memory interface (MIF) 150 can interface with non-volatile memory devices (e.g., Figure 1 The memory interface 150 can exchange data with the non-volatile memory device 300. The memory interface 150 can transfer write data to and receive read data from the non-volatile memory device 300. For example, the memory interface 150 can utilize standard protocols such as Toggle or ONFI.

[0062] The AES engine 180 can use a symmetric key algorithm to perform at least one of encryption and decryption operations on data input to the memory controller 100. Although not shown in detail, the AES engine 180 may include an encryption module and a decryption module. Depending on the example embodiment, the encryption module and the decryption module may be implemented as separate modules or as a single module.

[0063] Processor 110 can access external DRAM 80 via DRAM controller 130. Processor 110 can control DRAM controller 130, memory interface 150 and host interface 120 to transfer user data stored in external DRAM 80 to non-volatile memory device 300 or external host device.

[0064] Figure 4 This is a block diagram illustrating a non-volatile memory device according to an example embodiment.

[0065] refer to Figure 4 The non-volatile memory device 300 may include a memory cell array 500, a page buffer circuit 510, a data input / output (I / O) circuit 520, an address decoder 530, a control circuit 550, and a voltage generator 560. Reference will be made below. Figure 32 and Figure 33 As described, the CREG (cell region) and PREC (peripheral region) can be formed and set in different wafers.

[0066] The memory cell array 500 can be coupled to the address decoder 530 via the string select line SSL, the word line WL, and the ground select line GSL. The memory cell array 500 can be coupled to the page buffer circuitry 510 via the bit line BL. The memory cell array 500 may include memory cells coupled to the word line WL and the bit line BL. In some example embodiments, the memory cell array 500 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (e.g., a vertical structure). In this case, the memory cell array 500 may include a string of cells (e.g., a NAND string) vertically oriented such that at least one memory cell vertically overlaps with another memory cell.

[0067] Control circuitry 550 can receive command (signal) CMD and address (signal) ADDR from the memory controller. Therefore, control circuitry 550 can control erase, program, and read operations of the non-volatile memory device 300 in response to (or based on) at least one of the command signal CMD and the address signal ADDR. Erasing operations may include a sequence of executing erase cycles. Programming operations may include a sequence of executing programming cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. Read operations may include normal read operations and data recovery read operations.

[0068] For example, control circuit 550 can generate a control signal CTL for controlling the operation of voltage generator 560. Control circuit 550 can generate a page buffer control signal PBC for controlling page buffer circuit 510 based on command signal CMD, and generate row address R_ADDR and column address C_ADDR based on address signal ADDR. Control circuit 550 can provide row address R_ADDR to address decoder 530 and column address C_ADDR to data I / O circuit 520.

[0069] Address decoder 530 can be coupled to memory cell array 500 via serial select line SSL, word line WL, and ground select line GSL. During programming or reading operations, address decoder 530 can determine or select one of the word lines WL as the selected word line based on the row address R_ADDR, and determine the remaining word lines WL other than the selected word line as the unselected word lines.

[0070] During programming or reading operations, the address decoder 530 can determine one of the string select lines SSL as the selected string select line based on the row address R_ADDR, and determine the remaining string select lines SSL as the unselected string select lines.

[0071] Voltage generator 560 can generate the word line voltage VWL required for the operation of the memory cell array 500 of the non-volatile memory device 300 based on the control signal CTL. Voltage generator 560 can obtain the voltage from the memory controller (such as...) Figure 1 The memory controller 100 receives power PWR. The word line voltage VWL can be applied to the word line WL via the address decoder 530.

[0072] For example, during an erase operation, voltage generator 560 may apply an erase voltage to the well and / or common source line of the memory block, and apply an erase permission voltage (e.g., ground voltage) to all or a portion of the word lines of the memory block based on the erase address. During an erase verification operation, voltage generator 560 may apply an erase verification voltage simultaneously to all word lines of the memory block or sequentially (e.g., one after another) to the word lines.

[0073] For example, during programming operations, voltage generator 560 can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line. Additionally, during programming verification operations, voltage generator 560 can apply a programming verification voltage to the first word line and a verification pass voltage to the unselected word line.

[0074] During a normal read operation, voltage generator 560 can apply a read voltage to the selected word line and can apply a read pass voltage to an unselected word line. During a data recovery read operation, voltage generator 560 can apply a read voltage to the word line adjacent to the selected word line and can apply a recovery read voltage to the selected word line.

[0075] Page buffer circuitry 510 can be coupled to memory cell array 500 via bit line BL. Page buffer circuitry 510 may include multiple buffers. In some example embodiments, each buffer may be connected to a single bit line. In some example embodiments, each buffer may be connected to two or more bit lines. Page buffer circuitry 510 may temporarily store data to be programmed into a selected page or data read from a selected page of memory cell array 500.

[0076] Page buffer circuit 510 may include a first latch LTR for storing read data and a second latch LTW for storing write data. During the internal copy-back operation described above, read data read from the strong word line of the source block may be stored in the first latch LTR. Subsequently, the read data stored in the first latch LTR may be stored in the second latch LTW as write data for writing to the target block.

[0077] Data I / O circuit 520 can be coupled to page buffer circuit 510 via data line DL. During programming operations, data I / O circuit 520 can receive programming data DATA from the memory controller and provide the programming data DATA to page buffer circuit 510 based on the column address C_ADDR received from control circuit 550. During read operations, data I / O circuit 520 can provide read data DATA that has been read from memory cell array 500 and stored in page buffer circuit 510 to the memory controller based on the column address C_ADDR received from control circuit 550.

[0078] Page buffer circuit 510 and data I / O circuit 520 can read data from a first region of memory cell array 500 and write the read data to a second region of memory cell array 500 (e.g., without transferring data to a source outside the non-volatile memory device 1000, such as to a memory controller). For example, page buffer circuit 510 and data I / O circuit 520 can perform a copy-back operation.

[0079] Figure 5 This is a block diagram illustrating a storage device according to an example embodiment.

[0080] refer to Figure 5 The memory system or storage device 600 may include a non-volatile memory device 610 and a memory controller 100. The storage device 600 may support multiple channels CH1, CH2, ..., CHm, and the non-volatile memory device 610 can be connected to the memory controller 100 through multiple channels CH1 to CHm. For example, the storage device 600 may be implemented as a general-purpose flash memory (UFS), a solid-state drive (SSD), etc. The storage device 600 may correspond to... Figure 1 The memory system 10.

[0081] The non-volatile memory device 610 may include multiple non-volatile memories NVM11, NVM12, ..., NVM1n, NVM21, NVM22, ..., NVM2n, NVMm1, NVMm2, ..., NVMmn. Here, n and m can each be an integer. Each of the non-volatile memories NVM11 to NVMmn can be connected to one of the multiple channels CH1 to CHm in a corresponding manner. For example, non-volatile memories NVM11 to NVM1n can be connected to the first channel CH1 through paths W11, W12, ..., W1n; non-volatile memories NVM21 to NVM2n can be connected to the second channel CH2 through paths W21, W22, ..., W2n; and non-volatile memories NVMm1 to NVMmn can be connected to the m-th channel CHm through paths Wm1, Wm2, ..., Wmn. In some example embodiments, each of the non-volatile memories NVM11 to NVMmn can be implemented as a memory cell that can be operated according to individual commands from the memory controller 100. For example, each of the non-volatile memories NVM11 to NVMmn can be implemented as a chip or a die, but the example embodiments are not limited thereto.

[0082] The memory controller 100 can send signals to and receive signals from the non-volatile memory device 610 through multiple channels CH1 to CHm. For example, the memory controller 100 can send commands CMDa, CMDb, ..., CMDm, addresses ADDRa, ADDRb, ..., ADDRm, and data DATAa, DATAb, ..., DATAm to the non-volatile memory device 610 through channels CH1 to CHm, or it can receive data DATAa to DATAm from the non-volatile memory device 610 through channels CH1 to CHm.

[0083] The memory controller 100 can use one of the corresponding channels CH1 to CHm to select one non-volatile memory NVM11 to NVM1n connected to each of the channels CH1 to CHm, and can send signals to and receive signals from the selected non-volatile memory. For example, the memory controller 100 can select non-volatile memory NVM11 from the non-volatile memories NVM11 to NVM1n connected to the first channel CH1. The memory controller 100 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory NVM11 through the first channel CH1, or can receive data DATAa from the selected non-volatile memory NVM11 through the first channel CH1.

[0084] The memory controller 100 can send signals to and receive signals from the non-volatile memory device 610 in parallel through different channels. For example, the memory controller 100 can send the command CMDb to the non-volatile memory device 610 through the second channel CH2, while simultaneously sending the command CMDa to the non-volatile memory device 610 through the first channel CH1. For example, the memory controller 100 can receive data DATAb from the non-volatile memory device 610 through the second channel CH2, while simultaneously receiving data DATAa from the non-volatile memory device 610 through the first channel CH1.

[0085] The memory controller 100 can control the overall operation of the non-volatile memory device 610. The memory controller 100 can send signals to channels CH1 to CHm and can control each of the non-volatile memories NVM11 to NVM1n connected to channels CH1 to CHm. For example, the memory controller 100 can send the command CMDa and the address ADDRa to the first channel CH1 and can control the selection of one of the non-volatile memories NVM11 to NVM1n.

[0086] Each of the non-volatile memories NVM11 to NVMmn can operate under the control of the memory controller 100. For example, the non-volatile memory NVM11 can be programmed with data DATAa based on the command CMDa, address ADDRa, and data DATAa provided from the memory controller 100 via the first channel CH1. For example, the non-volatile memory NVM21 can read data DATAb based on the command CMDb and address ADDRb provided from the memory controller 100 via the second channel CH2, and can send the read data DATAb to the memory controller 100 via the second channel CH2.

[0087] although Figure 5 An example is shown of a non-volatile memory device 610 communicating with a memory controller 100 via m channels and including n non-volatile memories corresponding to each of the channels. However, the example embodiment is not limited thereto, and in some example embodiments, the number of channels and the number of non-volatile memories connected to a channel may be varied.

[0088] According to an example embodiment, the memory controller 100 may include an ECC circuit 170, and the word lines of a plurality of non-volatile memories NVM11, NVM12, ..., NVM1n, NVM21, NVM22, ..., NVM2n, NVMm1, NVMm2, ..., NVMmn may be grouped into weak word lines and strong word lines.

[0089] Figure 6It is shown that it includes Figure 4 A block diagram of a memory cell array in a non-volatile memory device, and Figure 7 It is shown that it includes Figure 6 The circuit diagram of the equivalent circuit of the memory block in the memory cell array.

[0090] In the following text, two directions parallel to the upper surface of the semiconductor substrate and intersecting each other are defined as the first direction D1 and the second direction D2, respectively, and a direction substantially perpendicular to the upper surface of the semiconductor substrate is defined as the third direction D3. For example, the first direction D1 and the second direction D2 may intersect each other substantially perpendicularly. The first direction D1 may be referred to as the row direction, the second direction D2 may be referred to as the column direction, and the third direction D3 may be referred to as the vertical direction. The directions indicated by the arrows in the accompanying drawings and their opposite directions are described as the same direction. The above definitions of directions may be the same in all subsequent drawings.

[0091] refer to Figure 6 The memory cell array 500 may include memory blocks BLK1 to BLKz. Here, z can be an integer. In some example embodiments, memory blocks BLK1 to BLKz may be... Figure 4 The address decoder 530 is selected. For example, the address decoder 530 can select a specific memory block BLK corresponding to the block address among memory blocks BLK1 to BLKz.

[0092] Figure 7 The memory block BLKi can be formed on the substrate in a three-dimensional structure (e.g., a vertical structure). For example, the NAND strings or cell strings included in the memory block BLKi can be arranged in a vertical direction D3 perpendicular to the upper surface of the substrate.

[0093] refer to Figure 7 The memory block BLKi may include cell strings or NAND strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and the common source line CSL. Each NAND string may include multiple memory cells stacked on the vertical direction D3, and multiple word lines may be stacked on the vertical direction D3.

[0094] Each of the NAND strings NS11 to NS33 may include a string select transistor SST, memory cells MC1 to MC8, and a ground select transistor GST. Figure 7 In the example, each of the NAND strings NS11 to NS33 is shown as comprising eight memory cells MC1 to MC8. However, the example embodiment is not limited thereto. In some example embodiments, each of the NAND strings NS11 to NS33 may include any number of memory cells.

[0095] Each string select transistor (SST) can be connected to a corresponding string select line (e.g., one of SSL1 through SSL3). Memory cells MC1 through MC8 can be connected to corresponding gate lines GTL1 through GTL8. Gate lines GTL1 through GTL8 can be word lines. Some of gate lines GTL1 through GTL8 can be dummy word lines. Each ground select transistor (GST) can be connected to a corresponding ground select line (e.g., one of GSL1 through GSL3). Each string select transistor (SST) can be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3). Each ground select transistor (GST) can be connected to the common source line CSL.

[0096] Word lines of the same height (each of gate lines GTL1 to GTL8) can be connected together. Ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separated. Figure 7 In the example, memory block BLKi is shown coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, the example embodiment is not limited to this. In some example embodiments, each memory block in the memory cell array 500 may be coupled to any number of word lines and any number of bit lines.

[0097] Figure 8 This is a diagram illustrating an example state of a multi-level cell included in a non-volatile memory device according to an example embodiment.

[0098] Figure 8 The diagram illustrates the first states S1 through the eighth state S8 of a three-level cell (TLC) memory, where each memory cell of the TLC memory can store three data bits. Figure 8 In the diagram, the horizontal axis represents the threshold voltage VTH of the memory cell, and the vertical axis represents the number of memory cells corresponding to the threshold voltage VTH. During the programming operation, the programming success of the first state S1 to the eighth state S8 can be distinguished by applying the first verification read voltage VVR1 to the seventh verification read voltage VVR7 to the selected word line, respectively.

[0099] Figure 9 It shows from Figure 8 A diagram of the degenerate state of the state.

[0100] Compared to Figure 8 The threshold voltage distribution of states S1 to S8 can be as follows: Figure 9The degradation shown is illustrated. During or after the programming of a memory cell, the intended distribution may be undesirably distorted due to a number of events or conditions, including, for example, charge leakage, programming interference, read interference, word line and / or bit line coupling, temperature variations, voltage variations, and memory cell degradation caused by repeated programming and erasing. For example, the intended distribution may be shifted and / or widened.

[0101] Based on the degree of degradation of memory cells, Figure 8 Reading operations using read voltages VR1 to VR7 may fail, resulting in the reading of erroneous data that differs from the stored data. When a read failure occurs, the non-volatile memory device can perform a recovery read operation, allowing the search to proceed as planned. Figure 9 The optimal read voltages VR1' to VR7' are shown to attempt another read operation based on the optimal read voltages VR1' to VR7'. However, if the degradation is severe, even with the optimal read voltages VR1' to VR7', states S1 to S7 may not be distinguishable. Furthermore, obtaining the optimal read voltages VR1' to VR7' may take a long time, thus degrading the performance of the memory system.

[0102] like Figure 9 As shown, the threshold voltage distribution of memory cells connected to weak word lines (WWL) may be more severely degraded than that of memory cells connected to strong word lines (SWL). According to an example embodiment, by performing an external copy-back operation including error correction for weak word lines (WWL) with a relatively high error probability and an internal copy-back operation without error correction for weak word lines (WWL) with a relatively low error probability, block reclamation can be effectively performed and the occurrence of uncorrectable errors can be reduced or prevented.

[0103] Figure 10 This is a sequence diagram illustrating an external copy-back operation of a storage device according to an example embodiment, and Figure 11 This illustrates the basis according to the example embodiment. Figure 10 A diagram of the data flow for the external copy operation.

[0104] refer to Figure 1 , Figure 4 , Figure 10 and Figure 11As described above, the Reclaim Manager RCM can select the source block SBL as the target of block reclamation (S10). The Reclaim Manager RCM can transmit a read command RD including the read row address RADD corresponding to the weak word line WWL of the source block SBL to the non-volatile memory device 300 (S11). The non-volatile memory device 300 can perform a read operation ROP for the read row address RADD of the source block SBL (S12) to store the read data RDT in the page buffer circuit 510 and transmit the read data RDT to the memory controller 100 (S13). The ECC circuit 170 of the memory controller 100 can perform ECC decoding on the read data RDT to generate corrected data CDT (S14) and perform ECC encoding on the corrected data CDT (S15).

[0105] The recycling manager RCM can transmit the write command WR, which includes the write line address WADD corresponding to the word line of the destination block, along with the corrected data CDT, in the form of a codeword to the non-volatile memory device 300 (S16).

[0106] The non-volatile memory device 300 can store the received corrected data CDT in the page buffer circuit 510. The non-volatile memory device 300 can perform a write operation WOP to write the corrected data CDT stored in the page buffer circuit 510 to the write address WADD of the destination block (S17), and transmit a response RES indicating the completion of the write operation WOP to the memory controller 100 (S18). The response RES may include switching the ready-busy signal to the ready state. For ease of illustration, Figure 10 The operation for a single weak word line WWL is illustrated. In some example embodiments, the operation can be performed for each weak word line in the WWL. Figure 10 The series of operations described in the text.

[0107] like Figure 11 As shown, in an external copy-back operation, read data RDT is transferred from non-volatile memory device 300 to memory controller 100, and corrected data CDT can be transferred from memory controller 100 to non-volatile memory device 300. During this process, read data RDT and / or corrected data CDT can be stored in external DRAM 80. With this configuration and operation, error correction can be performed in the external copy-back operation, but the hardware resources of memory controller 100 may be consumed significantly.

[0108] Figure 12 This is a sequence diagram illustrating the internal copy-back operation of a storage device according to an example embodiment, and Figure 13 This illustrates the basis according to some example embodiments. Figure 12 A diagram of the data flow for the internal copy operation.

[0109] refer to Figure 1 , Figure 4 , Figure 12 and Figure 13 As described above, the Recycling Manager RCM can select the source block SBL as the target of block recycling (S20). The Recycling Manager RCM can transmit a single command CB including a read row address RADD corresponding to the strong word line SWL of the source block SBL and a write row address WADD corresponding to the word line of the destination block to the non-volatile memory device 300 (S21). The non-volatile memory device (300) can perform a read operation ROP (S22) for the read row address RADD of the source block SBL to store the read data RDT in the page buffer circuit 510. Thereafter, the non-volatile memory device 300 can perform a write operation WOP (S23) to write the read data RDT stored in the page buffer circuit 510 to the write address WADD of the destination block, and transmit a response RES indicating that the write operation WOP is complete to the memory controller 100 (S24). The response RES may include transitioning a ready busy signal to a ready state. For ease of illustration, in Figure 12 The diagram illustrates the operations used for a strong word line SWL. In some example embodiments, this can be performed for each strong word line SWL. Figure 12 The series of operations described in the document.

[0110] like Figure 13 As shown, during the internal copy operation, the read data RDT read from the source block SBL can be moved to the destination block DBL and stored in the destination block DBL using the page buffer circuit 510 instead of being transferred from the non-volatile memory device 300 to the memory controller 100. In this way, error correction can be avoided during the internal copy operation, saving hardware resources of the memory controller 100.

[0111] Figure 14 This is a diagram illustrating an example structure of a cell string of a non-volatile memory device according to an example embodiment.

[0112] refer to Figure 14To form the cell string CS, pillars PL can be provided, extending in a vertical direction D3 perpendicular to the upper surface of the semiconductor substrate SUB. The ground select line GSL, word line WL, and string select line SSL can each be formed parallel to the conductive material (e.g., a metallic material) of the semiconductor substrate SUB. The pillars PL can penetrate the conductive material forming the ground select line GSL, word line WL, and string select line SSL. Furthermore, the word line WL may include dummy word lines not used for data storage. Dummy word lines can be used for various purposes. For example, in the fabrication process of the cell string CS, the width of the pillars PL, or the cross-sectional area parallel to the upper surface of the semiconductor substrate SUB, can be formed smaller as the distance from the semiconductor substrate SUB decreases. Therefore, when the same voltage is applied to... Figure 7 When the ground select transistor GST, memory cell MC, and string select transistor SST are connected, and the same voltage is applied to the ground select line GSL, word line WL, and string select line SSL, the electric field formed in the memory cell or ground select transistor GST adjacent to the semiconductor substrate SUB is greater than the electric field formed in the memory cell or string select transistor SST farther from the semiconductor substrate SUB. This characteristic affects interference occurring during programming and / or reading operations. The width of the pillar PL, or the cross-sectional area parallel to the upper surface of the semiconductor substrate SUB, is not limited to... Figure 14 As shown in the illustration. In some example embodiments, the width of the pillar PL, or the cross-sectional area parallel to the upper surface of the semiconductor substrate SUB, can be formed differently depending on the distance from the semiconductor substrate SUB, which depends on the etching process. Thus, the characteristics of the memory cells may differ depending on the physical location of the word lines or their height in the vertical direction D3. The pillar PL corresponds to the channel via of the cell string, and as... Figure 14 As shown, the diameter of the cross-sectional area of ​​the channel hole decreases as it descends. That is to say, as... Figure 14 As shown, the diameter of the cross-sectional area of ​​the via decreases as the distance from the semiconductor substrate SUB decreases. Therefore, the size of the floating gate of the flash memory cell decreases as it moves downwards within the via, and the retention capability of the memory cell decreases. In other words, the size of the floating gate of the flash memory cell decreases, and the distance between the via and the semiconductor substrate SUB decreases. Therefore, the retention capability of the memory cell connected to the word line WL0 located at the lowest part of the via can be minimal, and the retention capability of the memory cell connected to the word line WLn located at the highest part of the via can be maximum. On the other hand, the retention capability of the memory cell located at the end of the via may be reduced due to manufacturing process limitations, etc. Based on the characteristics of this physical structure, the aforementioned grouping of weak word lines WWL and strong word lines SWL can be performed.

[0113] Figure 15 and Figure 16This is a diagram illustrating the retention characteristics of a block reclamation method in a storage device according to an example embodiment.

[0114] In example embodiments, such as Figure 15 As shown, word lines WL0 to WLk arranged in the lower portion of the channel hole can be identified as weak word lines WWL, and word lines WLk+1 to WLn arranged in the upper portion of the channel hole can be identified as strong word lines SWL.

[0115] In example embodiments, such as Figure 16 As shown, word lines WL0 to WLk and WLm+1 to WLn at the end portions of the channel holes arranged in the vertical direction D3 can be identified as weak word lines WWL, and word lines WLk+1 to WLm at the central portion between the ends of the channel holes arranged in the vertical direction D3 can be identified as strong word lines SWL.

[0116] Figure 17 This is a diagram illustrating the change retention characteristic information in a block reclamation method in a storage device according to an example embodiment.

[0117] refer to Figure 17 As the retention characteristics of each memory block deteriorate, the number of weak word lines (WWLs) can be increased and the number of strong word lines (SWLs) can be decreased. In an example embodiment, the retention characteristics of a memory block can be represented by the program-erase count (NPE). As the program-erase count (NPE) of a memory block increases, the degradation of the retention characteristics of the memory block may increase. For example, as... Figure 17 As shown, when the programmable erase count (NPE) is less than the reference value No, three word lines WL0 to WL2 can be designated as weak word lines (WWL), and five word lines WL3 to WL7 can be designated as strong word lines (SWL). Subsequently, when the programmable erase count (NPE) exceeds the reference value No, five word lines WL0 to WL4 can be designated as weak word lines (WWL), and three word lines WL5 to WL7 can be designated as strong word lines (SWL).

[0118] Figure 18 This is a diagram illustrating a programming method in a storage device according to an example embodiment.

[0119] refer to Figure 18 Depending on the operating scenario of the non-volatile memory device, write or programming operations can be performed sequentially from the top word line downwards. In this case, as data is added to the memory block, it is filled in order from top to bottom (T2B).

[0120] The memory cells MC1 to MC7 with erase word lines are in erase state E0, and the memory cells MC8 to MC12 with program word lines can have erase state E0 or corresponding program states P1, P2 and P3, depending on the stored data.

[0121] Figure 19 and Figure 20 This is a diagram illustrating the execution sequence of a block reclamation method in a storage device according to an example embodiment.

[0122] refer to Figure 19 After performing an internal copy operation on the strong word line (SWL) of the source block SBL, an external copy operation on the weak word line (WWL) of the source block SBL can be performed. During block reclamation, garbage collection can be performed simultaneously to discard invalid data (shaded area) stored in the source block SBL, and only valid data stored in the source block SBL is stored in the destination block DBL.

[0123] As a result, when adopting Figure 18 During the T2B programming sequence, the valid data corresponding to word lines WL7, WL5, WL4, WL3, WL1 and WL0 of the source block SBL can be stored in the memory cells connected to word lines WL7 to WL2 of the destination block DBL.

[0124] refer to Figure 20 After performing an external copy operation on the weak word line WWL of the source block SBL, an internal copy operation on the strong word line SWL of the source block SBL can be performed. Therefore, the data read from the external copy operation can be primarily stored in the memory cells connected to the strong word line SWL of the destination block DBL, and the data read from the internal copy operation can then be stored in the destination block DBL.

[0125] With this configuration and operation, error accumulation can be reduced or prevented by reducing or preventing the continuous application of internal copy operations to the same data without error correction while recycling duplicate blocks.

[0126] Figure 21 This is a diagram illustrating a programming method in a storage device according to an example embodiment. For simplicity, details related to... Figure 18 Repeated description.

[0127] refer to Figure 21 Depending on the operating scenario of the non-volatile memory device, write or programming operations can be performed sequentially from the bottom word line upwards. In this case, as the data stored in the memory block increases, the data is filled in order from bottom to top (T2B).

[0128] Memory cells MC5 to MC12 with erase word lines are in erase state E0, and memory cells MC1 to MC4 with program word lines can be in erase state E0 or one of programming states P1, P2, and P3, depending on the stored data. Even when applications... Figure 21 When programming B2T sequentially, one can also selectively apply, for example... Figure 19 or Figure 20 The execution order of block reclamation.

[0129] Figure 22 This is a circuit diagram illustrating the structure of a memory cell array included in a non-volatile memory device according to an example embodiment, and Figure 23 This illustrates the relationship between the example embodiment and... Figure 22 The diagram shows the memory block corresponding to the structure.

[0130] For ease of explanation and description, Figure 22 The diagram illustrates NAND strings or cell strings STR1 to STRm within a memory block, connected to a bit line BL and a common source line CSL. However, in some example embodiments, the memory block may have, as shown in the reference... Figure 6 and Figure 7 The described three-dimensional structure.

[0131] refer to Figure 22 The memory block may include multiple cell strings STR1 to STRm connected between the same bit line BL and common source line CSL. Each of the cell strings STR1 to STRm may include string select transistors SST1 to SSTm controlled by string select lines SSL1 to SSLm, memory cells controlled by word line WL, intermediate switch transistors MST1 to MSTm controlled by intermediate switch line MSL, and ground select transistors GST1 to GSTm controlled by ground select line GSL. Memory cells connected to at least one word line located at both ends of the vertical direction D3 of the first stack ST1 and the second stack ST2 may be dummy cells. Data may not be stored in dummy cells. In some example embodiments, dummy cells may be configured to store fewer bits of data than other memory cells.

[0132] although Figure 22 An example embodiment is shown where ground select transistors are connected to the same ground select line GSL; however, many ground select transistors can be connected to each of multiple ground select lines. In some example embodiments, the number of ground select transistors connected to each of the ground select lines can be predetermined.

[0133] In example embodiments, such as Figure 23As shown, the boundary layer BND may include a gate line. A gate line corresponds to an intermediate switch line MSL and can simultaneously switch intermediate switch transistors MSL1 to MSLm connected to it. According to an example embodiment, the boundary layer BND may include two or more gate lines.

[0134] Figure 24 This is a cross-sectional view showing a boundary layer included in a non-volatile memory device according to an example embodiment.

[0135] Reference Figure 24 Each channel via forming each cell string may include a first sub-channel via 810 and a second sub-channel via 710. The first sub-channel via 810 may include a channel film 811, an internal material 812, and an insulating film 813. The second sub-channel via 710 may include a channel film 711, an internal material 712, and an insulating film 713. The channel film 811 of the first sub-channel via 810 and the channel film 711 of the second sub-channel via 710 can be SIP connected via P-type silicon pads. These plurality of sub-channel vias 810 and 710 may be formed using stop lines GTL5 with appropriate etch selectivity. For example, to achieve appropriate etch selectivity, the stop line GTL5 may be formed of polysilicon, and the remaining gate lines GTL1 to GTL4 and GTL6 to GTL8 may be formed of a metal such as tungsten. Depending on the doping concentration of the polysilicon, the resistance of the stop line GTL5 may be significantly greater than that of the remaining gate lines GTL1 to GTL4 and GTL6 to GTL8 by approximately 6 times.

[0136] The boundary layer between the aforementioned stacks may correspond to a stop layer GTL5 for progressively forming a plurality of sub-channel vias that form channel vias in a cell string. The cells of the stop layer may not be suitable for storing data, and the stop layer may be used as a boundary layer for forming intermediate switching transistors according to an example embodiment. One or more gate line layers perpendicularly adjacent to the stop layer GTL5 in the vertical direction D3 may be further included in the boundary layer. The intermediate switching transistors formed in the boundary layer may be implemented as either cell-type or transistor-type. Here, cell-type refers to a cell including a floating gate, such as a flash memory cell, and transistor-type refers to a cell omitting the floating gate.

[0137] refer to Figure 24 An example of each channel hole comprising two sub-channel holes is described, but the example embodiment is not limited thereto. According to the example embodiment, each channel hole may include three or more sub-channel holes stacked in the vertical direction D3.

[0138] Figure 25 This is a diagram illustrating a memory block included in a non-volatile memory device according to an example embodiment.

[0139] refer to Figure 25 The aforementioned boundary layer may include a lower boundary layer BNDL and an upper boundary layer BNDU. The memory block MB8 includes a first stack ST1 disposed below the lower boundary layer BNDL, a second stack ST2 disposed between the lower boundary layer BNDL and the upper boundary layer BNDU, and a third stack ST3 disposed above the upper boundary layer BNDU.

[0140] The aforementioned intermediate switching transistor includes a plurality of lower switching transistors disposed on the lower boundary layer BNDL and connected to the lower switching line LSL, and a plurality of upper switching transistors disposed on the upper boundary layer BNDU and connected to the upper switching line USL.

[0141] Figure 26 This is a diagram illustrating the retention characteristics and retention characteristic information of a non-volatile memory device according to an example embodiment.

[0142] Figure 26 An example is shown in which each channel hole CHH includes three sub-channel holes SCH1, SCH2, and SCH3 stacked in the vertical direction D3. Figure 26 In the diagram, WL# represents the word line number, with smaller word line numbers (WL#) corresponding to the word line located below the channel hole (CHH). NEB represents the number of error bits, and ta and tb represent the time elapsed after a write operation to the memory block. The second elapsed time tb is greater than the first elapsed time ta, and the number of error bits NEB increases with the elapsed time.

[0143] like Figure 26 As shown, for each of the sub-channel holes SCH1, SCH2, and SCH3, the number of error bits (NEB) at the bottom of the sub-channel hole increases. The number of error bits (NEB) at the boundary portions of sub-channel holes SCH1, SCH2, and SCH3 increases more than in the middle. Considering the retention characteristics caused by this physical structure, the word lines of each sub-channel hole of the multiple sub-channel holes SCH1, SCH2, and SCH3 can be grouped into weak word lines (WWL) and strong word lines (SWL).

[0144] Figure 27 This is a flowchart illustrating the determination of source blocks in a block reclamation method in a storage device according to an example embodiment, and Figure 28 This illustrates the relationship between the example embodiment and... Figure 27 The method corresponds to the graph of source block determination information.

[0145] refer to Figure 1 , Figure 27 and Figure 28The Recycle Manager (RCM) can monitor the elapsed time Te (S51) after a write operation is completed for each memory block BLi in multiple memory blocks. The RCM can store and manage Source Block Identification Information (SBDI), which includes the monitored elapsed times t0 to t3 for each of the memory blocks BL0 to BL3, such as... Figure 28 As shown.

[0146] The Recycler Manager (RCM) can determine whether the elapsed time Te is greater than or equal to the reference time Tr (S52). If the elapsed time Te is greater than or equal to the reference time Tr (S52: Yes), the Recycler Manager (RCM) can identify the corresponding memory block BLi as the source block SBL (S53). If the elapsed time Te is less than the reference time Tr (S52: No), the Recycler Manager (RCM) can return to the monitoring in S51.

[0147] Figure 29 This is a flowchart illustrating the determination of source blocks in a block reclamation method in a storage device according to an example embodiment, and Figure 30 This illustrates the relationship between the example embodiment and... Figure 29 The method corresponds to the graph of source block determination information.

[0148] refer to Figure 1 , Figure 29 and Figure 30 The Recycler Manager (RCM) can monitor the number of reads (Nrop) that have been performed on each of the multiple memory blocks (BL0 to BL3) (S61). The RCM can store and manage Source Block Determination Information (SBDI), which includes the monitored number of reads (N0 to N3) for each of the memory blocks BL0 to BL3, such as... Figure 30 As shown.

[0149] The Recycler Manager (RCM) determines whether the number of reads, Nrop, is greater than or equal to the reference number, Nr (S62). If the number of reads, Nrop, is greater than or equal to the reference number, Nr (S62: Yes), the Recycler Manager (RCM) identifies the corresponding memory block BLi as the source block (SBL) (S63). If the number of reads, Nrop, is less than the reference number, Nr (S62: No), the Recycler Manager (RCM) returns to the monitoring in S61.

[0150] Figure 31 This is a block diagram illustrating a data center including storage devices according to an example embodiment.

[0151] In some example embodiments, the above references Figures 1 to 30The described storage device can be used as an application server and / or storage server, and can be included in a data center 4000.

[0152] refer to Figure 31 A Data Center 4000 can collect various data and provide services, and is also known as a data storage center. For example, a Data Center 4000 could be a system configured to operate a search engine and database, or a computing system used by a company (such as a bank or government agency). Figure 31 As shown, data center 4000 may include application servers 50_1 to 50_n and storage servers 60_1 to 60_m (where each of m and n is an integer greater than 1). The number n of application servers 50_1 to 50_n and the number m of storage servers 60_1 to 60_m may be selected differently depending on the example embodiment. In some example embodiments, the number n of application servers 50_1 to 50_n may be different from the number m of storage servers 60_1 to 60_m.

[0153] Application servers 50_1 to 50_n may include any one or any combination of processors 51_1 to 51_n, memory 52_1 to 52_n, switches 53_1 to 53_n, network interface controllers (NICs) 54_1 to 54_n, and storage devices 55_1 to 55_n. In some example embodiments, storage devices 55_1 to 55_n may be as described above. Figure 1-30 The described storage device 10. Processors 51_1 to 51_n can control all operations of application servers 50_1 to 50_n, access memories 52_1 to 52_n, and execute instructions and / or data loaded in memories 52_1 to 52_n. Non-limiting examples of memories 52_1 to 52_n may include DDR SDRAM, high-bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory modules (DIMM), Optane DIMM, and / or non-volatile DIMM (NVDIIMM).

[0154] According to the example embodiments, the number of processors and memory included in application servers 50_1 to 50_n can be selected differently depending on the example embodiments. In some example embodiments, processors 51_1 to 51_n and memory 52_1 to 52_n can provide processor-memory pairs. In some example embodiments, the number of processors 51_1 to 51_n can be different from the number of memory 52_1 to 52_n. Processors 51_1 to 51_n can include single-core processors or multi-core processors. In some example embodiments, such as Figure 31As shown in dashed lines, storage devices 55_1 to 55_n can be omitted from application servers 50_1 to 50_n. The number of storage devices 55_1 to 55_n included in storage servers 50_1 to 50_n can be selected differently depending on the example embodiment. Processors 51_1 to 51_n, memories 52_1 to 52_n, switches 53_1 to 53_n, NICs 54_1 to 54_n, and / or storage devices 55_1 to 55_n can communicate with each other via the links described above with reference to the accompanying drawings.

[0155] Storage servers 60_1 to 60_m may include any one or any combination of processors 61_1 to 61_m, memory 62_1 to 62_m, switches 63_1 to 63_m, network interface controllers (NICs) 64_1 to 64_n, and storage devices 65_1 to 65_m. In some example embodiments, storage devices 65_1 to 65_m may be as described above. Figures 1 to 30 The storage device 10 described. Processors 61_1 to 61_m and memory 62_1 to 62_m can operate similarly to processors 51_1 to 51_n and memory 52_1 to 52_n of the application servers 50_1 to 50_n described above.

[0156] Application servers 50_1 to 50_n can communicate with storage servers 60_1 to 60_m via network 70. In some example embodiments, network 70 can be implemented using Fibre Channel (FC) or Ethernet. FC can be a medium for relatively high-speed data transmission. Optical switches providing high performance and high availability can be used as FC. Storage servers 60_1 to 60_m can be provided as file storage, block storage, or object storage depending on the access method of network 70.

[0157] In some example embodiments, network 70 may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN, which can be implemented using an FC network and the FC protocol (FCP). In another case, the SAN may be an Internet Protocol (IP)-SAN, which uses a Transmission Control Protocol / Internet Protocol (TCP / IP) network and is implemented according to SCSI over TCP / IP or Internet SCSI (iSCSI) protocols. In some example embodiments, network 70 may be a general-purpose network, such as a TCP / IP network. For example, network 70 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), or Network-based Non-Volatile Memory Fast (NVMe) (NVMe-oF).

[0158] The main focus will be on describing application server 50_1 and storage server 60_1. However, it should be noted that the description of application server 50_1 can also be applied to another application server (e.g., 50_n), and the description of storage server 60_1 can also be applied to another storage server (e.g., 60_m).

[0159] Application server 50_1 can store data requested by a user or client in one of storage servers 60_1 to 60_m via network 70. In some example embodiments, application server 50_1 can retrieve data requested by a user or client from one of storage servers 60_1 to 60_m via network 70. For example, application server 50_1 can be implemented using a web server or a database management system (DBMS).

[0160] Application server 50_1 can access, via network 70, the memory 52_n and / or storage device 55_n included in another application server 50_n, and / or via network 70, the memory 62_1 to 62_m and / or storage device 65_1 to 65_m included in storage servers 60_1 to 60_m. Therefore, application server 50_1 can perform various operations on data stored in application servers 50_1 to 50_n and / or storage servers 60_1 to 60_m. For example, application server 50_1 can execute instructions to migrate or copy data between application servers 50_1 to 50_n and / or storage servers 60_1 to 60_m. In this case, data can be migrated from the memory 62_1 to 62_m of storage servers 60_1 to 60_m or directly from the storage devices 65_1 to 65_m of storage servers 60_1 to 60_m to the memory 52_1 to 52_n of application servers 50_1 to 50_n. In some example embodiments, the data migrated over network 70 may be encrypted data for security or privacy purposes.

[0161] In storage server 60_1, interface IF can provide physical connections between processor 61_1 and controller CTRL, and between NIC 64_1 and controller CTRL. For example, interface IF can be implemented using a Direct Attached Storage (DAS) method where storage device 65_1 is directly connected to a dedicated cable. For example, interface IF can be implemented using various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), PCI, PCIe, NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded MMC (eMMC), UFS, Embedded UFS (eUFS), and / or Compact Flash Memory (CF) card interfaces.

[0162] In storage server 60_1, switch 63_1 can selectively connect processor 61_1 to storage device 65_1 or selectively connect NIC 64_1 to storage device 65_1 based on the control of processor 61_1.

[0163] In some example embodiments, the network interface controller (NIC) 64_1 may include a network interface card and a network adapter. NIC 64_1 can connect to network 70 via a wired interface, wireless interface, Bluetooth interface, or optical interface. NIC 64_1 may include internal memory, a digital signal processor (DSP), and a host bus interface and is connected to processor 61_1 and / or switch 63_1 via the host bus interface. In some example embodiments, NIC 64_1 may be integrated with any one or any combination of processor 61_1, switch 63_1, and storage device 65_1.

[0164] In application servers 50_1 to 50_n or storage servers 60_1 to 60_m, processors 51_1 to 51_m and 61_1 to 61_n can send commands to storage devices 55_1 to 55_n and 65_1 to 65_m or memories 52_1 to 52_n and 62_1 to 62_m and program or read data. In this case, the data can be data whose errors have been corrected by error-correcting code (ECC) circuitry. The data can be data processed using Data Bus Inversion (DBI) or Data Masking (DM) and includes Cyclic Redundancy Check (CRC) information. The data can be encrypted data for security or privacy purposes.

[0165] In response to a read command received from processors 51_1 to 51_m and 61_1 to 61_n, storage devices 55_1 to 55_n and 65_1 to 65_m can send control signals and command / address signals to a non-volatile memory device (e.g., a NAND flash memory device) NVM. Therefore, when reading data from the non-volatile memory device NVM, a read enable signal can be input as a data output control signal to output data to the DQ bus. The read enable signal can be used to generate a data strobe signal. The command and address signals can be latched based on the rising or falling edge of the write enable signal.

[0166] The controller CTRL can control all operations of storage device 65_1. In an example embodiment, the controller CTRL may include static RAM (SRAM). The controller CTRL can write data to the non-volatile storage device NVM in response to a write command, or read data from the non-volatile storage device NVM in response to a read command. For example, write and / or read commands can be generated based on requests provided from a host (e.g., processor 61_1 of storage server 60_1, processor 61_m of another storage server 60_m, or processors 51_1 to 51_n of application servers 50_1 to 50_n). The buffer BUF can temporarily store (or buffer) data to be written to or read from the non-volatile storage device NVM. In some example embodiments, the buffer BUF may include DRAM. The buffer BUF may store metadata. Metadata may refer to user data or data generated by the controller CTRL to manage the non-volatile storage device NVM. Storage device 65_1 may include a security element (SE) for security or privacy.

[0167] Figure 32 This is a cross-sectional view showing a non-volatile memory device according to an example embodiment.

[0168] refer to Figure 32 The memory device 5000 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell region and a lower chip including a peripheral circuit region (PREG) can be fabricated separately. The at least one upper chip and the lower chip can then be connected to each other by a bonding method to realize the C2C structure. For example, the bonding method may refer to a method of electrically and / or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, if the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively or otherwise, the bonding metal pattern may be formed of other metals, including but not limited to aluminum (Al) or tungsten (W).

[0169] The memory device 5000 may include at least one on-chip, said at least one on-chip including cell regions. For example, such as Figure 32 As shown, the memory device 5000 may include two upper chips. However, the number of upper chips is not limited to this. In the case where the memory device 5000 includes two upper chips, a first upper chip that may include a first cell region CREG1, a second upper chip that may include a second cell region CREG2, and a lower chip that may include a peripheral circuit region PREG can be manufactured separately. Subsequently, for example, the first upper chip, the second upper chip, and the lower chip can be connected to each other by a bonding method to manufacture the memory device 5000. In some example embodiments, the first upper chip can be flipped and then connected to the lower chip by a bonding method, and the second upper chip can also be flipped and then connected to the first upper chip by a bonding method. Hereinafter, the upper portion and lower portion of each of the first and second upper chips will be defined based on each of the first and second upper chips before they are flipped. In other words, the upper portion of the lower chip may refer to the upper portion defined based on the +Z axis direction, and the upper portion of each of the first and second upper chips may refer to the upper portion defined based on the +Z axis direction. Figure 32 The upper part is defined by the -Z axis direction. However, this disclosure is not limited thereto. For example, in some example embodiments, one of the first upper chip and the second upper chip can be flipped and then connected to the corresponding chip by a bonding method.

[0170] Each of the peripheral circuit region PREG and the first cell region CREG1 and the second cell region CREG2 of the memory device 5000 may include an external pad bonding region PA, a word line bonding region WLBA and a bit line bonding region BLBA.

[0171] The peripheral circuit region PREG may include a first substrate 5210 and a plurality of circuit elements (e.g., first circuit element 5220a, second circuit element 5220b, and third circuit element 5220c) formed on the first substrate 5210. An interlayer insulating layer 5215 including one or more insulating layers may be disposed on the plurality of circuit elements 5220a, 5220b, and 5220c, and a plurality of metal wires electrically connected to the plurality of circuit elements 5220a, 5220b, and 5220c may be disposed in the interlayer insulating layer 5215. For example, the plurality of metal wires may include first metal wires 5230a, 5230b, and 5230c connected to the plurality of circuit elements 5220a, 5230b, and 5220c, and second metal wires 5240a, 5240b, and 5240c formed on the first metal wires 5230a, 5230b, and 5230c. The plurality of metal wires may be formed of at least one of a variety of conductive materials. In some example embodiments, the first metal lines 5230a, 5230b and 5230c may be formed of tungsten, which has a relatively high resistivity, and the second metal lines 5240a, 5240b and 5240c may be formed of copper, which has a relatively low resistivity.

[0172] This exemplary embodiment illustrates and describes first metal lines 5230a, 5230b, and 5230c, and second metal lines 5240a, 5240b, and 5240c. However, this disclosure is not limited thereto. For example, in some exemplary embodiments, at least one or more additional metal lines may be further formed on the second metal lines 5240a, 5240b, and 5240c. In this case, the second metal lines 5240a, 5240b, and 5240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 5240a, 5240b, and 5240c may be formed of copper, which has a resistivity lower than that of aluminum in the second metal lines 5240a, 5240b, and 5240c.

[0173] An interlayer insulating layer 5215 may be disposed on a first substrate 5210 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0174] Each cell region in the first cell region CREG1 and the second cell region CREG2 may include at least one memory block. The first cell region CREG1 may include a second substrate 5310 and a common source line 5320. A plurality of word lines 5330 (e.g., 5331 to 5338) may be stacked on the second substrate 5310 in a direction perpendicular to the top surface of the second substrate 5310 (e.g., the Z-axis direction). Serial select lines and ground select lines may be disposed above and below the word lines 5330, and a plurality of word lines 5330 may be disposed between the serial select lines and the ground select lines. Alternatively or additionally, the second cell region CREG2 may include a third substrate 5410 and a common source line 5420, and a plurality of word lines 5430 (e.g., 5431 to 5438) may be stacked on the third substrate 5410 in a direction perpendicular to the top surface of the third substrate 5410 (e.g., the Z-axis direction). Each of the second substrate 5310 and the third substrate 5410 may be formed of at least one of a variety of materials, such as, but not limited to, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystal epitaxial layer grown on a single-crystal silicon substrate. Multiple channel structures CH may be formed in each of the first unit region CREG1 and the second unit region CREG2.

[0175] In some example embodiments, as shown in region "A1", a channel structure CH may be disposed in a bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 5310 to penetrate word line 5330, serial select line, and ground select line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to a first metal line 5350c and a second metal line 5360c in the bit line bonding region BLBA. For example, the second metal line 5360c may be a bit line and may be connected to the channel structure CH via the first metal line 5350c. The bit line 5360c may extend in a first direction (e.g., the Y-axis direction) parallel to the top surface of the second substrate 5310.

[0176] In some exemplary embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH that can be connected to each other. For example, the channel structure CH may be formed by a process for forming the lower channel LCH and a process for forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 5310 to penetrate the common source line 5320 and the lower word lines 5331 and 5332. The lower channel LCH may include a data storage layer, a channel layer, and a fill insulating layer and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 5333 to 5338. The upper channel UCH may include a data storage layer, a channel layer, and a fill insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 5350c and the second metal line 5360c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. The memory device 5000 according to this disclosure may include channels with improved width uniformity due to the lower channel LCH and upper channel UCH formed by sequentially performed processes.

[0177] In cases where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in region "A2", the word lines located near the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. For example, word lines 5332 and 5333 adjacent to the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively or otherwise, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the general word lines. The voltage level applied to the dummy word lines may differ from the voltage level applied to the general word lines, and therefore, it is possible to reduce the impact of the non-uniform channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device.

[0178] In some example embodiments, in region 'A2', the number of lower word lines 5331 and 5332 penetrated by the lower channel LCH may be less than the number of upper word lines 5333 to 5338 penetrated by the upper channel UCH. However, this disclosure is not limited thereto. For example, in some example embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. Alternatively or additionally, the structural features and connection relationships of the channel structure CH disposed in the second unit region CREG2 may be substantially the same as those of the channel structure CH disposed in the first unit region CREG1.

[0179] In the bit line bonding region BLBA, the first through-electrode THV1 can be disposed in the first cell region CREG1, and the second through-electrode THV2 can be disposed in the second cell region CREG2. For example... Figure 32 As shown, the first through electrode THV1 can penetrate the common source line 5320 and multiple word lines 5330. In some example embodiments, the first through electrode THV1 can further penetrate the second substrate 5310. The first through electrode THV1 may include a conductive material. Alternatively or additionally, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0180] In some example embodiments, the first through electrode THV1 and the second through electrode THV2 can be electrically connected to each other via a first through metal pattern 5372d and a second through metal pattern 5472d. The first through metal pattern 5372d can be formed at the bottom of a first upper chip including a first cell region CREG1, and the second through metal pattern 5472d can be formed at the top of a second upper chip including a second cell region CREG2. The first through electrode THV1 can be electrically connected to a first metal line 5350c and a second metal line 5360c. A lower via 5371d can be formed between the first through electrode THV1 and the first through metal pattern 5372d, and an upper via 5471d can be formed between the second through electrode THV2 and the second through metal pattern 5472d. The first through metal pattern 5372d and the second through metal pattern 5472d can be connected to each other by a bonding method.

[0181] In some example embodiments, in the bit line bonding region BLBA, an upper metal pattern 5252 may be formed in the uppermost metal layer of the peripheral circuit region PERI, and an upper metal pattern 5392 having the same shape as the upper metal pattern 5252 may be formed in the uppermost metal layer of the first cell region CREG1. The upper metal pattern 5392 of the first cell region CREG1 and the upper metal pattern 5252 of the peripheral circuit region PREG may be electrically connected to each other by a bonding method. In the bit line bonding region BLBA, bit lines 5360c may be electrically connected to page buffers included in the peripheral circuit region PERI. For example, some circuit elements 5220c of the peripheral circuit region PREG may constitute page buffers, and bit lines 5360c may be electrically connected to the circuit elements 5220c constituting page buffers through the upper bonding metal pattern 5370c of the first cell region CREG1 and the upper bonding metal pattern 5270c of the peripheral circuit region PERI.

[0182] Continue to refer to Figure 32In the word line bonding region WLBA, the word line 5330 of the first cell region CREG1 can extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 5310 and can be connected to a plurality of cell contact plugs 5340 (e.g., 5341 to 5347). A first metal line 5350b and a second metal line 5360b can be sequentially connected to the cell contact plugs 5340 connected to the word line 5330. In the word line bonding region WLBA, the cell contact plugs 5340 can be connected to the peripheral circuit region PREG via the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PERI.

[0183] Cell contact plug 5340 can be electrically connected to a line decoder included in the peripheral circuitry region PERI. For example, some of the circuit elements 5220b in the peripheral circuitry region PREG can constitute a line decoder, and cell contact plug 5340 can be electrically connected to the circuit elements 5220b constituting the line decoder via the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuitry region PERI. In some example embodiments, the operating voltage of the circuit elements 5220b constituting the line decoder can be different from the operating voltage of the circuit elements 5220c constituting the page buffer. For example, the operating voltage of the circuit elements 5220c constituting the page buffer can be greater than the operating voltage of the circuit elements 5220b constituting the line decoder.

[0184] In some example embodiments, in the word line bonding region WLBA, the word line 5430 of the second cell region CREG2 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 5410, and may be connected to a plurality of cell contact plugs 5440 (e.g., 5441 to 5447). The cell contact plugs 5440 may be connected to the peripheral circuit region PREG via the upper metal pattern of the second cell region CREG2, the lower and upper metal patterns of the first cell region CREG1, and the cell contact plug 5348.

[0185] In the word line bonding region WLBA, an upper bonding metal pattern 5370b can be formed in the first cell region CREG1, and an upper bonding metal pattern 5270b can be formed in the peripheral circuit region PERI. The upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG can be electrically connected to each other by bonding. The upper bonding metal patterns 5370b and 5270b can be formed of at least one metal, including but not limited to aluminum, copper, and tungsten.

[0186] In the external pad bonding area PA, a lower metal pattern 5371e can be formed in the lower part of the first cell region CREG1, and an upper metal pattern 5472a can be formed in the upper part of the second cell region CREG2. The lower metal pattern 5371e of the first cell region CREG1 and the upper metal pattern 5472a of the second cell region CREG2 can be connected to each other in the external pad bonding area PA by a bonding method. In some example embodiments, the upper metal pattern 5372a can be formed in the upper part of the first cell region CREG1, and the upper metal pattern 5272a can be formed in the upper part of the peripheral circuit region PERI. The upper metal pattern 5372a of the first cell region CREG1 and the upper metal pattern 5272a of the peripheral circuit region PREG can be connected to each other by a bonding method.

[0187] Common source line contact plugs 5380 and 5480 can be disposed in the external pad bonding region PA. Common source line contact plugs 5380 and 5480 can be formed of conductive materials such as metals, metal compounds, and / or doped polysilicon. Common source line contact plug 5380 of the first unit region CREG1 can be electrically connected to common source line 5320, and common source line contact plug 5480 of the second unit region CREG2 can be electrically connected to common source line 5420. First metal line 5350a and second metal line 5360a can be sequentially stacked on common source line contact plug 5380 of the first unit region CREG1, and first metal line 5450a and second metal line 5460a can be sequentially stacked on common source line contact plug 5480 of the second unit region CREG2.

[0188] Input / output pads 5205, 5405, and 5406 can be set in the external pad bonding area PA. For example... Figure 32 As shown, the lower insulating layer 5201 may cover the bottom surface of the first substrate 5210, and the first input / output pad 5205 may be formed on the lower insulating layer 5201. The first input / output pad 5205 may be connected to at least one of a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG via the first input / output contact plug 5203, and may be separated from the first substrate 5210 via the lower insulating layer 5201. Alternatively or additionally, a side insulating layer may be disposed between the first input / output contact plug 5203 and the first substrate 5210 to electrically isolate the first input / output contact plug 5203 from the first substrate 5210.

[0189] An upper insulating layer 5401 covering the top surface of the third substrate 5410 may be formed on the third substrate 5410. A second input / output pad 5405 and / or a third input / output pad 5406 may be disposed on the upper insulating layer 5401. The second input / output pad 5405 may be connected to at least one of a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG via second input / output contact plugs 5403 and 5303, and the third input / output pad 5406 may be connected to at least one of a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG via third input / output contact plugs 5404 and 5304.

[0190] In some example embodiments, the third substrate 5410 may not be disposed in the region where the input / output contact plug is disposed. For example, as shown in region "B", the third input / output contact plug 5404 may be separated from the third substrate 5410 in a direction parallel to the top surface of the third substrate 5410 and may penetrate the interlayer insulating layer 5415 of the second cell region CREG2 to connect to the third input / output pad 5406. In this case, the third input / output contact plug 5404 may be formed by at least one of various processes.

[0191] In some example embodiments, as shown in region "B1", the third input / output contact plug 5404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 5404 may gradually increase (e.g., widen) toward the upper insulating layer 5401. In other words, the diameter of the channel structure CH described in region "A1" may gradually decrease (e.g., become narrower) toward the upper insulating layer 5401, but the diameter of the third input / output contact plug 5404 may gradually increase toward the upper insulating layer 5401. For example, the third input / output contact plug 5404 may be formed after the second cell region CREG2 and the first cell region CREG1 are bonded to each other by a bonding method.

[0192] In some example embodiments, as shown in region "B2", the third input / output contact plug 5404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 5404 may gradually decrease (e.g., narrow) towards the upper insulating layer 5401. In other words, like the channel structure CH, the diameter of the third input / output contact plug 5404 may gradually decrease (e.g., narrow) towards the upper insulating layer 5401. For example, the third input / output contact plug 5404 may be formed together with the cell contact plug 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other.

[0193] In some example embodiments, the input / output contact plugs may overlap with the third substrate 5410. For example, as shown in region "C", the second input / output contact plug 5403 may penetrate the interlayer insulating layer 5415 of the second cell region CREG2 in a third direction (e.g., the Z-axis direction) and may be electrically connected to the second input / output pad 5405 through the third substrate 5410. In this case, the connection structure of the second input / output contact plug 5403 and the second input / output pad 5405 can be implemented by various methods.

[0194] In some exemplary embodiments, as shown in region "C1", an opening 5408 may be formed to penetrate the third substrate 5410, and the second input / output contact plug 5403 may be directly connected to the second input / output pad 5405 through the opening 5408 formed in the third substrate 5410. In this case, as shown in region "C1", the diameter of the second input / output contact plug 5403 may gradually increase (e.g., widen) toward the second input / output pad 5405. However, this disclosure is not limited thereto. For example, in some example embodiments, the diameter of the second input / output contact plug 5403 may gradually decrease (e.g., narrow) toward the second input / output pad 5405.

[0195] In some exemplary embodiments, as shown in region "C2", an opening 5408 penetrating the third substrate 5410 may be formed, and a contact 5407 may be formed in the opening 5408. One end of the contact 5407 may be connected to the second input / output pad 5405, and the other end of the contact 5407 may be connected to the second input / output contact plug 5403. Therefore, the second input / output contact plug 5403 can be electrically connected to the second input / output pad 5405 through the contact 5407 in the opening 5408. In this case, as shown in region "C2", the diameter of the contact 5407 may gradually increase (e.g., become wider) toward the second input / output pad 5405, and the diameter of the second input / output contact plug 5403 may gradually decrease (e.g., become narrower) toward the second input / output pad 5405. For example, the second input / output contact plug 5403 may be formed together with the cell contact plug 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other, and the contact 5407 may be formed after the second cell region CREG2 and the first cell region CREG1 are bonded to each other.

[0196] In some exemplary embodiments shown in region "C3", compared to the exemplary embodiments in region "C2", a stopper structure 5409 may be further formed on the bottom end of the opening 5408 of the third substrate 5410. The stopper structure 5409 may be a metal line formed in the same layer as the common source line 5420. Alternatively or additionally, the stopper structure 5409 may be a metal line formed in the same layer as at least one of the word lines 5430. The second input / output contact plug 5403 may be electrically connected to the second input / output pad 5405 via the contact 5407 and the stopper structure 5409.

[0197] Similar to the second input / output contact plug 5403 and the third input / output contact plug 5404 of the second unit region CREG2, the diameter of each of the second input / output contact plug 5303 and the third input / output contact plug 5304 of the first unit region CREG1 may gradually decrease (e.g., narrower) and / or may gradually increase (e.g., wider) towards the lower metal pattern 5371e.

[0198] In some example embodiments, slit 5411 may be formed in the third substrate 5410. For example, slit 5411 may be formed at a location in the outer pad bonding region PA. For example, as shown in region "D", when viewed in a plan view, slit 5411 may be located between the second input / output pad 5405 and the cell contact plug 5440. Alternatively or additionally, when viewed in a plan view, the second input / output pad 5405 may be located between slit 5411 and the cell contact plug 5440.

[0199] In some exemplary embodiments, as shown in region "D1", slit 5411 may be formed to penetrate the third substrate 5410. For example, slit 5411 may be used to prevent the third substrate 5410 from slightly cracking during the formation of opening 5408. However, this disclosure is not limited thereto. For example, in some example embodiments, slit 5411 may be formed to have a depth ranging from about 60% to about 70% of the thickness of the third substrate 5410.

[0200] In some exemplary embodiments, as shown in region 'D2', conductive material 5412 may be formed in slit 5411. For example, conductive material 5412 may be used to discharge leakage current occurring during the driving of circuit elements in the external pad bonding region PA to the outside. In this case, conductive material 5412 may be connected to an external ground wire.

[0201] In some exemplary embodiments, as shown in region "D3", an insulating material 5413 may be formed in the slit 5411. For example, the insulating material 5413 may be used to electrically isolate the second input / output pads 5405 and the second input / output contact plugs 5403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Because the insulating material 5413 is formed in the slit 5411, the voltage supplied through the second input / output pads 5405 can be prevented from affecting the metal layer disposed on the third substrate 5410 in the word line bonding region WLBA.

[0202] In some example embodiments, first input / output pads to third input / output pads 5205, 5405, and 5406 may be selectively formed. For example, memory device 5000 may be implemented to include only the first input / output pad 5205 disposed on the first substrate 5210, only the second input / output pad 5405 disposed on the third substrate 5410, and / or only the third input / output pad 5406 disposed on the upper insulating layer 5401.

[0203] In some example embodiments, at least one of the second substrate 5310 of the first cell region CREG1 and the third substrate 5410 of the second cell region CREG2 can be used as a sacrificial substrate and can be completely and / or partially removed before and / or after the bonding process. Additional layers can be stacked after substrate removal. For example, the second substrate 5310 of the first cell region CREG1 can be removed before and / or after the bonding process of the peripheral circuit region PREG and the first cell region CREG1. Subsequently, an insulating layer or a conductive layer for connection can be formed covering the top surface of the common source line 5320. Similarly, the third substrate 5410 of the second cell region CREG2 can be removed before and / or after the bonding process of the first cell region CREG1 and the second cell region CREG2, and subsequently, an upper insulating layer 5401 or a conductive layer for connection can be formed covering the top surface of the common source line 5420.

[0204] Figure 33 This is a diagram used to describe the manufacturing process of a stacked semiconductor device according to an example embodiment.

[0205] refer to Figure 33 The corresponding integrated circuits can be formed on the first wafer WF1 and the second wafer WF2. The memory cell array can be formed in the first wafer WF1, and the peripheral circuits can be formed in the second wafer WF2.

[0206] After various integrated circuits have been formed on the first wafer WF1 and the second wafer WF2 respectively, the first wafer WF1 and the second wafer WF2 can be bonded together. The bonded wafers WF1 and WF2 can then be diced (or partitioned) into individual chips, each chip corresponding to a semiconductor device, such as, for example, a non-volatile memory device 5000, comprising a vertically stacked first semiconductor die SD1 and a second semiconductor die SD2 (e.g., the first semiconductor die SD1 is stacked on the second semiconductor die SD2, etc.). Each diced portion of the first wafer WF1 corresponds to the first semiconductor die SD1, and each diced portion of the second wafer WF2 corresponds to the second semiconductor die SD2. Figure 32 The memory device can be based on Figure 33 Manufacturing process.

[0207] As described above, the storage device and block reclamation method according to the exemplary embodiments can effectively prevent or reduce the occurrence of uncorrectable errors and improve the reliability and performance of the storage device by selectively performing external copy-back operations or internal copy-back operations based on the retention characteristics of the physical location of the word lines.

[0208] Various example embodiments can be applied to any electronic device and system, including non-volatile memory devices. For example, various example embodiments can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMC), universal flash memory (UFS), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptops, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, automotive driving systems, and so on.

[0209] The foregoing is illustrative of various exemplary embodiments and should not be construed as limiting them. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without substantially departing from the scope defined by the appended claims.

Claims

1. A method for block reclamation in a storage device, the storage device comprising a non-volatile memory device and a memory controller for controlling the non-volatile memory device, the method comprising: Select the source block to be used as the target for block reclamation from among the multiple memory blocks included in the non-volatile memory device; Based on the preservation characteristics of the physical positions of the multiple word lines of the source block, the multiple word lines are grouped into weak word lines and strong word lines; An external copy-back operation is performed on the weak character line, and the external copy-back operation includes error correction; as well as An internal copy-back operation is performed on the strong text line, which does not include the error correction.

2. The method according to claim 1, wherein, Performing the external copy-back operation includes: transferring read data read from memory cells connected to weak word lines of the source block by the non-volatile memory device to the memory controller, and... In the internal copy-back operation, the non-volatile memory device does not transmit read data read from memory cells connected to the strong word line of the source block to the memory controller.

3. The method according to claim 1, wherein, Performing the external copy operation includes: the memory controller correcting errors in read data read from the memory cell connected to the weak word line of the source block to generate corrected data; the memory controller transmitting the corrected data to the non-volatile memory device; and the non-volatile memory device writing the corrected data into the destination block of the plurality of memory blocks.

4. The method according to claim 1, wherein, Performing the internal copy-back operation includes writing read data, which is read from the memory cell connected to the strong word line of the source block, by the non-volatile memory device to the destination block in the plurality of memory blocks.

5. The method according to claim 1, wherein, Performing the external copy operation includes: the memory controller sequentially transmitting read commands and write commands to the non-volatile memory device, wherein the read command includes a read line address corresponding to a weak word line of the source block, and the write command includes a write line address corresponding to a word line of the destination block among the plurality of memory blocks.

6. The method according to claim 1, wherein, Performing the internal copy-back operation includes: the memory controller transmitting a single command to the non-volatile memory device, wherein the single command includes a read line address corresponding to a strong word line of the source block and a write line address corresponding to a word line of the destination block among the plurality of memory blocks.

7. The method according to claim 1, further comprising: Based on the vertical position of the word lines in the source block, the word lines of the source block are determined to be weak word lines or strong word lines.

8. The method according to claim 1, wherein, The plurality of word lines of the source block are connected to memory cells stacked in a vertical direction and formed in a plurality of channel holes extending in the vertical direction, and the method further includes determining the word lines as weak word lines or strong word lines based on the height of the word lines of the source block in the vertical direction.

9. The method according to claim 8, wherein, The channel holes in the plurality of channel holes include a plurality of sub-channel holes stacked in the vertical direction, and The multiple word lines of the source block are grouped into weak word lines and strong word lines for each sub-channel aperture.

10. The method according to claim 8, wherein, The word lines arranged at the lower part of the plurality of channel holes are identified as the weak word lines, and the word lines arranged at the upper part of the plurality of channel holes are identified as the strong word lines.

11. The method according to claim 8, wherein, The word lines arranged at the ends of the plurality of channel holes are identified as the weak word lines, and the word lines arranged in the middle between the ends are identified as the strong word lines.

12. The method according to claim 1, wherein, After completing the external copy operation for the weak word line of the source block, the internal copy operation for the strong word line of the source block is performed.

13. The method according to claim 12, wherein, The read data read via the external copy-back operation is stored in the strong word line of the destination block in the plurality of memory blocks, and then the read data read via the internal copy-back operation is stored in the destination block.

14. The method according to claim 1, further comprising: Perform the block reclamation, and Garbage collection is performed concurrently with the block reclamation, such that invalid data stored in the source block is discarded, and only valid data stored in the source block is stored in the destination block of the plurality of memory blocks.

15. The method according to claim 1, further comprising: As the retention characteristics of the memory block deteriorate, the number of weak word lines in the memory block increases and the number of strong word lines in the memory block decreases.

16. The method according to claim 1, wherein, Selecting the source block includes: For each of the plurality of memory blocks, monitor the elapsed time after a write operation for each memory block is completed; and When the elapsed time corresponding to a memory block is greater than the reference time, the memory block is identified as the source block.

17. The method according to claim 1, wherein, Selecting the source block includes: For each of the plurality of memory blocks, monitor the number of reads for each memory block that have been read; and When the number of reads corresponding to a memory block is greater than the reference number, the memory block is identified as the source block.

18. The method according to claim 1, wherein, Each of the plurality of memory blocks is divided into multiple stacks, and The word lines of each of the plurality of stacks are grouped into the weak word lines and the strong word lines.

19. A storage device, comprising: Non-volatile memory devices, comprising multiple memory blocks; as well as The memory controller includes ECC circuitry configured to perform ECC encoding and decoding of error check codes. The memory controller is configured as follows: Select the source block to be used as the target for block reclamation from the plurality of memory blocks; Based on the preservation characteristics of the physical positions of the multiple word lines of the source block, the multiple word lines are grouped into weak word lines and strong word lines; and The non-volatile memory device is controlled to perform an external copy-back operation for the weak word line and an internal copy-back operation is performed by the ECC circuit for the strong word line, wherein the external copy-back operation includes error correction by the ECC circuit and the internal copy-back operation does not include the error correction by the ECC circuit.

20. A storage device, comprising: A non-volatile memory device includes a plurality of memory blocks, each of the plurality of memory blocks including a plurality of word lines and a plurality of memory cells, the plurality of memory cells being stacked in a vertical direction and formed in a plurality of channel holes; as well as The memory controller includes ECC circuitry configured to perform ECC encoding and decoding of error check codes. The memory controller is configured as follows: Select the source block to be used as the target for block reclamation from the plurality of memory blocks; Based on the height of each of the plurality of word lines in the vertical direction, the plurality of word lines are grouped into weak word lines and strong word lines; and The non-volatile memory device is controlled to perform an external copy-back operation for the weak word line and an internal copy-back operation for the strong word line, wherein the external copy-back operation includes error correction by the ECC circuitry and the internal copy-back operation does not include the error correction by the ECC circuitry. The non-volatile memory device is configured to transmit read data read from memory cells connected to weak word lines of the source block to the memory controller during the external copy operation, and not transmit read data read from memory cells connected to strong word lines of the source block to the memory controller during the internal copy operation.

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