Drive circuit and electronic device

Abstract

The invention discloses a driving circuit and electronic equipment, and relates to the technical field of electronic circuits, the driving circuit comprises a first amplifying circuit, a second amplifying circuit, a third amplifying circuit and a switching circuit, the first amplifying circuit can detect the voltage change between an input first driving signal and a reference ground, and the switching circuit can switch the first driving signal to the second driving signal; and the change is amplified and output to the second amplification circuit. The second amplification circuit processes and transmits the signal to the third amplification circuit, and the third amplification circuit determines whether to enter a nonlinear amplification state according to the level of the input signal, thereby outputting a high-level or low-level signal. The switching circuit receives a control signal from the third amplifying circuit, when the control signal is in a high level, the output end of the switching circuit outputs a second driving signal, and otherwise, the output end of the switching circuit outputs a first driving signal. Therefore, the technical problem of asymmetric driving capability of the driving circuit in the prior art can be solved, and the technical effects of improving the driving capability of the driving circuit and keeping the symmetry of the signal at any time are achieved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and more particularly to a driving circuit and an electronic device. Background Technology

[0002] In related technologies, the two signal transmitters of a SerDes (Serializer-Deserializer) often experience variations in their rise and fall times due to external environmental factors and the stability of internal transistors. One signal may have a steeper rise time, while the other has a relatively gentler fall time. This phenomenon directly leads to asymmetry between the P and N signals, which in turn results in an asymmetry in the driving capability of the drive circuit.

[0003] This indicates that there is an asymmetry in the driving capability of the driving circuit in the relevant technology.

[0004] No effective solution has yet been proposed to address the aforementioned problems in the relevant technologies. Summary of the Invention

[0005] This application provides a driving circuit and an electronic device to at least solve the problem of asymmetrical driving capability of driving circuits in the related art.

[0006] This application provides a driving circuit, comprising: a first amplifier circuit, wherein the negative input terminal of the first amplifier circuit is used to receive a first driving signal, and the positive input terminal of the first amplifier circuit is configured to be grounded; a second amplifier circuit, wherein the positive input terminal of the second amplifier circuit is connected to the output terminal of the first amplifier circuit, and the negative input terminal of the second amplifier circuit is configured to be grounded; a third amplifier circuit, wherein the negative input terminal of the third amplifier circuit is connected to the output terminal of the second amplifier circuit, and the positive input terminal of the third amplifier circuit is configured to be grounded; and a switching circuit, wherein the first input terminal of the switching circuit is used to receive a second driving signal, the second input terminal of the switching circuit is used to receive the first driving signal, the control terminal of the switching circuit is connected to the output terminal of the third amplifier circuit, and the output terminal of the switching circuit is used to supply power externally; wherein the switching circuit is configured to output the second driving signal when the third amplifier circuit outputs a high level, and the switching circuit is further configured to output the first driving signal when the third amplifier circuit outputs a low level.

[0007] In one exemplary embodiment, the driving circuit further includes a first diode, the input terminal of which is connected to the output terminal of the third amplifier circuit, and the output terminal of which is connected to the control terminal of the switching circuit.

[0008] In one exemplary embodiment, the driving circuit further includes a first resistor and a second resistor, wherein the positive input terminal of the first amplifier circuit is grounded through the first resistor, and the negative input terminal of the first amplifier circuit is connected to the output terminal of the first amplifier circuit through the second resistor; the resistance value of the first resistor is greater than the resistance value of the second resistor.

[0009] In one exemplary embodiment, the driving circuit further includes a third resistor, and the output terminal of the second amplifier circuit is connected to the negative input terminal of the third amplifier circuit through the third resistor.

[0010] In one exemplary embodiment, the driving circuit further includes a fourth resistor, and the negative input terminal of the third amplifier circuit is connected to the output terminal of the third amplifier circuit through the fourth resistor.

[0011] In one exemplary embodiment, the switching circuit includes a first transistor, a second transistor, and an inverter. The gate of the first transistor is connected to the output terminal of the third amplifier circuit through the inverter. The first electrode of the first transistor is used to receive a first driving signal, and the second electrode of the first transistor is used to output the first driving signal. The gate of the second transistor is connected to the output terminal of the third amplifier circuit. The first electrode of the second transistor is used to receive a second driving signal, and the second electrode of the second transistor is used to output the second driving signal. The first transistor and the second transistor are turned on when their gates are at a high level.

[0012] In one exemplary embodiment, the driving circuit further includes a second diode and a third diode, wherein the second electrode of the first transistor outputs a first driving signal through the second diode, and the second electrode of the second transistor outputs a second driving signal through the third diode.

[0013] In one exemplary embodiment, the driving circuit further includes a fourth amplifier circuit, the negative input terminal of which is used to receive the second driving signal, the positive input terminal of which is configured to be grounded, and the output terminal of which is connected to the second input terminal of the switching circuit.

[0014] In one exemplary embodiment, the driving circuit further includes a fifth resistor and a sixth resistor. The negative input terminal of the fourth amplifier circuit receives the second driving signal through the fifth resistor, and the negative input terminal of the fourth amplifier circuit is also connected to the output terminal of the fourth amplifier circuit through the sixth resistor.

[0015] This application also provides an electronic device, including: a driving circuit as described in any of the above claims.

[0016] This application allows a first amplifier circuit to detect the voltage change between the input first drive signal and a reference ground, amplify the change, and output it to a second amplifier circuit. The second amplifier circuit further processes the signal and transmits it to a third amplifier circuit, which determines whether to enter a nonlinear amplification state based on the level of the input signal, thereby outputting a high-level or low-level signal. A switching circuit receives a control signal from the third amplifier circuit. When the control signal is high, the switching circuit outputs a second drive signal; otherwise, it outputs a first drive signal. This allows a stronger drive signal to be output through the switching circuit when the slope (rise or fall time) of the first drive signal is slow, compensating for the signal strength and ensuring the symmetry of signal transmission. Therefore, this solves the technical problem of asymmetrical drive capability in related technologies, achieving the technical effect of improving the drive capability of the drive circuit and maintaining signal symmetry at all times. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the driving circuit structure according to an embodiment of this application;

[0019] Figure 2 This is a schematic diagram of the specific structure of the driving circuit according to an embodiment of this application;

[0020] Figure 3 This is a flowchart illustrating the working principle of the driving circuit according to a specific embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0022] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0023] SerDes is an interface technology that enables bidirectional conversion between parallel and serial data. Its core advantage lies in its high-speed serial differential signal transmission, effectively overcoming the timing synchronization challenges of parallel architectures through mixed-signal circuit design (such as CDR clock data recovery and equalization techniques). SerDes significantly improves channel speed and transmission distance while drastically reducing the number of pins and PCB routing resources required for interconnection, achieving superior signal integrity, lower power consumption, and lower system cost. Therefore, it has become the underlying foundation for high-speed interconnect standards such as PCIe, SATA, and Ethernet.

[0024] However, the strength of a SerDes signal is usually measured by its driving capability. Driving capability is generally proportional to the rise time of the signal, that is, the slope of the rising edge. In other words, the steeper the slope, the stronger the driving capability, because such signals have a larger proportion of high-frequency components, and the transmission line medium is usually a low-pass filter. Therefore, the steeper the slope, the farther the signal can usually be transmitted. In other words, such signals often have better signal integrity.

[0025] SerDes signals typically consist of two signal lines, P and N. These signals generally require perfect symmetry between P and N to ensure accurate and reliable information recovery at the receiver. A key indicator of perfect symmetry between P and N is that their rise times and fall times must be identical. This maintains the symmetrical characteristic of P and N at all times. However, due to external environmental factors and the stability of internal transistors, the transmitting ends of the two SerDes signals may sometimes exhibit variations in rise and fall times, with one signal being steeper than the other. This asymmetry, or asymmetry in driving capability, leads to incorrect interpretation of the received signals after subtraction, resulting in signal reception quality issues and impacting the stability and reliability of the entire system.

[0026] In related technologies, the weaker signal is typically redriven. This involves adding a redriven device in the middle of the signal path to enhance its driving capability, thereby ensuring that both signals P and N have equal driving capabilities. This allows them to be transmitted symmetrically to the receiving end, enabling the receiver to stably and reliably recover the information transmitted in the path, thus guaranteeing stable system operation. However, adding a redriven chip to the signal transmission path is often costly and limited by space constraints, making its implementation challenging and limiting.

[0027] In view of the above-mentioned problems existing in the related technologies, the following embodiments are proposed.

[0028] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] Embodiments of this application provide a driving circuit that can be used to enhance or adjust electrical signals to meet the specific requirements of subsequent circuits or loads. Figure 1 This is a schematic diagram of the driving circuit structure according to an embodiment of this application, such as... Figure 1 As shown, the driving circuit includes:

[0030] A first amplifier circuit 12, wherein the negative input terminal of the first amplifier circuit is used to receive a first driving signal, and the positive input terminal of the first amplifier circuit is configured to be grounded;

[0031] The second amplifier circuit 14 has its positive input terminal connected to the output terminal of the first amplifier circuit, and its negative input terminal configured to be grounded.

[0032] A third amplifier circuit 16, wherein the negative input terminal of the third amplifier circuit is connected to the output terminal of the second amplifier circuit, and the positive input terminal of the third amplifier circuit is configured to be grounded;

[0033] The switching circuit 18 has a first input terminal for receiving a second driving signal, a second input terminal for receiving a first driving signal, a control terminal for being connected to the output terminal of the third amplifier circuit, and an output terminal for supplying power to the outside.

[0034] The switching circuit is configured to output a second driving signal when the third amplifier circuit outputs a high level, and the switching circuit is also configured to output a first driving signal when the third amplifier circuit outputs a low level.

[0035] In this embodiment, the first amplification circuit can be used as a first-stage amplification circuit to process signals with weak driving capability, aiming to improve the driving strength of the first driving signal. The second amplification circuit can be another stage amplification circuit following the first amplification circuit, further processing the signal to achieve the expected signal shaping and driving capability enhancement. The third amplification circuit is responsible for processing the signal after the first two stages of amplification, ensuring that the signal output meets the requirements and forms a symmetrical relationship with the other signal. The switching circuit is a circuit used in electronic devices to control the current path, a key component used to switch different signal paths and realize signal compensation and correction. Among them, the first, second, and third amplification circuits can be operational amplifiers. The positive power supply pins of the first, second, and third amplification circuits can all be connected to the power supply terminal, and the negative power supply pins of the first, second, and third amplification circuits are grounded.

[0036] In this embodiment, the first driving signal can be a signal with weak driving capability in the signal processing system, which needs to be strengthened by the technical solution of this invention to achieve a symmetrical effect with the second driving signal. The second driving signal, in contrast to the first driving signal, has a stronger driving capability and serves as a standard reference for symmetrical signals in the signal processing system. When the input signal of the signal processing system is the signal output by SerDes, it is known that the P and N signals sent by the SerDes signal have different driving capabilities. The rise and fall times of the P signal are slower, meaning its driving capability is weaker, while the N signal is a normal, steeper signal with stronger driving capability. Therefore, the first driving signal can be the P signal, and the second driving signal can be the N signal.

[0037] In this embodiment, the negative input terminal can be a port in the circuit that receives a signal with an out-of-phase phase to the input signal, used to achieve feedback or differential amplification. The positive input terminal can be a port in the amplifier circuit that receives a signal with the same phase as the input signal or a reference signal. The output terminal can be the part of the circuit or device from which the signal flows out, and can send the processed signal to the receiving terminal.

[0038] In this embodiment, a detailed structural diagram of the driving circuit can be found in the appendix. Figure 2 ,like Figure 2 As shown, the first amplifier circuit is operational amplifier U1, the second amplifier circuit is operational amplifier U2, and the third amplifier circuit is operational amplifier U3. The negative input terminal of U1 is used to receive the first drive signal, the positive input terminal of U1 is grounded, the output terminal of U1 is connected to the positive input terminal of operational amplifier U2, the negative input terminal of U2 is grounded, the output terminal of U2 is connected to the negative input terminal of U3, and the positive input terminal of U3 is grounded.

[0039] In this embodiment, the driving circuit effectively solves the problem of asymmetric signal driving capability distortion caused by external factors during the transmission of high-speed SerDes signals. The core of the technical solution lies in utilizing a cascaded design of a first, second, and third amplification circuit, combined with an intelligent selection mechanism of a switching circuit, to achieve dynamic compensation for the signal driving capability. Specifically, the first amplification circuit detects the voltage change between the input first driving signal and the reference ground, amplifies this change, and outputs it to the second amplification circuit. The second amplification circuit further processes and transmits the signal to the third amplification circuit, which determines whether to enter a nonlinear amplification state based on the level of the input signal, thereby outputting a high-level or low-level signal. The switching circuit receives a control signal from the third amplification circuit. When the control signal is high, the output of the switching circuit will output the second driving signal; otherwise, it will output the first driving signal. This design allows the switching circuit to intelligently select a stronger driving signal to compensate for the signal strength when the slope (rise or fall time) of the first driving signal is slow, thus ensuring the symmetry of signal transmission. Compared to related technologies that use additional re-drive chips to address signal asymmetry, this ingenious combination of discrete components not only reduces cost and space requirements but also improves the flexibility and reliability of the signal link, offering significant advantages, especially in space-constrained or cost-sensitive applications. It also simplifies PCB routing, enhances signal integrity, and ultimately ensures the stable operation of the entire system.

[0040] In one exemplary embodiment, the driving circuit further includes a first diode, the input terminal of which is connected to the output terminal of the third amplifier circuit, and the output terminal of the first diode is connected to the control terminal of the switching circuit. In this embodiment, see Appendix Figure 2 The driving circuit may also include a first diode D1, and the output terminal of the third amplifier circuit can be connected to the control terminal of the switching circuit through the first diode.

[0041] In this embodiment, the driving circuit integrates a first diode D1, whose input is closely connected to the output of the third amplifier circuit U3, while the output of D1 is directly connected to the control terminal of the switching circuit. This configuration allows the first diode D1 to respond instantly when the output of the third amplifier circuit U3 changes, controlling the state of the switching circuit and ensuring the continuity and accuracy of signal processing. Specifically, D1 can be turned on or off when the signal flows through it, thereby achieving precise control of the NMOS transistors Q1 and Q2 in the signal path. This ensures that the driving capability of weaker signals can be effectively enhanced during the rising and falling edges of the signal, achieving symmetry with stronger signals. This design avoids the high cost and space limitations of re-driving chips. Through the ingenious combination of discrete components, dynamic compensation of signal driving capability is achieved, ensuring the integrity and reliability of the SerDes signal during transmission and improving the overall performance of the system.

[0042] In one exemplary embodiment, the driving circuit further includes a first resistor and a second resistor. The positive input terminal of the first amplifier circuit is grounded through the first resistor, and the negative input terminal of the first amplifier circuit is connected to the output terminal of the first amplifier circuit through the second resistor. The resistance value of the first resistor is greater than the resistance value of the second resistor. In this embodiment, see Appendix [reference needed]. Figure 2 The driving circuit also includes a first resistor R1 and a second resistor R2. Firstly, during the time period T0-T1, the Vin_P signal is routed through operational amplifier U1. Since the output of U1 is connected to the negative input of the operational amplifier, the operational amplifier is in the line-to-line amplification region. At this time, the operational amplifier satisfies the virtual open / virtual short characteristic, i.e., U1... + =U1 - =0. Since the positive input terminal is grounded through R1, U1+=0. Because it satisfies the virtual open circuit characteristic, the current flowing through C1 is equal to the current flowing through R2. Therefore, we can conclude that: Since P remains at a low level during the T0-T1 phase, From the above conditions, we know that the output a of U1 is 0. The signal then flows through operational amplifier U2, which is in a nonlinear state at this time, so the output b of U2 is also equal to 0.

[0043] During the T1-T2 phase, because the driving capability of P is relatively weak, its rising edge is slower than that of the N signal, appearing as a step. Similarly, when the P signal flows through U1, since it is a rising edge at this time, ,because Therefore, the output a of U1 is less than 0. Since U2 is in the nonlinear region at this time, the amplification factor is infinite, so the output b of U2 will be amplified to -1.

[0044] Similarly, in the T2-T3 phase, since the level of P remains unchanged during this interval, therefore... At this point, the situation is similar to that of the T0-T1 stage, and the output of U2 is b=0.

[0045] During the T3-T4 phase, because it is in the falling phase, the signal driving capability of P is weak and the falling edge is relatively slow. Therefore, we can conclude that: ,Depend on As can be seen, the output a of U1 is greater than 0. Therefore, when passing through U2, U2 is in a nonlinear state with an infinite amplification factor. Thus, the output b of U2 is 1, which is a high level.

[0046] In this embodiment, the driving circuit integrates a first resistor R1 and a second resistor R2. The positive input terminal of the first amplifier circuit U1 is grounded through R1, while the negative input terminal of U1 is connected to the output terminal of U1 through R2. It is worth noting that the resistance value of R1 is set greater than that of R2. This structural design allows the circuit to precisely control the signal slope during the rise and fall phases of the signal by adjusting the current from the input signal to the first amplifier circuit, thereby enhancing the driving capability of weaker signals. During the signal rise phase, the smaller value of R2 allows current to flow rapidly, accelerating the signal rise and enabling signals with weaker driving capabilities to quickly reach a high level. During the signal fall phase, the larger resistance value of R1 helps stabilize the voltage changes during the signal fall, ensuring that the signal can smoothly and quickly fall to a low level, thus improving the overall driving capability of the signal and maintaining symmetry with the other signal. This mechanism of adjusting the signal slope through the difference in resistance values ​​effectively solves the problem of asymmetrical driving capability caused by external environment or internal transistor stability, ensuring signal integrity and stable system operation.

[0047] In one exemplary embodiment, the driving circuit further includes a third resistor, and the output terminal of the second amplifier circuit is connected to the negative input terminal of the third amplifier circuit through the third resistor. In this embodiment, see Appendix [notation missing]. Figure 2 The driving resistor may also include a third resistor R3, and U2 is connected to the negative input terminal of U3 through R3.

[0048] In this embodiment, the optimization of the driving circuit is achieved by introducing a third resistor R3, which is connected between the output of the second amplifier circuit U2 and the negative input of the third amplifier circuit U3. This configuration aims to adjust the dynamic characteristics of signal processing, ensuring fine control of the rising and falling edges of the signal during signal conversion, thereby effectively compensating for the asymmetry of driving capability. When the weaker driving capability of the signal passes through U1, its rate of change is detected and converted into a corresponding voltage change, which is transmitted to U2 for nonlinear amplification. The output of U2 is connected to the negative input of U3 through R3. This path allows U3 to linearly amplify or suppress the signal based on the output of U2, thereby adjusting the signal slope. By precisely configuring the resistance value of R3, the rise and fall times of the signal can be finely adjusted, ensuring that the signal maintains ideal symmetry even under asymmetrical driving capability, thereby improving signal quality and system performance.

[0049] In one exemplary embodiment, the driving circuit further includes a fourth resistor, and the negative input terminal of the third amplifier circuit is connected to the output terminal of the third amplifier circuit through the fourth resistor. In this embodiment, see Appendix [notation missing]. Figure 2 The negative input terminal of U3 is connected to the output terminal of U3 through the fourth resistor R7. During the time period T0-T1, when the output of U2 is low (0) to U3, since the input of U3 is 0, the output d=0. During the T1-T2 stage, the output b of U2 is amplified to -1. Since the input of U3 is negative, D1 is turned on. Therefore, U3 is in a linear amplification state at this time, thus satisfying the virtual open / virtual short characteristic, so U3+=U3-=0V. At this point, R3 = R7, therefore d = -b. Thus, the output of d is a high level of 1. During the T2-T3 phase, the output of U2 is b = 0, and the output of U3 is d = 0. During the T3-T4 phase, the output of U2 is b = 1, a high level. At this point, the signal passes through U3. Since the negative terminal of D1 is greater than 0, D1 is cut off. Therefore, the output value of d is positive, greater than 0, just like b.

[0050] In an exemplary embodiment, the switching circuit includes a first transistor, a second transistor, and an inverter. The gate of the first transistor is connected to the output terminal of the third amplifier circuit through the inverter. The first electrode of the first transistor is used to receive a first drive signal, and the second electrode of the first transistor is used to output the first drive signal. The gate of the second transistor is connected to the output terminal of the third amplifier circuit. The first electrode of the second transistor is used to receive a second drive signal, and the second electrode of the second transistor is used to output the second drive signal. The first and second transistors are turned on when their gates are high. The inverter can be a NOT gate. In this embodiment, the first and second transistors can be MOS transistors, such as NMOS transistors. (Continue to see the appendix...) Figure 2 The first transistor is Q1, and the second transistor is Q2. The gate of the first transistor is connected to the output of U3 via inverter U5. The first electrode of the first transistor is the source, and the second electrode is the drain. The gate of the second transistor Q2 is connected to the output of U3. The first electrode of the second transistor Q2 is the source, and the second electrode is the drain.

[0051] In this embodiment, during the time period T0-T1, the input of U3 is 0, so the output d=0. After passing through the inverter U5, the output f of U5 is high (1), so the NMOS transistor Q1 is turned on, and Q2 is turned off because its gate level is 0. At this time, the output of P remains unchanged. During the T1-T2 stage, the output d of U3 is high (1). Since it passes through the inverter U5, the output f is low (0), so Q1 is turned off, and similarly, Q2 is turned on. During the T3-T4 stage, the output d of U3 and b are both positive (greater than 0), so Q1 is turned off, and Q2 is turned on.

[0052] In this embodiment, the switching circuit includes a first transistor, a second transistor, and an inverter. The first transistor Q1 and the second transistor Q2 are used to respond to the output signals of the third amplifier circuit U3 and the fourth amplifier circuit U4, respectively. Specifically, the gate of the first transistor Q1 is connected to the output terminal of the inverter U5, receiving a feedback signal to control its conduction state; while the gate of the second transistor Q2 is directly connected to the output terminal of the third amplifier circuit U3, similarly determining its conduction state based on the control signal. The first electrode of Q1 receives a drive signal from the P signal, and the second electrode outputs a processed first drive signal; the first electrode of Q2 receives a drive signal from the N signal, and the second electrode outputs a processed second drive signal. When the gate receives a high level, Q1 and Q2 will be in the conduction state, thereby realizing signal transmission or amplification.

[0053] In one exemplary embodiment, the driving circuit further includes a second diode and a third diode. The second electrode of the first transistor outputs a first driving signal through the second diode, and the second electrode of the second transistor outputs a second driving signal through the third diode. In this embodiment, see Appendix [notation missing]. Figure 2 The second diode is D2, and the third diode is D3. During the T0-T1 phase, the output of U5 is at a high level (1), so Q1 is turned on. Therefore, the positive input of D2 is 0. Since the gate level of Q2 is 0, Q2 is turned off, so the positive input of D3 is 0. Therefore, the overall output Vout_P level is 0. At this time, the output of P remains unchanged. During the T1-T2 phase, N is -1. After passing through U4, U4 is also in a linear amplification state. Therefore, U4+=U4-=0V. If R4 = R5, the output e = -N = 1, which is a high level. Therefore, Q2 conducts, and the positive input of D3 is high (1). Thus, Ci is Vout_P = 1 (high level). Therefore, during the T1-T2 phase, the output P directly becomes high, the slope becomes steeper, and the driving capability becomes stronger, symmetrical to N. During the T2-T3 phase, the positive input of D2 is P = 1 (high level), and the positive input of D3 is 0. Therefore, the output Vout_P = 1 (high level). During this time period, the position of P remains unchanged, at high level 1. During the T3-T4 phase, the positive input of D2 is 0, and the positive input of D3 is 1. Therefore, the output Vout_P = 1 (high level). Thus, the driving capability of P is also strengthened, and the falling edge becomes steeper, perfectly symmetrical to the N signal.

[0054] In this embodiment, D2 and D3 serve as key signal path elements, and their on / off states directly determine the final shape of the P signal. During the T1-T2 and T3-T4 stages, when the slope of the P signal is insufficient to be symmetrical with the N signal, the switching state changes of Q1 and Q2 trigger the action of D2 and D3 to ensure that the output Vout_P signal can quickly reach or recover to a high level, compensating for the insufficient driving capability of the original P signal. This real-time signal compensation mechanism avoids the use of additional chips or complex circuit designs, thereby optimizing the symmetry and integrity of the signal transmission process without sacrificing system performance.

[0055] In one exemplary embodiment, the driving circuit further includes a fourth amplifier circuit, the negative input terminal of which is used to receive the second driving signal, the positive input terminal of which is configured to be grounded, and the output terminal of which is connected to the second input terminal of the switching circuit. In this embodiment, see Appendix Figure 2The fourth amplifier circuit is U4. The negative input of U4 receives the second drive signal, and the positive input is grounded. Its output is connected to the second input of the switching circuit. When the switching circuit includes a first transistor and a second transistor, the output of U4 is connected to the source of the second transistor.

[0056] In this embodiment, during the T1-T2 stage, N is -1. After passing through U4, U4 is also in a linear amplification state. Therefore, U4+=U4-=0V. If R4 = R5, then the output e = -N = 1, which is a high level. Therefore, Q2 is turned on, and the positive input of D3 is a high level (1). Thus, Ci is a high level (Vout_P = 1). Therefore, during the T1-T2 stage, the output P level directly becomes high, the slope becomes steeper, and the driving capability becomes stronger, symmetrical to N. During the T3-T4 stage, N passes through U4. Since N < 0, therefore... Therefore, the output of U4 is -N=1 (high level), so the positive terminal of D2 is 0 and the positive terminal of D3 is 1, resulting in the output Vout_P=1 (high level). Thus, the driving capability of P is also enhanced, and the falling edge becomes steeper, perfectly symmetrical to the N signal.

[0057] During the entire T0-T4 time period, the P signal originally had a weak driving capability, with a relatively long rise and fall time and a relatively gentle slope. After the entire system was adjusted, the rise and fall slopes of the P signal became larger, and the driving capability was strengthened throughout the time period, becoming completely symmetrical with the N signal.

[0058] In one exemplary embodiment, the driving circuit further includes a fifth resistor and a sixth resistor. The negative input terminal of the fourth amplifier circuit receives the second driving signal through the fifth resistor, and the negative input terminal of the fourth amplifier circuit is also connected to the output terminal of the fourth amplifier circuit through the sixth resistor. In this embodiment, see Appendix Figure 2 The driving circuit may also include a fifth resistor R4 and a sixth resistor R5. The driving circuit may also include a seventh resistor R6, with the positive input terminal of U4 grounded through R6.

[0059] In this embodiment, the driving circuit further includes a fifth resistor R4 and a sixth resistor R5. The negative input terminal of the fourth amplifier circuit U4 receives the second driving signal via the fifth resistor R4, while the negative input terminal of the fourth amplifier circuit U4 is connected to its output terminal via the sixth resistor R5. This design effectively buffers and regulates the second driving signal, ensuring its stability and integrity during transmission. Specifically, the combination of R5 and R6 forms a feedback network that dynamically adjusts the gain of U4 according to the amplitude and frequency characteristics of the second driving signal, thereby optimizing signal transmission quality and reducing signal distortion and noise. Through this sophisticated circuit design, even in complex signal transmission environments, accurate signal transmission is ensured, improving the overall performance and reliability of the system.

[0060] In one exemplary embodiment, the driving circuit may further include a first capacitor C1, through which a first driving signal is input to the negative input terminal of U1, so as to output a stable first driving signal through the first capacitor. The driving circuit may further include an eighth resistor R8, and the second diode and the third diode are grounded through R8.

[0061] In one exemplary embodiment, the driving circuit may include an OR gate, with its first input connected to the second electrode of a first transistor, its second input connected to the second electrode of a second transistor, and its output connected to the output of the driving circuit. The OR gate outputs a high level when the second electrode of Q1 outputs a high level, and / or the second electrode of Q2 outputs a high level. The OR gate outputs a low level when both the second electrodes of Q1 and Q2 output a low level. In this embodiment, the OR gate ensures that at any given time, the output of the driving circuit receives only a signal from the activated transistor (either the first or the second transistor), avoiding interference between signals and thus improving signal integrity and clarity. The OR gate has a fast signal switching speed, meaning that signals can switch from one path to another in a shorter time. This speed improvement is crucial for maintaining high-quality signal transmission, especially in high-frequency signal processing scenarios. The integration of OR gates simplifies circuit design, reduces the use of discrete components, and makes the circuit layout more compact, saving PCB space and potentially reducing circuit complexity and manufacturing costs.

[0062] Figure 3 This is a flowchart illustrating the working principle of the driving circuit according to a specific embodiment of this application, such as... Figure 3 As shown, the process includes:

[0063] In step S302, Serdes sends a P signal (corresponding to the first driving signal mentioned above) and an N signal (corresponding to the second driving signal mentioned above), with the driving capabilities of the P signal and the N signal being asymmetrical.

[0064] In step S304, the weaker signal is amplified by the driving circuit to make the signal steeper and consistent with the symmetrical signal.

[0065] In step S306, the P and N signals, which are now symmetrical, are obtained and arrive at the signal receiver stably and reliably.

[0066] See appendix for further details. Figure 2 With VCC at 3.3V, R1, R6, and R8 at 100KΩ, R2, R3, R7, R4, and R5 at 10KΩ, C1 at 1uf, and U1, U2, U3, and U4 as LM307 op-amps, and NOT gate U5 as a 74LS04, Q1 and Q2 are CN30N06 NMOS transistors with T0=0s, T1=0.5s, T2=0.6s, T3=0.9s, and T4=1s, the following details are provided:

[0067] During the time interval T0-T1, that is, within the interval of 0-0.5s, the P signal (i.e., the first drive signal) is at a low level of 0V. .therefore, , can be obtained Therefore, a=0V. After passing through U2 and U3, the output d of U3 is 0V, and the output of U5 is 3.3V. Therefore, MOSFET Q1 is turned on, and Q2 is turned off. Thus, the positive input of D2 and D3 is 0V. Therefore, the output Vout_P=0V. At this point, the output remains consistent with the input.

[0068] Within the T1-T2 interval, that is, the interval between 0.5s and 0.6s, , , can be obtained Therefore, the output a = -0.33V is obtained and fed to U2. Since U2 is in a non-linear state, a is amplified infinitely to VCC = -3.3V, therefore b = -3.3V. Thus, the negative terminal of D1 is negative, and D1 conducts. Operational amplifier U3 operates in a linear amplification state. It can be known that: Therefore, d = 3.3V, so Q1 is cut off and Q2 is turned on. At this time, the N signal (i.e., the second drive signal) has a negative voltage of -3.3V. We can obtain: Therefore, e = 3.3V. At this time, the positive terminal of D3 is 3.3V, so the output Vout_P = 3.3V. Therefore, at this moment, the driving force of the signal at the P terminal is strengthened, changing from a signal with a certain slope to a steeper signal, which is symmetrical to the N signal.

[0069] During the T2-T3 phase, which is the 0.6-0.9s interval, , , can be obtained Therefore, a = 0V. Similarly, the outputs b of U2 and d of U3 are both 0V. Therefore, the output of U5 is 3.3V, Q1 is on, and Q2 is off. So the positive terminal of D2 is 3.3V, and the positive terminal of D3 is 0V. Therefore, Vout_P = 3.3V, which is consistent with the input and remains unchanged.

[0070] During the T3-T4 phase, which is the interval from 0.9s to 1s, P is in the decreasing phase, therefore , , can be obtained Therefore, the output of U1 is a = 0.33V. The negative terminal of D1 is 3.3V > 0, so D1 is cut off. Therefore, the voltage at terminal d equals the voltage at terminal b = 3.3V. The output of U5 is 0V, so Q1 is cut off and Q2 is turned on. Since N = -3.3V at this time, ... We can obtain: The output e = 3.3V. Therefore, the positive terminal of D3 is 3.3V, and thus Vout_P = 3.3V. Therefore, during this time interval, the driving capability of signal P is enhanced.

[0071] In summary, throughout the 0-1s interval, the P signal becomes steeper after processing by the entire system during the relatively slow rise and fall times. This means that the signal's driving capability is enhanced, achieving complete symmetry with the N signal and ensuring signal quality.

[0072] It should be noted that the driving circuit in any of the above embodiments can also be applied to other high-speed serial systems. Other high-speed serial systems may have asymmetrical driving capabilities due to external factors; in such cases, the driving circuit can be used in the correction and compensation link of those systems.

[0073] In the aforementioned embodiments, the driving circuit exhibits strong versatility. Utilizing discrete components, it achieves consistency between the two driving capabilities of the PN signal when the driving capability is asymmetrical. This is achieved by processing and strengthening the weaker signal, ensuring the entire signal reaches the receiver normally and thus guaranteeing signal integrity. Furthermore, the entire signal processing system constructed with discrete circuits often occupies less physical space, offers significant cost advantages, and is highly PCB-friendly. By strengthening the rising and falling edges of the weaker driving signal, the entire PN signal is kept perfectly symmetrical, reliably reaching the signal receiver and thus improving the overall system's stable and reliable operation.

[0074] Embodiments of this application provide an electronic device, including the driving circuit as described in any of the foregoing embodiments. The electronic device may include a computing device, a network communication device, a storage device, etc. The computing device may include a computer, a processor, etc.; the network communication device may include an Ethernet switch, a router, etc.; and the storage device may include a hard disk, etc.

[0075] The foregoing has provided a detailed description of a driving circuit and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A driving circuit, characterized in that, include: A first amplifier circuit, wherein the negative input terminal of the first amplifier circuit is used to receive a first drive signal, and the positive input terminal of the first amplifier circuit is configured to be grounded; A second amplifier circuit is provided, wherein the positive input terminal of the second amplifier circuit is connected to the output terminal of the first amplifier circuit, and the negative input terminal of the second amplifier circuit is configured to be grounded. A third amplifier circuit, wherein the negative input terminal of the third amplifier circuit is connected to the output terminal of the second amplifier circuit, and the positive input terminal of the third amplifier circuit is configured to be grounded; A switching circuit, wherein the first input terminal of the switching circuit is used to receive a second driving signal, the second input terminal of the switching circuit is used to receive a first driving signal, the control terminal of the switching circuit is connected to the output terminal of the third amplifier circuit, and the output terminal of the switching circuit is used to supply power to the outside. The switching circuit is configured to output a second driving signal when the third amplifier circuit outputs a high level, and the switching circuit is also configured to output a first driving signal when the third amplifier circuit outputs a low level.

2. The driving circuit according to claim 1, characterized in that, The driving circuit also includes a first diode, the input terminal of which is connected to the output terminal of the third amplifier circuit, and the output terminal of which is connected to the control terminal of the switching circuit.

3. The driving circuit according to claim 1, characterized in that, The driving circuit further includes a first resistor and a second resistor. The positive input terminal of the first amplifier circuit is grounded through the first resistor, and the negative input terminal of the first amplifier circuit is connected to the output terminal of the first amplifier circuit through the second resistor. The resistance value of the first resistor is greater than the resistance value of the second resistor.

4. The driving circuit according to claim 1, characterized in that, The driving circuit also includes a third resistor, and the output terminal of the second amplifier circuit is connected to the negative input terminal of the third amplifier circuit through the third resistor.

5. The driving circuit according to claim 1, characterized in that, The driving circuit also includes a fourth resistor, and the negative input terminal of the third amplifier circuit is connected to the output terminal of the third amplifier circuit through the fourth resistor.

6. The driving circuit according to claim 1, characterized in that, The switching circuit includes a first transistor, a second transistor, and an inverter. The gate of the first transistor is connected to the output terminal of the third amplifier circuit through the inverter. The first electrode of the first transistor is used to receive a first driving signal, and the second electrode of the first transistor is used to output the first driving signal. The gate of the second transistor is connected to the output terminal of the third amplifier circuit. The first electrode of the second transistor is used to receive a second driving signal, and the second electrode of the second transistor is used to output the second driving signal. The first transistor and the second transistor are turned on when their gates are at a high level.

7. The driving circuit according to claim 6, characterized in that, The driving circuit further includes a second diode and a third diode. The second electrode of the first transistor outputs a first driving signal through the second diode, and the second electrode of the second transistor outputs a second driving signal through the third diode.

8. The driving circuit according to claim 1, characterized in that, The driving circuit further includes a fourth amplifier circuit, the negative input terminal of which is used to receive the second driving signal, the positive input terminal of which is configured to be grounded, and the output terminal of which is connected to the second input terminal of the switching circuit.

9. The driving circuit according to claim 8, characterized in that, The driving circuit further includes a fifth resistor and a sixth resistor. The negative input terminal of the fourth amplifier circuit receives the second driving signal through the fifth resistor, and the negative input terminal of the fourth amplifier circuit is also connected to the output terminal of the fourth amplifier circuit through the sixth resistor.

10. An electronic device, characterized in that, Includes the drive circuit as described in any one of claims 1-9.

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