Bus support capacitance calculation method, equipment, medium and product

Abstract

The invention discloses a bus support capacitance calculation method and device, a medium and a product, and relates to the field of power electronics, and the method comprises the steps: firstly, calculating a neutral-point potential fluctuation allowable value according to a three-phase output voltage peak value and a load power factor angle of a three-level inverter; calculating the three-phase output current of the three-level inverter according to the three-phase output current peak value of the three-level inverter; capacitance current flowing through the subintervals is calculated; then calculating the charge cumulant of the bus capacitor in a charging period; and finally, calculating the minimum capacity of the bus capacitor according to the neutral-point potential fluctuation allowable value and the charge cumulant. The technical problem that the capacitance cost and the capacitance volume cannot be effectively reduced due to the fact that the existing method is low in calculation efficiency and difficult to accurately calculate the minimum capacitance capacity on the premise that the output waveform is not distorted is solved.

Description

Technical Field

[0001] This invention relates to the field of power electronics, specifically to a method, equipment, dielectric, and product for calculating busbar support capacitance. Background Technology

[0002] The statements in this section are provided only as background information in connection with this disclosure and may not constitute prior art.

[0003] In recent years, with the development of power electronics technology in the power industry, NPC three-level technology has been increasingly applied in various fields, including photovoltaic inverters, wind power converters, high-voltage frequency converters, UPS, APF / SVG, and high-frequency power supplies. The two most commonly used NPC topologies are: Type I NPC circuits and Type T NPC circuits. Figure 1 This is the main circuit topology diagram of the NPC1 three-level inverter. Compared to traditional two-level inverters, three-level inverters have many advantages: (1) It has a better output waveform. The harmonic content of the three-level circuit can be reduced by about half compared with the two-level circuit, which is of great help to reduce harmonic injection into the power grid.

[0004] (2) Improve electromagnetic interference (EMI) problem. Since the IGBT switching voltage is halved, the voltage change rate during the switching process is reduced, which means that the electromagnetic interference of the system is improved.

[0005] Currently, most literature on bus capacitance calculation obtains capacitance values ​​through simulations of different modulation methods. The amplitude of midpoint potential fluctuations is estimated empirically, failing to provide the maximum fluctuation margin. Its drawbacks include low efficiency and difficulty in minimizing capacitance while ensuring undistorted output waveforms, thus hindering cost and size reduction. Summary of the Invention

[0006] The purpose of this invention is to address the current situation where the calculation of bus capacitors in three-level inverters mainly relies on simulation, and the amplitude of midpoint potential fluctuations is often estimated empirically, making it difficult to accurately obtain the maximum fluctuation margin. This invention provides a method for determining the maximum threshold of midpoint potential fluctuations in three-phase four-wire three-level inverters, ensuring that the midpoint potential fluctuation magnitude meets the requirement of maintaining output voltage distortion while minimizing the bus capacitor capacity. Specifically, it provides a method, device, medium, and product for calculating bus support capacitors. This method determines the allowable value of midpoint potential fluctuations based on the condition of ensuring output voltage undistortion, and calculates the bus capacitor charge accumulation during the SPWM modulation wave charging and discharging cycle. This solves the technical problems of low calculation efficiency and difficulty in accurately calculating the minimum capacitor capacity while ensuring output waveform undistortion in existing methods, thus failing to effectively reduce capacitor costs and size.

[0007] The technical solution of the present invention is as follows: A method for calculating the bus support capacitance of a three-phase four-wire three-level circuit includes: Step S1: Based on the peak value of the three-phase output voltage of the three-level inverter and load power factor angle Calculate the allowable value of midpoint potential fluctuation. ; Step S2: Based on the peak value of the three-phase output current of the three-level inverter Calculate the three-phase output current of a three-level inverter. , , ; Step S3: Calculate subintervals Current flowing through the capacitor ; Step S4: Calculate the charge accumulation of the bus capacitor during one charging cycle. ; Step S5: Based on the allowable value of midpoint potential fluctuation and charge accumulation Calculate the minimum capacity of the bus capacitor. .

[0008] Furthermore, the allowable value of the midpoint potential fluctuation The calculation formula is as follows:

[0009] in: This is the peak value of the three-phase output voltage of the three-level inverter, which is also the DC bus voltage; , , This refers to the three-phase output voltage of a three-level inverter.

[0010] Furthermore, the three-phase output voltage of the three-level inverter , , The calculation is based on the DC bus voltage, as follows:

[0011]

[0012]

[0013] in: The modulation ratio of a three-level inverter; The angular velocity of the SVPWM three-phase modulation wave; This is a charging cycle.

[0014] Furthermore, the three-phase output current , , The calculation formula is as follows:

[0015]

[0016] .

[0017] Furthermore, the capacitor current The calculation formula is as follows: .

[0018] Furthermore, the accumulated charge The calculation formula is as follows: .

[0019] Furthermore, the minimum capacity of the bus capacitor The calculation formula is as follows: .

[0020] The present invention also proposes an electronic device, comprising: At least one processor; and a memory communicatively connected to said at least one processor; The memory stores instructions that can be executed by the at least one processor, and the at least one processor executes the instructions stored in the memory to perform the method described above.

[0021] The present invention also proposes a computer-readable storage medium for storing instructions that, when executed, cause the method described above to be implemented.

[0022] The present invention also proposes a computer program product, which implements the above-described method when executed by a processor.

[0023] Compared with existing technologies, the advantages of this invention are: 1. This invention achieves precise calculation and minimal design of bus capacitor capacity, reducing cost and size. It abandons the existing method of determining capacitor capacity based on simulation or empirical estimation. By calculating the allowable value of the midpoint potential fluctuation in a three-level inverter and the charge accumulation within a charge / discharge cycle, it can quantitatively calculate the minimum bus capacitor capacity that meets operating requirements. This not only avoids resource waste caused by overly large capacity designs but also effectively reduces the hardware cost and physical size of the capacitor.

[0024] 2. This invention ensures that the inverter output voltage waveform remains undistorted, improving system reliability. During the calculation process, the maximum allowable threshold for midpoint potential fluctuation is first determined based on the peak value of the three-phase output voltage and the load power factor angle. By limiting the midpoint potential fluctuation within this threshold range, it ensures that the DC bus voltage can still meet the inverter requirements while minimizing capacitor capacity, thereby effectively preventing output voltage waveform distortion.

[0025] 3. Provides clear theoretical calculation basis, improving design efficiency. For three-level inverters under SPWM modulation algorithm, this invention presents a complete mathematical calculation method for the maximum and minimum values ​​of midpoint voltage fluctuation and capacitor capacity. Compared with the traditional iterative simulation and trial-and-error method, the method of this invention can quickly obtain design parameters, significantly improving the efficiency and accuracy of circuit design. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0027] Figure 1 This is the main circuit topology diagram of an NPC three-level inverter; Figure 2 A flowchart illustrating a method for calculating the bus support capacitor in a three-phase four-wire three-level circuit. Figure 3 The waveform consists of an SPWM three-phase modulation wave and a carrier waveform. Figure 4 For the switching period T s Internal phase reference voltages and carrier waveforms; Figure 5 The topology of the line from PCS to the grid side; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0028] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0029] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0030] Example 1 Please see Figure 2 A method for calculating the bus support capacitor in a three-phase four-wire three-level circuit includes the following steps: Step S1: Based on the peak value of the three-phase output voltage of the three-level inverter and load power factor angle Calculate the allowable value of midpoint potential fluctuation. ; Step S2: Based on the peak value of the three-phase output current of the three-level inverter Calculate the three-phase output current of a three-level inverter. , , ; Step S3: Calculate subintervals Current flowing through the capacitor ; Step S4: Calculate the charge accumulation of the bus capacitor during one charging cycle. ; Step S5: Based on the allowable value of midpoint potential fluctuation and charge accumulation Calculate the minimum capacity of the bus capacitor. .

[0031] In this embodiment, specifically, the allowable value of midpoint potential fluctuation... The calculation formula is as follows:

[0032] in: This is the peak value of the three-phase output voltage of the three-level inverter, which is also the DC bus voltage; , , This refers to the three-phase output voltage of a three-level inverter. The symbol is used to determine the maximum or minimum value.

[0033] In this embodiment, specifically, the three-phase output voltage of the three-level inverter , , The calculation is based on the DC bus voltage, as follows:

[0034]

[0035]

[0036] in: The modulation ratio of a three-level inverter; The angular velocity of the SVPWM three-phase modulation wave; This is a charging cycle.

[0037] In this embodiment, specifically, the three-phase output current , , The calculation formula is as follows:

[0038]

[0039] .

[0040] In this embodiment, specifically, the capacitor current The calculation formula is as follows: .

[0041] In this embodiment, specifically, the charge accumulation amount The calculation formula is as follows: .

[0042] In this embodiment, specifically, the minimum capacity of the bus capacitor... The calculation formula is as follows: .

[0043] Based on the same technical concept, embodiments of the present invention also provide an electronic device that can implement the bus support capacitor calculation method for a three-phase four-wire three-level circuit provided in the above embodiments of the present invention. In one embodiment, the electronic device can be a server, a terminal device, or other electronic equipment. Figure 6 As shown, the electronic device may include: At least one processor and a memory connected to the at least one processor. In this embodiment of the invention, the specific connection medium between the processor and the memory is not limited. Figure 6 The example used is the connection between the processor and memory via a bus. The bus... Figure 6 The connections between other components are indicated by thick lines and are for illustrative purposes only, not as limiting information. Buses can be divided into address buses, data buses, control buses, etc., but for ease of representation, [the specific bus type is not shown here]. Figure 6 The processor is represented by a single thick line, but this does not imply that there is only one bus or one type of bus. Alternatively, a processor can also be called a controller; there are no restrictions on the name.

[0044] In this embodiment of the invention, the memory stores instructions executable by at least one processor. By executing the instructions stored in the memory, the at least one processor can perform the bus support capacitor calculation method for a three-phase four-wire three-level circuit described above. The processor can implement... Figure 6 The functions of each module in the device shown.

[0045] The processor is the control center of the device. It can connect to various parts of the control device through various interfaces and lines. By running or executing instructions stored in memory and calling data stored in memory, it can monitor the device's various functions and process data, thereby enabling overall monitoring of the device.

[0046] In an alternative design, the processor may include one or more processing units. The processor may integrate an application processor and a modem processor, wherein the application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may also not be integrated into the processor. In some embodiments, the processor and memory may be implemented on the same chip; in some embodiments, they may also be implemented separately on separate chips.

[0047] The processor can be a general-purpose processor, such as a CPU, digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method for calculating the bus support capacitor of a three-phase four-wire three-level circuit disclosed in the embodiments of this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0048] Memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory can include at least one type of storage medium, such as flash memory, hard disk, multimedia cards, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), and electrically erasable programmable read-only memory (EPROM). Only memory (EEPROM), magnetic storage, magnetic disks, optical disks, etc. A memory is any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited thereto. The memory in embodiments of this invention can also be a circuit or any other device capable of performing storage functions for storing program instructions and / or data.

[0049] By designing and programming the processor, the code corresponding to the bus support capacitor calculation method for a three-phase four-wire three-level circuit described in the foregoing embodiments can be embedded into the chip, thereby enabling the chip to execute the steps of the method described in the foregoing embodiments during operation. How to design and program the processor is a technique well-known to those skilled in the art, and will not be elaborated upon here.

[0050] Based on the same inventive concept, embodiments of the present invention also provide a storage medium storing computer instructions that, when executed on a computer, cause the computer to perform the bus support capacitor calculation method for a three-phase four-wire three-level circuit described above.

[0051] In some alternative embodiments, the present invention also provides a method for calculating the bus support capacitance of a three-phase four-wire three-level circuit, which can also be implemented as a program product including program code. When the program product is run on a device, the program code is used to cause the control device to perform the steps in the method for calculating the bus support capacitance of a three-phase four-wire three-level circuit according to various exemplary embodiments of the present invention as described above.

[0052] It should be noted that although several units or sub-units of the apparatus have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the invention, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units. Furthermore, although the operation of the method of the invention is described in a specific order in the drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0053] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can be implemented in one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs) containing computer-usable program code. The form of a computer program product implemented on ROM, optical memory, etc.

[0054] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a server, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0055] Program code for performing the operations of this invention can be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0056] In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0057] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0058] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0059] Furthermore, in some embodiments, a computer program product is also proposed, which, when executed by a processor, implements the above-described method for calculating the bus support capacitor of a three-phase four-wire three-level circuit.

[0060] Example 2 Example 2 is a further explanation of Example 1; please refer to [link / reference]. Figure 2 A method for calculating the bus support capacitor in a three-phase four-wire three-level circuit includes the following steps: Step S1: Based on the peak value of the three-phase output voltage of the three-level inverter and load power factor angle Calculate the allowable value of midpoint potential fluctuation. It should be noted that PWM three-phase modulation waves are commonly used drive signals for the development transistors in three-level inverters. The calculation of the drive signal varies depending on the PWM three-phase modulation wave. In this embodiment, a sinusoidal pulse width modulation (SPWM) three-phase modulation wave is used; therefore, the three-phase output voltage of the three-level inverter... , , The calculation is based on the DC bus voltage, as follows:

[0061]

[0062]

[0063] in: The modulation ratio of a three-level inverter; The angular velocity of the SVPWM three-phase modulation wave; This is a charging cycle; Considering practical situations, there is a filtering module between the PCS and the power grid, specifically for LC filtering, such as... Figure 5 As shown in the PCS-to-grid line topology, the PCS voltage and the grid voltage are compared through an inductor voltage drop. For an lc filter module with inductance L and capacitance C, the effective value of phase a voltage can be obtained:

[0064]

[0065] in: This represents the effective value of phase voltage a. This represents the effective value of the phase voltage on the grid side. Combination Figure 3 From the SPWM three-phase modulation waveform and carrier waveform, it can be seen that at π / 3, the capacitor voltage reaches its maximum / minimum value after one charging / discharging cycle. When the voltage across the capacitor reaches its maximum / minimum value, the corresponding output three-phase voltage value is... for:

[0066] Where max is the maximum value operation; To ensure that the three-phase output voltage waveform of a three-level inverter is not distorted, the capacitor voltage must be at least greater than the corresponding maximum value of the three-phase output voltage. Then the maximum value of the midpoint potential fluctuation is:

[0067] in: This is the peak value of the three-phase output voltage of the three-level inverter, which is also the DC bus voltage; , , This refers to the three-phase output voltage of a three-level inverter. The symbol is used to determine the maximum or minimum value.

[0068] Step S2: Based on the peak value of the three-phase output current of the three-level inverter Calculate the three-phase output current of a three-level inverter. , , In this embodiment, specifically, the three-phase output current , , The calculation formula is as follows:

[0069]

[0070] .

[0071] Step S3: Calculate subintervals Current flowing through the capacitor ;according to Figure 1 From the main circuit topology diagram of the NPC three-level inverter, we can see that:

[0072] Neglecting the AC component of the DC power supply current, and assuming the DC component of the bus capacitor is zero, the expression for the AC component of the bus capacitor is:

[0073] Figure 4 sub-interval The modulation wave and triangular carrier waveform of one switching cycle, V in the figure ref, A V ref, B and V ref, C These are the reference values ​​for the three-phase voltages. Therefore, the times T0, T1, and T2 are respectively:

[0074]

[0075]

[0076] in: For switching cycles; , These are the duty cycles of devices VA1 and VC1, respectively. according to Figure 4 Switching period T s From the reference voltages and carrier waveforms of each phase, the DC bus input current can be determined. for:

[0077] In subinterval Within one switching cycle The average value is:

[0078] Similarly, the DC bus input current can be obtained. In subinterval and The expression for the average value is similar to the one above, so its average value over (0, 2π / 3) is:

[0079] in, , Input current In subinterval and The average value is similar to the one above. To calculate the cumulative charge of the bus capacitance, a sub-interval is taken. Current flowing through the capacitor Analyze and determine the current. :

[0080] Step S4: Calculate the charge accumulation of the bus capacitor during one charging cycle. That is, analysis Figure 3 From the SPWM three-phase modulation waveform and carrier waveform, it can be seen that the current is positive and the capacitor is charging within (0, π / 3), and the currents within (0, π / 6) and (π / 6, π / 3) are completely symmetrical. Therefore, the cumulative charge on the bus capacitor within a single cycle is:

[0081] Step S5: Based on the allowable value of midpoint potential fluctuation and charge accumulation Calculate the minimum capacity of the bus capacitor. In this embodiment, specifically, the minimum capacity of the bus capacitor is... The calculation formula is as follows:

[0082] The embodiments described above merely illustrate specific implementation methods of this application, and while the descriptions are detailed and specific, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the technical solution of this application, and these modifications and improvements all fall within the scope of protection of this application.

[0083] This background section is provided to generally present the context of the invention. The work of the currently named inventors, the work to the extent described in this background section, and aspects described in this section that did not constitute prior art at the time of application are neither expressly nor impliedly acknowledged as prior art to the invention.

Claims

1. A method for calculating the bus support capacitance of a three-phase four-wire three-level circuit, characterized in that, include: Step S1: Based on the peak value of the three-phase output voltage of the three-level inverter and load power factor angle Calculate the allowable value of midpoint potential fluctuation. ; Step S2: Based on the peak value of the three-phase output current of the three-level inverter Calculate the three-phase output current of a three-level inverter. , , ; Step S3: Calculate subintervals Current flowing through the capacitor ; Step S4: Calculate the charge accumulation of the bus capacitor during one charging cycle. ; Step S5: Based on the allowable value of midpoint potential fluctuation and charge accumulation Calculate the minimum bus capacitance. .

2. The method for calculating the bus support capacitance of a three-phase four-wire three-level circuit according to claim 1, characterized in that, The allowable value of midpoint potential fluctuation The calculation formula is as follows: in: This is the peak value of the three-phase output voltage of the three-level inverter, which is also the DC bus voltage; , , This refers to the three-phase output voltage of a three-level inverter.

3. The method for calculating the bus support capacitance of a three-phase four-wire three-level circuit according to claim 2, characterized in that, Three-phase output voltage of a three-level inverter , , The calculation is based on the DC bus voltage, as follows: in: The modulation ratio of a three-level inverter; The angular velocity of the SVPWM three-phase modulation wave; This is a charging cycle.

4. The method for calculating the bus support capacitance of a three-phase four-wire three-level circuit according to claim 3, characterized in that, The three-phase output current , , The calculation formula is as follows: 。 5. The method for calculating the bus support capacitance of a three-phase four-wire three-level circuit according to claim 4, characterized in that, The capacitor current The calculation formula is as follows: 。 6. The method for calculating the bus support capacitance of a three-phase four-wire three-level circuit according to claim 5, characterized in that, The charge accumulation The calculation formula is as follows: 。 7. The method for calculating the bus support capacitance of a three-phase four-wire three-level circuit according to claim 6, characterized in that, The minimum capacity of the bus capacitor The calculation formula is as follows: 。 8. An electronic device, characterized in that, include: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores instructions executable by the at least one processor, which executes the instructions stored in the memory to perform the method as described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store instructions that, when executed, cause the method as described in any one of claims 1-7 to be implemented.

10. A computer program product, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-7.

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