High-linearity grid voltage bootstrapped switch circuit

Abstract

The invention discloses a high-linearity gate voltage bootstrapped switching circuit which comprises an NMOS tube M1, a load capacitor, a capacitor charging circuit, a first control circuit, a second control circuit, a first switching circuit, a second switching circuit and a third switching circuit. A lower pole plate of the load capacitor is electrically connected with the signal input end through a first switching circuit, and an upper pole plate of the load capacitor is electrically connected with a grid electrode of the NMOS tube M1 through a second switching circuit; the first control circuit and the second control circuit enable the first switching circuit and the second switching circuit to be switched on in the tracking sampling state and enable the first switching circuit and the second switching circuit to be switched off in the holding state. According to the invention, the first control circuit is separated from the sampling tube, so that the stray capacitance on the grid electrode of the sampling tube is reduced, the charging and discharging speed on the grid electrode of the sampling tube is increased, the on-resistance of the grid electrode of the sampling tube is reduced, and the problems of overlarge stray capacitance, low switching speed, low linearity and the like of the sampling tube are effectively solved.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital converter circuits, and in particular relates to a gate voltage bootstrap switching circuit with high linearity. Background Technology

[0002] Analog-to-digital converters (ADCs) are widely used in signal acquisition, control systems, communication, and sensor interfaces. In high-precision, high-speed ADCs, the sample-and-hold (S / H) circuit is one of the core modules, and its function relies on high-speed, high-linearity analog switches to sample and hold the input analog signal.

[0003] To ensure sufficient conduction capability of the analog switch across the entire input range, its gate drive voltage must be higher than the signal level, especially when the input signal is close to the external power supply voltage (VDD). In this case, if an N-channel MOSFET is used as the switch, its source voltage may rise to near VDD. If the gate is still controlled by a fixed drive voltage, this will lead to a decrease in the switch's conduction capability or even turn it off. Furthermore, its on-resistance will vary with the input signal, introducing high-order harmonics at the output, resulting in nonlinear errors or sampling distortion.

[0004] To address this issue, introducing gate voltage bootstrapping technology can effectively improve the conduction performance of analog switches. By adding a bootstrapping switch circuit to the gate control path, the gate voltage is boosted to a value higher than the source voltage at the moment the MOSFET is turned on, ensuring low on-resistance across the entire signal range, thereby improving the linearity, dynamic range, and sampling accuracy of the ADC. However, traditional gate voltage bootstrapping switches introduce significant parasitic capacitance due to the connection of multiple MOSFETs to the sampling transistor, requiring a trade-off between circuit bandwidth and on-resistance.

[0005] Therefore, it is necessary to design a gate voltage bootstrap switch with a simple structure and low parasitic capacitance, which can achieve high bandwidth while maintaining low on-resistance, thereby effectively improving the linearity of the analog switch and the overall sampling accuracy of the system. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a gate voltage bootstrap switching circuit with high linearity.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A high-linearity gate voltage bootstrap switching circuit, including The source of NMOS transistor M1 is electrically connected to the signal input terminal of the gate voltage bootstrap switch circuit, and the drain is electrically connected to the signal output terminal of the gate voltage bootstrap switch circuit. The lower plate of the load capacitor C1 is electrically connected to the signal input terminal of the gate voltage bootstrap switch circuit through the first switching circuit, and its upper plate is electrically connected to the gate of the NMOS transistor M1 through the second switching circuit. The third switching circuit is used to discharge the voltage of the gate of NMOS transistor M1 to a low level in the holding state; A capacitor charging circuit is used to charge the load capacitor C1 in a holding state. A first control circuit is configured to turn on the first switching circuit in a tracking sampling state and turn off the first switching circuit in a holding state; and The second control circuit is used to turn on the second switching circuit in the tracking sampling state and turn off the second switching circuit in the holding state.

[0008] Furthermore, the gate voltage bootstrap switch circuit is connected to an external clock control signal CLK and an external clock control inverse signal CLKB, wherein the external clock control inverse signal CLKB is the inverse signal of the external clock control signal CLK; when the external clock control signal CLK switches to a low level, the gate voltage bootstrap switch circuit enters a holding state; when the external clock control signal CLK switches to a high level, the gate voltage bootstrap switch circuit enters a tracking sampling state.

[0009] Furthermore, the control terminal of the first control circuit is electrically connected to the first switching circuit, and is used to output a low level in the holding state and a high level in the tracking sampling state; the control terminal of the second control circuit is electrically connected to the second switching circuit, and is used to output a high level in the holding state and a low level in the tracking sampling state.

[0010] Furthermore, the first control circuit includes NMOS transistors M3, M4, and M5; the source of NMOS transistor M3 is grounded, and the gate of NMOS transistor M3 is connected to an external clock control inverting signal CLKB; the source of NMOS transistor M4 is electrically connected to the drain of NMOS transistor M3, and the gate of NMOS transistor M3 is connected to a power supply; the drain of PMOS transistor M5 is electrically connected to the drain of NMOS transistor M4 and serves as the control terminal of the first control circuit, which is electrically connected to the first switching circuit; the gate of PMOS transistor M5 is electrically connected to the control terminal of the second control circuit, and the source of PMOS transistor M5 is electrically connected to the upper plate of the load capacitor C1.

[0011] Furthermore, it also includes a faster switching circuit, which is defined as an NMOS transistor M13. The source of the NMOS transistor M13 is connected to an external clock control inverted signal CLKB, and the connection of the NMOS transistor M13 to an external clock control inverted delayed signal is also included. The external clock controls the inverse delay signal It is obtained by a short delay of the external clock control inverse signal CLKB.

[0012] Furthermore, the second control circuit includes a PMOS transistor M6 and an NMOS transistor M7. The source of the PMOS transistor M6 is connected to the power supply. The drain of the PMOS transistor M6 is electrically connected to the drain of the NMOS transistor M7 and serves as the control terminal of the second control circuit, which is electrically connected to the gate of the PMOS transistor M5 and the second switching circuit respectively. The gates of the PMOS transistor M6 and the NMOS transistor M7 are both connected to an external clock control signal CLK. The source of the NMOS transistor M7 is electrically connected to the lower plate of the load capacitor C1.

[0013] Furthermore, the first switching circuit is defined as an NMOS transistor M2; the drain of the NMOS transistor M2 is electrically connected to the signal input terminal of the gate voltage bootstrap switching circuit, the source of the NMOS transistor M2 is electrically connected to the lower plate of the load capacitor C1, and the gate of the NMOS transistor M2 is electrically connected to the control terminal of the first control circuit; the substrate of the NMOS transistor M1 is electrically connected to both the substrate of the NMOS transistor M2 and the source of the NMOS transistor M2.

[0014] Furthermore, the second switching circuit is defined as a PMOS transistor M8; the drain of the PMOS transistor M8 is electrically connected to the gate of the NMOS transistor M1, the source of the PMOS transistor M8 is electrically connected to the upper plate of the load capacitor C1, the gate of the PMOS transistor M8 is electrically connected to the control terminal of the second control circuit, and the substrate of the PMOS transistor M8 is electrically connected to its source.

[0015] Furthermore, the capacitor charging circuit includes a PMOS transistor M11 and an NMOS transistor M12. The drain of the PMOS transistor M11 is connected to the power supply, its gate is electrically connected to the gate of the NMOS transistor M1, and its source is electrically connected to the upper plate of the load capacitor C1. The drain of the NMOS transistor M12 is electrically connected to the lower plate of the load capacitor C1, its gate is connected to an external clock control inverted signal CLKB, and its source is grounded.

[0016] Furthermore, the third switching circuit includes NMOS transistors M9 and M10. The drain of NMOS transistor M9 is electrically connected to the gate of NMOS transistor M10, and the gate is connected to the power supply. The source of NMOS transistor M9 is electrically connected to the drain of NMOS transistor M10. The gate of NMOS transistor M10 is connected to an external clock control inverting signal CLKB, and the source is grounded. In this invention, by separating the first control circuit that controls the conduction of NMOS transistor M2 from NMOS transistor M1, the parasitic capacitance on the gate of MOS sampling transistor M1 is reduced, thereby increasing the charging and discharging speed of the gate of NMOS transistor M1 and reducing its on-resistance. By connecting the substrate of NMOS transistor M1 to the lower plate of load capacitor C1, the non-correlation between the gate voltage bootstrap switch on-resistance and the input signal is effectively improved, and the input-to-output coupling caused by the parasitic capacitance from the substrate to the output terminal is eliminated. This invention is suitable for the high-speed and high-precision sampling requirements of analog-to-digital converter circuits and effectively solves problems such as excessive parasitic capacitance of the sampling transistor, slow switching speed, and low linearity. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a circuit diagram of an embodiment of the high linearity gate voltage bootstrap switching circuit of the present invention.

[0018] Figure 2 This is a schematic diagram of the transient simulation of the gate-source voltage of a MOS sampling transistor.

[0019] Figure 3 This is a spectrum analysis diagram of the gate voltage bootstrap switch in this embodiment. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0021] Please see Figure 1 , Figure 1 This is a circuit diagram of an embodiment of the high linearity gate voltage bootstrap switching circuit of the present invention. The high linearity gate voltage bootstrap switching circuit of this embodiment includes an NMOS transistor M1, a load capacitor C1, a capacitor charging circuit, a first control circuit, a second control circuit, a first switching circuit, a second switching circuit, and a third switching circuit.

[0022] The gate voltage bootstrap switch circuit is generally connected to an external clock control signal CLK and an external clock control inverse signal CLKB. The external clock control inverse signal CLKB is the inverse signal of the external clock control signal CLK. When the external clock control signal CLK switches to a low level, the gate voltage bootstrap switch circuit enters a holding state. When the external clock control signal CLK switches to a high level, the gate voltage bootstrap switch circuit enters a tracking sampling state.

[0023] The NMOS transistor M1 is a MOS sampling transistor for the gate bootstrap switch. The source of the NMOS transistor M1 is electrically connected to the signal input terminal of the gate bootstrap switch circuit, and the drain of the NMOS transistor M1 is electrically connected to the signal output terminal of the gate bootstrap switch circuit. The lower plate of the load capacitor C1 is electrically connected to the signal input terminal of the gate bootstrap switch circuit through a first switching circuit, and the upper plate of the load capacitor C1 is electrically connected to the gate of the NMOS transistor M1 through a second switching circuit.

[0024] In this embodiment, the first switching circuit is defined as an NMOS transistor M2. The drain of the NMOS transistor M2 is electrically connected to the signal input terminal of the gate voltage bootstrap switching circuit, the source of the NMOS transistor M2 is electrically connected to the lower plate of the load capacitor C1, and the gate of the NMOS transistor M2 is electrically connected to the control terminal of the first control circuit; the substrate of the NMOS transistor M1 is electrically connected to both the substrate of the NMOS transistor M2 and the source of the NMOS transistor M2.

[0025] In this embodiment, the second switching circuit is defined as a PMOS transistor M8. The drain of the PMOS transistor M8 is electrically connected to the gate of the NMOS transistor M1, the source of the PMOS transistor M8 is electrically connected to the upper plate of the load capacitor C1, and the gate of the PMOS transistor M8 is electrically connected to the control terminal of the second control circuit; the substrate of the PMOS transistor M8 is electrically connected to its source.

[0026] The third switching circuit is used to discharge the gate voltage of NMOS transistor M1 to a low level in the holding state. In this embodiment, the third switching circuit includes NMOS transistors M9 and M10. The drain of NMOS transistor M9 is electrically connected to the gate of NMOS transistor M1. The gate of NMOS transistor M9 is connected to a power supply (voltage VDD), and the source of NMOS transistor M9 is electrically connected to the drain of NMOS transistor M10. The gate of NMOS transistor M10 is connected to an external clock control inverting signal CLKB, and the source of NMOS transistor M10 is grounded.

[0027] The capacitor charging circuit is used to charge the load capacitor C1 in a holding state. In this embodiment, the capacitor charging circuit may include a PMOS transistor M11 and an NMOS transistor M12. The drain of the PMOS transistor M11 is connected to the power supply, the gate of the PMOS transistor M11 is electrically connected to the gate of the NMOS transistor M1, and the source of the PMOS transistor M11 is electrically connected to the upper plate of the load capacitor C1. The drain of the NMOS transistor M12 is electrically connected to the lower plate of the load capacitor C1, the gate of the NMOS transistor M12 is connected to an external clock control inverting signal CLKB, and the source of the NMOS transistor M12 is grounded.

[0028] The first control circuit is used to turn on the first switching circuit in the tracking sampling state and to turn off the first switching circuit in the hold state. Specifically, the control terminal of the first control circuit is electrically connected to the gate of the NMOS transistor M2 in the first switching circuit. In the tracking sampling state, the control terminal of the first control circuit outputs a high level, turning on the NMOS transistor M2, thereby forming a connection path between the lower plate of the load capacitor C1 and the signal input terminal of the gate voltage bootstrap switching circuit. In the hold state, the control terminal of the first control circuit outputs a low level, turning off the NMOS transistor M2, thereby breaking the connection path between the lower plate of the load capacitor C1 and the signal input terminal of the gate voltage bootstrap switching circuit.

[0029] In this embodiment, the first control circuit includes NMOS transistors M3, M4, and M5; the source of NMOS transistor M3 is grounded, and the gate of NMOS transistor M3 is connected to an external clock control inverting signal CLKB; the source of NMOS transistor M4 is electrically connected to the drain of NMOS transistor M3, and the gate of NMOS transistor M3 is connected to a power supply; the drain of PMOS transistor M5 is electrically connected to the drain of NMOS transistor M4 and serves as the control terminal of the first control circuit, which is electrically connected to the first switching circuit; the gate of PMOS transistor M5 is electrically connected to the control terminal of the second control circuit, and the source of PMOS transistor M5 is electrically connected to the upper plate of the load capacitor C1.

[0030] To accelerate the switching speed from the hold state to the tracking sampling state, this embodiment also includes a faster switching circuit, which can be defined as an NMOS transistor M13. The source of the NMOS transistor M13 is connected to an external clock control inverted signal CLKB, and the connection of the NMOS transistor M13 to the external clock control inverted delayed signal... The external clock controls the inverse delay signal It is obtained by a short delay of the external clock control inverse signal CLKB.

[0031] The second control circuit is used to turn on the second switching circuit in the tracking sampling state and to turn off the second switching circuit in the hold state. Specifically, the control terminal of the second control circuit is electrically connected to the gate of the PMOS transistor M8 in the second switching circuit; in the tracking sampling state, the control terminal of the second control circuit outputs a low level, turning on the PMOS transistor M8, thereby forming a connection path between the upper plate of the load capacitor C1 and the gate of the NMOS transistor M1. In the hold state, the control terminal of the second control circuit outputs a high level, turning off the PMOS transistor M8, thereby breaking the connection path between the upper plate of the load capacitor C1 and the gate of the NMOS transistor M1.

[0032] In this embodiment, the second control circuit includes a PMOS transistor M6 and an NMOS transistor M7. The source of the PMOS transistor M6 is connected to the power supply. The drain of the PMOS transistor M6 is electrically connected to the drain of the NMOS transistor M7 and serves as the control terminal of the second control circuit, which is electrically connected to the gate of the PMOS transistor M5 and the second switching circuit respectively. The gates of the PMOS transistor M6 and the NMOS transistor M7 are both connected to an external clock control signal CLK. The source of the NMOS transistor M7 is electrically connected to the lower plate of the load capacitor C1.

[0033] The working principle of this embodiment is as follows: When the external clock control signal CLK is low, the external clock control inverting signal CLKB is high, and PMOS transistor M11 and NMOS transistor M12 are also turned on, charging the load capacitor C1. After charging is complete, the formula for calculating the charge Q of the load capacitor is: Q=VDD*C1 Since NMOS transistors M9 and M10 are turned on at this time, the voltage VG on the gate of MOS sampling transistor M1 (i.e., NMOS transistor M1) is discharged to a low level, thus turning off MOS sampling transistor M1. At this time, the gate bootstrap switch is in the holding state, and the output remains unchanged. Since the substrate of MOS sampling transistor M1 is connected to the lower plate of load capacitor C1, and the lower plate of load capacitor C1 is discharged to a low level through NMOS transistor M12, the substrate of MOS sampling transistor M1 is at a fixed level in the holding state. This eliminates the coupling from the input signal (i.e., the signal input from the signal input terminal of the gate bootstrap switch circuit) through the drain substrate capacitance of the MOS sampling transistor M1 to the signal output terminal of the gate bootstrap switch circuit.

[0034] When the external clock control signal CLK is high, the external clock control inverse signal CLKB is low. At this time, NMOS transistor M7 discharges the gate voltage VP of PMOS transistor M8 to a low level, turning on PMOS transistor M8. The power supply voltage VDD stored on the upper plate of load capacitor C1 is transferred to the gate voltage VG of MOS sampling transistor M1, causing MOS sampling transistor M1 to turn on. At this time, the gate voltage bootstrap switch is in tracking sampling mode, and its output voltage CDAC changes with the input voltage VIN. Simultaneously, PMOS transistor M5 turns on, and the power supply voltage stored on the upper plate of load capacitor C1 is also transferred to the gate of NMOS transistor M2, increasing the gate voltage of NMOS transistor M2 and turning it on. This allows the input signal voltage VIN to be transferred to the lower plate of load capacitor C1. Due to the conservation of charge on load capacitor C1, the voltage across load capacitor C1 remains constant, resulting in VG = VDD + VIN. At this time, the gate-source voltage VGS = VG - VIN = VDD on NMOS transistor M1 remains constant. Furthermore, due to the activation of NMOS transistor M2, the substrate of MOS sampling transistor M1 also changes with the input voltage VIN, eliminating the influence of substrate bias on the threshold voltage of MOS sampling transistor M1. According to the on-resistance formula for a MOS transistor in the deep linear region:

[0035] Where Ron is the on-resistance of the MOS sampling transistor M1. For electron mobility, The capacitance per unit area of ​​the gate oxide layer. The aspect ratio of the MOS sampling transistor M1 is... This is the threshold voltage of the MOS sampling transistor M1. Therefore, during the tracking sampling state, the on-resistance of the MOS sampling transistor M1 is very small and remains constant.

[0036] In addition, this embodiment also introduces an NMOS transistor M13, whose working principle is as follows: Due to the external clock control reverse delay signal The external clock control inverted signal CLKB is obtained after a short delay. At the beginning of the sampling phase, the external clock control inverted signal CLKB goes low, while the external clock control inverted delayed signal... The voltage remains high, turning on NMOS transistor M13 and rapidly pulling down voltage VP, thus accelerating the turn-on of PMOS transistors M5 and M8. After a short delay, before NMOS transistor M2 fully turns on, PMOS transistor M13 has already turned off, thus not affecting the normal operation of the gate bootstrap circuit.

[0037] The parasitic capacitance Cg on the gate of the MOS sampling transistor M1 limits the circuit bandwidth. According to the principle of charge conservation, Q = (C1 + Cg)VG, therefore VG = This reduces the voltage on the gate of the sampling transistor, which in turn increases the on-resistance of the MOS sampling transistor M1. Compared to a traditional gate-bootstrapping switch, this embodiment uses a first control circuit (including NMOS transistors M3, M4, and M5) separate from the MOS sampling transistor M1 to control the NMOS transistor M2, reducing the parasitic capacitance on the gate of the MOS sampling transistor M1. This increases the charging and discharging speed of the gate of the MOS transistor M1 and reduces its on-resistance. Furthermore, using a deep N-well MOS transistor to connect the substrate of the MOS sampling transistor M1 to the lower plate of the load capacitor C1 ensures the constant source-substrate voltage of the MOS sampling transistor M1 during tracking sampling, i.e., the constant threshold voltage of the MOS sampling transistor M1. This effectively improves the decorrelation between the on-resistance of the gate-bootstrapping switch and the input signal, maintains a constant state substrate voltage, and eliminates input-to-output coupling caused by the parasitic capacitance from the substrate to the output.

[0038] Please see Figure 2 The transient voltages of the gate voltage Vg and input voltage Vs of the MOS sampling transistor M1 were recorded. The power supply voltage VDD was 1.8V. During the sampling phase, the voltage Vgs between the gate and source was fixed near the power supply voltage by the bootstrap circuit. Please refer to [link to relevant documentation]. Figure 3 The diagram shows the spectrum analysis of the gate voltage bootstrap switch. The clock frequency used is 80MHz, the analog input swing is 3.5V, and under Nyquist input conditions, the invented gate voltage bootstrap switch achieves an SNDR of 108.12dB, an SFDR of 109.42dB, and an ENOB of 17.67 bits.

[0039] In this embodiment, by separating the first control circuit that controls the conduction of NMOS transistor M2 from MOS sampling transistor M1, the parasitic capacitance on the gate of MOS sampling transistor M1 is reduced, thereby increasing the charging and discharging speed of the gate of MOS sampling transistor M1 and reducing its on-resistance. By connecting the substrate of MOS sampling transistor M1 to the lower plate of load capacitor C1, the non-correlation between the gate voltage bootstrap switch on-resistance and the input signal is effectively improved, and the input-to-output coupling caused by the parasitic capacitance from the substrate to the output terminal is eliminated. This circuit is suitable for the high-speed and high-precision sampling requirements of analog-to-digital converter circuits, and effectively solves the problems of excessive parasitic capacitance of sampling transistors, slow switching speed, and low linearity.

[0040] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A high-linearity gate voltage bootstrap switching circuit, characterized in that: include The source of NMOS transistor M1 is electrically connected to the signal input terminal of the gate voltage bootstrap switch circuit, and the drain is electrically connected to the signal output terminal of the gate voltage bootstrap switch circuit. The lower plate of the load capacitor C1 is electrically connected to the signal input terminal of the gate voltage bootstrap switch circuit through the first switching circuit, and its upper plate is electrically connected to the gate of the NMOS transistor M1 through the second switching circuit. The third switching circuit is used to discharge the voltage of the gate of NMOS transistor M1 to a low level in the holding state; A capacitor charging circuit is used to charge the load capacitor C1 in a holding state. The first control circuit is used to turn on the first switching circuit in the tracking sampling state and turn off the first switching circuit in the holding state. as well as The second control circuit is used to turn on the second switching circuit in the tracking sampling state and turn off the second switching circuit in the holding state.

2. The high linearity gate voltage bootstrap switching circuit as described in claim 1, characterized in that: The gate voltage bootstrap switch circuit is connected to an external clock control signal CLK and an external clock control inverse signal CLKB. The external clock control inverse signal CLKB is the inverse signal of the external clock control signal CLK. When the external clock control signal CLK switches to a low level, the gate voltage bootstrap switch circuit enters a hold state. When the external clock control signal CLK switches to a high level, the gate voltage bootstrap switch circuit enters a tracking sampling state.

3. The high linearity gate voltage bootstrap switching circuit as described in claim 2, characterized in that: The control terminal of the first control circuit is electrically connected to the first switching circuit, and is used to output a low level in the holding state and a high level in the tracking sampling state; the control terminal of the second control circuit is electrically connected to the second switching circuit, and is used to output a high level in the holding state and a low level in the tracking sampling state.

4. The high linearity gate voltage bootstrap switching circuit as described in claim 3, characterized in that: The first control circuit includes NMOS transistors M3, M4, and M5; the source of NMOS transistor M3 is grounded, and the gate of NMOS transistor M3 is connected to an external clock control inverting signal CLKB; the source of NMOS transistor M4 is electrically connected to the drain of NMOS transistor M3, and the gate of NMOS transistor M3 is connected to a power supply; the drain of PMOS transistor M5 is electrically connected to the drain of NMOS transistor M4 and serves as the control terminal of the first control circuit, which is electrically connected to the first switching circuit; the gate of PMOS transistor M5 is electrically connected to the control terminal of the second control circuit, and the source of PMOS transistor M5 is electrically connected to the upper plate of the load capacitor C1.

5. The high linearity gate voltage bootstrap switching circuit as described in claim 4, characterized in that: It also includes a faster switching circuit, which is defined as an NMOS transistor M13. The source of the NMOS transistor M13 is connected to an external clock control inverted signal CLKB, and the connection of the NMOS transistor M13 to an external clock control inverted delayed signal is... The external clock controls the inverse delay signal It is obtained by a short delay of the external clock control inverse signal CLKB.

6. The high linearity gate voltage bootstrap switching circuit as described in claim 3, characterized in that: The second control circuit includes a PMOS transistor M6 and an NMOS transistor M7. The source of the PMOS transistor M6 is connected to the power supply. The drain of the PMOS transistor M6 is electrically connected to the drain of the NMOS transistor M7 and serves as the control terminal of the second control circuit. It is also electrically connected to the gate of the PMOS transistor M5 and the second switching circuit. The gates of both the PMOS transistor M6 and the NMOS transistor M7 are connected to an external clock control signal CLK. The source of the NMOS transistor M7 is electrically connected to the lower plate of the load capacitor C1.

7. The high linearity gate voltage bootstrap switching circuit as described in any one of claims 1 to 6, characterized in that: The first switching circuit is defined as an NMOS transistor M2; the drain of the NMOS transistor M2 is electrically connected to the signal input terminal of the gate voltage bootstrap switching circuit, the source of the NMOS transistor M2 is electrically connected to the lower plate of the load capacitor C1, and the gate of the NMOS transistor M2 is electrically connected to the control terminal of the first control circuit; the substrate of the NMOS transistor M1 is electrically connected to the substrate of the NMOS transistor M2 and the source of the NMOS transistor M2, respectively.

8. The high linearity gate voltage bootstrap switching circuit as described in any one of claims 1 to 6, characterized in that: The second switching circuit is defined as a PMOS transistor M8; the drain of the PMOS transistor M8 is electrically connected to the gate of the NMOS transistor M1, the source of the PMOS transistor M8 is electrically connected to the upper plate of the load capacitor C1, the gate of the PMOS transistor M8 is electrically connected to the control terminal of the second control circuit, and the substrate of the PMOS transistor M8 is electrically connected to its source.

9. The high linearity gate voltage bootstrap switching circuit as described in any one of claims 2 to 6, characterized in that: The capacitor charging circuit includes a PMOS transistor M11 and an NMOS transistor M12. The drain of the PMOS transistor M11 is connected to the power supply, the gate is electrically connected to the gate of the NMOS transistor M1, and the source is electrically connected to the upper plate of the load capacitor C1. The drain of the NMOS transistor M12 is electrically connected to the lower plate of the load capacitor C1, the gate is connected to the external clock control inverted signal CLKB, and the source is grounded.

10. The high linearity gate voltage bootstrap switching circuit as described in any one of claims 2 to 6, characterized in that: The third switching circuit includes NMOS transistors M9 and M10. The drain of NMOS transistor M9 is electrically connected to the gate of NMOS transistor M1, and the gate is connected to the power supply. The source of NMOS transistor M9 is electrically connected to the drain of NMOS transistor M10. The gate of NMOS transistor M10 is connected to the external clock control inverted signal CLKB, and the source is grounded.

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