Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes: a first insulating layer having a first surface and a second surface opposite to each other in a thickness direction of the printed circuit board; a second insulating layer provided on a first surface side of the first insulating layer; a conductive via extending between the first surface and the second surface of the first insulating layer; an inner conductor layer disposed between an inner wall of a through hole formed in the thickness direction of the first insulating layer and the conductive via hole; a first pad disposed on a first surface side of the first insulating layer, the first pad including a first conductor layer and a second conductor layer disposed on the first conductor layer; and a second pad disposed on a second surface of the first insulating layer, the second pad including a third conductor layer and a fourth conductor layer. The inner conductor layer forms an interface with and is in contact with the first conductor layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0142935, filed on October 18, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a printed circuit board. Background Technology

[0003] Recently, in response to the trend of lighter and smaller mobile devices, the demand for lighter and thinner printed circuit boards (PCBs) mounted on them has been increasing. Furthermore, as mobile devices become lighter and thinner, undercutting may occur during the manufacturing process of fine circuits, potentially causing defects in these circuits. To address this technological need, ongoing research is being conducted on achieving circuits with fine linewidths and spacing while improving reliability. Summary of the Invention

[0004] This disclosure provides a printed circuit board on which circuits with fine linewidths and spacing can be implemented.

[0005] According to an example embodiment of this disclosure, a printed circuit board includes: a first insulating layer having a first surface and a second surface opposite to each other in the thickness direction of the printed circuit board; a second insulating layer disposed on the first surface side of the first insulating layer; a conductive via disposed in a through-hole formed in the first insulating layer along the thickness direction; an inner conductor layer disposed between the inner wall of the through-hole and the conductive via; and a first pad disposed on the first surface side of the first insulating layer, and including a first conductor layer and a second conductor layer disposed on the first conductor layer, wherein the inner conductor layer forms an interface with the first conductor layer and is in contact with the first conductor layer.

[0006] The upper surface of the inner conductor layer can contact the lower surface of the first conductor layer.

[0007] The upper surface of the inner conductor layer and the upper surface of the second insulating layer can form a coplanar surface.

[0008] The inner conductor layer may not cover the upper surface of the second insulating layer.

[0009] The inner conductor layer may not be in contact with the second conductor layer.

[0010] The inner conductor layer includes a first inner conductor layer and a second inner conductor layer, wherein the first inner conductor layer may be configured to be closer to the inner wall of the via than the second inner conductor layer.

[0011] The upper surfaces of the first inner conductor layer and the second inner conductor layer can contact the lower surface of the first conductor layer.

[0012] The upper surfaces of the first inner conductor layer and the second inner conductor layer can form coplanar surfaces with the upper surface of the second insulating layer.

[0013] The first inner conductor layer and the second inner conductor layer may not cover the upper surface of the second insulating layer.

[0014] The first inner conductor layer and the second inner conductor layer may not be in contact with the second conductor layer.

[0015] The conductive via may have the form of protruding from the first surface of the first insulating layer to the outside of the first insulating layer beyond the inner conductor layer.

[0016] The region of the second conductor layer corresponding to the conductive via may have a shape that protrudes outward toward the first pad.

[0017] The conductive via can also be configured to protrude outward from the second surface of the first insulating layer.

[0018] The thickness of the first conductor layer can be greater than or equal to 0.5 μm and less than or equal to 2 μm.

[0019] The distance by which the first pad protrudes laterally from the via in the first insulating layer can be less than or equal to 25 μm.

[0020] According to another example embodiment of this disclosure, a printed circuit board includes: a first insulating layer having a first surface and a second surface opposite to each other in the thickness direction of the printed circuit board; a second insulating layer disposed on the first surface side of the first insulating layer; a conductive via disposed in a through-hole formed in the first insulating layer along the thickness direction; an inner conductor layer disposed between the inner wall of the through-hole and the conductive via; a first pad disposed on the first surface side of the first insulating layer, the first pad including a first conductor layer and a second conductor layer disposed on the first conductor layer; and a second pad disposed on the second surface side of the first insulating layer, the second pad including a third conductor layer and a fourth conductor layer disposed on the third conductor layer, wherein the inner conductor layer forms an interface with the first conductor layer and is in contact with the first conductor layer. Attached Figure Description

[0021] The above and other aspects, features, and advantages of this disclosure will be more clearly understood through the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1It is a block diagram that schematically illustrates an example of an electronic device system; Figure 2 It is a perspective view schematically illustrating an example of an electronic device; Figure 3 This is a schematic cross-sectional view illustrating an example of a printed circuit board; Figure 4 yes Figure 3 An enlarged view of part A; Figure 5 This is a schematic cross-sectional view illustrating another example of a printed circuit board; Figure 6 This is a schematic cross-sectional view illustrating another example of a printed circuit board; and Figures 7 to 15 An example of a method for manufacturing printed circuit boards is shown. Detailed Implementation

[0022] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. However, the present disclosure may be exemplified in many different forms and should not be construed as being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Therefore, for clarity of description, the shape and size of the elements in the drawings may be exaggerated, and in the drawings, elements denoted by the same reference numerals are the same elements.

[0023] Electronic devices Figure 1 This is a block diagram that schematically illustrates an example of an electronic device system.

[0024] Reference Figure 1 The electronic device 1000 may house a motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the motherboard 1010. These components may be connected to other electronic components described below via various signal lines 1090.

[0025] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing unit (CPU)), graphics processing units (e.g., graphics processing unit (GPU)), digital signal processors, encryption processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 can be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips.

[0026] Network-related components 1030 may include components compatible with or operating according to standards or protocols such as: Wireless Fidelity (Wi-Fi) (IEEE 802.11 series, etc.), Global Microwave Access Interoperability (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolved Data Optimized (Ev-DO), High Speed ​​Packet Access+ (HSPA+), High Speed ​​Downlink Packet Access+ (HSDPA+), High Speed ​​Uplink Packet Access+ (HSUPA+), Global System for Mobile Communications (GSM), Evolution of GSM with Enhanced Data Rates (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), 3G, 4G, and 5G protocols, and any other wireless or wired standards or protocols specified after the foregoing. However, network-related components 1030 are not limited to these and may also include components compatible with or operating according to various other wireless or wired standards or protocols. In addition, the network-related component 1030 can be combined with the aforementioned chip-related component 1020.

[0027] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with the aforementioned chip-related components 1020 and / or network-related components 1030.

[0028] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, other electronic components are not limited to these and may include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. Depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0029] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital video camera, digital camera, network system, computer, monitor, tablet computer, laptop computer, netbook, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these, but can be any other electronic device capable of processing data.

[0030] Figure 2 It is a perspective view schematically showing an example of an electronic device.

[0031] Reference Figure 2 The electronic device can be a smartphone 1100. A motherboard 1110 can be housed in the smartphone 1100, and various components 1120 can be physically and / or electrically connected to the motherboard 1110. Furthermore, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the motherboard 1110 or not physically and / or electrically connected to the motherboard 1110 can be housed in the smartphone 1100. A portion of component 1120 can be a chip-related component, such as component package 1121, but its exemplary embodiments are not limited thereto. Component package 1121 can have the form where electronic components (including active and / or passive components) are surface-mounted on a printed circuit board. Optionally, component package 1121 can have the form where electronic components (including active and / or passive components) are embedded in a printed circuit board. The electronic device is not limited to the smartphone 1100 and can be other electronic devices as described above.

[0032] Printed Circuit Board Figure 3 It is a schematic cross-sectional view of an example of a printed circuit board, and Figure 4 yes Figure 3 An enlarged view of part A. (Refer to...) Figure 3 and Figure 4 The printed circuit board 100 according to this embodiment includes a first insulating layer 101, a second insulating layer 102, a conductive via 130, an inner conductor layer 140, and a first pad 110 including a first conductor layer 111 and a second conductor layer 112. Here, the inner conductor layer 140 disposed in the via of the first insulating layer 101 forms an interface with and contacts the first conductor layer 111. In other words, the inner conductor layer 140 and the first conductor layer 111 are not an integral structure but independent structures to form an interface between them. With this structure, the conductive via 130, the first pad 110, etc., can be finer, and the pitch between them can be effectively reduced.

[0033] The first insulating layer 101 may be a core insulating layer. The first insulating layer 101 may include insulating materials, such as insulating resins (e.g., thermosetting resins such as epoxy resins or thermoplastic resins such as polyimide), materials that mix these insulating resins with inorganic fillers (e.g., silica), or materials prepared by impregnating a core material (e.g., glass fiber (e.g., glass fabric, such as glass cloth)) together with inorganic fillers into thermosetting and / or thermoplastic resins (e.g., copper-clad laminates (CCLs)), but exemplary embodiments thereof are not limited thereto. The first insulating layer 101 has a thickness direction (based on) of the printed circuit board 100. Figure 3 The first surface S1 and the second surface S2 are opposite to each other in the vertical direction as shown in the diagram. Additionally, a through-hole H is formed in the first insulating layer 101 along the thickness direction (e.g., ...). Figure 8 (As shown in the diagram). The first insulating layer 101 may be thicker than the second insulating layer 102 and the third insulating layer 103, which are respectively disposed on the first surface S1 side and the second surface S2 side. In this case, the thickness of the corresponding layer can be measured using a scanning electron microscope or an optical microscope based on a polished or cut section of the printed circuit board in the vertical direction. When the thickness is not constant, the thickness relationship between the corresponding layers can be compared by using the average of the thicknesses of the corresponding layers measured at five arbitrary points.

[0034] The second insulating layer 102 may be disposed on the first surface S1 side of the first insulating layer 101, and the third insulating layer 103 may be disposed on the second surface S2 side of the first insulating layer 101. Examples of insulating materials that may be included in the second insulating layer 102 and the third insulating layer 103 include insulating resins (such as thermosetting resins (such as epoxy resins) or thermoplastic resins (such as polyimide)), materials that mix these insulating resins with inorganic fillers (such as silica), or materials prepared by impregnating a core material (such as glass fiber (such as glass fabric, for example glass cloth)) together with inorganic fillers into thermosetting and / or thermoplastic resins (e.g., Ajinomoto laminate (ABF), prepreg, etc.), but exemplary embodiments are not limited thereto. Additionally, as further insulating layers, a fourth insulating layer 104 and a fifth insulating layer 105 may be disposed on the first surface S1 side and the second surface S2 side of the first insulating layer 101, respectively, and the fourth insulating layer 104 and the fifth insulating layer 105 may be laminated insulating layers.

[0035] The printed circuit board 100 may further include a second pad 120. A conductive via 130 may be disposed in a through-hole formed along the thickness direction in the first insulating layer 101, and the first pad 110 and the second pad 120 may be connected to each other through the conductive via 130. Additionally, an inner conductor layer 140 may be disposed between the inner wall of the through-hole in the first insulating layer 101 and the conductive via 130. In this case, the inner conductor layer 140 may include multiple conductor layers; for example, the inner conductor layer 140 may include a first inner conductor layer 141 and a second inner conductor layer 142. Here, the first inner conductor layer 141 may be positioned closer to the inner wall of the through-hole in the first insulating layer 101 than the second inner conductor layer 142.

[0036] The conductive via 130 may comprise metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and may perform various functions depending on its design. For example, the conductive via 130 may comprise a ground via, a power via, a signal via, etc. In the example, after forming the inner conductor layer 140 by plating, the conductive via 130 may be formed by filling the via with a plug. Based on the plane of the printed circuit board viewed from above, the conductive via 130 may have a generally circular or elliptical shape. Additionally, in terms of ensuring adhesion by increasing the specific surface area, the conductive via 130 may have a polygonal shape on the plane, as well as the shape of a flower in which many circles or ellipses are stacked, for example, a flower may have multiple petals arranged in a radially symmetrical or bilaterally symmetrical manner around a stamen. Specifically, when viewed from above, the conductive via 130 may have a trumpet shape, a lip shape, but is not limited to these; the conductive via 130 may have other flower shapes.

[0037] The first pad 110 is disposed on the first surface S1 side of the first insulating layer 101 and includes a first conductor layer 111 and a second conductor layer 112. Additionally, the second pad 120 may be disposed on the second surface S2 side of the first insulating layer 101, and the second pad 120 may include a third conductor layer 121 and a fourth conductor layer 122 disposed on the third conductor layer 121. The second pad 120 may be implemented in the same form as the first pad 110, and the structure of the first pad 110 and the conductive via 130 located on the first surface S1 side of the first insulating layer 101 will be described below; however, this description can also be applied to the second pad 120 and the conductive via 130 located on the second surface S2 side of the first insulating layer 101.

[0038] In this embodiment, the inner conductor layer 140 forms an interface with and contacts the first conductor layer 111. As a more specific example, the upper surface of the inner conductor layer 140 may contact the lower surface of the first conductor layer 111. Additionally, as... Figure 4 As shown, the upper surface of the inner conductor layer 140 and the upper surface of the second insulating layer 102 can form a coplanar surface. Such a coplanar structure can be obtained by performing a process such as polishing the portion of the inner conductor layer 140 disposed above the second insulating layer 102 (described later). More specifically, the inner conductor layer 140 may not cover the upper surface of the second insulating layer 102. Furthermore, the inner conductor layer 140 may not be in contact with the second conductor layer 112.

[0039] When the inner conductor layer 140 includes a first inner conductor layer 141 and a second inner conductor layer 142, the upper surfaces of the first inner conductor layer 141 and the second inner conductor layer 142 may contact the lower surface of the first conductor layer 111. The upper surfaces of the first inner conductor layer 141 and the second inner conductor layer 142 may be coplanar with the upper surface of the second insulating layer 102. The first inner conductor layer 141 and the second inner conductor layer 142 may not cover the upper surface of the second insulating layer 102. The first inner conductor layer 141 and the second inner conductor layer 142 may not contact the second conductor layer 112.

[0040] As described above, in this embodiment, the inner conductor layer 140 can be formed by a separate process (e.g., a separate plating process) instead of being integrally formed with the first conductor layer 111, allowing the inner conductor layer 140 and the first conductor layer 111 to form an interface and be in contact with each other. If the inner conductor layer 140 and the first conductor layer 111 are plated simultaneously and integrally formed, it may be difficult to achieve fine circuitry in subsequent etching processes. In this embodiment, after etching the region of the inner conductor layer 140 formed on the second insulating layer 102, a relatively thin first conductor layer 111 can be formed, thus allowing the first pad 110 to be finer. In other words, the inner conductor layer 140 can be formed separately from the first conductor layer 111, allowing the first pad 110 to be formed thin and narrow even after etching, thus enabling a greater number of conductive vias 130 to be provided in the same space. Specifically, the thickness t of the first conductor layer 111 can be greater than or equal to 0.5 μm and less than or equal to 2 μm. Furthermore, the distance d from which the first pad 110 protrudes laterally from the via in the first insulating layer 101 can be reduced to less than or equal to 25 μm. Therefore, the size of the first pad 110 can be reduced, and alignment with the conductive via 130 can be improved. In addition, the spacing between the conductive vias 130 can be finer; for example, the spacing between adjacent conductive vias 130 can be less than or equal to 300 μm.

[0041] In addition, such as Figure 5 As shown in the variant example, the conductive via 130 may have the form of protruding outward from the first surface S1 of the first insulating layer 101 beyond the inner conductor layer 140. In this case, as... Figure 6 In a variant example, the second conductor layer 112 may have a shape in which the region corresponding to the conductive via 130 protrudes outward toward the first pad 110. Additionally, the conductive via 130 may protrude outward from the first surface S1 of the first insulating layer 101. When the conductive via 130 has the protruding structure shown in the variant example, the electrical and physical contact between the conductive via 130 and the first pad 110 is improved.

[0042] Furthermore, when describing other components of the printed circuit board 100, conductor patterns 151 and 161 may be respectively disposed on the first pad 110 and the second pad 120. In this case, vias 152 connecting the first pad 110 and conductor pattern 151 and vias 162 connecting the second pad 120 and conductor pattern 161 may be provided. In addition, conductor patterns 151 and 161 may also be disposed at the same height as the first pad 110 and the second pad 120.

[0043] In the following text, reference will be made to Figures 7 to 15An example describing a method for manufacturing printed circuit boards. First, refer to... Figure 7 and Figure 8 A first insulating layer 101 is provided, and a through-hole H penetrating the first insulating layer 101 in the thickness direction is formed. Here, a second insulating layer 102 and a third insulating layer 103 are respectively provided on the first surface S1 and the second surface S2 of the first insulating layer 101. As an example, the second insulating layer 102 and the third insulating layer 103 can be formed by stacking ABF on the two surfaces of the first insulating layer 101 remaining after removing copper foil from the two surfaces of the copper clad laminate (CCL). The through-hole H of the first insulating layer 101 can be formed by a suitable processing method (e.g., laser processing), and then a decontamination process can be performed.

[0044] Next, as Figure 9 As shown, an inner conductor layer 140 can be formed in the through-hole H of the first insulating layer 101, and in addition to forming the inner conductor layer 140 in the through-hole H, the inner conductor layer 140 can also be formed on the first surface S1 side and the second surface S2 side of the first insulating layer 101. The inner conductor layer 140 may include a first inner conductor layer 141 and a second inner conductor layer 142, and in this case, the first inner conductor layer 141 can be formed by an electroless plating process, and the second inner conductor layer 142 can be formed by an electrolytic plating process. Subsequently, refer to Figure 10 The conductive via 130' can be formed using processes such as filling the via H of the first insulating layer 101 with a plug, and in addition, plating processes used in related technical fields can be used. Subsequently, if necessary, the outwardly protruding areas of the conductive via 130' can be removed by a polishing process (e.g., Figure 11 As shown in the image).

[0045] Next, as Figure 12 As shown, at least a portion of the inner conductor layer 140 disposed on the first surface S1 side and the second surface S2 side of the first insulating layer 101 is removed. In this process, the upper surface of the second insulating layer 102 and the upper surface of the inner conductor layer 140 can form a coplanar surface. Additionally, the conductive via 130 can be further polished to remove areas protruding in the vertical direction. Optionally, refer back to the reference. Figure 11 The area of ​​the conductive via 130 protruding vertically from the second insulating layer 102 can be kept as is, and in this case, the following can be obtained: Figure 5 The structure. (Refer to...) Figure 13 and Figure 14 This forms a first conductor layer 111, a third conductor layer 121, a second conductor layer 112, and a fourth conductor layer 122. Here, as an example of the process, the second conductor layer 112 and the fourth conductor layer 122 can be formed by forming a mask layer 250 and then performing a patterning deposition process on the opening areas. Subsequently, as... Figure 15As shown, the mask layer 250 can be removed, and a portion of the conductor layers 111, 112, 121, and 122 can be removed by an etching process to obtain the first pad 110 and the second pad 120 having the above-described structure. Subsequently, a printed circuit board of the above-described form can be obtained by a suitable deposition process.

[0046] In this disclosure, the term "section" can refer to a section when an object is cut vertically, or a section when the object is viewed from the side. Furthermore, the term "plane" can refer to a plane when an object is cut horizontally, or a plane when the object is viewed from the top or bottom.

[0047] In this disclosure, for convenience, the term "upper" in "upper side," "upper part," and "upper surface" refers to the upward direction relative to the cross-section of the drawing, and the term "lower side," "lower part," and "lower surface" refers to the direction opposite to the upward direction. However, the above directions are defined for ease of interpretation, and the scope of the claims is not specifically limited by the description of the directions, and the concepts of upper / lower can be changed at any time.

[0048] In this disclosure, the term "connection" includes not only direct connections but also indirect connections such as those via adhesive layers. Furthermore, the term "electrical connection" encompasses both physical and non-physical connections. Additionally, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component.

[0049] The term "example embodiment" as used in this disclosure does not imply the same embodiment, but is provided to explain different unique features. However, the example embodiments presented above do not preclude implementation in combination with features of other example embodiments. For example, even if matters described in a particular example embodiment are not described in other example embodiments, they may be understood as explanations relating to other example embodiments, unless there is an interpretation contrary to or contradicting the matters in other example embodiments.

[0050] The terminology used in this disclosure is for describing exemplary embodiments only and is not intended to limit the disclosure. In this context, singular expressions include plural expressions as well, unless the context clearly indicates otherwise.

[0051] As described above, the printed circuit board according to the exemplary embodiments of this disclosure may be provided with circuits having fine linewidths and spacing.

[0052] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: The first insulating layer has a first surface and a second surface that are opposite to each other in the thickness direction of the printed circuit board; The second insulating layer is disposed on the first surface side of the first insulating layer; A conductive via is disposed in a through-hole formed in the first insulating layer along the thickness direction; An inner conductor layer is disposed between the inner wall of the through hole and the conductive via; and A first pad is disposed on the first surface side of the first insulating layer, and includes a first conductor layer and a second conductor layer disposed on the first conductor layer. The inner conductor layer forms an interface with the first conductor layer and is in contact with the first conductor layer.

2. The printed circuit board according to claim 1, wherein, The upper surface of the inner conductor layer is in contact with the lower surface of the first conductor layer.

3. The printed circuit board according to claim 2, wherein, The upper surface of the inner conductor layer and the upper surface of the second insulating layer form a coplanar surface.

4. The printed circuit board according to claim 2, wherein, The inner conductor layer does not cover the upper surface of the second insulating layer.

5. The printed circuit board according to claim 1, wherein, The inner conductor layer does not contact the second conductor layer.

6. The printed circuit board according to claim 1, wherein, The inner conductor layer includes a first inner conductor layer and a second inner conductor layer, wherein the first inner conductor layer is configured to be closer to the inner wall of the via than the second inner conductor layer.

7. The printed circuit board according to claim 6, wherein, The upper surfaces of the first inner conductor layer and the second inner conductor layer are in contact with the lower surface of the first conductor layer.

8. The printed circuit board according to claim 7, wherein, The upper surfaces of the first inner conductor layer and the second inner conductor layer form coplanar surfaces with the upper surface of the second insulating layer.

9. The printed circuit board according to claim 7, wherein, The first inner conductor layer and the second inner conductor layer do not cover the upper surface of the second insulating layer.

10. The printed circuit board according to claim 7, wherein, The first inner conductor layer and the second inner conductor layer are not in contact with the second conductor layer.

11. The printed circuit board according to claim 1, wherein, The conductive via protrudes outward from the first surface of the first insulating layer beyond the inner conductor layer.

12. The printed circuit board according to claim 11, wherein, The region of the second conductor layer corresponding to the conductive via has a shape that protrudes outward toward the first pad.

13. The printed circuit board according to claim 12, wherein, The conductive via is also configured to protrude outward from the second surface of the first insulating layer.

14. The printed circuit board according to claim 1, wherein, The thickness of the first conductor layer is greater than or equal to 0.5 μm and less than or equal to 2 μm.

15. The printed circuit board according to claim 1, wherein, The distance by which the first pad protrudes laterally from the via in the first insulating layer is less than or equal to 25 μm.

16. A printed circuit board, comprising: The first insulating layer has a first surface and a second surface that are opposite to each other in the thickness direction of the printed circuit board; The second insulating layer is disposed on the first surface side of the first insulating layer; A conductive via is disposed in a through-hole formed along the thickness direction of the first insulating layer; An inner conductor layer is disposed between the inner wall of the through hole and the conductive via. A first pad is disposed on the first surface side of the first insulating layer. The first pad includes a first conductor layer and a second conductor layer disposed on the first conductor layer. as well as The second pad is disposed on the second surface side of the first insulating layer. The second pad includes a third conductor layer and a fourth conductor layer disposed on the third conductor layer. The inner conductor layer forms an interface with the first conductor layer and is in contact with the first conductor layer.

17. The printed circuit board according to claim 16, wherein, The conductive via has a protruding structure that extends along the thickness direction beyond the first surface of the first insulating layer and the second surface of the first insulating layer.

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