Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a semiconductor column and a gate structure, the semiconductor column extends in the first direction, the gate structure is located on the side wall, extending in the first direction, of the semiconductor column and comprises a gate layer and a barrier layer, and the barrier layer is located on the side, away from the semiconductor column, of the gate layer.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and in particular to semiconductor devices and their fabrication methods and storage systems. Background Technology

[0002] Semiconductor devices are memory devices used to store information in modern information technology. Their main function is to store programs and various data, and to perform high-speed and automatic access to programs or data during computer operation. Taking DRAM (Dynamic Random Access Memory) as an example, DRAM typically includes multiple memory cells. Each memory cell includes a transistor and a capacitor. One end of the transistor is connected to the capacitor, and the other end of the transistor is connected to the bit line.

[0003] Currently, how to further improve the performance of semiconductor devices is one of the technical problems that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a semiconductor device, a method for fabricating the same, and a storage system.

[0005] The first aspect of this application provides a semiconductor device including a semiconductor pillar and a gate structure. The semiconductor pillar extends along a first direction, and the gate structure is located on the sidewall of the semiconductor pillar extending along the first direction. The gate structure includes a gate layer and a barrier layer, and the barrier layer is located on the side of the gate layer opposite to the semiconductor pillar.

[0006] In some embodiments, the gate structure further includes a gate dielectric layer located between the gate layer and the semiconductor pillar.

[0007] In some embodiments, the gate structure further includes a gate adhesive layer located between the gate dielectric layer and the gate layer.

[0008] In some implementations, the gate adhesive layer and the barrier layer are made of the same material.

[0009] In some embodiments, the thickness of the gate adhesive layer in the second direction is the same as the thickness of the barrier layer in the second direction, and the second direction intersects the first direction.

[0010] In some implementations, the barrier layer is made of metallic elements.

[0011] In some embodiments, the material of the barrier layer includes at least one of titanium nitride and / or molybdenum oxide.

[0012] In some implementations, the thickness of the barrier layer in the second direction is greater than 1.7 nm, and the second direction intersects the first direction.

[0013] In some embodiments, the semiconductor device further includes an isolation structure located on one side of the semiconductor pillar in a second direction, and a gate structure located on the side of the semiconductor pillar away from the isolation structure in the second direction, the second direction intersecting the first direction.

[0014] In some embodiments, the isolation structure includes a conductive structure and an isolation dielectric layer, wherein the isolation dielectric layer covers the conductive structure, and the material of the conductive structure is the same as the material of the barrier layer.

[0015] In some embodiments, the semiconductor device further includes a capacitor and a bit line, the capacitor being located on one side of the semiconductor pillar in a first direction and connected to the semiconductor pillar, the bit line being located on the side of the semiconductor pillar away from the capacitor in the first direction and connected to the semiconductor pillar, the gate structure extending in a third direction, the bit line extending in a second direction, and the first direction, the second direction, and the third direction intersecting each other.

[0016] A second aspect of this application provides a method for fabricating a semiconductor device, the method comprising: forming an initial semiconductor pillar extending along a first direction; and forming a gate structure on a sidewall of the initial semiconductor pillar extending along the first direction; wherein the gate structure includes a gate layer and a barrier layer, the barrier layer being located on the side of the gate layer opposite to the initial semiconductor pillar.

[0017] In some embodiments, forming a gate structure on the sidewall of the initial semiconductor pillar extending along a first direction includes: forming a gate dielectric layer on the sidewall of the initial semiconductor pillar; forming a gate layer covering the gate dielectric layer; and forming a barrier layer covering the gate layer; wherein the gate structure further includes the gate dielectric layer.

[0018] In some embodiments, the fabrication method further includes forming a gate adhesive layer covering the gate dielectric layer before forming the gate layer; wherein the gate structure further includes the gate adhesive layer.

[0019] In some embodiments, forming an initial semiconductor pillar extending along a first direction includes: forming a plurality of first trenches spaced apart in a third direction and all extending in a second direction in a wafer; filling the first trenches with a dielectric material to form a first dielectric layer; and forming a plurality of second trenches and third trenches alternately distributed in the second direction and all extending in a third direction in a wafer to divide the wafer into a plurality of initial semiconductor pillars; wherein the first direction, the second direction and the third direction intersect each other.

[0020] In some embodiments, forming a gate structure on the sidewall of the initial semiconductor pillar extending along a first direction includes: forming an initial gate structure covering the inner wall of a second trench; forming a gate isolation layer within the gap formed by the initial gate structure; and dividing the initial gate structure into two gate structures disposed opposite each other along a second direction.

[0021] In some embodiments, dividing the initial gate structure into two gate structures includes: at least removing the portion of the initial gate structure that covers the bottom surface of the second trench; and forming gate cut-out structures at both ends of the initial gate structure along a third direction, the gate cut-out structures penetrating the initial gate structure along a first direction.

[0022] A third aspect of this application provides a storage system, which includes a controller and a semiconductor device according to the first aspect of this application. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0024] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of the application. In the drawings:

[0025] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to one embodiment of this application;

[0026] Figure 2 This is a top view schematic diagram of a semiconductor device according to another embodiment of this application;

[0027] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of this application;

[0028] Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor device according to another embodiment of this application;

[0029] Figures 5 to 21 This is a schematic diagram of the fabrication method of a semiconductor device according to another embodiment of this application; and

[0030] Figure 22 This is a block diagram of a system having semiconductor devices according to one embodiment of this application.

[0031] Figure label:

[0032] 100. Wafer; 101. First trench; 102. Second trench; 103. Third trench;

[0033] 104. Fourth groove; 105. Fifth groove; 106. First surface;

[0034] 107, Second surface; 110, Semiconductor pillar; 110', Initial semiconductor pillar;

[0035] 111. Source; 112. Drain; 113. Channel; 200. Initial gate structure;

[0036] 210. Gate structure; 211. Gate layer; 212. Barrier layer; 213. Gate dielectric layer;

[0037] 214. Gate adhesive layer; 220. Gate isolation layer; 230. Gate sacrificial layer;

[0038] 240. Gate notch structure; 300. Initial isolation structure; 310. Isolation structure;

[0039] 311. Conductive structure; 312. Isolation dielectric layer; 320. Conductive sacrificial structure;

[0040] 400, First dielectric layer; 500, Capacitor; 600, Bit line; 700, System;

[0041] 701. Memory system; 702. Semiconductor device; 703. Memory controller;

[0042] 704, host computer. Detailed Implementation

[0043] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0045] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0046] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0047] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0048] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0050] With the rapid development of semiconductor technology, the size of DRAM memory cells is getting smaller and smaller, and their array architecture has expanded from 8F... 2 Developed to 6F 2 And from 6F 2 Developed to 4F 2The architecture of memory has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried saddle fin array transistors, and finally from buried saddle fin array transistors to vertical gate transistors.

[0051] Figure 1 A cross-sectional schematic diagram of a semiconductor device according to one embodiment of this application is shown. Figure 1 As shown, this application provides a semiconductor device including a semiconductor pillar 110, a gate structure 210, and a gate isolation layer 220. The semiconductor pillar 110 extends along a first direction, the gate structure 210 is located on the sidewall of the semiconductor pillar 110 extending along the first direction, and at least a portion of the gate isolation layer 220 is located on the side of the gate structure 210 opposite to the semiconductor pillar 110. The gate structure 210 includes a gate dielectric layer 213, a gate adhesive layer 214, and a gate layer 211. The gate adhesive layer 214 is located on the side of the gate dielectric layer 213 opposite to the semiconductor pillar 110, and the gate layer 211 is located on the side of the gate adhesive layer 214 opposite to the gate dielectric layer 213. As an example, the semiconductor device may further include a contact structure (not shown) and a capacitor 500. The contact structure is located between the semiconductor pillar 110 and the capacitor 500 in the first direction, and the contact structure includes a metal contact layer.

[0052] The gate layer 211 is formed using atomic layer deposition (ALD) with tungsten hexafluoride (WF6) as a precursor and borane (B2H6) as a reducing agent. The tungsten layer formed by this process is the gate layer 211. However, because the gate layer 211 contains a large amount of fluorine- and boron-containing tungsten impurities, it releases fluorine and boron-containing gases after high-temperature treatment. These gases diffuse into the gate isolation layer 220 located on one side of the gate layer 211 and recrystallize to form tungsten hexafluoride, thus causing tungsten diffusion. Furthermore, the metal contact layer of the contact structure is typically made of tungsten. Electrochemical reactions occur during 3P treatments such as doping, heat treatment, and passivation of the metal contact layer. The diffusion of tungsten impurities in the gate layer 211 also causes the diffusion of dopants such as boron in the semiconductor pillar 110. The diffusion of boron leads to a potential difference between the semiconductor pillar 110 and the contact structure, resulting in the loss of tungsten in the metal contact layer.

[0053] Based on this, the present application provides another semiconductor device in its implementation. Figure 2 A top view schematic diagram of a semiconductor device according to another embodiment of this application is shown. Figure 3 A cross-sectional schematic diagram of a semiconductor device according to another embodiment of this application is shown. For example... Figure 2 and Figure 3 As shown, the semiconductor device includes a semiconductor pillar 110 and a gate structure 210. The semiconductor pillar 110 extends along a first direction, and the gate structure 210 is located on the sidewall of the semiconductor pillar 110 extending along the first direction. The gate structure 210 may include a gate layer 211 and a barrier layer 212, with the barrier layer 212 located on the side of the gate layer 211 opposite to the semiconductor pillar 110.

[0054] Because a barrier layer 212 is provided on the side of the gate layer 211 facing away from the semiconductor pillar 110 in this embodiment, the presence of the barrier layer 212 can not only effectively suppress the diffusion of metal impurities in the gate layer 211, but also increase the process window. It should be noted that the semiconductor device provided in this embodiment can be a memory or a part of a memory. For example, the memory may include peripheral circuitry and the aforementioned semiconductor device, with the peripheral circuitry coupled to the semiconductor device. In this case, the aforementioned semiconductor device is part of the memory. As another example, the memory may be a memory array, in which case the memory array is the aforementioned semiconductor device. As an example, in this embodiment, the first direction can be the z-direction shown in the figures.

[0055] As an example, the material of the barrier layer 212 in this embodiment includes metallic elements. For example, the material of the barrier layer 212 may include, but is not limited to, at least one of titanium nitride and / or molybdenum oxide. In some embodiments, the thickness of the barrier layer 212 in the second direction is greater than 1.7 nm, and the second direction intersects the first direction. The intersection of the first and second directions can generally be understood as having an angle between them. For example, the first and second directions are perpendicular or approximately perpendicular to each other. As an example, in this embodiment, the first direction may be the z-direction in the figures, and the second direction may be the x-direction in the figures.

[0056] In some embodiments, the gate structure 210 may further include a gate dielectric layer 213, which is located between the gate layer 211 and the semiconductor pillar 110. The material of the gate dielectric layer 213 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. The material of the gate layer 211 may include, but is not limited to, polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride, or any combination thereof. To improve the adhesion between the gate layer 211 and the gate dielectric layer 213, the gate structure 210 may further include a gate adhesive layer 214, which is located between the gate dielectric layer 213 and the gate layer 211. The material of the gate adhesive layer 214 may include, but is not limited to, at least one of titanium nitride, tantalum nitride, and tungsten carbide. It should be noted that in the embodiments of this application, the materials of the gate adhesive layer 214 and the barrier layer 212 may be the same or different. For example, both the material of the gate adhesive layer 214 and the barrier layer 212 may be titanium nitride. When the material of the gate adhesive layer 214 includes a material containing metal elements such as titanium nitride or tantalum nitride, the gate adhesive layer 214 can also effectively suppress the diffusion of metal impurities in the gate layer 211.

[0057] As an example, the thickness of the gate adhesive layer 214 in the second direction can be the same as or different from the thickness of the barrier layer 212 in the second direction. For example, the thickness of the gate adhesive layer 214 in the second direction is the same as the thickness of the barrier layer 212 in the second direction. The fact that the thickness of the gate adhesive layer 214 is the same as the thickness of the barrier layer 212 can generally be understood as the thickness of the gate adhesive layer 214 being completely equal to the thickness of the barrier layer 212 or having a slight deviation; for example, the difference between the thickness of the gate adhesive layer 214 and the thickness of the barrier layer 212 does not exceed 15% of either of their thicknesses.

[0058] In some embodiments, the semiconductor device may further include an isolation structure 310 located on one side of the semiconductor pillar 110 in a second direction, and a gate structure 210 located on the side of the semiconductor pillar 110 opposite to the isolation structure 310 in the second direction. As an example, the isolation structure 310 may include a conductive structure 311 and an isolation dielectric layer 312, with the isolation dielectric layer 312 covering the conductive structure 311. The material of the isolation dielectric layer 312 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride; the material of the conductive structure 311 may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver. In other embodiments, the isolation structure 310 may include an isolation layer having an air gap.

[0059] In some embodiments, the semiconductor device may further include a capacitor 500, which is located on one side of the semiconductor pillar 110 in a first direction and connected to the semiconductor pillar 110. The capacitor 500 may include an electrode core, a capacitor dielectric layer, and a first electrode layer (not shown). The electrode core is connected to the semiconductor pillar 110 and extends along the first direction. The capacitor dielectric layer is located on at least a portion of the sidewall of the electrode core extending along the first direction, and the first electrode layer is located on the side of the capacitor dielectric layer opposite to the electrode core. The electrode core may be a single-layer structure or a multi-layer structure; this application does not limit this. For example, the electrode core may be a columnar conductive structure, and the projection shape of the electrode core onto a plane perpendicular to the first direction may be rectangular, circular, elliptical, semi-circular, or any other arbitrary shape. Alternatively, the electrode core may include a support core and a second electrode layer. The support core extends along the first direction, and the second electrode layer is located on at least a portion of the surface of the support core and connected to the semiconductor pillar 110. For example, the second electrode layer may cover the sidewall of the support core extending along the first direction. For example, to reduce contact resistance, the second electrode layer can be located on the sidewall of the support core extending along the first direction, and also on the end face of the support core facing the semiconductor pillar 110, with the second electrode layer connected to the semiconductor pillar 110. The materials of the first and second electrode layers can include, but are not limited to, at least one of metals, metal compounds, and semiconductor materials. The material of the support core can include, but is not limited to, elemental semiconductor materials such as silicon (Si), composite semiconductor materials such as germanium silicon (GeSi), or polycrystalline silicon doped with dopants such as boron. The material of the capacitor dielectric layer can include, but is not limited to, at least one of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, and praseodymium oxide.

[0060] In some embodiments, the semiconductor device may further include a bit line 600, which is located on the side of the semiconductor pillar 110 away from the capacitor 500 and connected to the semiconductor pillar 110 in a first direction. The bit line 600 extends along a second direction, and the gate structure 210 extends along a third direction. The first direction, the second direction, and the third direction intersect each other pairwise. This pairwise intersection can generally be understood as an angle between the first direction and the second direction, an angle between the second direction and the third direction, and an angle between the first direction and the third direction. As an example, in the embodiments of this application, the first direction can be the z-direction in the figures, the second direction can be the x-direction in the figures, and the third direction can be the y-direction in the figures.

[0061] As an example, the semiconductor pillar 110 may include a source 111, a drain 112, and a channel 113 located between the source 111 and the drain 112 in a first direction. The semiconductor pillar 110 and the gate structure 210 constitute a transistor. The source 111 is connected to the capacitor 500, and the drain 112 is connected to the bit line 600. The gate structure 210 may be a word line. The word line is used to apply a voltage to control the transistor to turn on or off. The bit line 600 is used to perform read or write operations on the capacitor 500 when the transistor is on. The amount of charge stored in the capacitor 500 represents a binary bit.

[0062] Figure 4 A schematic flowchart of a method for fabricating a semiconductor device according to another embodiment of this application is shown. Figures 5 to 21 A schematic diagram of a process for fabricating a semiconductor device according to another embodiment of this application is shown. Figures 4 to 21 As shown, the preparation method includes:

[0063] S100, forming an initial semiconductor pillar 110' extending along the first direction;

[0064] S200, a gate structure 210 is formed on the sidewall of the initial semiconductor pillar 110' extending along a first direction; wherein the gate structure 210 includes a gate layer 211 and a barrier layer 212, the barrier layer 212 being located on the side of the gate layer 211 away from the initial semiconductor pillar 110'.

[0065] The following is a detailed description of each step in the semiconductor device fabrication method in the embodiments of this application.

[0066] Step S100

[0067] In step S100, an initial semiconductor pillar 110' is formed, and the initial semiconductor pillar 110' extends along a first direction. The projection shape of the initial semiconductor pillar 110' onto a plane perpendicular to the first direction can be, but is not limited to, a rectangle, a circle, an ellipse, a semicircle, or any other arbitrary shape, and this application does not limit it in this regard.

[0068] Figure 5 This is a top view schematic diagram showing the formation of a first trench 101, a second trench 102 and a third trench 103 in a wafer 100 according to one embodiment of the present application; Figure 6 It shows Figure 5 Schematic diagram of cross-section at AA.

[0069] As an example, such as Figure 5 and Figure 6As shown, the initial semiconductor pillars 110' can be formed by etching the wafer 100. The material of the wafer 100 can be any suitable semiconductor material, such as a single semiconductor material like silicon (Si) or germanium (Ge), or a composite semiconductor material like silicon-on-insulator (SOI) or germanium-on-insulator (GeOI). For example, the initial semiconductor pillars 110' can be formed by forming a plurality of first trenches 101 spaced apart in a third direction and extending in a second direction in the wafer 100; and forming a plurality of second trenches 102 and third trenches 103 alternately distributed in the second direction and extending in a third direction in the wafer 100 to divide the wafer 100 into a plurality of initial semiconductor pillars 110'. The first trenches 101, second trenches 102, and third trenches 103 can be formed in the wafer 100 by, but not limited to, wet etching, dry etching such as plasma etching or reactive ion etching, or any combination of the above processes.

[0070] Subsequently, a gate structure 210 can be formed on at least a portion of the sidewalls extending along the first direction of the initial semiconductor pillar 110', and a semiconductor pillar 110 is formed based on the initial semiconductor pillar 110'. The gate structure 210 and the semiconductor pillar 110 together constitute a transistor. The gate structure 210 can cover part or all of the sidewalls of the semiconductor pillar 110. Thus, the transistor can be classified as a single-gate transistor, a dual-gate transistor, a tri-gate transistor, or a gate-all-around (GAA) transistor. Specifically, in a single-gate transistor, the gate structure 210 may be located only on one side of the semiconductor pillar 110 in the direction intersecting the first direction; in a dual-gate transistor, the gate structure 210 is located on opposite sides of the semiconductor pillar 110 in the direction intersecting the first direction; in a tri-gate transistor, the gate structure 210 partially surrounds the semiconductor pillar 110 in the direction intersecting the first direction; and in a gate-all-around transistor, the gate structure 210 surrounds the semiconductor pillar 110 in the direction intersecting the first direction. For example, the semiconductor pillar 110 includes a first sidewall and a second sidewall disposed opposite to each other in a second direction, and a third sidewall and a fourth sidewall disposed opposite to each other in a third direction. If the gate structure 210 is located on any one of the first sidewall, second sidewall, third sidewall, and fourth sidewall of the semiconductor pillar 110, then the transistor formed by it and the semiconductor pillar 110 is a single-gate transistor; if the gate structure 210 is located on the first sidewall and the second sidewall (third sidewall and fourth sidewall) of the semiconductor pillar 110, then the transistor formed by it and the semiconductor pillar 110 is a dual-gate transistor; if the gate structure 210 is located on any three of the first sidewall, second sidewall, third sidewall, and fourth sidewall of the semiconductor pillar 110, then the transistor formed by it and the semiconductor pillar 110 is a tri-gate transistor; if the gate structure 210 is located on the first sidewall, second sidewall, third sidewall, and fourth sidewall of the semiconductor pillar 110, then the transistor formed by it and the semiconductor pillar 110 is a full-ring gate transistor.

[0071] The following example uses a single-gate transistor, such as... Figure 5 and Figure 6As shown, a plurality of first trenches 101 are formed on the first surface 106 of wafer 100, spaced apart in a third direction and extending in a second direction. Wafer 100 includes a first surface 106 and a second surface 107 disposed opposite to each other in a first direction. A first dielectric layer 400 is formed by filling the first trenches 101 with dielectric material. The material of the first dielectric layer 400 may include, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxide. A plurality of second trenches 102 and third trenches 103 are formed on the first surface 106 of wafer 100, alternatingly distributed in a second direction and extending in a third direction, to divide wafer 100 into a plurality of initial semiconductor pillars 110'. The dimensions of the first trenches 101, second trenches 102, and third trenches 103 in the first direction are smaller than the dimensions of wafer 100 in the first direction. Therefore, a gate structure 210 can be subsequently formed in the second trenches 102, and an isolation structure 310 can be formed in the third trenches 103.

[0072] Step S200

[0073] In step S200, a gate structure 210 is formed on the sidewall of the initial semiconductor pillar 110' extending along a first direction. The gate structure 210 includes a gate layer 211 and a barrier layer 212, with the barrier layer 212 located on the side of the gate layer 211 opposite to the initial semiconductor pillar 110'.

[0074] Figure 10 This illustration shows a top view of an embodiment of the present application in which a gate dielectric layer 213, a gate adhesive layer 214, and a gate layer 211 are formed in a second trench 102. Figure 11 It shows Figure 10 Cross-sectional view at BB; Figure 12 It shows Figure 10 Cross-sectional view at CC; Figure 13 This is a top view schematic diagram showing a barrier layer 212 formed in a second trench 102 according to one embodiment of the present application; Figure 14 It shows Figure 12 Cross-sectional view at DD; Figure 15 It shows Figure 12 Schematic diagram of cross section at EE.

[0075] In some embodiments, the gate structure 210 may include a gate dielectric layer 213 in addition to the gate layer 211 and the barrier layer 212. As an example, the gate structure 210 may be formed in the following manner: Figures 10 to 12As shown, a gate dielectric layer 213 is formed on the sidewall of the initial semiconductor pillar 110'. For example, the gate dielectric layer 213 can be formed by in-situ oxidation of the sidewall of the initial semiconductor pillar 110', or by thin film deposition. The material of the gate dielectric layer 213 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. A gate layer 211 is formed on the side of the gate dielectric layer 213 facing away from the initial semiconductor pillar 110'. The material of the gate layer 211 may include, but is not limited to, polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride, or any combination thereof. Figures 13 to 15 As shown, a barrier layer 212 is formed on the side of the gate layer 211 facing away from the gate dielectric layer 213; wherein, the material of the barrier layer 212 may include, but is not limited to, at least one of titanium nitride and / or molybdenum oxide. Thus, the presence of the barrier layer 212 can not only effectively suppress the diffusion of metal impurities in the gate layer 211, but also increase the process window.

[0076] In other embodiments, to improve the adhesion between the gate layer 211 and the gate conductive layer, a gate adhesive layer 214 covering the gate dielectric layer 213 can be formed on the side of the gate dielectric layer 213 facing away from the initial semiconductor pillar 110' before forming the gate layer 211; wherein, the material of the gate adhesive layer 214 may include, but is not limited to, at least one of titanium nitride, tantalum nitride, and tungsten carbide. It should be noted that the materials of the gate adhesive layer 214 and the barrier layer 212 in the embodiments of this application may be the same or different. For example, the material of both the gate adhesive layer 214 and the barrier layer 212 may be titanium nitride. When the material of the gate adhesive layer 214 is a material containing metal elements, such as titanium nitride or tantalum nitride, the gate adhesive layer 214 can also effectively suppress the diffusion of metal impurities in the gate layer 211.

[0077] The gate dielectric layer 213, gate adhesive layer 214, gate layer 211 and barrier layer 212 mentioned above can all be formed by thin film deposition process. The thin film deposition process can be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) process or any combination of the above processes.

[0078] Figure 16 This illustration shows a cross-sectional schematic diagram of a gate isolation layer 220 formed in a second trench 102 according to one embodiment of the present application; Figure 17This illustration shows a cross-sectional view of a portion of the initial gate structure 200 and gate isolation layer 220 removed using a CMP process in one embodiment of this application. Figure 18 This illustration shows a cross-sectional schematic diagram of a gate trench filled with an isolation material in one embodiment of this application.

[0079] Furthermore, as mentioned above, transistors can be categorized into single-gate transistors, dual-gate transistors, tri-gate transistors, or gate-all-around (GAA) transistors. The following example, using a single-gate transistor, illustrates the formation of the gate structure 210 from another perspective: Figures 10 to 15 As shown, an initial gate structure 200 is formed covering the inner wall of the second trench 102; wherein, the initial gate structure 200 may include a gate dielectric layer 213, a gate layer 211, and a barrier layer 212. For example, a gate dielectric layer 213 is formed on the inner wall of the second trench 102; a gate layer 211 is formed on the side of the gate dielectric layer 213 facing away from the inner wall of the second trench 102; and a barrier layer 212 is formed on the side of the gate layer 211 facing away from the gate dielectric layer 213. In some embodiments, before forming the barrier layer 212, high-temperature degassing may be used to remove fluorine-containing and boron-containing gases from the gate layer 211. Figure 16 As shown, a gate isolation layer 220 is formed within the gap formed by the initial gate structure 200. The material of the gate isolation layer 220 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. Furthermore, since the initial gate structure 200 and the gate isolation layer 220 are formed using a thin-film deposition process, the initial gate structure 200 and the gate isolation layer 220 will cover the first surface 106 of the wafer 100. Therefore, as... Figure 17 As shown, after the gate isolation layer 220 is formed, a chemical mechanical polishing (CMP) process can be used to remove the portion of the initial gate structure 200 and the gate isolation layer 220 covering the first surface 106 of the wafer 100. For example... Figure 18 As shown, at least a portion of the initial gate structure 200 is removed from the first surface 106 of the wafer 100 to form a gate trench (not shown); an isolation material is filled in the gate trench; the initial gate structure 200 is divided into two gate structures 210, which are arranged opposite to each other along a second direction.

[0080] Since a barrier layer 212 is provided on the side of the gate layer 211 away from the semiconductor pillar 110 in this embodiment, the presence of the barrier layer 212 can not only effectively suppress the diffusion of metal impurities in the gate layer 211, thereby avoiding electrical leakage between the two gate layers 211 disposed opposite to each other in the second direction, but also increase the process window.

[0081] Figure 19 A cross-sectional schematic diagram of wafer 100 being thinned in one embodiment of this application is shown; Figure 20 A cross-sectional schematic diagram is shown in one embodiment of this application, in which the initial gate structure 200 is divided into two gate structures 210; Figure 21 This illustration shows a top view of an embodiment of the present application in which an initial gate structure 200 is divided into two gate structures 210.

[0082] As an example, the initial gate structure 200 can be divided into two gate structures 210 by removing at least the portion of the initial gate structure 200 covering the bottom surface of the second trench 102, for example, as Figure 18 and Figure 19 As shown, wafer 100 is thinned from its second surface 107 to expose a first dielectric layer 400; a portion of the first dielectric layer 400 is removed to form a first sub-trench (not shown) exposing an initial gate structure 200, the first sub-trench extending along a second direction; a portion of the initial gate structure 200 is removed through the first sub-trench to form a second sub-trench extending along a third direction; dielectric material is filled in the first and second sub-trenches; thereby, the remaining initial gate structure 200 covers the sidewalls of the second trench 102 extending in the first direction and is annular. Figure 21 As shown, gate cutout structures 240 are formed at both ends of the initial gate structure 200 along a third direction. The gate cutout structures 240 penetrate the initial gate structure 200 along a first direction to divide the remaining initial gate structure 200 into two gate structures 210 disposed opposite each other in a second direction. It should be noted that in some other embodiments, the gate cutout structures 240 may be formed at both ends of the initial gate structure 200 first, and then the portion of the initial gate structure 200 covering the bottom surface of the second trench 102 may be removed.

[0083] In other embodiments, the preparation method may further include: filling the second trench 102 and the third trench 103 with sacrificial material; removing the sacrificial material from the third trench 103; such as Figure 9 As shown, an initial isolation structure 300 is formed within the third trench 103; as Figure 14 As shown, the sacrificial material, i.e., the gate sacrificial layer 230, is removed from the second trench 102 to facilitate the subsequent formation of the initial gate structure 200 within the second trench 102; as Figure 20 As shown, a portion of the initial isolation structure 300 is removed to form an isolation structure 310. In some other embodiments, the sacrificial material filled in the second trench 102 may be removed first to form an initial gate structure 200 in the second trench 102; then the sacrificial material filled in the third trench 103 may be removed to form an initial isolation structure 300 in the third trench 103.

[0084] As an example, the initial isolation structure 300 includes an isolation layer, which can be formed within the third trench 103 by depositing isolation material within the third trench 103 to form an isolation layer with air gaps. Two different deposition rates can be used to deposit the isolation material within the third trench 103 when forming the isolation layer. For example, a portion of the isolation layer can be formed on the inner wall of the third trench 103 using a first deposition rate, while another portion is formed at the opening of the third trench 103 using a second deposition rate greater than the first. Because the second deposition rate is greater than the first deposition rate, when both portions are deposited simultaneously, the isolation material at the opening of the third trench 103 quickly seals the opening. Since the first deposition rate is slower, after sealing, some space within the third trench 103 remains unfilled with isolation material, thus forming air gaps. Because air gaps have a low dielectric constant, close to that of a vacuum, the presence of air gaps can reduce the overall dielectric constant of the isolation layer, thereby reducing parasitic capacitance and reducing electrical interference between adjacent semiconductor pillars 110. During the formation of air gaps, the size and position of the air gaps can be adjusted by controlling the first and second deposition rates. A larger ratio between the second and first deposition rates results in a larger air gap within the isolation layer, thus improving its effect on reducing parasitic capacitance. For example, the ratio α between the second and first deposition rates can range from 1 to 3. As an example, the ratio α can range from 1.5 to 2. Furthermore, those skilled in the art should understand that the structure, composition, and formation process of the isolation layer with air gaps can be modified without departing from the technical claims of this application to obtain the various results and advantages described in this specification.

[0085] It should be noted that, in addition to improving the isolation effect through air gaps, the isolation structure 310 can also improve the isolation effect by setting a conductive structure 311. Subsequently, grounding or connecting the conductive structure 311 to a negative voltage can change the coupling effect between two adjacent transistors. As an example, to further improve the isolation effect of the isolation structure 310 and reduce electrical interference between two adjacent semiconductor pillars 110, the initial isolation structure 300 may include an isolation dielectric layer 312, a conductive structure 311, and a conductive sacrificial structure 320. In this case, the isolation structure 310 can be formed as follows: Figures 7 to 9 As shown, an initial isolation structure 300 is formed within the third trench 103. Specifically, an isolation material is deposited on the inner wall of the third trench 103. The isolation material may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. The remaining space of the third trench 103 is filled with conductive material to form a conductive sacrificial structure 320. The material of the conductive sacrificial structure 320 may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver. Figure 7 As shown, at least a portion of the conductive sacrificial structure 320 is removed to form a fourth trench 104; an insulating material is deposited on the inner wall of the fourth trench 104 to cover the conductive sacrificial structure 320; as Figure 8 As shown, the remaining space of the fourth trench 104 is filled with conductive material to form a conductive structure 311. The material of the conductive structure 311 may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver; at least a portion of the conductive structure 311 is removed to form a fifth trench (not shown); and an insulating material is filled into the fifth trench. Thus, as Figure 9 As shown, all the remaining insulating material within the third trench 103 constitutes the insulating dielectric layer 312, which surrounds the conductive structure 311 and the conductive sacrificial structure 320. Figure 20 As shown, the conductive sacrificial structure 320 is removed to form the isolation structure 310. During this process, a portion of the initial gate structure 200 can be removed simultaneously through the first sub-trench, and the portion of the isolation dielectric layer 312 located between the conductive sacrificial structure 320 and the conductive structure 311 can serve as an etch stop layer.

[0086] In some embodiments, the fabrication method may further include forming a semiconductor pillar 110 based on an initial semiconductor pillar 110'. For example, a source 111 and a drain 112 can be formed by doping both ends of the initial semiconductor pillar 110', respectively. The source 111 and drain 112 can be both doped with P-type dopant or both doped with N-type dopant. The dopant for the source 111 and drain 112 can be the same or different. For example, the dopant can include, but is not limited to, boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), or antimony (Sb). Thus, the gate structure 210 and the semiconductor pillar 110 together constitute a transistor.

[0087] In some embodiments, the fabrication method may further include: forming a stacked structure (not shown) on one side of the semiconductor pillar 110 along a first direction, the stacked structure including a second dielectric layer and a filling sacrificial layer alternately stacked in the first direction; wherein, the material of the second dielectric layer may include, but is not limited to, at least one of silicon nitride, silicon oxynitride, and aluminum oxide, and the material of the second dielectric layer may also be doped with dopants such as boron or carbon. For example, the material of the second dielectric layer may include silicon carbide (SiCN) or silicon boron nitride (SiBN); the material of the filling sacrificial layer may include, but is not limited to, silicon oxide and / or silicon oxynitride. For example, the material of the filling sacrificial layer may include silicon oxide or silicon oxide treated with an organic solution, the organic solution may include, but is not limited to, TEOS (Tetraethoxysilane), BPSG (Boron-Phosphosilicate Glass), or PGS (Phosphosilicate Glass). A capacitor aperture is formed through the stacked structure along a first direction; an electrode core is formed within the capacitor aperture; a filling sacrificial layer is removed to expose at least a portion of the sidewalls of the electrode core; a capacitor dielectric layer is formed on the exposed sidewalls of the electrode core; wherein the material of the capacitor dielectric layer may include, but is not limited to, at least one of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, and praseodymium oxide; a first electrode layer is formed on the side of the capacitor dielectric layer opposite to the electrode core; wherein the material of the first electrode layer may include, but is not limited to, titanium nitride, titanium silicide, or nickel silicide.

[0088] The electrode core can be a single-layer structure or a multi-layer structure. For example, the electrode core can be a conductive pillar formed by depositing conductive material inside the capacitor hole. Alternatively, the electrode core can include a second electrode layer and a support core. The second electrode layer can be formed first on the inner wall of the capacitor hole, and then the support core can be formed within the gap formed by the second electrode layer. The material of the second electrode layer can include, but is not limited to, at least one of metals, metal compounds, and semiconductor materials. The material of the support core can include, but is not limited to, elemental semiconductor materials such as silicon (Si), composite semiconductor materials such as germanium-silicon (GeSi), or polycrystalline silicon doped with dopants such as boron.

[0089] It should be noted that the capacitor 500 in the embodiments of this application is not limited to the above-described structure, and any other suitable capacitor 500 can be applied to this application.

[0090] In some embodiments, the fabrication method may further include: forming a bit line conductive layer on one side of the semiconductor pillar 110 along a first direction; forming a plurality of bit line trenches spaced apart along a third direction and penetrating the bit line conductive layer along the first direction to divide the bit line conductive layer into a plurality of bit lines 600. The bit lines 600 extend along a second direction and are connected to the plurality of semiconductor pillars 110 spaced apart in the second direction; filling the bit line trenches with an insulating material to form a bit line isolation layer. To reduce the overall dielectric constant of the bit line isolation layer and thus reduce parasitic capacitance, the bit line isolation layer may have air gaps.

[0091] In addition, this application also provides a storage system, which includes a controller and the aforementioned semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0092] Figure 22 A block diagram of a system with semiconductor devices according to one embodiment of this application is shown. System 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage located therein. Figure 22 As shown, system 700 may include host 704 and memory system 701, the memory system 701 having one or more semiconductor devices 702 and memory controller 703. Host 704 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-a-chip (SoC), such as an application processor (AP). Host 704 may be configured to send or receive data from semiconductor device 702.

[0093] Semiconductor device 702 can be any semiconductor device disclosed in this application, such as Figure 2 and Figure 3 The semiconductor device is shown. According to some embodiments, a memory controller 703 is coupled to the semiconductor device 702 and the host 704, and is configured to control the semiconductor device 702. The memory controller 703 can manage data stored in the semiconductor device 702 and communicate with the host 704.

[0094] In some embodiments, the memory controller 703 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 703 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 703 can be configured to control the operation of the semiconductor device 702, such as read, erase, and program operations. The memory controller 703 can also be configured to manage various functions related to data stored in or to be stored in the semiconductor device 702, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 703 is further configured to process error correction codes (ECC) related to data read from or written to the semiconductor device 702. The memory controller 703 may also perform any other suitable functions, such as formatting the semiconductor device 702. The memory controller 703 may communicate with an external device (e.g., the host 704) according to a specific communication protocol. For example, the memory controller 703 may communicate with an external device via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0095] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0096] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, comprising: Semiconductor pillars, extending along a first direction; as well as A gate structure is located on the sidewall of the semiconductor pillar extending along the first direction; The gate structure includes a gate layer and a barrier layer, wherein the barrier layer is located on the side of the gate layer opposite to the semiconductor pillar.

2. The semiconductor device according to claim 1, wherein, The gate structure further includes: A gate dielectric layer is located between the gate layer and the semiconductor pillar.

3. The semiconductor device according to claim 2, wherein, The gate structure further includes: A gate adhesive layer is located between the gate dielectric layer and the gate layer.

4. The semiconductor device according to claim 3, wherein, The gate adhesive layer is made of the same material as the barrier layer.

5. The semiconductor device according to claim 3, wherein, The thickness of the gate adhesive layer in the second direction is the same as the thickness of the barrier layer in the second direction, and the second direction intersects the first direction.

6. The semiconductor device according to claim 1, wherein, The barrier layer is made of metallic elements.

7. The semiconductor device according to claim 1, wherein, The material of the barrier layer includes at least one of titanium nitride and / or molybdenum oxide.

8. The semiconductor device according to claim 1, wherein, The thickness of the barrier layer in the second direction is greater than 1.7 nm, and the second direction intersects the first direction.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The semiconductor device further includes: An isolation structure is located on one side of the semiconductor pillar in the second direction; The gate structure is located on the side of the semiconductor pillar away from the isolation structure in the second direction, and the second direction intersects with the first direction.

10. The semiconductor device according to claim 9, wherein, The isolation structure includes: Conductive structure; and An insulating dielectric layer covers the conductive structure; The conductive structure is made of the same material as the barrier layer.

11. The semiconductor device according to any one of claims 1 to 8, wherein, The semiconductor device further includes: A capacitor, located on one side of the semiconductor pillar and connected to the semiconductor pillar in the first direction; and Bit lines are located on the side of the semiconductor pillar away from the capacitor in the first direction and are connected to the semiconductor pillar; The gate structure extends along a third direction, the bit line extends along a second direction, and the first direction, the second direction, and the third direction intersect each other.

12. A method for fabricating a semiconductor device, comprising: An initial semiconductor pillar is formed extending along the first direction; as well as A gate structure is formed on the sidewall of the initial semiconductor pillar extending along the first direction; The gate structure includes a gate layer and a barrier layer, wherein the barrier layer is located on the side of the gate layer opposite to the initial semiconductor pillar.

13. The method for fabricating a semiconductor device according to claim 12, wherein, Forming a gate structure on the sidewall of the initial semiconductor pillar extending along the first direction includes: A gate dielectric layer is formed on the sidewall of the initial semiconductor pillar; The gate layer forming the gate dielectric layer; and The barrier layer is formed to cover the gate layer; The gate structure further includes the gate dielectric layer.

14. The method for fabricating a semiconductor device according to claim 13, wherein, Before forming the gate layer, the fabrication method further includes: Form a gate adhesive layer covering the gate dielectric layer; The gate structure further includes the gate adhesive layer.

15. The method for fabricating a semiconductor device according to any one of claims 12 to 14, wherein, Forming the initial semiconductor pillar extending along the first direction includes: Multiple first trenches are formed in the wafer, spaced apart in a third direction and all extending in a second direction; The first trench is filled with a dielectric material to form a first dielectric layer; and A plurality of second trenches and third trenches, which are alternately distributed in the second direction and all extend upward in the third direction, are formed in the wafer to divide the wafer into a plurality of the initial semiconductor pillars; The first direction, the second direction, and the third direction intersect each other.

16. The method for fabricating a semiconductor device according to claim 15, wherein, Forming a gate structure on the sidewall of the initial semiconductor pillar extending along the first direction includes: An initial gate structure is formed covering the inner wall of the second trench; A gate isolation layer is formed within the gap enclosed by the initial gate structure; and The initial gate structure is divided into two gate structures, which are arranged opposite to each other along the second direction.

17. The method for fabricating a semiconductor device according to claim 16, wherein, Dividing the initial gate structure into two gate structures includes: At least the portion of the initial gate structure covering the bottom surface of the second trench must be removed; and Gate cutout structures are formed at both ends of the initial gate structure along the third direction, and the gate cutout structures penetrate the initial gate structure along the first direction.

18. A storage system, characterized in that, The storage system includes a controller and a semiconductor device according to any one of claims 1 to 11, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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