Semiconductor device and preparation method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method and a memory system. The semiconductor device comprises a semiconductor main body, a gate structure and a medium filling part. The semiconductor body extends in a first direction, the gate structure is located on the side wall of the semiconductor body extending in the first direction, the dielectric filling part is at least located on the side, away from the semiconductor body, of the gate structure, the gate structure comprises a gate dielectric layer located on the side wall, and the dielectric constant of the dielectric filling part is smaller than that of the gate dielectric layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor design and fabrication, and more specifically, to semiconductor devices, methods for fabricating semiconductor devices, and memory systems. Background Technology

[0002] Memory is one of the most important semiconductor devices in electronic systems. Taking Dynamic Random Access Memory (DRAM) as an example, a semiconductor device can include memory cells composed of capacitors and transistors, where multiple memory cells can be arranged in a two-dimensional array. To further reduce the size of the two-dimensional array, the transistors can include a Vertical Gate Transistor (VGT). In this structure, the source and drain of the transistor can be formed at opposite ends of the transistor channel, and the gate structure of the transistor can be formed on at least one side of the channel.

[0003] However, with the rapid development of semiconductor technology, the shrinking size of semiconductor devices and the increase in integration, optimizing the overall performance of semiconductor devices and improving their yield has become one of the important research directions in the industry. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above-mentioned problems or other problems in the art.

[0005] This disclosure provides a semiconductor device comprising: a semiconductor body extending in a first direction; a gate structure located on a sidewall of the semiconductor body extending in the first direction; and a dielectric filling portion located at least on a side of the gate structure opposite to the semiconductor body, wherein the gate structure includes a gate dielectric layer located on the sidewall; and the dielectric constant of the dielectric filling portion is less than the dielectric constant of the gate dielectric layer.

[0006] In some embodiments of this disclosure, the dielectric constant of the dielectric filling portion is less than or equal to 3.

[0007] In some embodiments of this disclosure, the dielectric filling portion includes at least one of fluorine-doped silicon oxide, carbon-doped silicon oxide, amorphous fluorinated carbon, and silsesquioxane.

[0008] In some embodiments of this disclosure, the dielectric filling portion includes a plurality of filling portions with different dielectric constants, wherein the dielectric constant of the plurality of filling portions is less than or equal to 3.

[0009] In some embodiments of this disclosure, the plurality of filling portions include: a first filling portion; and a second filling portion located on one side of the first filling portion in a first direction, wherein the first filling portion is located between adjacent gate structures in a second direction, the second direction intersecting the first direction; and in the direction intersecting the first direction, the size of the first filling portion is smaller than the size of the second filling portion.

[0010] In some embodiments of this disclosure, the plurality of filling portions further include a third filling portion, wherein the first filling portion is located between the second filling portion and the third filling portion in a first direction; and in a direction intersecting the first direction, the size of the first filling portion is smaller than the size of the third filling portion.

[0011] In some embodiments of this disclosure, the first filling portion includes: a first sub-part; and a second sub-part surrounding the first sub-part.

[0012] In some embodiments of this disclosure, the semiconductor device further includes a bit line structure extending in a second direction and connected to a plurality of semiconductor bodies, wherein a second sub-part includes an end portion and a side portion connected to the end portion, the end portion being close to the bit line structure; and a first sub-part is located on one side of the end portion in the first direction and is surrounded by the side portion.

[0013] In some embodiments of this disclosure, the semiconductor device further includes a back gate structure, wherein the back gate structure extends in a third direction intersecting the first direction and is connected to the sidewalls of a plurality of semiconductor bodies.

[0014] In some embodiments of this disclosure, the back gate structure includes: a first dielectric layer; and a second dielectric layer located between the first dielectric layer and the sidewall of the semiconductor body, wherein the dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the second dielectric layer.

[0015] In some embodiments of this disclosure, the dielectric constant of the first dielectric layer is less than or equal to 3.

[0016] In some embodiments of this disclosure, the back gate structure further includes an air gap located on one side of the first dielectric layer in the first direction.

[0017] In some embodiments of this disclosure, the semiconductor device further includes a bit line structure extending in a second direction intersecting the first direction and connected to a plurality of semiconductor bodies, wherein an air gap is close to the bit line structure relative to the first dielectric layer.

[0018] In some embodiments of this disclosure, in a first direction, the size of the air gap is larger than the size of the first dielectric layer.

[0019] In some embodiments of this disclosure, the back gate structure further includes: a third dielectric layer located on one side of the first dielectric layer in the first direction; and a fourth dielectric layer located on the other side of the first dielectric layer in the first direction, wherein the dielectric constant of the third dielectric layer is different from the dielectric constant of the first dielectric layer, and the dielectric constant of the fourth dielectric layer is different from the dielectric constant of the first dielectric layer.

[0020] In some embodiments of this disclosure, the semiconductor device further includes a bit line structure extending in a second direction intersecting both the first and third directions and connected to a plurality of semiconductor bodies. The back gate structure further includes an air gap located between the first dielectric layer and the third dielectric layer in the first direction; and the dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the third dielectric layer.

[0021] In some embodiments of this disclosure, the size of the first dielectric layer is smaller than the size of the third dielectric layer in the direction intersecting the first direction.

[0022] In some embodiments of this disclosure, the dielectric constant of the third dielectric layer is different from that of the fourth dielectric layer.

[0023] In some embodiments of this disclosure, the size of the first dielectric layer is smaller than the size of the fourth dielectric layer in the direction intersecting the first direction.

[0024] In some embodiments of this disclosure, the dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the fourth dielectric layer.

[0025] In some embodiments of this disclosure, the dielectric constant of the first dielectric layer is equal to the dielectric constant of the dielectric filling portion.

[0026] This disclosure also provides a semiconductor device comprising: a semiconductor body extending in a first direction and including sidewalls extending in the first direction; and a back gate structure extending in a direction intersecting the first direction and connected to the sidewalls of a plurality of semiconductor bodies, the back gate structure including: a first dielectric layer; and a second dielectric layer located between the first dielectric layer and the sidewalls, wherein the dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the second dielectric layer.

[0027] In some embodiments of this disclosure, the semiconductor device according to claim 22, wherein the dielectric constant of the first dielectric layer is less than or equal to 3.

[0028] In some embodiments of this disclosure, the back gate structure further includes an air gap located on one side of the first dielectric layer in the first direction.

[0029] In some embodiments of this disclosure, the semiconductor device further includes a bit line structure extending in a second direction intersecting the first direction and connected to a plurality of semiconductor bodies, wherein an air gap is close to the bit line structure relative to the first dielectric layer.

[0030] In some embodiments of this disclosure, in a first direction, the size of the air gap is larger than the size of the first dielectric layer.

[0031] In some embodiments of this disclosure, the back gate structure further includes: a third dielectric layer located on one side of the first dielectric layer in the first direction; and a fourth dielectric layer located on the other side of the first dielectric layer in the first direction, wherein the dielectric constant of the third dielectric layer is different from the dielectric constant of the first dielectric layer, and the dielectric constant of the fourth dielectric layer is different from the dielectric constant of the first dielectric layer.

[0032] In some embodiments of this disclosure, the semiconductor device further includes a bit line structure extending in a second direction intersecting the first direction and connected to a plurality of semiconductor bodies, wherein the back gate structure further includes an air gap located in the first direction between a first dielectric layer and a third dielectric layer; and the dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the third dielectric layer.

[0033] In some embodiments of this disclosure, the size of the first dielectric layer is smaller than the size of the third dielectric layer in the direction intersecting the first direction.

[0034] In some embodiments of this disclosure, the dielectric constant of the third dielectric layer is different from that of the fourth dielectric layer.

[0035] In some embodiments of this disclosure, the size of the first dielectric layer is smaller than the size of the fourth dielectric layer in the direction intersecting the first direction.

[0036] In some embodiments of this disclosure, the dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the fourth dielectric layer.

[0037] This disclosure also provides a method for fabricating a semiconductor device, the method comprising: forming a semiconductor body extending in a first direction; forming a gate structure on a sidewall of the semiconductor body extending in the first direction; forming a dielectric filling portion on at least one side of the gate structure opposite to the semiconductor body, wherein the gate structure includes a gate dielectric layer located on the sidewall; and the dielectric constant of the dielectric filling portion is less than the dielectric constant of the gate dielectric layer.

[0038] In some embodiments of this disclosure, the fabrication method further includes forming a back gate structure that extends in a direction intersecting the first direction and is connected to the sidewalls of a plurality of semiconductor bodies.

[0039] In some embodiments of this disclosure, a plurality of semiconductor bodies are located on one side of a substrate in a first direction. A back gate structure extending in a direction intersecting the first direction and connected to the sidewalls of the plurality of semiconductor bodies includes: forming an initial second dielectric layer in the sidewalls and the substrate between adjacent semiconductor bodies; forming a back gate sacrificial layer on the surface of the initial second dielectric layer; and forming a first dielectric layer on one side of the back gate sacrificial layer in the first direction, wherein the back gate sacrificial layer has a predetermined dimension in the first direction.

[0040] In some embodiments of this disclosure, the back gate structure formed extending in a direction intersecting the first direction and connected to the sidewalls of a plurality of semiconductor bodies further includes: removing a portion of the substrate and a portion of the initial second dielectric layer to expose the end of the back gate sacrificial layer away from the first dielectric layer; removing the back gate sacrificial layer to form an air gap; and using a third dielectric layer to seal the air gap.

[0041] In some embodiments of this disclosure, the fabrication method further includes: forming a gate-side sacrificial layer at least on the remaining sidewalls of the semiconductor body during the formation of the initial second dielectric layer; and removing the gate-side sacrificial layer after the formation of the first dielectric layer.

[0042] Another aspect of this disclosure provides a memory system including a semiconductor device provided in this disclosure and a controller coupled to the semiconductor device, the controller being used to store data in the semiconductor device. Attached Figure Description

[0043] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0044] Figures 1-2 These are cross-sectional schematic diagrams of semiconductor devices according to exemplary embodiments of the present disclosure;

[0045] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0046] Figure 4 This is a top view schematic diagram of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0047] Figures 5-16 These are cross-sectional schematic diagrams of semiconductor devices according to exemplary embodiments of the present disclosure;

[0048] Figure 17 This is a flowchart of a method for fabricating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0049] Figures 18-34These are schematic diagrams illustrating a method for fabricating a semiconductor device according to one embodiment of this disclosure; and

[0050] Figure 35 This is a block diagram of a system with a memory system provided by way of example in this disclosure. Detailed Implementation

[0051] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this disclosure, the first direction discussed herein may also be referred to as the second direction, and vice versa.

[0053] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0054] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0055] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0056] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0057] Furthermore, in this disclosure, the use of "connection" or "linkage" may indicate a direct or indirect connection between the corresponding components, and the use of "contact" may indicate a direct connection between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0058] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0059] This disclosure provides a semiconductor device through some embodiments. Figures 1-2 These are cross-sectional schematic diagrams of a semiconductor device 1000 according to exemplary embodiments of the present disclosure.

[0060] like Figures 1-2 As shown, the semiconductor device 1000 includes a semiconductor body 100, a gate structure 200, and a dielectric filling portion 400. The gate structure 200 is located on a sidewall 101 of the semiconductor body 100 extending along a first direction (z-direction). The dielectric filling portion 400 is located at least on the side of the gate structure 200 opposite to the semiconductor body 100. The gate structure 200 may include a gate dielectric layer 210 located on the sidewall 101 of the semiconductor body 100, and the dielectric constant of the dielectric filling portion 400 is less than the dielectric constant of the gate dielectric layer 210.

[0061] In the semiconductor device provided in this disclosure, the gate structure includes a gate dielectric layer located on the sidewall of the semiconductor body, and a dielectric filling portion is located at least on the side of the gate structure opposite to the semiconductor body. Furthermore, the dielectric constant of the dielectric filling portion is lower than that of the gate dielectric layer. In other words, the material of the dielectric filling portion has a relatively low dielectric constant, which helps to reduce the parasitic capacitance effect between gate structures, reduce the electric field coupling between two adjacent transistors disposed in the xy plane intersecting the z-direction, improve the sensing tolerance of the semiconductor device, and improve both the overall performance and yield of the semiconductor device.

[0062] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device 1000 according to an exemplary embodiment of the present disclosure. Figure 4 This is a top view schematic diagram of a semiconductor device 1000 according to an exemplary embodiment of the present disclosure.

[0063] Specifically, such as Figure 3 and Figure 4 As shown, in some embodiments of this disclosure, taking DRAM as an example, the semiconductor device 1000 may include a transistor structure layer 1 and a memory cell layer 2. The transistor structure layer 1 is located on one side of the memory cell layer 2 along the z-direction, where the z-direction can be understood as the stacking direction of the transistor structure layer 1 and the memory cell layer 2. The transistor structure layer 1 may include a plurality of transistors 11, and the memory cell layer 2 may include memory cells 21 connected to the transistors 11 in the transistor structure layer 1. The plurality of transistors 11 may be spaced apart in a second direction (x-direction). Alternatively, the plurality of transistors 11 may also be spaced apart in a third direction (y-direction), where the x-direction, y-direction, and z-direction may intersect each other. In other words, as an option, the plurality of transistors 11 in the transistor structure layer 1 may be spaced apart in the x-direction and spaced apart in the y-direction.

[0064] Furthermore, the semiconductor device 1000 may also include a peripheral circuit structure 1000-2, the peripheral circuit of which may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the transistor structure layer 1 and the memory cell layer 2. For example, the peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0065] Optionally, the peripheral circuit structure 1000-2 may be located on one side of the first semiconductor structure 1000-1 of the semiconductor device 1000 along the z-direction. The peripheral circuit structure 1000-2 and the first semiconductor structure 1000-1 may be connected by bonding or other bonding methods, wherein the transistor structure layer 1 and the memory cell layer 2 may both be located in the first semiconductor structure 1000-1.

[0066] Optionally, to further reduce the size of the two-dimensional array, transistor 11 may include a vertical gate transistor (VGT) array. In this structure, the source 110 and drain 120 of transistor 11 can be formed at both ends of the channel extension direction, and the gate structure 200 of transistor 11 can be formed on at least one side of the channel. The specific arrangement details of transistor 11 will be described in detail below with reference to the accompanying drawings.

[0067] In some embodiments of this disclosure, vertical transistors, such as vertical metal-oxide-semiconductor field-effect transistors (MOSFETs), can replace conventional planar transistors as transfer transistors for memory cells, thereby reducing the area occupied by the transfer transistors, coupling capacitance, and interconnect wiring complexity. In some embodiments, unlike planar transistors where the active region is formed in the substrate, a vertical transistor type transistor 11 may include a semiconductor body 100 extending vertically along the z-direction. The semiconductor body 100 may extend along the z-direction, exposing not only its top surface but also one or more sidewalls, such as a first sidewall 101, a second sidewall 102, a third sidewall 103, and a fourth sidewall 104, etc.

[0068] Optionally, the semiconductor body 100 may have a cubic shape and four exposed sidewalls, such as a first sidewall 101, a second sidewall 102, a third sidewall 103, and a fourth sidewall 104. However, those skilled in the art will understand that the semiconductor body 100 may also have any suitable 3D shape, such as a polyhedral or cylindrical shape. In other words, the cross-section of the semiconductor body 100 in the xy plane may have a square, rectangular, trapezoidal, circular, elliptical, or any other suitable shape. It should be understood that, consistent with the scope of this disclosure, for a semiconductor body with a circular or elliptical cross-section in the aforementioned plane, the semiconductor body 100 may still be considered to have multiple sidewalls such that the gate structure 200 contacts one sidewall of the semiconductor body 100. Furthermore, in accordance with the semiconductor device fabrication process described below, the semiconductor body 100 may be formed from a substrate by, for example, etching or epitaxial processes, and thus may have the same semiconductor material as the substrate.

[0069] Alternatively, the substrate material may include, but is not limited to, silicon (e.g., single-crystal silicon c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable semiconductor material. For example, the substrate may be a silicon substrate. Accordingly, the semiconductor body 100 may include at least one of the above-described materials.

[0070] Combination Figures 1-4The transistor 11 may include a gate structure 200 in contact with a sidewall of the semiconductor body 100. For example, the gate structure 200 may be located on one of two sidewalls of the semiconductor body 100 opposite each other in the x-direction. Optionally, the gate structure 200 may also be located on multiple sidewalls of the semiconductor body 100. For example, if the semiconductor body 100 has a cubic shape and includes a first sidewall 101, a second sidewall 102, a third sidewall 103, and a fourth sidewall 104, the gate structure 200 may be located on the first sidewall 101, the third sidewall 103, and the fourth sidewall 104 of the semiconductor body 100. Having multiple sidewalls of the semiconductor body as gate structures enhances the gate control capability of the gate structure.

[0071] refer to Figure 3 In some embodiments of this disclosure, the source 110 and drain 120 formed at the two ends of the semiconductor body 100 in the z-direction can be understood as heavily doped regions of the semiconductor body 100, and can also be referred to as source electrodes and drain electrodes. Specifically, the source 110 and drain 120 can be doped with any suitable P-type dopant, which may include any one or a combination of boron (B) or gallium (Ga). Alternatively, the source 110 and drain 120 can be doped with any suitable N-type dopant, which may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). The source 110 and drain 120 are separated in the z-direction by the gate structure 200. In other words, the gate structure 200 is formed between the source and drain along the z-direction. Therefore, when the gate voltage applied to the gate structure 200 is higher than the threshold voltage of the transistor 11, the channel of the transistor 11 can be formed in the semiconductor body 100 along the z-direction between the source and the drain, which can be understood as the gate control capability of the gate structure.

[0072] like Figure 2 As shown, in some embodiments of this disclosure, the gate structure 200 may include a gate dielectric layer 210 located on the sidewall of the semiconductor body 100. Furthermore, the gate structure 200 may also include a gate adhesive layer 220 and a gate conductor layer 230, wherein the gate adhesive layer 220 is located on the side of the gate dielectric layer 210 away from the sidewall of the semiconductor body 100, and the gate conductor layer 230 is located on the side of the gate adhesive layer 220 away from the gate dielectric layer 210. In other words, the gate adhesive layer 220 is located on the surface of the gate dielectric layer 210 and in contact with the gate dielectric layer 210, and the gate conductor layer 230 is located on the surface of the gate adhesive layer 220 and in contact with the gate adhesive layer 220.

[0073] The gate dielectric layer 210 may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. The gate adhesive layer 220 may include, but is not limited to, titanium, titanium nitride, tantalum, or tantalum nitride. The gate conductor layer 230 may include any suitable conductive material, such as, but not limited to, metallic materials like tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al), or any suitable semiconductor material like silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), and germanium (Ge). The gate adhesive layer serves to block the diffusion of conductive materials in the gate conductor layer and also to improve the adhesion between the gate conductor layer and the gate dielectric layer.

[0074] Optionally, the dielectric constant (k) of the gate dielectric layer 210 can be greater than 3, or in other words, a high-k dielectric material can be used to fabricate the gate dielectric layer 210. As the size of transistors shrinks, the gate leakage current and the source-drain leakage current increase dramatically. By using a high-k dielectric material for the gate dielectric layer, the gate leakage current can be reduced and the reliability of semiconductor devices can be improved while maintaining the gate capacitance unchanged.

[0075] The dielectric filling portion 400 is located at least on the side of the gate structure 200 facing away from the semiconductor body 100. Furthermore, the two opposite ends of the dielectric filling portion 400 along the z-direction can extend in the xy-plane, contacting the semiconductor body 100 and enclosing the gate structure 200 with the semiconductor body 100. The material of the dielectric filling portion has a relatively low dielectric constant, which helps to reduce the parasitic capacitance effect between gate structures, reduce the electric field coupling between two adjacent transistors in the xy-plane, improve the sensing tolerance of the semiconductor device, and improve the overall performance and yield of the semiconductor device.

[0076] Optionally, the dielectric constant of the dielectric filling portion 400 may be less than or equal to 3. For example, the dielectric filling portion 400 may include at least one of fluorine-doped silicon oxide (SiOF), carbon-doped silicon oxide (SiOC), amorphous fluorinated carbon (aC:F), and hydrogen silsesquioxane (HSQ). It is understood that the materials of the dielectric filling portion provided in this disclosure are merely examples and are not intended to limit the scope and application of the invention. Those skilled in the art can make corresponding adjustments to the specific materials of the dielectric filling portion according to the concept of the invention to achieve the same technical effect.

[0077] Refer again Figures 1-4In at least some embodiments of this disclosure, the semiconductor device 1000 further includes a back gate structure 300. The back gate structure 300 can reduce interference between adjacent gate structures 200 in the semiconductor device 1000. The back gate structure 300 may be located on a sidewall of the semiconductor body 100. In other words, the back gate structure 300 may extend in the y-direction and connect to one of two sidewalls of the semiconductor body 100 opposite each other in the x-direction, such as the second sidewall 102.

[0078] Optionally, such as Figure 2 As shown, the back gate structure 300 may include a first dielectric layer 310 and a second dielectric layer 320, wherein the second dielectric layer 320 is located between the first dielectric layer 310 and the sidewall of the semiconductor body 100. Both the first dielectric layer 310 and the second dielectric layer 320 may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0079] Alternatively, the dielectric constant of the first dielectric layer 310 may be less than or equal to the dielectric constant of the second dielectric layer 320. In other words, the material of the first dielectric layer may have a relatively low dielectric constant, which helps to reduce the parasitic capacitance effect between gate structures, reduce the electric field coupling between two adjacent transistors in the xy plane, improve the sensing tolerance of the semiconductor device, and improve the overall performance and yield of the semiconductor device. For example, the dielectric constant of the first dielectric layer 310 may be less than or equal to 3.

[0080] Furthermore, to enhance the aforementioned effects, as an alternative, the second dielectric layer 320 can also be fabricated using a low-k dielectric material. For example, the dielectric constant of both the first dielectric layer 310 and the second dielectric layer 320 can be less than or equal to 3.

[0081] In addition, to enhance the above effects, as another option, the back gate structure 300 may also include an air gap 330 located on one side of the first dielectric layer 310 in the z-direction. Air has a very low dielectric constant, approaching that of a vacuum. Therefore, by providing an air gap in the back gate structure 300 located on one side of the first dielectric layer in the z-direction, the parasitic capacitance effect between gate structures can be reduced, improving the sensing tolerance of the semiconductor device.

[0082] Furthermore, in some embodiments of this disclosure, the semiconductor device 1000 also includes a bit line structure 500, wherein the bit line structure 500 extends in the x-direction and contacts the ends of a plurality of semiconductor bodies 100. Thus, the plurality of semiconductor bodies 100 can be connected via the bit line structure 500. Additionally, the plurality of bit line structures 500 can be connected in the y-direction (e.g., ...). Figure 4 (As shown) Interval settings.

[0083] Optionally, the bit line structure 500 may be a composite structure, such as comprising a first bit line layer (not shown) and a second bit line layer (not shown) stacked sequentially in the z-direction. Optionally, the first bit line layer may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicides, etc. The second bit line layer may include, but is not limited to, silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable semiconductor material. Optionally, the second bit line layer may be located on one side of the first bit line layer along the z-direction and contact the ends of the plurality of semiconductor bodies 100. Furthermore, when the material of the second bit line layer is the same as the material of the semiconductor body 100, there is no obvious boundary between the second bit line layer and the ends of the semiconductor body 100.

[0084] Optionally, the air gap 330 may be closer to the bit line structure 500 relative to the first dielectric layer 310. Furthermore, to enhance the reduction of parasitic capacitance between gate structures and improve the sensing tolerance of the semiconductor device, in some embodiments of this disclosure, the dimension L1 of the air gap 330 in the z-direction may be larger than the dimension L2 of the first dielectric layer 310. By maximizing the size of the air gap, the parasitic capacitance between gate structures can be effectively reduced.

[0085] Figures 5-8 These are cross-sectional schematic diagrams of a semiconductor device 1000 according to exemplary embodiments of the present disclosure.

[0086] like Figures 5-6 As shown, in at least some embodiments of this disclosure, the back gate structure 300 may further include a third dielectric layer 340 and a fourth dielectric layer 350, wherein the third dielectric layer 340 is located on one side of the first dielectric layer 310 in the z direction, and the fourth dielectric layer 350 is located on the other side of the first dielectric layer 310 in the z direction.

[0087] In this embodiment, the air gap 330 can be located between the first dielectric layer 310 and the third dielectric layer 340 along the z-direction. The third dielectric layer 340 is closer to the bit line structure 500 than the fourth dielectric layer 350. Furthermore, the third dielectric layer 340 is closer to the bit line structure 500 than the first dielectric layer 310.

[0088] like Figure 6As shown, alternatively, the dielectric constant of the third dielectric layer 340 may be different from that of the first dielectric layer 310, and the dielectric constant of the fourth dielectric layer 350 may also be different from that of the first dielectric layer 310. For example, the dielectric constant of the first dielectric layer 310 may be less than or equal to that of the third dielectric layer 340; the dielectric constant of the first dielectric layer 310 may be less than or equal to that of the fourth dielectric layer 350. Furthermore, the dielectric constants of the third dielectric layer 340 and the fourth dielectric layer 350 may also be different.

[0089] Optionally, in the direction intersecting the z-direction (e.g., the x-direction), the size m1 of the first dielectric layer 310 is smaller than the size m2 of the third dielectric layer 340. Furthermore, in the direction intersecting the z-direction (e.g., the x-direction), the size m1 of the first dielectric layer 310 is smaller than the size m3 of the fourth dielectric layer 340.

[0090] like Figures 6-8 As shown, the back gate structure 300 may include only the third dielectric layer 340 and exclude the fourth dielectric layer 350, provided that it includes the first dielectric layer 310 and the second dielectric layer 320. Alternatively, the back gate structure 300 may include only the fourth dielectric layer 350 and exclude the third dielectric layer 340, provided that it includes the first dielectric layer 310 and the second dielectric layer 320.

[0091] In other words, the back gate structure 300 may include multiple filling portions, which can be formed in different steps during the formation of the back gate structure 300. Furthermore, these filling portions can be formed using different dielectric materials, thus the final back gate structure may include multiple filling portions. For example, materials with different dielectric constants can be used to form the back gate structure 300 in different steps. However, it should be noted that if the filling portions of the back gate structure formed in different steps are made of the same material, these filling portions made of the same material do not have clear boundaries with each other.

[0092] Refer again Figure 2 In at least some embodiments of this disclosure, the dielectric filling portion 400 may also include multiple filling portions with different dielectric constants, such as a first filling portion 401 and a second filling portion 402. Optionally, the dielectric constants of the multiple filling portions may all be less than or equal to 3.

[0093] In other words, the dielectric filling portion 400 may include multiple filling portions, which may be formed in different steps during the formation of the dielectric filling portion 400. Furthermore, these filling portions may be formed using different dielectric materials, thus the final dielectric filling portion 400 may include multiple filling portions. For example, materials with different dielectric constants may be used to form the dielectric filling portion 400 in different steps. However, it should be noted that if the filling portions of the dielectric filling portion 400 formed in different steps are made of the same material, these filling portions made of the same material do not have clear boundaries with each other.

[0094] Optionally, the first filling portion 401 is located between adjacent gate structures 200 in the x-direction, and the second filling portion 402 is located on one side of the first filling portion 401 in the z-direction. In the direction intersecting the z-direction (e.g., the x-direction), the size d1 of the first filling portion 401 is smaller than the size d2 of the second filling portion 402.

[0095] Furthermore, the medium filling portion 400 may also include a third filling portion 403, wherein the first filling portion 401 is located between the second filling portion 402 and the third filling portion 403 in the z-direction. In a direction intersecting the z-direction (e.g., the x-direction), the dimension d1 of the first filling portion 401 is smaller than the dimension d3 of the third filling portion 403.

[0096] Optionally, such as Figure 2 and Figure 6 As shown, the material of the second filling portion 402 can be the same as the material of the third filling portion 403. In addition, the material of the first filling portion 401 can be different from the material of the second filling portion 402 and the material of the third filling portion 403.

[0097] Optionally, such as Figure 2 and Figure 8 As shown, the medium filling portion 400 may include only the second filling portion 402, excluding the third filling portion 403, even when the first filling portion 401 is included. In this embodiment, the material of the first filling portion 401 may be different from the material of the second filling portion 402. Alternatively, the medium filling portion 400 may include only the third filling portion 403, excluding the second filling portion 402, even when the first filling portion 401 is included. In this embodiment, the material of the first filling portion 401 may be different from the material of the third filling portion 403.

[0098] like Figures 9-12As shown, in at least some embodiments of this disclosure, the medium filling portion 400 may also be made of only one material. For example, multiple portions of the medium filling portion 400 may be formed in different steps, and the same material may be used to form the multiple portions in each of these different steps. In this way, although different portions of the medium filling portion 400 are formed in different steps, there are no obvious boundaries between these multiple portions made of the same material.

[0099] As an option, such as Figure 10 As shown, the dielectric filling portion 400 can be made of the same material as the first dielectric layer 310 of the back gate structure 300, so the dielectric constant of the dielectric filling portion 400 can be the same as the dielectric constant of the first dielectric layer 310 of the back gate structure 300.

[0100] As another option, such as Figure 12 As shown, the dielectric filling portion 400 may be made of a different material than the first dielectric layer 310 of the back gate structure 300, and thus the dielectric constant of the dielectric filling portion 400 may be different from the dielectric constant of the first dielectric layer 310 of the back gate structure 300.

[0101] Figures 13-14 These are cross-sectional schematic diagrams of a semiconductor device 1000 according to exemplary embodiments of the present disclosure.

[0102] like Figures 13-14 As shown, in at least some embodiments of this disclosure, the first filling portion 401 of the medium filling portion 400 may include a plurality of sub-portions, such as a first sub-portion 401-1 and a second sub-portion 401-2, wherein the second sub-portion 401-2 may be disposed around the first sub-portion 401-1.

[0103] Optionally, the second sub-part 401-2 may include an end portion 4111 and a side portion 4112 connected to the end portion 4111, the end portion 4111 being close to the bit line structure 500. The first sub-part 401-1 may be located on one side of the end portion 4111 of the second sub-part 401-2 in the z-direction and surrounded by the side portion 4112 of the second sub-part 401-2.

[0104] In addition, the multiple sub-parts of the first filling portion 401 can also be arranged along the z-direction. This application does not limit the specific arrangement of the multiple sub-parts of the first filling portion.

[0105] Therefore, in the semiconductor device provided in this disclosure, the gate structure includes a gate dielectric layer located on the sidewall of the semiconductor body, the dielectric filling portion is located at least on the side of the gate structure away from the semiconductor body, and the dielectric constant of the dielectric filling portion is lower than the dielectric constant of the gate dielectric layer. In other words, the material of the dielectric filling portion has a relatively low dielectric constant, which helps to reduce the parasitic capacitance effect between gate structures, reduce the electric field coupling effect between two adjacent transistors disposed in the xy plane intersecting the z-direction, improve the sensing tolerance of the semiconductor device, and improve the overall performance and yield of the semiconductor device.

[0106] This disclosure provides another semiconductor device through some embodiments. Figures 15-16 These are cross-sectional schematic diagrams of a semiconductor device 1000 according to exemplary embodiments of the present disclosure.

[0107] like Figure 4 , Figures 15-16 As shown, the semiconductor device 1000 includes a semiconductor body 100 and a back gate structure 300. The semiconductor body 100 extends in the z-direction and includes sidewalls 102 extending in the z-direction. The back gate structure 300 extends in a direction intersecting the z-direction (e.g., the y-direction) and is connected to the sidewalls 102 of the plurality of semiconductor bodies 100. The back gate structure 300 may include a first dielectric layer 310 and a second dielectric layer 320, wherein the second dielectric layer 320 is located between the first dielectric layer 310 and the sidewalls 102 of the semiconductor body 100, and the dielectric constant of the first dielectric layer 310 is less than or equal to the dielectric constant of the second dielectric layer 320.

[0108] Therefore, in the semiconductor device provided by the present disclosure, the material of the first dielectric layer in the back gate structure can have a relatively low dielectric constant, which helps to reduce the parasitic capacitance effect between gate structures, reduce the electric field coupling effect between two adjacent transistors in the xy plane, improve the sensing tolerance of the semiconductor device, and improve the overall performance of the semiconductor device while increasing the yield of the semiconductor device.

[0109] Optionally, the first dielectric layer 310 may be fabricated using a low-k dielectric material. For example, the dielectric constant of the first dielectric layer 310 may be less than or equal to 3. Furthermore, to enhance the above effect, as another option, the second dielectric layer 320 may also be fabricated using a low-k dielectric material. For example, the dielectric constants of both the first dielectric layer 310 and the second dielectric layer 320 may be less than or equal to 3.

[0110] In addition, to enhance the above effects, as another option, the back gate structure 300 may also include an air gap 330 located on one side of the first dielectric layer 310 in the z-direction. Air has a very low dielectric constant, close to that of a vacuum. Therefore, providing an air gap in the back gate structure 300 on one side of the first dielectric layer in the z-direction can reduce the parasitic capacitance effect between gate structures and improve the sensing tolerance of the semiconductor device.

[0111] Furthermore, the air gap 330 can be closer to the bit line structure 500 relative to the first dielectric layer 310. In order to enhance the effect of reducing the parasitic capacitance effect between gate structures and improving the sensing tolerance of the semiconductor device, in some embodiments of this disclosure, the size L1 of the air gap 330 in the z direction can be larger than the size L2 of the first dielectric layer 310. By maximizing the size of the air gap, the parasitic capacitance between gate structures can be effectively reduced.

[0112] In at least some embodiments of this disclosure, the back gate structure 300 may further include a third dielectric layer 340 and a fourth dielectric layer 350, wherein the third dielectric layer 340 is located on one side of the first dielectric layer 310 in the z-direction, and the fourth dielectric layer 350 is located on the other side of the first dielectric layer 310 in the z-direction.

[0113] In this embodiment, the air gap 330 can be located between the first dielectric layer 310 and the third dielectric layer 340 along the z-direction. The third dielectric layer 340 is closer to the bit line structure 500 than the fourth dielectric layer 350. Furthermore, the third dielectric layer 340 is closer to the bit line structure 500 than the first dielectric layer 310.

[0114] Alternatively, the dielectric constant of the third dielectric layer 340 may be different from that of the first dielectric layer 310, and the dielectric constant of the fourth dielectric layer 350 may also be different from that of the first dielectric layer 310. For example, the dielectric constant of the first dielectric layer 310 may be less than or equal to that of the third dielectric layer 340; the dielectric constant of the first dielectric layer 310 may be less than or equal to that of the fourth dielectric layer 350. Furthermore, the dielectric constants of the third dielectric layer 340 and the fourth dielectric layer 350 may also be different.

[0115] Optionally, in the direction intersecting the z-direction (e.g., the x-direction), the size m1 of the first dielectric layer 310 is smaller than the size m2 of the third dielectric layer 340. Furthermore, in the direction intersecting the z-direction (e.g., the x-direction), the size m1 of the first dielectric layer 310 is smaller than the size m3 of the fourth dielectric layer 340.

[0116] Furthermore, the back gate structure 300 may include only the third dielectric layer 340 and exclude the fourth dielectric layer 350, provided that it includes the first dielectric layer 310 and the second dielectric layer 320. Alternatively, the back gate structure 300 may include only the fourth dielectric layer 350 and exclude the third dielectric layer 340, provided that it includes the first dielectric layer 310 and the second dielectric layer 320.

[0117] In other words, the back gate structure 300 may include multiple filling portions, which can be formed in different steps during the formation of the back gate structure 300. Furthermore, these filling portions can be formed using different dielectric materials, thus the final back gate structure may include multiple filling portions. For example, materials with different dielectric constants can be used to form the back gate structure 300 in different steps. However, it should be noted that if the filling portions of the back gate structure formed in different steps are made of the same material, these filling portions made of the same material do not have clear boundaries with each other.

[0118] Therefore, in the semiconductor device provided by the present disclosure, the material of the first dielectric layer in the back gate structure can have a relatively low dielectric constant, which helps to reduce the parasitic capacitance effect between gate structures, reduce the electric field coupling effect between two adjacent transistors in the xy plane, improve the sensing tolerance of the semiconductor device, and improve the overall performance of the semiconductor device while increasing the yield of the semiconductor device.

[0119] In addition, some embodiments of this disclosure also provide a method for manufacturing a semiconductor device 2000. Figure 17 This is a flowchart of a method 2000 for preparing a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 18-34 These are schematic diagrams of a semiconductor device fabrication method 2000 according to one embodiment of the present disclosure.

[0120] like Figure 17 As shown, this disclosure provides a method for fabricating a semiconductor device 2000, which may include:

[0121] S1, forming a semiconductor body extending along the first direction.

[0122] S2, a gate structure is formed on a sidewall extending along a first direction of the semiconductor body, wherein the gate structure includes a gate dielectric layer located on the sidewall of the semiconductor body.

[0123] S3, at least on the side of the gate structure away from the semiconductor body, a dielectric filling portion is formed, wherein the dielectric constant of the dielectric filling portion is less than the dielectric constant of the gate dielectric layer.

[0124] The following will combine Figures 17-34 The specific processes for each step of the above preparation method 2000 are described in detail.

[0125] Step S1

[0126] Figure 18 This is a top view schematic diagram of the structure formed after forming intermediate 100' according to a preparation method according to one embodiment of the present disclosure. Figure 19 This is a top view schematic diagram of the structure formed after forming the first groove 201 according to a preparation method according to an embodiment of the present disclosure. Figure 20 This is a cross-sectional schematic diagram of the structure formed after forming the first groove 201 according to a preparation method according to one embodiment of the present disclosure. Figure 21 This is a top view schematic diagram of the structure formed after forming the second trench 301 according to a preparation method according to one embodiment of the present disclosure. Figure 22 This is a cross-sectional schematic diagram of the structure formed after forming the second trench 301 according to a preparation method according to one embodiment of the present disclosure.

[0127] like Figures 18-22 As shown, step S1, forming a semiconductor body extending along a first direction, may include, for example, providing a substrate; and forming a semiconductor body 100 extending along the first direction (z direction) based on the substrate.

[0128] Specifically, in some embodiments of this disclosure, the material used to prepare the substrate can be any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide, etc., which are group III-V compounds. Alternatively, the substrate can be single-crystal silicon.

[0129] In some embodiments of this disclosure, the substrate may be, for example, a composite substrate for supporting a device structure thereon. A substrate can be formed by sequentially depositing multiple layers made of different materials using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0130] In some embodiments of this disclosure, the substrate may include a substrate sacrificial layer (not shown). Optionally, the substrate sacrificial layer may include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the substrate sacrificial layer may be a high-dielectric-constant dielectric layer. Alternatively, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer sequentially disposed, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. As yet another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer may be monocrystalline silicon or polycrystalline silicon. Specifically, in some embodiments of this disclosure, an exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0131] Furthermore, a portion of the substrate may also form a well region doped with an N-type or P-type dopant via ion implantation or diffusion processes. The dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb); or any one or a combination of boron (B), gallium (Ga), or indium (In). In some embodiments of this disclosure, the well regions may be prepared using the same or different dopants; furthermore, the doping concentration of the well regions may be the same or different, and this disclosure does not limit this.

[0132] After the substrate is formed, alternatively, a semiconductor substrate (epitaxy layer) extending along the z-direction can be selectively formed on the substrate using epitaxial growth processes, including but not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. The material of the epitaxial layer can be at least one of silicon, silicon-germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials.

[0133] In addition, such as Figures 18-22 As shown, as another option, it can also be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove part of the substrate and form a semiconductor body 100 extending along the z-direction.

[0134] Specifically, such as Figure 18As shown, the initial trenches (not shown) can be formed in the substrate by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to form initial trenches (not shown) extending in a direction intersecting the z-direction (e.g., the x-direction). Multiple initial trenches can be spaced apart in a direction intersecting the z-direction (e.g., the y-direction), thereby forming at least a portion of the substrate as multiple strip semiconductors 100'-1 spaced apart in the y-direction. After forming the multiple strip semiconductors 100'-1, an intermediate 100' can be formed by filling the initial trenches with an initial dielectric layer 100'-2 using one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0135] Optionally, the initial dielectric layer 100'-2 may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0136] like Figures 18-20 As shown, after forming the intermediate body 100', it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to form a first trench 201 extending in the y-direction in the intermediate body 100', and a plurality of first trenches 201 can be arranged at intervals in the x-direction. Furthermore, the first trenches 201 can extend in the intermediate body 100' along the z-direction, dividing the strip semiconductor 100'-1 into a plurality of initial semiconductor bodies 100-1.

[0137] like Figures 19-22 As shown, the first trench 201 can be filled with a gate-side sacrificial layer 202 by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0138] Alternatively, before filling the first trench 201 with the gate-side sacrificial layer 202, a first isolation layer 203 may be formed at least on the inner wall of the first trench 201 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first isolation layer 203 may be a composite structure, for example, comprising an initial gate dielectric layer 210' and an initial gate adhesive layer 220' sequentially formed on the inner wall of the first trench 201, wherein the initial gate dielectric layer 210' and the initial gate adhesive layer 220' can be used as the gate dielectric layer and gate adhesive layer in the subsequent formation of the gate structure. The first isolation layer 203 protects the initial semiconductor body 100-1 from contamination in subsequent processes.

[0139] In addition, a first isolation layer 203 can be formed on the inner wall of the first trench 201, the surface of the intermediate body on which the first trench 201 is formed, and the surface of the gate-side sacrificial layer 202 through multiple thin film deposition processes. The thin film deposition process may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0140] Optionally, the gate-side sacrificial layer 202 may be formed of a material with a high deposition rate to facilitate rapid filling of the first trench 201, and the gate-side sacrificial layer 202 should be any material with high dry etching selectivity relative to the first isolation layer 203 and the initial semiconductor body 100-1 to facilitate removal in subsequent steps. For example, the material of the gate-side sacrificial layer 202 may be tungsten (W).

[0141] After forming the gate-side sacrificial layer 202, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to form a second trench 301 extending in the y-direction. The second trench 301 can be located between adjacent gate-side sacrificial layers 202 distributed in the x-direction. Furthermore, the second trench 301 can extend in the z-direction, dividing the initial semiconductor body 100-1 into two semiconductor bodies 100.

[0142] The semiconductor body 100 may have a cubic shape and four exposed sidewalls, such as a first sidewall 101 and a second sidewall 102 facing away from each other in the x-direction. Furthermore, the semiconductor body 100 may also have any suitable 3D shape, such as a polyhedral or cylindrical shape. In other words, the cross-section of the semiconductor body 100 in the xy-plane may have a square, rectangular, trapezoidal, circular, elliptical, or any other suitable shape. It should be understood that, consistent with the scope of this disclosure, for a semiconductor body having a circular or elliptical cross-section in the aforementioned plane, the semiconductor body 100 may still be considered to have multiple sidewalls such that the gate structure 200 contacts one sidewall of the semiconductor body 100.

[0143] Steps S2 and S3

[0144] To simplify the semiconductor device fabrication process and reduce its cost, the following implementation method provides a parallel execution of steps S2 and S3. It should be noted that steps S2 and S3 can also be executed separately; this application does not limit the execution order of steps S2 and S3.

[0145] Figure 23 This is a cross-sectional schematic diagram of the structure formed after forming the back gate sacrificial layer 302 according to a preparation method according to one embodiment of the present disclosure. Figure 24 This is a cross-sectional schematic diagram of the structure formed after forming an initial first dielectric layer 310' according to a preparation method of one embodiment of the present disclosure. Figure 25 This is a cross-sectional schematic diagram of the structure formed after forming a first dielectric layer 310” and a process gate-side sacrificial layer 202’ according to a preparation method according to an embodiment of the present disclosure. Figure 26 For the preparation method according to one embodiment of this disclosure, the gate-side sacrificial layer 202' (e.g.) is removed during the process. Figure 25 (See diagram) A cross-sectional view of the structure formed after (shown). Figure 27 This is a cross-sectional schematic diagram of the structure formed after forming the initial gate conductor layer 230' according to a preparation method of one embodiment of the present disclosure. Figure 28 This is a cross-sectional schematic diagram of the structure formed after forming the initial medium filling portion 400' according to a preparation method according to an embodiment of the present disclosure. Figure 29 This is a cross-sectional schematic diagram of the structure formed after forming the process medium filling portion 400” according to a preparation method according to one embodiment of the present disclosure. Figure 30 This is a cross-sectional schematic diagram of the structure formed after forming the process medium filling portion 400” according to a preparation method according to one embodiment of the present disclosure. Figure 31 To prepare a method for removing the back gate sacrificial layer 303 (e.g., according to one embodiment of this disclosure) Figure 30 (See diagram) A cross-sectional view of the structure formed after (shown). Figure 32 This is a cross-sectional schematic diagram of the structure formed after forming an air gap 330 according to a preparation method according to one embodiment of the present disclosure. Figure 33 This is a cross-sectional schematic diagram of the structure formed after forming the gate structure 200 according to a preparation method according to one embodiment of the present disclosure. Figure 34 This is a cross-sectional schematic diagram of the structure formed after forming the fourth dielectric layer 350 according to a preparation method according to one embodiment of the present disclosure.

[0146] like Figure 22 and Figure 23 As shown, after the gate-side sacrificial layer 202 is formed, the intermediate body 111 having the gate-side sacrificial layer 202 and the semiconductor body 100 may include a substrate 111-1, wherein a plurality of semiconductor bodies 100 are located on one side of the substrate 111-1 in the z direction.

[0147] like Figures 22-26 As shown, in some embodiments of this disclosure, the method 2000 for fabricating a semiconductor device may further include forming a back gate structure. Optionally, forming the back gate structure may include: forming an initial second dielectric layer 302 on the sidewalls of the semiconductor body 100 and the portion of the substrate 111-1 between adjacent semiconductor bodies 100; forming a back gate sacrificial layer 303 on the surface of the initial second dielectric layer 302; and forming a first dielectric layer 310 on one side of the back gate sacrificial layer 303 in the z-direction, wherein the back gate sacrificial layer 310 has a predetermined dimension h1 in the z-direction.

[0148] Specifically, such as Figures 22-23 As shown, an initial second dielectric layer 302 can be formed on the sidewalls of the semiconductor body 100 and the portion of the substrate 111-1 between adjacent semiconductor bodies 100 using one or more thin-film deposition processes. The thin-film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The initial second dielectric layer 302 can be used to form the second dielectric layer of the back gate structure in subsequent processes. Optionally, the initial second dielectric layer 302 may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. Alternatively, a low-k dielectric material may be used to prepare the initial second dielectric layer 302 so that the subsequently formed back gate structure can more effectively reduce the parasitic capacitance effect between gate structures and improve the sensing tolerance of the semiconductor device. The low-k dielectric material may include at least one of fluorine-doped silicon oxide (SiOF), carbon-doped silicon oxide (SiOC), amorphous fluorinated carbon (aC:F), and hydrogen silsesquioxane (HSQ).

[0149] After the initial second dielectric layer 302 is formed, a back gate sacrificial layer 303 may be formed on the surface of the initial second dielectric layer 302 by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0150] The back gate sacrificial layer 303 is used to form the air gap in the back gate structure in subsequent steps. Optionally, to simplify the fabrication process, the back gate sacrificial layer 303 may fill the bottom of the second trench 301 where the initial second dielectric layer 302 has been formed and the portion of the sidewall connected to the bottom. The back gate sacrificial layer 310 has a predetermined dimension h1 in the z-direction, which can be used to define the size of the air gap in the z-direction. In order to enhance the effect of reducing the parasitic capacitance effect between gate structures and improving the sensing tolerance of the semiconductor device, in some embodiments of this disclosure, the predetermined size of the back gate sacrificial layer may be maximized so that the size of the air gap with a relatively low dielectric constant is large enough to effectively reduce the parasitic capacitance between gate structures.

[0151] Optionally, the back gate sacrificial layer 303 may be formed of a material with a high deposition rate to facilitate rapid filling formation, and the back gate sacrificial layer 303 should be any material with high dry etching selectivity relative to the initial second dielectric layer 302 to facilitate removal in subsequent steps. For example, the material of the back gate sacrificial layer 303 may be titanium nitride.

[0152] like Figures 23-26 As shown, after the back gate sacrificial layer 303 is formed, a first dielectric layer 310 can be formed on one side of the back gate sacrificial layer 303 in the z direction by one or more thin film deposition processes, wherein the thin film deposition process may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0153] Optionally, such as Figures 23-24 As shown, an initial first dielectric layer 310' can be formed first through the above process. The initial first dielectric layer 310' can cover the surface of the gate-side sacrificial layer 202 and fill the second trench 301 (e.g., where the back gate sacrificial layer 303 and the initial second dielectric layer 302 have been formed) Figure 22 As shown in the figure.

[0154] When the first isolation layer 203 covers the gate-side sacrificial layer 202, the initial first dielectric layer 310' can cover a portion of the surface of the first isolation layer 203 and fill the second trench 301 (e.g., where the back gate sacrificial layer 303 and the initial second dielectric layer 302 have been formed) Figure 22 As shown in the figure.

[0155] like Figures 24-25 As shown, after the initial first dielectric layer 310' is formed, a planarization process, such as grinding and / or chemical mechanical polishing, can be performed to remove part of the initial first dielectric layer 310' to form the process first dielectric layer 310". The process first dielectric layer 310" formed by the planarization process can have a relatively flat surface to facilitate the execution of subsequent processes.

[0156] In addition, during the planarization process of the initial first dielectric layer 310', the same planarization process can be performed on the gate-side sacrificial layer 202, and the process gate-side sacrificial layer 202' is formed by removing part of the gate-side sacrificial layer 202.

[0157] like Figures 25-26 As shown, the first dielectric layer 310 can be partially removed using, for example, a planarization process to form the first dielectric layer 310. After the first dielectric layer 310 is formed, it is formed using, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to remove the gate-side sacrificial layer 202 (e.g., Figure 24 (As shown). Alternatively, if a planarization process has been performed on the gate-side sacrificial layer 202 to form a process gate-side sacrificial layer 202', the process gate-side sacrificial layer 202' can be removed by the above-described process after the formation of the first dielectric layer 310. After removing the gate-side sacrificial layer 202 or the process gate-side sacrificial layer 202', a first isolation layer 203 can be formed at least on the inner wall of the first trench 201.

[0158] In other words, such as Figures 22-26 As shown, in some embodiments of this disclosure, a gate-side sacrificial layer 202 may be formed at least on the remaining sidewalls of the semiconductor body 100 before the initial second dielectric layer 302 is formed; and the gate-side sacrificial layer 202 may be removed after the first dielectric layer 310 is formed.

[0159] like Figures 26-27 As shown, an initial gate conductor layer 230' can be formed on the surface of the first isolation layer 203 by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0160] The initial gate conductor layer 230' can be used to form the gate conductor layer of the gate structure. Optionally, the material of the initial gate conductor layer 230' may include any suitable conductive material, such as metal materials including but not limited to tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al), or any suitable semiconductor material such as silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), and germanium (Ge).

[0161] like Figures 27-28 As shown, after the initial gate conductor layer 230' is formed, the first trench 201 (e.g., ) can be filled using an initial dielectric filling portion 400' through one or more thin film deposition processes. Figure 26 The remaining space (as shown) includes, but is not limited to, thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. An initial dielectric filling portion 400' can be used to form a dielectric filling portion in subsequent processes. The dielectric filling portion may include multiple filling portions, which may be formed separately in different steps during the formation of the dielectric filling portion. In this step, an initial first filling portion 401' for subsequent formation of a first filling portion of the dielectric filling portion can be formed.

[0162] Optionally, a low-k dielectric material is selected to form the initial first filling portion 401'. The low-k dielectric material may include at least one of fluorine-doped silicon oxide (SiOF), carbon-doped silicon oxide (SiOC), amorphous fluorinated carbon (aC:F), and hydrogen silsesquioxane (HSQ).

[0163] Furthermore, the initial dielectric filling portion 400' also covers the first dielectric layer 310, and since both are made of the same material, there is no obvious boundary between them.

[0164] like Figures 28-29 As shown, a planarization process, such as grinding and / or chemical mechanical polishing, can be performed on the initial medium filling portion 400' to remove part of the initial medium filling portion 400' to form the process medium filling portion 400" (which can also be understood as forming the first filling portion 401 of the process). The process medium filling portion 400" formed by the planarization process can have a relatively flat surface to facilitate the subsequent inversion of the intermediate body 112 including the process medium filling portion 400".

[0165] like Figures 29-30As shown, the intermediate 112 can be rotated 180°, with the z-direction opposite to the z-direction. Alternatively, the intermediate 112 can be inverted so that its bottom faces upwards. The intermediate 112 includes a substrate 111-1, with a plurality of semiconductor bodies 100 located on one side of the substrate 111-1 in the z-direction. After inverting the intermediate 112, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to at least remove a portion of the substrate 111-1, forming the intermediate 113. Optionally, the first isolation layer 203 can be an etching stop layer in the process of at least partially removing the substrate 111-1 described above.

[0166] like Figures 30-32 As shown, in some embodiments of this disclosure, forming an air gap 330 may include: removing a portion of the substrate 111-1 and a portion of the initial second dielectric layer 302 to expose the first end 3031 of the back gate sacrificial layer 303 away from the first dielectric layer 310; removing the back gate sacrificial layer 303 to form an air gap 330; and using a third dielectric layer 340 to close the air gap 330.

[0167] Specifically, such as Figures 30-31 As shown, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, etc., to remove part of the substrate 111-1 and part of the initial second dielectric layer 302, exposing the first end 3031 of the back gate sacrificial layer 303 and the first dielectric layer 310, wherein the back gate sacrificial layer 303 may have two ends opposite to each other along the z direction, such as the first end 3031 and the second end 3032, the first end 3031 being further away from the first dielectric layer 310 than the second end 3032.

[0168] In addition, during the process of removing part of the substrate 111-1 and part of the initial second dielectric layer 302, a portion of the first isolation layer 203 and a portion of the initial gate conductor layer 230' can also be removed to form the process first isolation layer 203' and the process gate conductor layer 230, respectively.

[0169] Subsequently, it can be formed by, for example, dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove the back gate sacrificial layer 303.

[0170] Furthermore, the end of the process second dielectric layer 302' formed after removing part of the initial second dielectric layer 302 is lower than the end of the process first isolation layer 203' in the z-direction.

[0171] like Figures 31-32 As shown, the back gate sacrificial layer 203 (e.g., ...) can be formed through one or more thin film deposition processes. Figure 30 The third dielectric layer 340 formed after the formation of the space (as shown) may be a thin film deposition process including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Furthermore, the third dielectric layer 340 may also cover the semiconductor body 100, the first process filling portion 401", the first process isolation layer 203', and the second process dielectric layer 302'.

[0172] The third dielectric layer 340 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. Alternatively, a low-k dielectric material may be used to fabricate the third dielectric layer 340, enabling the subsequently formed back gate structure including the third dielectric layer 340 to more effectively reduce parasitic capacitance effects between gate structures and improve the sensing tolerance of the semiconductor device. The low-k dielectric material may comprise at least one of fluorine-doped silicon oxide (SiOF), carbon-doped silicon oxide (SiOC), amorphous fluorinated carbon (aC:F), and hydrogen silsesquioxane (HSQ).

[0173] It should be noted that, during the process of forming the third dielectric layer 340, the dielectric material 403' covering the first filling portion 401" and the first isolation layer 203' can be used to form the third portion of the dielectric filling portion. In other words, to simplify the fabrication process of semiconductor devices, a portion of the back gate structure and a portion of the dielectric filling portion can be formed in the same step.

[0174] Furthermore, after the third dielectric layer 340 is formed, a planarization process, such as grinding and / or chemical mechanical polishing, can be performed to remove part of the third dielectric layer 340. After the planarization process, the third dielectric layer 340 can have a relatively flat surface, which facilitates the execution of subsequent processes.

[0175] like Figure 32 and Figure 33 As shown, the intermediate body on which the third dielectric layer 340 is formed can be flipped 180° to facilitate the formation of the gate structure, the remaining portion of the dielectric filling portion, and the remaining portion of the back gate structure.

[0176] Optionally, an etching process is performed on the inverted intermediate, formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove part of the first process filling portion 401” until the first process isolation layer 203' and the process gate conductor layer 230 are exposed.

[0177] Subsequently, the above process can be continued to remove part of the first filling portion 401", part of the first isolation layer 203' and part of the gate conductor layer 230" to form the first filling portion 401 of the dielectric filling portion, as well as the gate dielectric layer 210, the gate adhesive layer 220 and the gate conductor layer 230. The gate dielectric layer 210 and the gate adhesive layer 220 are formed by removing part of the first isolation layer 203' and can form the gate structure 200 of the semiconductor device with the gate conductor layer 230.

[0178] In this process, the first dielectric layer 310 and the second dielectric layer 302' can be exposed by removing part of the first filling portion 401". Then, the second dielectric layer 320 of the back gate structure can be formed by removing part of the second dielectric layer 302'.

[0179] Optionally, one end of the gate dielectric layer 210 along the z-direction is higher than one end of the second dielectric layer 320 along the z-direction, and the other end of the gate dielectric layer 210 along the z-direction is lower than the other end of the second dielectric layer 320 along the z-direction.

[0180] like Figure 33 and Figure 34 As shown, a dielectric material layer covering the gate structure 200, the first fill portion 401, the second dielectric layer 320, and the first dielectric layer 310 can be formed through one or more thin-film deposition processes. The thin-film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. A portion of the dielectric material layer covering the gate structure 200 and the first fill portion 401 is formed as the second fill portion 402 of the dielectric fill portion, and a portion of the dielectric material layer covering the second dielectric layer 320 and the first dielectric layer 310 is formed as the fourth dielectric layer 350 of the back gate structure. In other words, to simplify the semiconductor device fabrication process, a portion of the dielectric fill portion and a portion of the back gate structure can be formed in the same step.

[0181] It should be noted that if the filling portions of the back grid structure or the dielectric filling portions formed in the different steps are made of the same material, then there are no obvious boundaries between these filling portions made of the same material in the back grid structure or the dielectric filling portions made of the same material.

[0182] Therefore, in the semiconductor device provided in this disclosure, the gate structure includes a gate dielectric layer located on the sidewall of the semiconductor body, the dielectric filling portion is located at least on the side of the gate structure away from the semiconductor body, and the dielectric constant of the dielectric filling portion is lower than the dielectric constant of the gate dielectric layer. In other words, the material of the dielectric filling portion has a relatively low dielectric constant, which helps to reduce the parasitic capacitance effect between gate structures, reduce the electric field coupling effect between two adjacent transistors disposed in the xy plane intersecting the z-direction, improve the sensing tolerance of the semiconductor device, and improve the overall performance and yield of the semiconductor device.

[0183] Some embodiments of this disclosure also provide a memory system. Figure 35 This is a block diagram of a system with a memory system provided by way of example in this disclosure.

[0184] like Figure 35 As shown, system 3000 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 3100 located therein). Figure 35 As shown, system 3000 may include host 3200 and memory system 3100. Memory system 3100 may have one or more memories 3110 and controller 3120. The memories 3110 may include semiconductor structures as described in the embodiments above (e.g., Figure 4 The semiconductor device 1000 shown is illustrated. The host 3200 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 3200 may be configured to send or receive data to and from the memory 3110.

[0185] In some embodiments, controller 3120 may be coupled to memory 3110 and host 3200 and configured to control memory 3110. For example, controller 3120 may be configured to control memory 3110 to perform operations such as read, erase, and program. Controller 3120 may also manage data stored in memory 3110 and communicate with host 3200. For example, controller 3120 may communicate with external devices (e.g., host 3200) according to a specific communication protocol. Although exemplary fabrication methods and structures of semiconductor devices have been described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor device. Furthermore, the materials of the exemplified layers are merely exemplary.

[0186] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this disclosure.

Claims

1. A semiconductor device, comprising: The semiconductor body extends in the first direction; A gate structure is located on the sidewall of the semiconductor body extending in the first direction; The dielectric filling portion is located at least on the side of the gate structure opposite to the semiconductor body. The gate structure includes a gate dielectric layer located on the sidewall; as well as The dielectric constant of the dielectric filling portion is less than the dielectric constant of the gate dielectric layer.

2. The semiconductor device according to claim 1, wherein, The dielectric constant of the dielectric filling portion is less than or equal to 3.

3. The semiconductor device according to claim 1, wherein, The dielectric filling portion includes at least one of fluorine-doped silicon oxide, carbon-doped silicon oxide, amorphous fluorinated carbon, and silsesquioxane.

4. The semiconductor device according to claim 1, wherein, The dielectric filling portion includes multiple filling portions with different dielectric constants. The dielectric constant of each of the plurality of filling portions is less than or equal to 3.

5. The semiconductor device according to claim 4, wherein, The plurality of filling portions include: The first filling part; and The second filling portion is located on one side of the first filling portion in the first direction. Wherein, the first filling portion is located between the gate structures adjacent in the second direction, and the second direction intersects the first direction; and In the direction intersecting the first direction, the size of the first filling portion is smaller than the size of the second filling portion.

6. The semiconductor device according to claim 5, wherein, The plurality of filling portions also includes a third filling portion. Wherein, the first filling portion is located between the second filling portion and the third filling portion in the first direction; and In the direction intersecting the first direction, the size of the first filling portion is smaller than the size of the third filling portion.

7. The semiconductor device according to claim 5, wherein, The first filling portion includes: First subsection; and The second sub-section surrounds the first sub-section.

8. The semiconductor device according to claim 7, wherein, The semiconductor device further includes a bit line structure extending in the second direction and connected to the plurality of semiconductor bodies. The second sub-part includes an end portion and a side portion connected to the end portion, the end portion being close to the bit line structure; and The first sub-part is located on one side of the end in the first direction and is surrounded by the side portion.

9. The semiconductor device according to claim 1, wherein, The semiconductor device also includes a back gate structure. The back gate structure extends in a third direction intersecting the first direction and is connected to the sidewalls of the plurality of semiconductor bodies.

10. The semiconductor device according to claim 9, wherein, The back gate structure includes: First dielectric layer; and A second dielectric layer is located between the first dielectric layer and the sidewall of the semiconductor body. Wherein, the dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the second dielectric layer.

11. The semiconductor device according to claim 10, wherein, The dielectric constant of the first dielectric layer is less than or equal to 3.

12. The semiconductor device according to claim 10, wherein, The back gate structure also includes an air gap located on one side of the first dielectric layer in the first direction.

13. The semiconductor device according to claim 12, wherein, The semiconductor device further includes a bit line structure that extends in a second direction intersecting the first direction and is connected to a plurality of the semiconductor bodies. The air gap is located closer to the bit line structure than the first dielectric layer.

14. The semiconductor device according to claim 13, wherein, In the first direction, the size of the air gap is larger than the size of the first dielectric layer.

15. The semiconductor device according to claim 10, wherein, The back gate structure also includes: A third dielectric layer is located on the side of the first dielectric layer in the first direction; and The fourth dielectric layer is located on the opposite side of the first dielectric layer in the first direction. The dielectric constant of the third dielectric layer is different from that of the first dielectric layer, and the dielectric constant of the fourth dielectric layer is different from that of the first dielectric layer.

16. The semiconductor device according to claim 15, wherein, The semiconductor device further includes a bit line structure that extends in a second direction intersecting both the first direction and the third direction, and is connected to a plurality of semiconductor bodies. The back gate structure further includes an air gap located between the first dielectric layer and the third dielectric layer in the first direction; and The dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the third dielectric layer.

17. The semiconductor device according to claim 15, wherein, In the direction intersecting the first direction, the size of the first dielectric layer is smaller than the size of the third dielectric layer.

18. The semiconductor device according to claim 15, wherein, The dielectric constant of the third dielectric layer is different from that of the fourth dielectric layer.

19. The semiconductor device according to claim 15, wherein, In the direction intersecting the first direction, the size of the first dielectric layer is smaller than the size of the fourth dielectric layer.

20. The semiconductor device according to claim 15, wherein, The dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the fourth dielectric layer.

21. The semiconductor device according to claim 10, wherein, The dielectric constant of the first dielectric layer is equal to the dielectric constant of the dielectric filling portion.

22. A semiconductor device, comprising: A semiconductor body extends in a first direction and includes a sidewall extending in the first direction; as well as A back gate structure extends in a direction intersecting the first direction and is connected to the sidewalls of the plurality of semiconductor bodies. The back gate structure includes: First dielectric layer; and The second dielectric layer is located between the first dielectric layer and the sidewall. Wherein, the dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the second dielectric layer.

23. The semiconductor device according to claim 22, wherein, The dielectric constant of the first dielectric layer is less than or equal to 3.

24. The semiconductor device according to claim 22, wherein, The back gate structure also includes an air gap located on one side of the first dielectric layer in the first direction.

25. The semiconductor device according to claim 24, wherein, The semiconductor device further includes a bit line structure that extends in a second direction intersecting the first direction and is connected to a plurality of the semiconductor bodies. The air gap is located closer to the bit line structure than the first dielectric layer.

26. The semiconductor device according to claim 25, wherein, In the first direction, the size of the air gap is larger than the size of the first dielectric layer.

27. The semiconductor device according to claim 22, wherein, The back gate structure also includes: A third dielectric layer is located on the side of the first dielectric layer in the first direction; and The fourth dielectric layer is located on the opposite side of the first dielectric layer in the first direction. The dielectric constant of the third dielectric layer is different from that of the first dielectric layer, and the dielectric constant of the fourth dielectric layer is different from that of the first dielectric layer.

28. The semiconductor device according to claim 27, wherein, The semiconductor device further includes a bit line structure that extends in a second direction intersecting the first direction and is connected to a plurality of the semiconductor bodies. The back gate structure further includes an air gap located between the first dielectric layer and the third dielectric layer in the first direction; and The dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the third dielectric layer.

29. The semiconductor device according to claim 27, wherein, In the direction intersecting the first direction, the size of the first dielectric layer is smaller than the size of the third dielectric layer.

30. The semiconductor device according to claim 27, wherein, The dielectric constant of the third dielectric layer is different from that of the fourth dielectric layer.

31. The semiconductor device according to claim 27, wherein, In the direction intersecting the first direction, the size of the first dielectric layer is smaller than the size of the fourth dielectric layer.

32. The semiconductor device according to claim 27, wherein, The dielectric constant of the first dielectric layer is less than or equal to the dielectric constant of the fourth dielectric layer.

33. A method for fabricating a semiconductor device, comprising: A semiconductor body extending in the first direction is formed; A gate structure is formed on the sidewall of the semiconductor body extending in the first direction; A dielectric filling portion is formed at least on the side of the gate structure opposite to the semiconductor body. The gate structure includes a gate dielectric layer located on the sidewall; and The dielectric constant of the dielectric filling portion is less than the dielectric constant of the gate dielectric layer.

34. The method according to claim 33, wherein, The method further includes: A back gate structure is formed extending in a direction intersecting the first direction and connected to the sidewalls of the plurality of semiconductor bodies.

35. The method according to claim 34, wherein, A back gate structure comprising a plurality of semiconductor bodies located on one side of a substrate in the first direction, extending in a direction intersecting the first direction and connected to the sidewalls of the plurality of semiconductor bodies, includes: An initial second dielectric layer is formed on the sidewalls and the substrate between adjacent semiconductor bodies. A back gate sacrificial layer is formed on the surface of the initial second dielectric layer; and A first dielectric layer is formed on one side of the back gate sacrificial layer in the first direction. The back gate sacrificial layer has a predetermined size in the first direction.

36. The method according to claim 35, wherein, The back gate structure, which extends in a direction intersecting the first direction and is connected to the sidewalls of the plurality of semiconductor bodies, further includes: Remove a portion of the substrate and a portion of the initial second dielectric layer to expose the end of the back gate sacrificial layer away from the first dielectric layer; Remove the back gate sacrificial layer to form an air gap; and The air gap is sealed using a third dielectric layer.

37. The method of claim 35, wherein, The method further includes: Before forming the initial second dielectric layer, a gate-side sacrificial layer is formed at least on the remaining sidewalls of the semiconductor body; and After the first dielectric layer is formed, the gate-side sacrificial layer is removed.

38. A storage system comprising a controller and a semiconductor device as claimed in any one of claims 1-32, the controller being coupled to the semiconductor device and configured to control the semiconductor device to store data.

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