Semiconductor structure and manufacturing method thereof
By introducing a dielectric barrier layer into the semiconductor structure and forming an air gap thereon, the leakage current and parasitic capacitance problems caused by embedded word lines are solved, thereby improving the performance of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2024-11-26
- Publication Date
- 2026-04-21
AI Technical Summary
Existing technologies are insufficient to effectively prevent leakage current caused by embedded word lines and reduce parasitic capacitance between embedded word lines and other components.
A dielectric barrier layer is introduced into the substrate, and multiple air gaps are formed on it. The width of the dielectric barrier layer is larger than the width of the embedded word line structure, thereby reducing parasitic capacitance and preventing leakage current.
It effectively prevents leakage current and reduces parasitic capacitance, thereby improving the performance of the semiconductor structure.
Smart Images
Figure CN121908549A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure with an air gap and a method for manufacturing the same. Background Technology
[0002] Currently, some semiconductor devices (such as dynamic random access memory (DRAM) devices) have embedded word lines located in the substrate. However, preventing leakage current caused by embedded word lines and reducing parasitic capacitance between embedded word lines and other components remain ongoing goals. Summary of the Invention
[0003] This invention provides a semiconductor structure and its manufacturing method, which can effectively prevent leakage current and reduce parasitic capacitance.
[0004] This invention proposes a semiconductor structure including a substrate, a buried word line structure, and a dielectric barrier layer. The buried word line structure is located within the substrate. The buried word line structure includes buried word lines. The buried word lines are located within the substrate. The dielectric barrier layer is located in the substrate above the buried word line structure. The width of the dielectric barrier layer within the substrate is greater than the width of the buried word line structure. The dielectric barrier layer has multiple air gaps adjacent to the substrate.
[0005] This invention proposes a method for manufacturing a semiconductor structure, comprising the following steps: Providing a substrate. Forming a buried word line structure in the substrate. The buried word line structure includes buried word lines. The buried word lines are located in the substrate. Forming a dielectric barrier layer in the substrate above the buried word line structure. The width of the dielectric barrier layer in the substrate is greater than the width of the buried word line structure. The dielectric barrier layer has a plurality of air gaps adjacent to the substrate.
[0006] Based on the above, in the semiconductor structure and manufacturing method proposed in this invention, since the width of the dielectric barrier layer located in the substrate is greater than the width of the buried word line structure, leakage current (e.g., gate-induced drain leakage, GIDL) can be effectively prevented. Furthermore, since the dielectric barrier layer has multiple air gaps adjacent to the substrate, the parasitic capacitance between the buried word line structure and the subsequently formed doped regions (e.g., source and / or drain regions) in the substrate can be effectively reduced.
[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0008] Figures 1A to 1J This is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention;
[0009] Figures 2A to 2J This is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention.
[0010] Explanation of icon numbers:
[0011] 10,20: Semiconductor Structure
[0012] 100, 200: Substrate
[0013] 102: Mask layer
[0014] 104,202: Embedded character line structure
[0015] 106,204: Embedded letter lines
[0016] 108, 206: Gate dielectric layer
[0017] 110, 114, 208, 212: Conductive layer
[0018] 112,210: Barrier layer
[0019] 116: Top Cover Material Layer
[0020] 116a,214: Top cover layer
[0021] 118, 122a, 124, 218a, 220, 222: Dielectric layers
[0022] 120,216: Spacer material layer
[0023] 120a, 216a: Spacers
[0024] 122,218: Dielectric material layer
[0025] 126,224: Dielectric barrier layer
[0026] AR1, AR2: Air gap
[0027] OP1, OP2, OP3: Openings
[0028] P1: lower part
[0029] P2: upper part
[0030] W1~W8: Width Detailed Implementation
[0031] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity of explanation.
[0032] Figures 1A to 1J This is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention.
[0033] Please refer to Figure 1A A substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Next, an opening OP1 may be formed in the substrate 100. The opening OP1 may be formed by performing a self-aligned double patterning (SADP) process or a lithography etching process on the substrate 100. Then, an opening OP2 may be formed in the substrate 100 above the opening OP1, wherein the width W2 of the opening OP2 is greater than the width W1 of the opening OP1. The opening OP2 may be formed by performing a self-aligned double patterning process or a lithography etching process on the substrate 100. Furthermore, a mask layer 102 may be formed during the formation of openings OP1 and OP2. The material of the mask layer 102 is, for example, an oxide (e.g., silicon oxide).
[0034] Please refer to Figure 1B An embedded word line structure 104 can be formed in the opening OP1. Thus, the embedded word line structure 104 can be formed in the substrate 100. The embedded word line structure 104 includes embedded word lines 106 and a gate dielectric layer 108. The embedded word lines 106 are located in the substrate 100. The gate dielectric layer 108 is located between the embedded word lines 106 and the substrate 100. The material of the gate dielectric layer 108 is, for example, an oxide (e.g., silicon oxide). The method of forming the gate dielectric layer 108 may include thermal oxidation. The embedded word lines 106 may include a conductive layer 110, a barrier layer 112, and a conductive layer 114. The material of the conductive layer 110 is, for example, a metal such as tungsten. The barrier layer 112 is located between the conductive layer 110 and the gate dielectric layer 108. The material of the barrier layer 112 is, for example, titanium, titanium nitride, or a combination thereof. The conductive layer 114 is located on the conductive layer 110 and the barrier layer 112. The gate dielectric layer 108 may also be located between the conductive layer 114 and the substrate 100. The material of the conductive layer 114 is, for example, doped polysilicon.
[0035] Next, a capping material layer 116 can be formed in openings OP1 and OP2. The capping material layer 116 can also be formed on the mask layer 102. The material of the capping material layer 116 is, for example, a nitride (e.g., silicon nitride). The capping material layer 116 can be formed by, for example, chemical vapor deposition.
[0036] Please refer to Figure 1C A back-etch process can be performed on the top cover material layer 116 to form a top cover layer 116a in the opening OP1. The top cover layer 116a can be formed on the buried word line structure 104. The gate dielectric layer 108 can be located between the top cover layer 116a and the substrate 100. In the above-described back-etch process, a portion of the mask layer 102 and a portion of the gate dielectric layer 108 can be removed simultaneously. The above-described back-etch process is, for example, a dry etching process.
[0037] Please refer to Figure 1D A dielectric layer 118 can be conformally formed in the opening OP2. The dielectric layer 118 can also be formed on the mask layer 102. The material of the dielectric layer 118 is, for example, a nitride (e.g., silicon nitride). The method for forming the dielectric layer 118 is, for example, atomic layer deposition (ALD).
[0038] Please refer to Figure 1E A spacer material layer 120 can be conformally formed on the dielectric layer 118. The material of the spacer material layer 120 is, for example, an oxide (e.g., silicon oxide). The method for forming the spacer material layer 120 is, for example, atomic layer deposition.
[0039] Please refer to Figure 1F A back-etching process can be performed on the spacer material layer 120 to form a plurality of spacers 120a on the dielectric layer 118 on both sides of the embedded word line structure 104. The aforementioned back-etching process is, for example, a dry etching process.
[0040] Please refer to Figure 1G A dielectric material layer 122 may be conformally formed on the dielectric layer 118 and the plurality of spacers 120a. The material of the dielectric material layer 122 may be, for example, a nitride (e.g., silicon nitride). The dielectric material layer 122 may be formed by, for example, atomic layer deposition.
[0041] Please refer to Figure 1H The dielectric material layer 122 can be etched back to form multiple dielectric layers 122a and expose multiple spacers 120a. The etch-back process described above is, for example, a dry etching process.
[0042] Please refer to Figure 1I Multiple spacers 120a can be removed to form multiple air gaps AR1. The removal method for the multiple spacers 120a is, for example, wet etching.
[0043] Please refer to Figure 1J A dielectric layer 124 can be formed to seal the top of multiple air gaps AR1. The dielectric layer 124 can fill the opening OP2. The material of the dielectric layer 124 is, for example, a nitride (e.g., silicon nitride). The method for forming the dielectric layer 124 is, for example, chemical vapor deposition.
[0044] Using the above method, a dielectric barrier layer 126 can be formed in the substrate 100 above the buried word line structure 104. The dielectric barrier layer 126 can be formed on the capping layer 116a. The dielectric barrier layer 126 may include a dielectric layer 118, a plurality of dielectric layers 122a and a dielectric layer 124.
[0045] The following is through Figure 1J The semiconductor structure 10 of the above embodiment will be explained here. Furthermore, although the method for forming the semiconductor structure 10 is described using the above method as an example, the present invention is not limited thereto.
[0046] Please refer to Figure 1J The semiconductor structure 10 includes a substrate 100, a buried word line structure 104, and a dielectric barrier layer 126. In some embodiments, the semiconductor structure 10 can be used in a dynamic random access memory (DRAM) structure. The buried word line structure 104 is located in the substrate 100. The buried word line structure 104 includes buried word lines 106 and a gate dielectric layer 108. The buried word lines 106 are located in the substrate 100. The gate dielectric layer 108 is located between the buried word lines 106 and the substrate 100. The dielectric barrier layer 126 is located in the substrate 100 above the buried word line structure 104. The width W4 of the dielectric barrier layer 126 located in the substrate 100 is greater than the width W3 of the buried word line structure 104. The dielectric barrier layer 126 has a plurality of air gaps AR1 adjacent to the substrate 100. The plurality of air gaps AR1 may be located above both sides of the buried word line structure 104.
[0047] The dielectric barrier layer 126 may include a dielectric layer 118, a plurality of dielectric layers 122a, and a dielectric layer 124. Dielectric layer 118 is located between the plurality of air gaps AR1 and the substrate 100. The plurality of dielectric layers 122a are located on dielectric layer 118. The plurality of air gaps AR1 are located between dielectric layer 118 and the plurality of dielectric layers 122a. Dielectric layer 124 may seal the top of the plurality of air gaps AR1. Dielectric layer 124 may fill the plurality of air gaps AR1, but not completely fill the plurality of air gaps AR1. Dielectric layer 124 is located beside the plurality of dielectric layers 122a. The plurality of dielectric layers 122a are located between the plurality of air gaps AR1 and dielectric layer 124. Dielectric layer 124 is located on dielectric layer 118 and between the plurality of dielectric layers 122a. The materials of dielectric layer 118, the plurality of dielectric layers 122a, and dielectric layer 124 are, for example, nitrides (e.g., silicon nitride).
[0048] The semiconductor structure 10 may further include a capping layer 116a. The capping layer 116a is located between the buried word line structure 104 and the dielectric barrier layer 126. The gate dielectric layer 108 may also be located between the capping layer 116a and the substrate 100.
[0049] Furthermore, the remaining components in the semiconductor structure 10 can be described with reference to the above embodiments. Additionally, the details of each component in the semiconductor structure 10 (e.g., materials and formation methods) have been described in detail in the above embodiments and will not be repeated here.
[0050] As can be seen from the above embodiments, in the semiconductor structure 10 and its manufacturing method, since the width W4 of the dielectric barrier layer 126 located in the substrate 100 is greater than the width W3 of the buried word line structure 104, leakage current (e.g., gate-induced drain leakage current) can be effectively prevented. Furthermore, since the dielectric barrier layer 126 has multiple air gaps AR1 adjacent to the substrate 100, the parasitic capacitance between the buried word line structure 104 and the subsequently formed doped regions (e.g., source and / or drain regions) in the substrate 100 can be effectively reduced.
[0051] Figures 2A to 2J This is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention.
[0052] Please refer to Figure 2A A substrate 200 is provided. The substrate 200 may be a semiconductor substrate, such as a silicon substrate. Next, an opening OP3 may be formed in the substrate 200. The opening OP3 includes a lower portion P1 and an upper portion P2. The opening OP3 may be formed by performing a self-aligned dual patterning process or a photolithography etching process on the substrate 200.
[0053] Please refer to Figure 2B An embedded word line structure 202 can be formed in the lower part P1 of the opening OP3. Thus, the embedded word line structure 202 can be formed in the substrate 200. The embedded word line structure 202 includes embedded word lines 204 and a gate dielectric layer 206. The embedded word lines 204 are located in the substrate 200. The gate dielectric layer 206 is located between the embedded word lines 204 and the substrate 200. The material of the gate dielectric layer 206 is, for example, an oxide (e.g., silicon oxide). The method of forming the gate dielectric layer 206 may include thermal oxidation. The embedded word lines 204 may include a conductive layer 208, a barrier layer 210, and a conductive layer 212. The material of the conductive layer 208 is, for example, a metal such as tungsten. The barrier layer 210 is located between the conductive layer 208 and the gate dielectric layer 206. The material of the barrier layer 210 is, for example, titanium, titanium nitride, or a combination thereof. The conductive layer 212 is located on the conductive layer 208 and the barrier layer 210. The gate dielectric layer 206 may also be located between the conductive layer 212 and the substrate 200. The material of the conductive layer 212 is, for example, doped polysilicon.
[0054] Next, a capping layer 214 can be formed in the opening OP3. The material of the capping layer 214 is, for example, a nitride (e.g., silicon nitride). The method of forming the capping layer 214 may include the following steps. First, a capping material layer (not shown) is formed to fill the opening OP3. Then, the capping material layer located outside the opening OP3 is removed to form the capping layer 214.
[0055] Please refer to Figure 2C A back-etch process can be performed on the capping layer 214 to form the capping layer 214 in the lower part P1 of the opening OP3. The capping layer 214 can be formed on the buried word line structure 202. The gate dielectric layer 206 can be located between the capping layer 214 and the substrate 200. In the above-described back-etch process, a portion of the gate dielectric layer 206 can be removed simultaneously. The above-described back-etch process is, for example, a dry etching process.
[0056] Please refer to Figure 2D A spacer material layer 216 can be formed on the substrate 200 by thermal oxidation, such that the width W6 of the upper part P2 of the opening OP3 is greater than the width W5 of the lower part P1 of the opening OP3. The material of the spacer material layer 216 is, for example, an oxide (e.g., silicon oxide).
[0057] Please refer to Figure 2E A back-etching process can be performed on the spacer material layer 216 to form multiple spacers 216a. Thus, multiple spacers 216a can be formed on the sidewall of the upper part P2 of the opening OP3. The aforementioned back-etching process is, for example, a dry etching process.
[0058] Please refer to Figure 2F A dielectric material layer 218 may be formed on the substrate 100 and the plurality of spacers 216a and in the opening OP3. The material of the dielectric material layer 218 is, for example, a nitride (e.g., silicon nitride). The dielectric material layer 218 may be formed by, for example, chemical vapor deposition.
[0059] Please refer to Figure 2G A back-etching process can be performed on the dielectric material layer 218 to form a dielectric layer 218a, exposing multiple spacers 216a and the substrate 200. Thus, the dielectric layer 218a can be formed in the upper part P2 of the opening OP3. The dielectric layer 218a is located between the multiple spacers 216a. The aforementioned back-etching process is, for example, a dry etching process.
[0060] Please refer to Figure 2H Multiple spacers 216a can be removed to form multiple air gaps AR2. The removal method for the multiple spacers 216a is, for example, wet etching.
[0061] Please refer to Figure 2IMultiple dielectric layers 220 can be formed on the substrate 200 exposed by the upper part P2 of the opening OP3. The dielectric layers 220 can also be formed on the top surface of the substrate 200. Multiple air gaps AR2 are located between the dielectric layer 218a and the multiple dielectric layers 220. The multiple dielectric layers 220 can be formed by, for example, thermal oxidation. The material of the dielectric layers 220 is, for example, an oxide (e.g., silicon oxide).
[0062] Please refer to Figure 2J A dielectric layer 222 can be formed to seal the top of multiple air gaps AR2. The material of the dielectric layer 222 is, for example, a nitride (e.g., silicon nitride). The method for forming the dielectric layer 222 is, for example, chemical vapor deposition.
[0063] Using the above method, a dielectric barrier layer 224 can be formed in the substrate 200 above the buried word line structure 202. The dielectric barrier layer 224 can be formed on the capping layer 214. The dielectric barrier layer 224 may include a dielectric layer 218a, a plurality of dielectric layers 220 and dielectric layers 222.
[0064] The following is through Figure 2J The semiconductor structure 20 of the above embodiment will be explained here. Furthermore, although the method for forming the semiconductor structure 20 is described using the above method as an example, the present invention is not limited thereto.
[0065] Please refer to Figure 2J The semiconductor structure 20 includes a substrate 200, a buried word line structure 202, and a dielectric barrier layer 224. In some embodiments, the semiconductor structure 20 can be used in a dynamic random access memory (DRAM) structure. The buried word line structure 202 is located in the substrate 200. The buried word line structure 202 includes a buried word line 204 and a gate dielectric layer 206. The buried word line 204 is located in the substrate 200. The gate dielectric layer 206 is located between the buried word line 204 and the substrate 200. The dielectric barrier layer 224 is located in the substrate 200 above the buried word line structure 202. The width W8 of the dielectric barrier layer 224 located in the substrate 200 is greater than the width W7 of the buried word line structure 202. The dielectric barrier layer 224 has a plurality of air gaps AR2 adjacent to the substrate 200. The plurality of air gaps AR2 may be located above both sides of the buried word line structure 202.
[0066] The dielectric barrier layer 224 may include a dielectric layer 218a, a plurality of dielectric layers 220, and a dielectric layer 222. Dielectric layer 218a is located in the substrate 200. The plurality of dielectric layers 220 are located between the plurality of sidewalls of dielectric layer 218a and the substrate 200. A plurality of air gaps AR2 are located between dielectric layer 218a and the plurality of dielectric layers 220. The dielectric layer 222 may seal the tops of the plurality of air gaps AR2.
[0067] Dielectric layer 222 may fill multiple air gaps AR2, but dielectric layer 222 may not completely fill the multiple air gaps AR2. Dielectric layer 222 may be located on dielectric layer 218a and dielectric layer 220. The materials of dielectric layer 218a and dielectric layer 222 include nitrides (e.g., silicon nitride), and the materials of the multiple dielectric layers 220 include oxides (e.g., silicon oxide).
[0068] The semiconductor structure 20 may also include a capping layer 214. The capping layer 214 is located between the buried word line structure 202 and the dielectric barrier layer 224. The gate dielectric layer 206 may also be located between the capping layer 214 and the substrate 200.
[0069] Furthermore, the remaining components in the semiconductor structure 20 can be described with reference to the above embodiments. Additionally, the details of each component in the semiconductor structure 20 (e.g., materials and formation methods) have been described in detail in the above embodiments and will not be repeated here.
[0070] As can be seen from the above embodiments, in the semiconductor structure 20 and its manufacturing method, since the width W8 of the dielectric barrier layer 224 located in the substrate 200 is greater than the width W7 of the buried word line structure 202, leakage current (e.g., gate-induced drain leakage current) can be effectively prevented. Furthermore, since the dielectric barrier layer 224 has multiple air gaps AR2 adjacent to the substrate 200, the parasitic capacitance between the buried word line structure 202 and the subsequently formed doped regions (e.g., source and / or drain regions) in the substrate 200 can be effectively reduced.
[0071] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.
Claims
1. A semiconductor structure, comprising: Substrate; An embedded word line structure, located in the substrate, and comprising; Embedded word lines are located within the substrate; as well as A dielectric barrier layer is located in the substrate above the embedded word line structure, wherein The width of the dielectric barrier layer located in the substrate is greater than the width of the buried word line structure, and The dielectric barrier layer has a plurality of air gaps adjacent to the substrate.
2. The semiconductor structure according to claim 1, wherein the plurality of air gaps are located above both sides of the embedded word line structure.
3. The semiconductor structure according to claim 1, wherein the dielectric barrier layer comprises: A first dielectric layer is located between the plurality of air gaps and the substrate; A plurality of second dielectric layers are located on the first dielectric layer, wherein a plurality of air gaps are located between the first dielectric layer and the plurality of second dielectric layers; as well as A third dielectric layer seals the top of the plurality of air gaps.
4. The semiconductor structure according to claim 3, wherein the third dielectric layer fills the plurality of air gaps, and the third dielectric layer does not completely fill the plurality of air gaps.
5. The semiconductor structure of claim 3, wherein the third dielectric layer is located adjacent to the plurality of second dielectric layers, and the plurality of second dielectric layers are located between the plurality of air gaps and the third dielectric layer.
6. The semiconductor structure of claim 3, wherein the third dielectric layer is located on the first dielectric layer and between the plurality of second dielectric layers.
7. The semiconductor structure of claim 3, wherein the material of the first dielectric layer, the materials of the plurality of second dielectric layers, and the material of the third dielectric layer comprises a nitride.
8. The semiconductor structure according to claim 1, wherein the dielectric barrier layer comprises: A first dielectric layer is located in the substrate; A plurality of second dielectric layers are located between a plurality of sidewalls of the first dielectric layer and the substrate, wherein a plurality of air gaps are located between the first dielectric layer and the plurality of second dielectric layers; as well as A third dielectric layer seals the top of the plurality of air gaps.
9. The semiconductor structure of claim 8, wherein the material of the first dielectric layer and the material of the third dielectric layer comprises a nitride, and the material of the plurality of second dielectric layers comprises an oxide.
10. The semiconductor structure according to claim 1, further comprising: The top cover layer is located between the embedded word line structure and the dielectric barrier layer.
11. A method for manufacturing a semiconductor structure, comprising: Provide substrate; An embedded word line structure is formed in the substrate, wherein the embedded word line structure includes; Embedded word lines are located within the substrate; as well as A dielectric barrier layer is formed in the substrate above the embedded word line structure, wherein The width of the dielectric barrier layer located in the substrate is greater than the width of the buried word line structure, and The dielectric barrier layer has a plurality of air gaps adjacent to the substrate.
12. The method for manufacturing a semiconductor structure according to claim 11, wherein the method for forming the buried word line structure and the dielectric barrier layer comprises: A first opening is formed in the substrate; A second opening is formed in the substrate above the first opening, wherein the width of the second opening is greater than the width of the first opening; The embedded letter line structure is formed in the first opening; A first dielectric layer is conformally formed in the second opening; Multiple spacers are formed on the first dielectric layer on both sides of the embedded word line structure; A dielectric material layer is formed conformally on the first dielectric layer and the plurality of spacers; The dielectric material layer is etched back to form multiple second dielectric layers, exposing multiple spacers. Multiple spacers are removed to form multiple air gaps; as well as A third dielectric layer is formed to seal the top of the plurality of air gaps, wherein The dielectric barrier layer includes a first dielectric layer, a plurality of second dielectric layers, and the third dielectric layer.
13. The method for manufacturing a semiconductor structure according to claim 12, further comprising: A top cover layer is formed in the first opening, wherein the top cover layer is formed on the embedded letter line structure, and the dielectric barrier layer is formed on the top cover layer.
14. The method for manufacturing a semiconductor structure according to claim 11, wherein the method for forming the buried word line structure and the dielectric barrier layer comprises: An opening is formed in the substrate, wherein the opening includes a lower portion and an upper portion; The embedded letter line structure is formed in the lower part of the opening; A plurality of spacers are formed on the upper sidewall of the opening; A first dielectric layer is formed in the upper portion of the opening, wherein the first dielectric layer is located between the plurality of spacers; Multiple spacers are removed to form multiple air gaps; A plurality of second dielectric layers are formed on the substrate exposed by the upper portion of the opening, wherein a plurality of air gaps are located between the first dielectric layer and the plurality of second dielectric layers; A third dielectric layer is formed to seal the top of the plurality of air gaps, wherein The dielectric barrier layer includes a first dielectric layer, a plurality of second dielectric layers, and the third dielectric layer.
15. The method for manufacturing a semiconductor structure according to claim 14, wherein the method for forming the plurality of said spacers comprises: A spacer material layer is formed on the substrate by thermal oxidation, such that the width of the upper part of the opening is greater than the width of the lower part of the opening; as well as A back etching process is performed on the spacer material layer to form multiple spacers, wherein... Methods for forming multiple second dielectric layers include thermal oxidation.
16. The method for manufacturing a semiconductor structure according to claim 14, further comprising: A top cover layer is formed in the lower part of the opening, wherein the top cover layer is formed on the embedded letter line structure, and the dielectric barrier layer is formed on the top cover layer.