Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes; a memory cell region including memory cells; and a core / peripheral region including a capacitor. The capacitor includes a lower electrode and an upper electrode, a first potential level is applied to the lower electrode through the first metal pattern, and the lower electrode is formed on the core / peripheral region, a second potential level lower than the first potential level is applied to the upper electrode through the second metal pattern, and the upper electrode is formed over the lower electrode. The capacitor has a first reliability breakdown voltage when a voltage higher than a voltage applied to the upper electrode is applied to the lower electrode, and has a second reliability breakdown voltage lower than the first reliability breakdown voltage when a voltage lower than the voltage applied to the upper electrode is applied to the lower electrode.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0143320, filed on October 18, 2024, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to semiconductor memory devices. Background Technology

[0003] Due to their characteristics (such as small size, versatility, and / or low manufacturing cost), semiconductor devices have always been a key component in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that operate and process logic data, and hybrid semiconductor devices that include both memory elements and logic elements.

[0004] Recently, with the increasing speed and low power consumption of electronic devices, the semiconductor devices embedded in them also require fast operating speeds and / or low operating voltages. To meet these demands, highly integrated semiconductor devices are needed. However, with increasing integration, the reliability and electrical characteristics of semiconductor devices can decrease. Therefore, research is underway to improve the reliability and electrical characteristics of semiconductor devices. Summary of the Invention

[0005] Some aspects of this disclosure provide semiconductor memory devices with improved reliability and electrical characteristics.

[0006] In some embodiments, a semiconductor memory device includes: a memory cell region including memory cells; and a core / peripheral region including a capacitor. The capacitor includes a lower electrode and an upper electrode, a first potential level is applied to the lower electrode via a first metal pattern, and the lower electrode is formed on the core / peripheral region; a second potential level lower than the first potential level is applied to the upper electrode via a second metal pattern, and the upper electrode is formed above the lower electrode. When a voltage higher than the voltage applied to the upper electrode is applied to the lower electrode, the capacitor has a first reliability breakdown voltage, and when a voltage lower than the voltage applied to the upper electrode is applied to the lower electrode, the capacitor has a second reliability breakdown voltage, the second reliability breakdown voltage being lower than the first reliability breakdown voltage.

[0007] In some embodiments, a semiconductor memory device includes: a memory cell region including memory cells; and a core / peripheral region including a first capacitor and a second capacitor. The first capacitor includes a first lower electrode and a first upper electrode. A first potential level is applied to the first lower electrode via a first metal pattern, and the first lower electrode is formed on the core / peripheral region. A second potential level lower than the first potential level is applied to the first upper electrode via a second metal pattern, and the first upper electrode is formed above the first lower electrode. The second capacitor includes a second lower electrode and a second upper electrode. A first potential level is applied to the second lower electrode via a third metal pattern connected to the first metal pattern, and the second lower electrode is formed on the core / peripheral region. A second potential level is applied to the second upper electrode via a fourth metal pattern connected to the second metal pattern, and the second upper electrode is formed above the second lower electrode. When a voltage higher than the voltage applied to the first upper electrode is applied to the first lower electrode, the first capacitor has a first reliability breakdown voltage. When a voltage lower than the voltage applied to the first upper electrode is applied to the first lower electrode, the first capacitor has a second reliability breakdown voltage, the second reliability breakdown voltage being lower than the first reliability breakdown voltage. When a voltage higher than that applied to the second upper electrode is applied to the second lower electrode, the second capacitor has a third reliability breakdown voltage, and when a voltage lower than that applied to the second upper electrode is applied to the second lower electrode, the second capacitor has a fourth reliability breakdown voltage, which is lower than the third reliability breakdown voltage.

[0008] In some embodiments, a semiconductor memory device includes: a memory cell region including memory cells; and a core / peripheral region including a first capacitor cell and a second capacitor cell. The first capacitor cell includes a first capacitor and a second capacitor connected in parallel, and the second capacitor cell includes a third capacitor and a fourth capacitor connected in parallel. Each of the first to fourth capacitors includes a lower electrode and an upper electrode. A first potential level is applied to the lower electrode via first to fourth metal patterns connected to each other, and the lower electrode is formed on the core / peripheral region. A second potential level lower than the first potential level is applied to the upper electrode via fifth to eighth metal patterns connected to each other, and the upper electrode is formed above the lower electrode. Each of the first to fourth capacitors has a first reliability breakdown voltage when a voltage higher than the voltage applied to the upper electrode is applied to the lower electrode, and each of the first to fourth capacitors has a second reliability breakdown voltage lower than the first reliability breakdown voltage when a voltage lower than the voltage applied to the upper electrode is applied to the lower electrode. Attached Figure Description

[0009] The above and other objects and features of this disclosure will become clear from the detailed description of examples of this disclosure with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating an example of a memory system including memory devices.

[0011] Figure 2 This is a plan view of an example memory device.

[0012] Figure 3A It is a plan view showing a portion of the memory cell area.

[0013] Figure 3B It is along Figure 3A The sectional view taken by line T-T' in the middle.

[0014] Figure 4 This is a cross-sectional view of a memory device, wherein the cross-sectional view is along... Figure 2 The direction of the cross section intercepted by the line S-S' corresponds to that of the line S-S'.

[0015] Figure 5 It includes metal wiring. Figure 2 A cross-sectional view of a memory device, wherein the cross-sectional view is along... Figure 2 The line S-S' is intercepted.

[0016] Figure 6 It shows that it is aimed at Figure 4 Metal wiring and Figure 5 A graph illustrating the reliability assessment of metallic wiring.

[0017] Figure 7 It is along Figure 2 A sectional view taken by line S-S'.

[0018] Figure 8 This is a schematic diagram showing the wiring layer of two capacitors connected in series and the equivalent circuit of the capacitors.

[0019] Figure 9 This is a schematic diagram showing the wiring layer of two capacitors connected in parallel and the equivalent circuit of the capacitors.

[0020] Figure 10 This is a schematic diagram showing the wiring layer and the equivalent circuit of the capacitors that connect two capacitor units in series.

[0021] Figure 11 This is a schematic diagram showing the wiring layer and the equivalent circuit of the capacitors connecting two capacitor units in parallel.

[0022] Figure 12 This is a schematic diagram showing the wiring layer of four capacitors connected in series and the equivalent circuit of the capacitors.

[0023] Figure 13 This is a schematic diagram showing the wiring layer and the equivalent circuit of the capacitors, which are connected in series in two stages.

[0024] Figure 14 This is a schematic diagram showing the wiring layer and the corresponding equivalent circuit of multiple capacitors connected in series in three stages. Detailed Implementation

[0025] Figure 1 This is a block diagram illustrating a memory system 10 including a memory device 1000 according to some embodiments of the present disclosure. (Refer to...) Figure 1 The memory system 10 may include a memory controller 11 and a memory device 1000.

[0026] The memory controller 11 controls the overall operation of the memory system 10 and the overall data exchange between the external host device and the memory device 1000. For example, the memory controller 11 can generate a command CMD and an address ADDR in response to a request from the host device, and based on the command CMD and the address ADDR, the memory controller 11 can write data represented by the data signal DQ to or read data from the memory device 1000. For example, the memory controller 11 can provide a clock signal CLK for writing or reading data to the memory device 1000.

[0027] Memory device 1000 may include memory cell region 1100 and core / peripheral region 1200. Memory device 1000 may be a semiconductor memory device and may be a volatile memory device or a non-volatile memory device. For example, memory device 1000 may be a dynamic random access memory (DRAM) device, a synchronous DRAM (SDRAM) device, etc. In the following, memory device 1000 will be considered as a DRAM device. However, other types of memory devices are also within the scope of this disclosure.

[0028] Memory cell region 1100 may include a plurality of memory cells for storing data. For example, memory cell region 1100 may include a memory cell array in which the plurality of memory cells are arranged in a plurality of rows and columns. The memory cell array may include a plurality of memory cells. The plurality of memory cells may be connected to word lines and bit lines, respectively. In some embodiments, each of the plurality of memory cells may be a dynamic random access memory (DRAM) cell. However, the type of memory cells is not limited to this.

[0029] In some implementations, each of the plurality of memory cells may include a transistor and a capacitor. However, other numbers of transistors and / or capacitors are also within the scope of this disclosure.

[0030] The core / peripheral region 1200 may include peripheral circuitry associated with the memory cell array. For example, the core / peripheral region 1200 may include multiple circuits associated with memory cells for writing, reading, and managing data. References will follow below. Figure 2 Provide a more detailed description of them.

[0031] Figure 2 This is a plan view of a memory device according to some embodiments of the present disclosure. (Refer to...) Figure 2 The memory cell region 1100 and the core / peripheral region 1200 can be formed in conjunction with... Figure 1 On the substrate 100 corresponding to the memory device 1000.

[0032] The core / peripheral region 1200 may be formed near the memory cell region 1100. For example, the core / peripheral region 1200 may be formed side-by-side with the memory cell region 1100 on the same plane. The core / peripheral region 1200 may include elements that perform power (or electrical) pumping, voltage dividers, and decoupling.

[0033] The core / peripheral region 1200 may include decoupling capacitors and pump capacitors, with the decoupling capacitors used to perform decoupling operations and the pump capacitors used to perform power pumping operations.

[0034] In some embodiments, the decoupling capacitor structure and the pump capacitor structure can be formed in the same manner as the capacitors (e.g., DRAM cell capacitors) of the memory cells in the memory cell region 1100. Reference will be made below. Figures 3A to 3B and Figure 4 Provide a more detailed description of them.

[0035] Figure 3A This is a plan view showing a portion of a memory cell region according to some embodiments of the present disclosure. (Refer to...) Figure 3A , showed Figure 2 A plan view of a portion (memory cell region A) of memory cell region 1100. Figure 3B It is along Figure 3A The sectional view taken by line T-T' in the middle.

[0036] In this specification, the first direction D1 is defined as a direction parallel to the upper surface of the semiconductor substrate 100. The second direction D2 is defined as a direction parallel to the upper surface of the semiconductor substrate 100 and perpendicular to the first direction D1. The third direction D3 is defined as a direction perpendicular to the upper surface of the semiconductor substrate 100.

[0037] Reference Figure 3A and Figure 3BThe active pattern ACTc of the cell can be disposed on the memory cell region of the semiconductor substrate 100.

[0038] like Figure 3A As shown, when viewed in a plan view, the cell active patterns ACTc may be spaced apart from each other in a first direction D1 and a second direction D2. The cell active patterns ACTc may have a strip shape that is parallel to the upper surface of the semiconductor substrate 100 and extends in a diagonal direction intersecting the first direction D1 and the second direction D2.

[0039] like Figure 3B As shown, a device isolation layer 120 may be disposed on the memory cell region A between cell active patterns ACTc. The device isolation layer 120 may be disposed inside the semiconductor substrate 100 to define the cell active patterns ACTc.

[0040] Device isolation layer 120 may be disposed between memory cell region A and core / peripheral region. Device isolation layer 120 can separate memory cell region A and core / peripheral region from each other.

[0041] Word lines WL may intersect with the cell active pattern ACTc and the device isolation layer 120 on the memory cell region A. Word lines WL may be disposed in grooves formed on the cell active pattern ACTc and the device isolation layer 120. Word lines WL may extend in a second direction D2 and may be spaced apart from each other in a first direction D1. Word lines WL may be embedded in the semiconductor substrate 100. A cell gate insulating layer may be disposed between the word lines WL and the semiconductor substrate 100, and a word line cover pattern may be disposed on the word lines WL. The upper surface of the word line cover pattern may be coplanar with the upper surface of the semiconductor substrate 100. Impurity regions 110 may be included in the upper portion of the semiconductor substrate 100 on the word line WL side. Impurity regions 110 may correspond to source regions or drain regions.

[0042] An interlayer insulating layer 60 may be disposed on the upper surface of the semiconductor substrate 100. The lower surface of the interlayer insulating layer 60 may contact the upper surface of the device isolation layer 120 and the upper surface of the semiconductor substrate 100. The interlayer insulating layer 60 may include an insulating material. The insulating material may include at least one of, for example, silicon nitride and silicon oxide.

[0043] like Figure 3A and Figure 3BAs shown, bit lines BL intersecting word lines WL may be disposed on memory cell region A of semiconductor substrate 100. Bit lines BL may extend in a first direction D1 and may be spaced apart from each other in a second direction D2. An interlayer insulating layer 60 may surround bit line contact plugs DC, and bit lines BL may be spaced apart from semiconductor substrate 100, with the interlayer insulating layer 60 situated between bit lines BL and semiconductor substrate 100. The side surface of each of the bit lines BL may be covered by bit line spacers SP. The upper surface of the bit lines BL may be covered by bit line cover pattern 15. Bit line cover pattern 15 may include an insulating material (such as a silicon nitride layer). Impurity region 110 may be connected to lower electrode contact plug BC. Landing pads (or contact pads, mating pads, or landing pads) LP may be disposed on lower electrode contact plug BC. Landing pads LP may be insulated from each other by interlayer insulating layer 50. Interlayer insulating layer 50 may include an insulating material. The insulating material may include at least one of, for example, silicon nitride and silicon oxide. The lower electrode contact plug BC may include a pattern of polysilicon doped with impurities, and the bonding pad LP may include a barrier metal layer and a metal. The barrier metal layer may include, for example, a titanium / titanium nitride layer. The metal may include, for example, tungsten. The bit line spacer SP may extend in a first direction D1 on each of the bit lines BL. The bit line contact plug DC may be located between the bit line BL and the impurity region 110, and may electrically connect the bit line BL and the impurity region 110.

[0044] A first lower electrode BE1 may be disposed on a bonding pad LP and spaced apart from each other in a first direction D1 and / or a second direction D2. The first lower electrode BE1 may comprise at least one of doped polycrystalline silicon, a metal nitride (such as titanium nitride), and a metal layer (such as tungsten, aluminum, or copper). Each of the first lower electrodes BE1 may have a cylindrical shape, a hollow cylindrical shape, or a cup shape. A second support pattern SL2 may support the upper sidewall of the first lower electrode BE1, and the first support pattern SL1 may support the lower sidewall of the first lower electrode BE1. The first support pattern SL1 and the second support pattern SL2 may comprise an insulating material (such as silicon nitride, silicon oxide, or silicon oxynitride).

[0045] The first capacitor dielectric DL1 may cover the surface of the first lower electrode BE1, the surface of the first support pattern SL1, and the surface of the second support pattern SL2. The first capacitor dielectric DL1 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material. The first upper electrode UE1 may be disposed above the first capacitor dielectric DL1 and may fill the space between the first lower electrodes BE1. The first upper electrode UE1 may include at least one of a polycrystalline silicon layer doped with impurities, a metal nitride (such as titanium nitride), and a metal layer (such as tungsten, aluminum, or copper). The first lower electrode BE1, the first capacitor dielectric DL1, and the first upper electrode UE1 may constitute a first capacitor.

[0046] A plate 200 may be disposed on a first capacitor. The plate 200 may comprise SiGe or a metallic material. The first capacitor may be connected to a metallic pattern in the wiring layer of the plate 200 via a metal plug MP.

[0047] The outer side of plate 200 may include a molding layer MD. See below for further details. Figure 4 Provide a more detailed description of the molding layer (MD).

[0048] Figure 4 It is a cross-sectional view of a memory device including contrasting metal wiring, wherein the cross-sectional view is along... Figure 2 The direction of the cross section intercepted by line S-S' corresponds to that of the other line. (Refer to...) Figure 4 This shows a plan view of a portion of the core / peripheral area. Figure 4 In, with Figure 3A and Figure 3B Components shown in the figure that have the same reference numerals and symbols can be respectively compared with those of the components shown in the figure. Figure 3A and Figure 3B The components shown correspond to those in the diagram. For ease of description, references are omitted. Figure 3A and Figure 3B The given description is a duplicate.

[0049] An intermediate layer 300, including an interlayer insulating layer, a perimeter cover pattern, and impurity regions, may be formed on a substrate 100 in the core / peripheral region. A first pad (or solder pad) BP1 may be disposed on the intermediate layer 300. The perimeter cover pattern may cover the upper surface of the interlayer insulating layer of the intermediate layer 300. The perimeter cover pattern may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0050] A second capacitor CA2 may be disposed on the first pad BP1. The second capacitor CA2 may include a second upper electrode UE2, a second lower electrode BE2, and a second capacitor dielectric DL2. The second lower electrodes BE2 may be spaced apart from each other in a first direction D1 (e.g., and / or a second direction D2), and a portion of the lower end of the second lower electrode BE2 may be connected to the first pad BP1. The portion of the lower end of the second lower electrode BE2 may be configured to penetrate the first pad BP1. The second lower electrode BE2 may be made of the same material as the first lower electrode BE1. The second lower electrode BE2 may have a cylindrical or columnar shape. Although not shown, the first pad BP1 may be connected to the impurity region of the intermediate layer 300 (e.g., ...) through at least one contact element. Figure 3B The impurity region 110) is connected.

[0051] A third support pattern SL3 and a fourth support pattern SL4 may be provided, extending in a first direction D1 (e.g., and / or a second direction D2). The fourth support pattern SL4 may support the upper sidewall of the second lower electrode BE2, and the third support pattern SL3 may support the lower sidewall of the second lower electrode BE2.

[0052] The second capacitor dielectric DL2 may cover the surface of the second lower electrode BE2, as well as the surfaces of the third support pattern SL3 and the fourth support pattern SL4. The second capacitor dielectric DL2 may be made of the same material as the first capacitor dielectric DL1. The second upper electrode UE2 may be disposed on the second capacitor dielectric DL2 and may fill the space between the second lower electrodes BE2. The second upper electrode UE2 may be made of the same material as the first upper electrode UE1.

[0053] An interlayer insulating layer 30 may be disposed on the first pad BP1. The interlayer insulating layer 30 may include an insulating material. The insulating material may include at least one of, for example, silicon nitride and silicon oxide.

[0054] Plate 200 may be disposed on interlayer insulating layer 30. Plate 200 may have a shape that covers the second capacitor CA2, and the shape of plate 200 is not limited to the shape shown in the figures. Plate 200 may comprise SiGe or a metallic material.

[0055] A molding layer MD may be included between the interlayer insulating layer 30 and the wiring layer 40. The molding layer MD may include a silicon nitride layer. The molding layer MD may be included in a form that fills the upper surface of the interlayer insulating layer 30, the outer side of the board 200, the wiring layer 40, and the lower surface of the metal patterns UM and BM.

[0056] Wiring layer 40 may be disposed above the second capacitor CA2. Metal patterns may be included in or formed by wiring layer 40. The metal patterns may include an upper metal pattern UM and a lower metal pattern BM. The lower metal pattern BM may be connected to the second lower electrode BE2 via a first metal plug MP1 and a first pad BP1. The upper metal pattern UM may be connected to the second upper electrode UE2 via a second metal plug MP2 and a plate 200.

[0057] Depending on the reliability of the capacitors, they can have different connection relationships within multiple circuits in a memory device. For example, the number of capacitors in each circuit, the connection relationships between capacitors, and the connection relationships between capacitors and other components can vary to meet the circuit's required capacitance, critical leakage current, and lifespan.

[0058] For example, when a voltage greater than or equal to the reliability breakdown voltage of a capacitor is applied to it, the reliability of the capacitor may deteriorate. When the reliability of the capacitor deteriorates, leakage current exceeding the critical leakage current may occur, or the life of the capacitor may be reduced. As a result, the performance of the memory device may deteriorate. Therefore, circuits including capacitors (e.g., decoupling circuits (e.g., power supply decoupling circuits) and voltage pump circuits) can be designed such that voltages greater than the reliability breakdown voltage are not applied to the capacitor.

[0059] In some implementations, the reliability breakdown voltage may correspond to a critical voltage that causes a leakage current in the capacitor exceeding a critical leakage current. Optionally or additionally, the reliability breakdown voltage may correspond to the critical voltage at which the capacitor is damaged or destroyed before its reference lifetime. For example, the reliability breakdown voltage, critical leakage current, and reference lifetime may be values ​​determined in advance through experiments, machine learning, etc.

[0060] Capacitors can be classified as capacitors not connected in series with another capacitor (e.g., a 1-series capacitor) and capacitors connected in series with another capacitor (e.g., a 2-series capacitor or a 4-series capacitor).

[0061] Typically, the reliability breakdown voltage of a single-series capacitor is determined based on the fact that a first potential level applied to the lower metal pattern BM of the capacitor is lower than a second potential level applied to the upper metal pattern UM. Therefore, in the design of memory devices, when a voltage exceeding the reliability breakdown voltage is applied, reliability can be ensured by connecting capacitors in the form of two or four series capacitors.

[0062] According to some embodiments of this disclosure, a potential level higher than that applied to the upper metal pattern UM can be applied to the lower metal pattern BM to improve the reliability breakdown voltage of the capacitor. Furthermore, in two-series or four-series capacitors, by modifying the potential levels applied to the upper metal pattern UM or the lower metal pattern BM of each capacitor and the connection relationships between the capacitors, it is possible to reduce the number of capacitors while maintaining the same capacitance or increase the capacitance while maintaining the number of capacitors. In some embodiments, a metal pattern to which a lower potential level is applied (e.g., Figure 4 The lower metal pattern BM or Figure 5 The upper metal pattern (UM) in the middle can be referred to as the low-potential metal pattern (LPM), and the metal pattern to which a higher potential level is applied (e.g., Figure 4 The upper metal pattern UM or Figure 5 The lower metal pattern (BM) in the middle can be called the high potential metal pattern (HPM).

[0063] Figure 5 This is a cross-sectional view of a memory device including a metal wiring according to the present disclosure, where the cross-sectional view corresponds to the direction of a cross-section taken along line S-S' Figure 2 . Referring to Figure 2 , a plan view showing a part of the core / peripheral region is illustrated. In Figure 5 and Figure 5 and Figure 4 , components having the same reference numerals or symbols may correspond to each other. For ease of description, repeated descriptions identical to those given in reference to Figure 4 will be omitted.

[0064] Figure 5 The wiring layer 40 of Figure 4 includes an upper metal pattern UM and a lower metal pattern BM. Different from

[0065] , the potential level of the lower metal pattern BM may be higher than the potential level of the upper metal pattern UM. For example, the first potential level applied to the lower metal pattern BM may be higher than the second potential level applied to the upper metal pattern UM.

[0066] Thus, the lower metal pattern BM may be referred to as a high-potential metal pattern HPM, and the upper metal pattern UM may be referred to as a low-potential metal pattern LPM. Figure 5 In some embodiments, Figure 4 the metal wiring of

[0067] may be formed by swapping the upper metal pattern UM and the lower metal pattern BM of

[0068] However, the wiring and connection configuration is not limited to this, and in some embodiments, a separate wiring layer may be added (e.g., on substrate 100) such that the second lower electrode BE2 has a higher potential level than the second upper electrode UE2.

[0069] The reliability of the second capacitor CA2 can be improved when the second lower electrode BE2 has a higher potential level than the second upper electrode UE2, compared to when the second lower electrode BE2 has a lower potential level than the second upper electrode UE2. For example, in some embodiments, when the potential level applied to the lower electrode is higher than the potential level applied to the upper electrode, the capacitor may have a leakage current smaller than its critical leakage current.

[0070] For example, when the second lower electrode BE2 has a higher potential level than the second upper electrode UE2, the first reliability breakdown voltage of the second capacitor CA2 can be a first voltage (or a first potential difference). When the second lower electrode BE2 has a lower potential level than the second upper electrode UE2, the second reliability breakdown voltage of the second capacitor CA2 can be a second voltage (or a second potential difference) that is lower than the first voltage.

[0071] The following will refer to Figure 6 Provide a more detailed description of them.

[0072] Figure 6 It is used to show the target Figure 4 Metal wiring and Figure 5 A graph illustrating the reliability assessment of metallic wiring. Figure 6 This describes a situation where the upper electrode of a capacitor has a higher potential level than the lower electrode (e.g., Figure 4 The lifespan versus voltage (shown by dashed lines) of the capacitor is related to its reliability when the metal wiring is in use. Furthermore, Figure 6 This describes a situation where the lower electrode of a capacitor has a higher potential level than the upper electrode (e.g., Figure 5 The reliability-related lifespan of a capacitor to voltage (shown by solid lines) during the metal wiring process.

[0073] The horizontal axis of the graph represents voltage, and the vertical axis represents lifetime (where [au] represents any unit). In some implementations, the capacitor can be rapidly charged to a target voltage and discharged from the target voltage repeatedly, thereby allowing the lifetime to be evaluated according to the number of repetitions.

[0074] In some implementations, capacitors (e.g., Figure 5The capacitor dielectric of the second capacitor (CA2) can be a multilayer dielectric. The multilayer dielectric can include multiple dielectric layers. Each of the multiple dielectric layers can be parallel to the surface of the lower electrode, and the multiple dielectric layers can be stacked in a direction perpendicular to the surface of the lower electrode.

[0075] For example, the dielectric of a capacitor may include a first dielectric layer and a second dielectric layer. The first dielectric layer may be located between the lower electrode and the second dielectric layer, and the second dielectric layer may be located between the first dielectric layer and the upper electrode. The first and second dielectric layers may be formed of different materials.

[0076] Therefore, the electrical characteristics observed from the top electrode to the bottom electrode of a capacitor and the electrical characteristics observed from the bottom electrode to the top electrode can be asymmetrical. For example, lifetime, capacitance, or critical leakage current can vary depending on which of the bottom or top electrodes has a higher potential level.

[0077] However, capacitor construction is not limited to this, and even when the capacitor dielectric is a single dielectric, other factors (such as the treatment of the lower electrode, the type and amount of impurities included in the process of forming the upper electrode, and / or other reasons) can lead to asymmetry in capacitor characteristics, resulting in improved lifespan / reliability when a higher voltage is applied to the lower electrode.

[0078] Refer again Figure 6 The graph shows that the lifetime is longer when the lower electrode has a higher potential level than when the upper electrode has a higher potential level. In particular, the lifetime difference tends to increase as the charge / discharge test (experiment) voltage decreases from approximately 2.3V.

[0079] For example, the lifetime difference can increase by several thousand times or more in the range of approximately 1.1V to approximately 1.2V, which is the range of voltages that the memory device receives from the outside.

[0080] When compared to capacitors with applied metal wiring, capacitors with applied metal wiring according to some embodiments of the present disclosure may have improved reliability. Therefore, in some embodiments, a memory device comprising a capacitor having increased lifetime, reduced leakage current, and increased reliability breakdown voltage can be provided.

[0081] Therefore, in some implementations, a decoupling circuit including a capacitor with improved reliability can reduce the time required to stabilize the power supply voltage. Furthermore, a pump circuit including a capacitor with improved reliability can increase efficiency (e.g., reduce the number of capacitors required and reduce the area occupied).

[0082] Furthermore, in some implementations, as the reliability breakdown voltage increases, the number of capacitors required by the peripheral circuitry can be reduced, allowing for a smaller memory device size, or providing increased capacitance even with the same number of capacitors. References will follow. Figure 7 Provide a more detailed description of them.

[0083] Figure 7 It is along Figure 2 A sectional view taken along line S-S'. (Refer to...) Figure 7 The peripheral circuitry in the core / peripheral region includes multiple capacitors.

[0084] The peripheral circuit may include a second capacitor CA2 (e.g., with...) Figure 4 and Figure 5 The second capacitor CA2 corresponds to the third capacitor CA3. Similar to the second capacitor CA2, the third capacitor CA3 may be formed between the substrate 100 and the wiring layer 40. For ease of description, repeated descriptions will be omitted below.

[0085] The second capacitor CA2 and Figure 4 and Figure 5 The second capacitor CA2 corresponds to the first upper metal pattern UM1 and Figure 4 or Figure 5 The upper metal pattern UM corresponds to the lower metal pattern BM1. Figure 4 or Figure 5 The lower metal pattern BM1 corresponds to this.

[0086] The third capacitor CA3 may be spaced apart from the second capacitor CA2 in the first direction D1. Similar to the second capacitor CA2 disposed on the first pad BP1, the third capacitor CA3 may be disposed on the second pad BP2.

[0087] The third capacitor CA3 may include a third upper electrode UE3, a third lower electrode BE3, and a third capacitor dielectric DL3. The third lower electrodes BE3 may be spaced apart from each other in a first direction D1 (e.g., and / or a second direction D2). The lower end of the third lower electrode BE3 may have a shape that connects to the second pad BP2. A portion of the lower end of the third lower electrode BE3 may be configured to penetrate the second pad BP2. The third lower electrode BE3 may be formed of a conductive material. For example, the third lower electrode BE3 may be formed of polycrystalline silicon doped with impurities, or it may be formed of a metal-containing layer (such as a titanium nitride layer). The third lower electrode BE3 may have a pillar shape or a cylindrical shape.

[0088] A fifth support pattern SL5 and a sixth support pattern SL6 extending in a first direction D1 (e.g., and / or a second direction D2) may be disposed between the third lower electrode BE3. The fifth support pattern SL5 may support the upper sidewall of the third lower electrode BE3, and the sixth support pattern SL6 may support the lower sidewall of the third lower electrode BE3. For example, the fifth support pattern SL5 and the sixth support pattern SL6 may comprise materials such as silicon nitride, silicon oxide, or silicon oxynitride.

[0089] The third capacitor dielectric DL3 may cover the surface of the third lower electrode BE3 and the surfaces of the fifth support pattern SL5 and the sixth support pattern SL6. The third capacitor dielectric DL3 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material. The third upper electrode UE3 may be disposed on the third capacitor dielectric DL3 and may fill the space between the third lower electrodes BE3. The third upper electrode UE3 may include at least one of a polycrystalline silicon layer doped with impurities, a metal nitride (such as titanium nitride), and a metal layer (such as tungsten, aluminum, or copper).

[0090] Wiring layer 40 may be disposed above the third capacitor CA3. Metal patterns may be included in wiring layer 40. The metal patterns may include a second upper metal pattern UM2 and a second lower metal pattern BM2.

[0091] A third metal plug MP3 can be connected to the second pad BP2. The third metal plug MP3 may include a diffusion barrier pattern 342 and metal pillars 343 on the diffusion barrier pattern 342. The diffusion barrier pattern 342 may include, for example, a metal nitride (e.g., TiN, TSN, TaN, etc.). The metal pillars 343 may include a metallic material (e.g., tungsten, aluminum, etc.). The upper end of the third metal plug MP3 may be connected to a metal pattern included in the wiring layer 40. The third metal plug MP3 may be disposed on a third direction D3 perpendicular to the upper surface of the second pad BP2. A fourth metal plug MP4 can electrically connect the plate 200 on the third capacitor CA3 to the wiring layer 40.

[0092] Despite Figure 7 Only two capacitors, CA2 and CA3, are shown in the circuit, but the spirit and scope of this disclosure are not limited thereto, and the peripheral circuit may include three or more capacitors.

[0093] Figure 8 This is a schematic diagram showing the contrast wiring layer 40 and the equivalent circuit of the capacitors connected in series. (Refer to...) Figure 8The wiring layer 40 may include a first lower metal pattern BM1, a first upper metal pattern UM1, a second lower metal pattern BM2, a second upper metal pattern UM2, and a first connection pattern (or a first connection line) L1. The first lower metal pattern BM1, the first upper metal pattern UM1, the second lower metal pattern BM2, and the second upper metal pattern UM2 may respectively correspond to... Figure 7 The first lower metal pattern BM1, the first upper metal pattern UM1, the second lower metal pattern BM2, and the second upper metal pattern UM2.

[0094] When the lower electrode has a potential level higher than that of the upper electrode, the capacitor can have a first reliable breakdown voltage. When the lower electrode has a potential level lower than that of the upper electrode, the capacitor can have a second reliable breakdown voltage lower than the first reliable breakdown voltage.

[0095] In some implementations, the difference between the first potential level V1 and the second potential level V2 may be less than the first reliability breakdown voltage and greater than the second reliability breakdown voltage.

[0096] Therefore, when the potential level applied to the lower electrode is lower than the potential level applied to the upper electrode in at least one of the first capacitor C1 and the second capacitor C2, the reliability of the corresponding capacitor and the performance of the memory device may be degraded when the corresponding capacitor is directly connected between the first potential level V1 and the second potential level V2.

[0097] In this configuration, for example, a first potential level V1 (high potential) can be applied to the first lower metal pattern BM1. The first upper metal pattern UM1 and the second upper metal pattern UM2 can be electrically connected via a first connecting line L1. A second potential level V2 (low potential) can be applied to the second lower metal pattern BM2.

[0098] In other words, referring to the equivalent circuit, the first capacitor C1 and the second capacitor C2 can be connected to the first node N1 between the first potential level V1 and the second potential level V2, and therefore can be connected in series. For example, the first capacitor C1 can be connected between the first potential level V1 and the first node N1, and the second capacitor C2 can be connected between the first node N1 and the second potential level V2.

[0099] Figure 9 This is a schematic diagram illustrating the wiring layer and equivalent circuit of two capacitors connected in parallel according to some embodiments of the present disclosure. (Refer to...) Figure 9 The first lower metal pattern BM1, the first upper metal pattern UM1, the second lower metal pattern BM2, and the second upper metal pattern UM2 can respectively correspond to Figure 7The first lower metal pattern BM1, the first upper metal pattern UM1, the second lower metal pattern BM2, and the second upper metal pattern UM2.

[0100] Reference Figure 9 The following describes how capacitors are connected in the following way: Figure 8 The condition between the first potential level V1 and the second potential level V2 in the capacitor. When the lower electrode of the capacitor has a potential level higher than the potential level of the upper electrode of the capacitor, the capacitor can have a first reliable breakdown voltage. When the difference between the first potential level V1 and the second potential level V2 is greater than the second reliable breakdown voltage but less than the first reliable breakdown voltage, the reliability will not deteriorate even if two capacitors are connected in parallel between the first potential level V1 and the second potential level V2.

[0101] For example, a first potential level V1 (high potential) can be applied to a first lower metal pattern BM1 and a second lower metal pattern BM2, and a second potential level V2 (low potential) can be applied to a first upper metal pattern UM1 and a second upper metal pattern UM2.

[0102] In some embodiments, the first lower metal pattern BM1 and the second lower metal pattern BM2 may be connected, and the first upper metal pattern UM1 and the second upper metal pattern UM2 may be electrically connected.

[0103] In some implementations, the first lower metal pattern BM1 may be the same as the second lower metal pattern BM2. For example, the first lower metal pattern BM1 and the second lower metal pattern BM2 may be integral to each other, or they may be the same metal pattern.

[0104] In some implementations, the first upper metal pattern UM1 may be the same as the second upper metal pattern UM2. For example, the first upper metal pattern UM1 and the second upper metal pattern UM2 may be integral to each other, or they may be the same metal pattern.

[0105] Therefore, the two capacitors can be connected in parallel between the first potential level V1 and the second potential level V2. Therefore, in Figure 9 In, the number of capacitors and Figure 8 The number of capacitors in the two capacitors is the same, but the total capacitance can be increased. For example, when two capacitors have the same capacitance, Figure 9 The total capacitance of the equivalent circuit can be Figure 8 The total capacitance of the equivalent circuit is four times that of the equivalent circuit.

[0106] Alternatively, alternatives such as Figure 9 By connecting two capacitors in parallel, one capacitor with improved reliability can be connected between the first potential level V1 and the second potential level V2, and the area occupied by the capacitor can be reduced.

[0107] The following will describe in detail the case of including three or more capacitors as the capacitance required by the peripheral circuit gradually increases, the case of applying comparative metal wiring, and the case of applying metal wiring according to some embodiments of this disclosure. In the case of including three or more capacitors, the capacitors can be, as... Figure 7 They are spaced apart from each other in the first direction D1 (or the second direction D2). Figure 7 The second capacitor CA2 and the third capacitor CA3 are similar, and the capacitors can be formed between the substrate 100 and the wiring layer 40.

[0108] Figure 10 This is a schematic diagram illustrating the contrast wiring layer 40 and the equivalent circuit of the capacitors, showing two capacitor cells connected in series. A capacitor cell may include two or more capacitors connected in parallel. (Refer to...) Figure 10 The first capacitor unit CU1 comprises n capacitors connected in parallel, and the second capacitor unit CU2 comprises (mn) capacitors. Here, n is a natural number greater than or equal to 2, and m is a natural number greater than or equal to (n+2).

[0109] The first capacitor unit CU1 may include a first capacitor C1 to an nth capacitor Cn. The first capacitor C1 to the nth capacitor Cn may each include a first lower metal pattern BM1 to an nth lower metal pattern BMn, and may each include a first upper metal pattern UM1 to an nth upper metal pattern UMn.

[0110] The second capacitor unit CU2 may include the (n+1)th capacitor Cn+1 to the mth capacitor Cm. The (n+1)th capacitor Cn+1 to the mth capacitor Cm may each include the (n+1)th lower metal pattern BMn+1 to the mth lower metal pattern BMm, and may each include the (n+1)th upper metal pattern UMn+1 to the mth upper metal pattern UMm.

[0111] When contrast metal wiring is applied, due to the reliability breakdown voltage limitation of at least one of the first capacitors C1 to the m-th capacitor Cm, the first capacitor unit CU1 and the second capacitor unit CU2 can be connected in series as follows: Figure 8 Between the first potential level V1 and the second potential level V2 in the middle.

[0112] In some embodiments, when a potential level higher than that applied to the upper electrode is applied to the lower electrode, each of the first capacitor C1 to the m-th capacitor Cm may have a first reliable breakdown voltage. Conversely, when a potential level lower than that applied to the upper electrode is applied to the lower electrode, each of the first capacitor C1 to the m-th capacitor Cm may have a second reliable breakdown voltage, which is lower than the first reliable breakdown voltage. In this case, the difference between the first potential level V1 and the second potential level V2 may be greater than the second reliable breakdown voltage and less than the first reliable breakdown voltage.

[0113] For example, if a potential level lower than that applied to the upper electrode is applied to the lower electrode in at least one of the first capacitors C1 to the m-th capacitor Cm, the performance of the memory device may be degraded when the corresponding capacitor is directly connected between the first potential level V1 and the second potential level V2.

[0114] Therefore, refer to Figure 10 In the wiring layer 40, a first potential level V1 (high potential) is applied to the first lower metal pattern BM1 to the nth lower metal pattern BMn. A second potential level V2 (low potential) is applied to the (n+1)th lower metal pattern BMn+1 to the mth lower metal pattern BMm. The first upper metal pattern UM1 to the mth upper metal pattern UMm are connected to each other through a second connection line L2.

[0115] In other words, refer to Figure 10 In order to ensure the reliability of the capacitor, the first capacitor unit CU1 and the second capacitor unit CU2 can be connected in series between the first potential level V1 and the second potential level V2 through the second node N2 corresponding to the second connection line L2.

[0116] Figure 11 This is a schematic diagram showing the wiring layer 40 and the equivalent circuit of the capacitors, which are connected in parallel according to some embodiments of the present disclosure. Figure 11 The first capacitor unit CU1, the second capacitor unit CU2, the first upper metal pattern UM1 to the m-th upper metal pattern UMm, and the first lower metal pattern BM1 to the m-th lower metal pattern BMm can be connected with Figure 10 The components with the same reference number correspond to each other.

[0117] A first potential level V1 (high potential) can be applied to the first lower metal pattern BM1 to the m-th lower metal pattern BMm. A second potential level V2 (low potential) can be applied to the first upper metal pattern UM1 to the m-th upper metal pattern UMm.

[0118] Therefore, the lower electrode of each of the first capacitors C1 to the m-th capacitor Cm has a higher potential level than the upper electrode; therefore, the reliability breakdown voltage of each of the first capacitors C1 to the m-th capacitor Cm is the first reliability breakdown voltage. (Refer to the above...) Figure 10 As described, the first reliability breakdown voltage can be greater than the difference between the first potential level V1 and the second potential level V2. Therefore, the first capacitor C1 to the m-th capacitor Cm can be directly connected between the first potential level V1 and the second potential level V2. That is, the first capacitor C1 to the m-th capacitor Cm can be connected in parallel between the first potential level V1 and the second potential level V2.

[0119] In addition, due to Figure 11 The first capacitor C1 to the Mth capacitor Cm are all connected in parallel, therefore the total capacitance is comparable to that of the first capacitor C1. Figure 10 The total capacitance is large when the first capacitor unit CU1 and the second capacitor unit CU2 are connected in series.

[0120] Therefore, in some implementations, when the metal wiring is configured such that the lower electrode of the capacitor has a higher potential level than the upper electrode, the total capacitance within the same area can be increased, or the area occupied by the capacitor can be reduced while maintaining the same total capacitance.

[0121] Figure 12 This is a schematic diagram showing the contrast wiring layer 40 with four capacitors connected in series and the equivalent circuit of the capacitors. (Refer to...) Figure 12 The diagram shows a first capacitor C1 to a fourth capacitor C4 connected between a first potential level V1 and a second potential level V2.

[0122] The first capacitor C1 to the fourth capacitor C4 can be as follows: Figure 7 The capacitors are spaced apart from each other in the first direction D1 (or the second direction D2). The first capacitor C1 to the fourth capacitor C4 each include a first lower metal pattern BM1 to a fourth lower metal pattern BM4. The first capacitor C1 to the fourth capacitor C4 each include a first upper metal pattern UM1 to a fourth upper metal pattern UM4.

[0123] Due to the limitation of the reliability breakdown voltage of at least one of the first capacitors C1 to the fourth capacitor C4, the first capacitors C1 to the fourth capacitor C4 are connected in series between the first potential level V1 and the second potential level V2. For example, when the first capacitors C1 to the fourth capacitor C4 all have the same reliability breakdown voltage, the difference between the first potential level V1 and the second potential level V2 can be four times the corresponding reliability breakdown voltage.

[0124] For example, a first potential level V1 can be applied to a first lower metal pattern BM1. A first upper metal pattern UM1 and a second upper metal pattern UM2 can be electrically connected via a third connecting line L3. A second lower metal pattern BM2 and a third lower metal pattern BM3 can be electrically connected via a fourth connecting line L4. A third upper metal pattern UM3 and a fourth upper metal pattern UM4 can be electrically connected via a fifth connecting line L5.

[0125] Referring to the equivalent circuit, the third node N3 corresponding to the third connection line L3, the fourth node N4 corresponding to the fourth connection line L4, and the fifth node N5 corresponding to the fifth connection line L5 are shown between the first potential level V1 and the second potential level V2. A first capacitor C1 can be connected between the first potential level V1 and the third node N3. A second capacitor C2 can be connected between the third node N3 and the fourth node N4. A third capacitor C3 can be connected between the fourth node N4 and the fifth node N5. A fourth capacitor C4 can be connected between the fifth node N5 and the second potential level V2.

[0126] Figure 13 This is a schematic diagram illustrating a wiring layer 40 and the equivalent circuit of four capacitors connected in series in two stages according to some embodiments of the present disclosure. (Refer to...) Figure 13 By changing Figure 12 The metal wiring of the wiring layer 40 has four capacitors connected in series in two stages between the first potential level V1 and the second potential level V2.

[0127] For example, a first potential level V1 is applied to the first lower metal pattern BM1 and the second lower metal pattern BM2. The first upper metal pattern UM1 and the second upper metal pattern UM2 are electrically connected via a sixth connection line L6. The third lower metal pattern BM3 and the fourth lower metal pattern BM4 are electrically connected via an eighth connection line L8. The sixth connection line L6 and the eighth connection line L8 are electrically connected via a seventh connection line L7. However, the connections are not limited to this, and the circuit connection relationship of connecting the first capacitor C1 to the fourth capacitor C4 in series can be varied.

[0128] Since the lower electrode of each of the first capacitors C1 to the fourth capacitor C4 has a higher potential level than the upper electrode, the reliability of each capacitor can be ensured even if the first capacitors C1 to the fourth capacitor C4 are connected in series between the first potential level V1 and the second potential level V2.

[0129] For example, the first through fourth capacitors may have the same reliability breakdown voltage. In this case, the difference between the first potential level V1 and the second potential level V2 may be less than twice the corresponding reliability breakdown voltage.

[0130] Referring to the equivalent circuit, the sixth node N6 between the first potential level V1 and the second potential level V2 can correspond to the sixth connection line L6 to the eighth connection line L8. The first capacitor C1 and the second capacitor C2 can be connected in parallel between the first potential level V1 and the sixth node N6. The third capacitor C3 and the fourth capacitor C4 can be connected in parallel between the sixth node N6 and the second potential level V2.

[0131] Figure 14 This is a schematic diagram illustrating a wiring layer 40 and an equivalent circuit of multiple capacitors connected in series in three stages according to some embodiments of the present disclosure. (Refer to...) Figure 14 An example is shown where m capacitor units are connected in three-stage series between a first potential level V1 and a second potential level V2.

[0132] The first capacitor C1 to the nth capacitor Cn each include a first lower metal pattern BM1 to an nth lower metal pattern BMn, and each includes a first upper metal pattern UM1 to an nth upper metal pattern UMn. The (n+1)th capacitor Cn+1 to the kth capacitor Ck each include a (n+1)th lower metal pattern BMn+1 to a kth lower metal pattern BMk, and each includes a (n+1)th upper metal pattern UMn+1 to a kth upper metal pattern UMk. The (k+1)th capacitor Ck+1 to the mth capacitor Cm each include a (k+1)th lower metal pattern BMk+1 to a mth lower metal pattern BMm, and each includes a (k+1)th upper metal pattern UMk+1 to a mth upper metal pattern UMm.

[0133] A first potential level V1 (high potential) can be applied to the first lower metal pattern BM1 to the nth lower metal pattern BMn. The first upper metal pattern UM1 to the nth upper metal pattern UMn can be electrically connected via the ninth connection line L9. The (n+1)th lower metal pattern BMn+1 to the kth lower metal pattern BMk can be electrically connected via the eleventh connection line L11. The ninth connection line L9 and the eleventh connection line L11 can be electrically connected via the tenth connection line L10. The (n+1)th upper metal pattern UMn+1 to the kth upper metal pattern UMk can be electrically connected to each other via the twelfth connection line L12. The (k+1)th lower metal pattern BMk+1 to the mth lower metal pattern BMm can be electrically connected to each other via the fourteenth connection line L14. The twelfth connection line L12 and the fourteenth connection line L14 can be electrically connected via the thirteenth connection line L13. A second potential level V2 (low potential) can be applied to the (k+1)th upper metal pattern UMk+1 to the mth upper metal pattern UMm. Referring to the equivalent circuit, the seventh node N7 between the first potential level V1 and the second potential level V2 can correspond to the ninth connection line L9 to the eleventh connection line L11, and the eighth node N8 between the seventh node N7 and the second potential level V2 can correspond to the twelfth connection line L12 to the fourteenth connection line L14. The first capacitor C1 to the nth capacitor Cn can be connected in parallel between the first potential level V1 and the seventh node N7, the (n+1)th capacitor Cn+1 to the kth capacitor Ck can be connected in parallel between the seventh node N7 and the eighth node N8, and the (k+1)th capacitor Ck+1 to the mth capacitor Cm can be connected in parallel between the eighth node N8 and the second potential level V2.

[0134] The lower electrode of each of the first capacitor C1 to the m-th capacitor Cm may have a higher potential level than the upper electrode.

[0135] In some implementations, the first capacitor C1 through the m-th capacitor Cm may have the same first reliability breakdown voltage. For example, the reliability of the first capacitor C1 through the m-th capacitor Cm can be ensured when the difference between the first potential level V1 and the second potential level V2 is less than three times the first reliability breakdown voltage.

[0136] Conversely, when the lower electrode of at least one of the first capacitors C1 to the m-th capacitor Cm has a potential level lower than that of the upper electrode and a second reliability breakdown voltage lower than the first reliability breakdown voltage, in order to ensure the target reliability, the same m capacitors can be used as follows: Figure 12 The components are connected in series in four or more stages.

[0137] Therefore, in some embodiments, the reliability of the capacitors can be improved because the lower electrode of all capacitors has a higher potential level than the upper electrode. Thus, the total capacitance can be increased while maintaining the number of capacitors, or the number of capacitors can be reduced while maintaining the total capacitance, thereby reducing the area occupied by the capacitors.

[0138] Therefore, in some implementations, a semiconductor memory device with improved reliability and electrical characteristics can be provided.

[0139] In some implementations, in capacitors where the reliability varies depending on which of the lower and upper electrodes has a higher potential level, a potential level higher than that applied to the upper electrode is applied to the lower electrode. Therefore, capacitor reliability can be improved, the number of capacitors can be reduced while maintaining the capacitance of the memory device, or the capacitance can be increased while maintaining the number of capacitors.

[0140] While this disclosure contains numerous details of specific implementations, these details should not be construed as limiting the scope of the claims. Specific features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features from that combination may be removed from the combination, and the combination may involve sub-combinations or variations thereof.

[0141] Although this disclosure has been described with reference to various examples, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A semiconductor memory device, comprising: The memory cell region includes memory cells; as well as Core / peripheral area, including capacitors, Among them, capacitors include: The lower electrode is configured to receive a first potential level via a first metal pattern, wherein the lower electrode is located in the core / peripheral region; and The upper electrode is configured to receive a second potential level lower than the first potential level via a second metal pattern, wherein the upper electrode is above the lower electrode, and Among them, capacitors have: Based on the first reliability breakdown voltage applied to the lower electrode, the first voltage is higher than the voltage applied to the upper electrode; and Based on the second reliability breakdown voltage applied to the lower electrode, the second voltage is lower than the voltage applied to the upper electrode. The second reliability breakdown voltage is lower than the first reliability breakdown voltage.

2. The semiconductor memory device of claim 1, wherein, The capacitor has a leakage current smaller than the critical leakage current of the capacitor based on a second potential level applied to the upper electrode and a first potential level applied to the lower electrode.

3. The semiconductor memory device of claim 1, wherein, The difference between the first potential level and the second potential level is less than the first reliability breakdown voltage and greater than the second reliability breakdown voltage.

4. The semiconductor memory device of claim 1, wherein, A capacitor also includes: a capacitor dielectric, located between the lower and upper electrodes. The lower electrode has a cylindrical shape. In this capacitor, the dielectric covers the surface of the lower electrode, and The upper electrode covers the surface of the capacitor dielectric.

5. The semiconductor memory device of claim 1, wherein, A capacitor also includes: a capacitor dielectric, located between the lower and upper electrodes. The capacitor dielectric includes a first dielectric layer and a second dielectric layer made of different materials, and The first dielectric layer is disposed on the lower electrode, and the second dielectric layer is disposed between the first dielectric layer and the upper electrode.

6. The semiconductor memory device of claim 1, wherein, The capacitor is a decoupling capacitor.

7. The semiconductor memory device of claim 1, wherein, The capacitor is a pump capacitor.

8. The semiconductor memory device of claim 1, further comprising: A wiring layer, located above the upper electrode, includes the first metal pattern and the second metal pattern; A first pad and a first metal plug, the first pad being on the core / peripheral region, the first metal plug being connected to the first pad, wherein a first metal pattern is connected to the first metal plug, and wherein a lower electrode is configured to receive a first potential level through the first pad; and A plate and a second metal plug, the plate being on the upper electrode and the second metal plug being on the plate, wherein a second metal pattern is connected to the second metal plug, and wherein the upper electrode is configured to receive a second potential level through the plate.

9. The semiconductor memory device of claim 1, wherein, The memory cell includes a cell capacitor, and The capacitors in the core / peripheral region are the same as those in the unit capacitors.

10. The semiconductor memory device of claim 1, wherein, The semiconductor memory device is a dynamic random access memory device.

11. A semiconductor memory device, comprising: The memory cell region includes memory cells; as well as The core / peripheral region includes the first capacitor and the second capacitor. The first capacitor includes: A first lower electrode is configured to receive a first potential level via a first metal pattern, wherein the first lower electrode is located in the core / peripheral region; and The first upper electrode is configured to receive a second potential level lower than the first potential level via a second metal pattern, wherein the first upper electrode is above the first lower electrode. The second capacitor includes: The second lower electrode is configured to receive a first potential level via a third metal pattern connected to the first metal pattern, wherein the second lower electrode is located in the core / peripheral region; and The second upper electrode is configured to receive a second potential level via a fourth metal pattern connected to the second metal pattern, wherein the second upper electrode is above the second lower electrode. The first capacitor has the following characteristics: Based on a first reliability breakdown voltage applied to the first lower electrode, the first voltage is higher than the voltage applied to the first upper electrode; and Based on the second reliability breakdown voltage applied to the first lower electrode, the second voltage is lower than the voltage applied to the first upper electrode, wherein the second reliability breakdown voltage is lower than the first reliability breakdown voltage, and The second capacitor has the following characteristics: Based on the third reliability breakdown voltage applied to the second lower electrode, the third voltage is higher than the voltage applied to the second upper electrode; and The fourth reliability breakdown voltage is based on a fourth voltage applied to the second lower electrode, which is lower than the voltage applied to the second upper electrode, wherein the fourth reliability breakdown voltage is lower than the third reliability breakdown voltage.

12. The semiconductor memory device of claim 11, wherein, The first capacitor has a leakage current smaller than the critical leakage current of the first capacitor based on the second potential level applied to the first upper electrode and the first potential level applied to the first lower electrode.

13. The semiconductor memory device of claim 11, wherein, The first reliability breakdown voltage and the third reliability breakdown voltage are equal to each other. Among them, the second reliability breakdown voltage and the fourth reliability breakdown voltage are equal to each other, and The difference between the first potential level and the second potential level is greater than the second reliability breakdown voltage and less than the first reliability breakdown voltage.

14. The semiconductor memory device of claim 11, wherein, The first capacitor further includes: a first capacitor dielectric, located between the first lower electrode and the first upper electrode. The first lower electrode has a cylindrical shape. Wherein, the dielectric of the first capacitor covers the surface of the first lower electrode, and The first upper electrode covers the surface of the dielectric of the first capacitor.

15. The semiconductor memory device of claim 11, comprising: The power supply decoupling circuit includes the first capacitor and the second capacitor.

16. The semiconductor memory device of claim 11, comprising: The pump circuit includes the first capacitor and the second capacitor.

17. The semiconductor memory device of claim 11, wherein, The memory cell includes a cell capacitor, and The first capacitor and the second capacitor are the same as the unit capacitor.

18. The semiconductor memory device of claim 17, wherein, The semiconductor memory device is a dynamic random access memory device.

19. The semiconductor memory device of claim 11, wherein: The first metal pattern is the same as the third metal pattern; The second metal pattern is the same as the fourth metal pattern; or The first metal pattern is the same as the third metal pattern, and the second metal pattern is the same as the fourth metal pattern.

20. A semiconductor memory device, comprising: The memory cell region includes memory cells; as well as The core / peripheral region includes the first capacitor unit and the second capacitor unit. The first capacitor unit includes a first capacitor and a second capacitor connected in parallel. The second capacitor unit includes a third capacitor and a fourth capacitor connected in parallel. Each of the first to fourth capacitors includes: The lower electrode is configured to receive a first potential level via at least one of a first to a fourth metal pattern connected to each other, wherein the lower electrode is located in the core / peripheral region; and The upper electrode is configured to receive a second potential level lower than the first potential level via at least one of the fifth to eighth metal patterns connected to each other, wherein the upper electrode is above the lower electrode, and Each of the first to fourth capacitors has: Based on the first reliability breakdown voltage applied to the lower electrode, the first voltage is higher than the voltage applied to the upper electrode; and Based on the second reliability breakdown voltage applied to the lower electrode, the second voltage is lower than the voltage applied to the upper electrode. The second reliability breakdown voltage is lower than the first reliability breakdown voltage.

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