Method for patterning and memory structure

Abstract

The present disclosure describes a patterning process for a stripe region in a memory cell for removing material between polysilicon lines. The patterning process includes: depositing a first hard mask layer in a skin layer formed on the top of a polycrystalline silicon layer interposed between a first polycrystalline silicon gate structure and a second polycrystalline silicon gate structure; a second hard mask layer is deposited on the first hard mask layer. The patterning process further includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the skin layer; performing a second etch to remove the first hard mask layer from the skin layer; and executing third etching to remove the polycrystalline silicon layer which is not covered by the first hard mask layer and the second hard mask layer so as to form a gap between the first polycrystalline silicon gate structure and the second polycrystalline silicon gate structure. The embodiment of the invention also relates to a method for patterning and a memory structure.

Description

[0001] Divisional application

[0002] This application is a divisional application of patent application No. 202110501268.3, filed on May 8, 2021, entitled "Method for Patterning and Memory Structure". Technical Field

[0003] Embodiments of the present invention relate to methods for patterning and memory structures. Background Technology

[0004] Non-volatile memory devices (such as flash memory) are widely used in various electronic devices or instruments (e.g., computers, mobile phones, tablets, digital cameras, scientific instruments, etc.) to store data and / or programming instructions, which can be subsequently read, erased, programmed, and retained when power is off. Therefore, non-volatile memory (NVM) cells are important components of modern chips. Summary of the Invention

[0005] According to one aspect of the present invention, a method for patterning is provided, comprising: forming a first polysilicon line having a first width and a second polysilicon line having a second width on a substrate, wherein the first polysilicon line and the second polysilicon line are spaced apart by a polysilicon layer, and each of the first polysilicon line and the second polysilicon line includes a contact region wider than the first width and the second width; depositing a mask layer on the first polysilicon line, the contact region of the second polysilicon line, and the polysilicon layer; etching the mask layer from the polysilicon layer using a dry etching process to remove a portion of the mask layer and expose a first portion of the polysilicon layer; etching an unremoved portion of the mask layer from the polysilicon layer using a wet etching process to expose a second portion of the polysilicon layer larger than the first portion, wherein the second portion is narrower than the polysilicon layer inserted between the contact region of the second polysilicon line and the first polysilicon line; and removing the exposed second portion of the polysilicon layer to form a gap between the contact region of the second polysilicon line and the first polysilicon line.

[0006] According to another aspect of the present invention, a method for patterning is provided, comprising: depositing a first hard mask layer in a skin layer formed on top of a polysilicon layer inserted between a first polysilicon gate structure and a second polysilicon gate structure; depositing a second hard mask layer on the first hard mask layer, wherein the first hard mask layer and the second hard mask layer cover the sidewalls and bottom surface of the skin layer; performing a first etching to remove the second hard mask layer and portions of the first hard mask layer from the first sidewalls of the skin layer; performing a second etching to remove the second hard mask layer from the first sidewalls and the bottom surface of the skin layer; and performing a third etching to remove a polysilicon layer not covered by the first hard mask layer and the second hard mask layer to form a gap between the first polysilicon gate structure and the second polysilicon structure.

[0007] According to another aspect of the present invention, a memory structure is provided, comprising: a substrate; a first polysilicon line and a second polysilicon line disposed parallel to each other on the substrate, each of the first polysilicon line and the second polysilicon line including a contact region and a non-contact region, wherein each contact region is wider than each non-contact region, and wherein the contact region of the first polysilicon line is offset relative to the contact region of the second polysilicon line; a polysilicon layer disposed on a sidewall of the non-contact region of the first polysilicon line and opposite to the contact region of the second polysilicon line; a space between the polysilicon layer and the contact region of the second polysilicon line; and a contact member disposed on the contact region of the second polysilicon line. Attached Figure Description

[0008] Various aspects of this disclosure can be best understood in conjunction with the accompanying drawings, based on the following detailed description.

[0009] Figure 1A and Figure 1B This is a top view of polysilicon lines in the strip region of a memory cell, according to some embodiments.

[0010] Figure 2A This is a cross-sectional view of a polysilicon line in the strip region of a memory cell, according to some embodiments.

[0011] Figure 2B This is a cross-sectional view of a polysilicon line in a memory cell region outside the strip region, according to some embodiments.

[0012] Figure 2C This is a cross-sectional view of a polysilicon line in the strip region of a memory cell, according to some embodiments.

[0013] Figure 3 This is a flowchart of a patterning method for removing polysilicon material from strip regions of memory cells, according to some embodiments.

[0014] Figure 4 This is a cross-sectional view of an intermediate structure during a patterning method for removing polysilicon material in a strip region of a memory cell, according to some embodiments.

[0015] Figure 5A , Figure 5B and Figure 5C This is a cross-sectional view of an intermediate structure during a patterning method for removing polysilicon material in a strip region of a memory cell, in a memory cell region outside the strip region, and in a region outside the memory cell, according to some embodiments.

[0016] Figure 6A and Figure 6BIt is a cross-sectional view of an intermediate structure used in a patterning method for removing polysilicon material in the striped region of a memory cell and in the memory cell region outside the striped region, respectively.

[0017] Figure 7A and Figure 7B It is a cross-sectional view of an intermediate structure used in a patterning method for removing polysilicon material in the striped region of a memory cell and in the memory cell region outside the striped region, respectively.

[0018] Figure 8A , Figure 8B and Figure 8C This is a cross-sectional view of an intermediate structure during a patterning method for removing polysilicon material in a strip region of a memory cell, in a memory cell region outside the strip region, and in a region outside the memory cell, according to some embodiments.

[0019] Figure 9A , Figure 9B and Figure 9C This is a cross-sectional view of an intermediate structure during a patterning method for removing polysilicon material in a strip region of a memory cell, in a memory cell region outside the strip region, and in a region outside the memory cell, according to some embodiments.

[0020] Figure 10A This is a cross-sectional view of a contact formed on a strip region of a memory cell according to some embodiments.

[0021] Figure 10B This is a cross-sectional view of a contact formed in a memory cell region outside the strip region according to some embodiments. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is provided between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition, in itself, does not indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" are used herein to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. In addition to the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0024] As used herein, the term "nominal" refers to the expected or target value of a feature or parameter for the operation of a component or process, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​can be attributed to minor variations in manufacturing processes and / or tolerances.

[0025] In some embodiments, the terms "approximately" and "substantially" may refer to a given quantity of value that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. The terms "approximately" and "substantially" may refer to a percentage of a value as interpreted by one skilled in the art in light of the teachings herein.

[0026] Flash memory is a type of non-volatile memory that stores information in an array of memory cells made of floating-gate transistors. Each memory cell is similar to a metal-oxide-semiconductor field-effect transistor (MOSFET), except that the transistor has two gates instead of one. The memory cell acts as an electrical switch, where current flows between two terminals (e.g., source and drain), and the memory cell is controlled by a floating gate (FG) and a control gate (CG) made of polysilicon. The CG is similar to the gate in other MOS transistors, but beneath it, the FG is completely insulated by an oxide layer. The FG is inserted between the CG and the MOSFET channel. Because the FG is electrically isolated through its insulating layer, it traps electrons placed on it. When electrons are charged in the FG, this charge shields the electric field of the CG, thus increasing the threshold voltage (VT1) of the memory cell. If there is charge in the FG, a higher voltage (VT2) must be applied to the CG to make the channel conductive. To read a value from the transistor, an intermediate voltage between the threshold voltages (VT1 and VT2) is applied to the CG. If the channel is conductive at the intermediate voltage, FG is considered uncharged because if it were charged, no current would flow in the channel between the source and drain terminals. In this case, a logic "1" can be interpreted based on this state of FG. If the channel is not conductive at the intermediate voltage, this indicates that FG is charged; here, a logic "0" can be interpreted based on this state of FG. When an intermediate voltage is applied to CG, the presence of charge on FG is "sensed" by determining whether current flows through the transistor. In multi-level cell devices where each cell stores more than one bit, the amount of current can be sensed (as opposed to simply determining whether current is present or absent) to more accurately determine the charge level on FG.

[0027] Within the flash memory cell region, transistor gates are formed as densely packed lines called polysilicon lines. These polysilicon lines are parallel to each other and spaced apart. A voltage is applied to the CG portion of the polysilicon line by contacts formed on areas of the CG polysilicon lines that act as contact bonding pads. These contact bonding pads are wider than the rest of the polysilicon line to facilitate contact formation, and these contact bonding pads are referred to as "contact regions" or "strip regions." According to some embodiments, the spacing is narrowest at the strip location between two adjacent polysilicon lines.

[0028] With each generation of (node) technology, the spacing between adjacent polysilicon lines decreases, increasing memory cell density and storage capacity. Consequently, the region between adjacent polysilicon lines becomes increasingly challenging in terms of patterning—for example, selectively removing any deposited material (e.g., polysilicon). This is crucial for the strip regions with the narrowest polysilicon line spacing between adjacent lines. Residue left between tightly packed polysilicon lines can cause "bridging," leading to electrical short circuits.

[0029] To address the aforementioned drawbacks, this disclosure relates to a patterning process that removes excess material between polysilicon lines near the memory cell stripe region and reduces (or eliminates) residues left by the removal process. In some embodiments, the reduction (or elimination) of residues is achieved through photolithography and etching processes, which facilitate the removal of excess material between closely spaced adjacent polysilicon lines.

[0030] Figure 1A This is a partial top view of a memory cell (e.g., a flash memory cell) 100A, wherein polysilicon lines 110 are formed parallel to each other at a nominal pitch d. The polysilicon lines 110 are characterized by wider portions (e.g., strip regions or contact regions 120) to facilitate formation. Figure 1A The contact element is not shown. In some embodiments, the spacing between adjacent polysilicon lines near the contact region 120 decreases from d to d'. In some embodiments, d' is the minimum spacing between two adjacent polysilicon lines 110. Figure 1A As shown, the contact region 120 is intentionally offset in the y-direction to allow for a closer spacing d between adjacent polysilicon lines 110. Furthermore, this design allows the formed contacts to be sufficiently separated to avoid bridging between them. The layout of the memory cell 100 is not limited to... Figure 1A The description is provided, and alternative layouts are possible. For example, such as Figure 1B As shown, for memory cells 100B and 100C, the contact region 120 from the adjacent polysilicon line 110 can be formed without offset in the y direction. Figure 1B The layouts shown are within the spirit and scope of this disclosure, and the embodiments described herein are equally applicable to layouts 100A, 100B, and 100C or variations thereof.

[0031] Each polysilicon line 110 represents a gate stack structure shared among a plurality of transistors formed within a flash memory cell. Furthermore, each polysilicon line 110 includes... Figure 1A and Figure 1B The CG and FG structures are not shown in the diagram. Both the CG and FG structures are made of polycrystalline silicon and are positioned parallel to each other. Figure 1Aand Figure 1B As shown, the polycrystalline silicon line extends longitudinally along the y-direction. For simplicity, in Figure 1A and Figure 1B Only selective elements of memory cells 100A-C are shown, and other elements, features, or layers are not shown. These other layers include, but are not limited to, isolation regions, capping layers, spacers, additional polysilicon features (e.g., erase gates), doped regions, dielectric layers, contacts, etc. These other elements, features, or layers are within the spirit and scope of this disclosure.

[0032] In some embodiments, depending on the cell layout, the spacing d ranges from approximately 400 nm to 500 nm, while the spacing d' ranges from approximately 200 nm to approximately 300 nm. The foregoing ranges are not limiting, and other values ​​or ranges of spacing d and d' are possible. These other values ​​or ranges are within the spirit and scope of this disclosure. In some embodiments, spacing d and d' are governed by design rules set for a particular technology node. References Figure 1A The contact region 120 of the polysilicon line 110 is offset by a distance L in the y-direction, which is greater than the pitch d'. As an example and not a limitation, the distance L can be approximately 600 nm. Gate contacts are formed on the polysilicon line 110 within the designated contact region 120. Each gate contact allows for the simultaneous control of multiple transistor gates. In other words, several gate structures can be "bundled" together and controlled with the same signal. The contact region 120 may also be referred to as a "strip" or "strip location." In some embodiments, the contacts formed in the contact region 120, for example, provide word line electrical signals to the CG of the transistor.

[0033] As an example, not a limitation. Figure 2A This is a cross-sectional view of two adjacent polysilicon line / gate structures 110A and 110B. In some embodiments, Figure 2A It is cut along the dicing line AB before the CG contact is formed on the gate structure 110B. Figure 1A Cross-sectional view. As mentioned above regarding... Figure 1A and Figure 1B In the area under discussion, near contact region 120, one of the polysilicon line / gate structures is wider than the other. Figure 2A In the example, gate structure 110B is wider than gate structure 110A because Figure 2A This is a cross-sectional view taken along the contact region 120 of gate structure 110B. Each gate structure includes a CG and one or more FGs isolated by a dielectric layer 210. Furthermore, each CG in gate structures 110A and 110B is isolated by a nitride layer 220. By way of example and not limitation, the nitride layer 220 may comprise silicon nitride, and the dielectric layer 210 may comprise silicon oxide. In some embodiments, such as Figure 2AAs shown, gate structures 110A and 110B are formed on semiconductor substrate 230. In other embodiments, gate structures 110A and 110B are formed on isolation regions such as shallow trench isolation regions. In some embodiments, gate structures formed in regions outside contact region 120 (e.g., outside strip regions and within memory cells) may appear different from gate structures 110A or 110B. For example, for gate structures 110C and 110D, such as Figure 2B As shown, such a gate structure can be characterized by a single FG that extends along the entire width of the CG in the X direction.

[0034] refer to Figure 2A Gate structures 110A and 110B are separated by a polysilicon layer 200 that laterally fills the space between the “inner” sidewall surfaces of gate structures 110A and 110B. Due to the spacing d’ between gate structures 110A and 110B, the polysilicon layer 200 is characterized by a skin layer 240, the width w of which is between approximately 30 nm and approximately 50 nm, and the height h of which is between approximately 50 nm and approximately 70 nm. In some embodiments, the aspect ratio of the skin layer 240 depends on the spacing d’ between gate structures 110A and 110B. For example, as the spacing d’ decreases (e.g., d’ << d), the aspect ratio of the skin layer 240 increases. Conversely, as the spacing d’ increases (e.g., d’ ≈ d), the aspect ratio of the skin layer decreases (e.g., the aspect ratio may be less than approximately 1), such as... Figure 2B The skin layer 240' is shown in the diagram, wherein the spacing between adjacent gate structures 110C and 110D is equal to d. In some embodiments, Figure 2A The aspect ratio (h / w) of the skin layer 240 shown (e.g., near the contact area 120) is in the range of approximately 2.3 to approximately 1. In some embodiments, Figure 2B The cortex 240' shown (e.g., outside the contact area 120) is wider than the cortex 240 by a less aggressive aspect ratio (e.g., having an aspect ratio of less than about 1) (e.g., about 50 nm wider).

[0035] Additionally, erase gate (EG) structures are formed on the “outer” sidewall surfaces of gate structures 110A and 110B. The EG structures are formed of polysilicon, similar to CG and FG as discussed above. In some embodiments, the polysilicon layer 200 is subsequently etched to form a gap within the pitch d'.

[0036] In some embodiments, Figure 2C It was cut along the cutting line CD. Figure 1BThe diagram shows cross-sectional views of gate structures 110A' and 110B' of memory cell 100B. Due to layout differences between memory cells 100B and 100A, regarding gate structures 110A' and 110B', Figure 2C The cross-sectional view looks different Figure 2A A cross-sectional view. For example, the cleaving line CD traverses the contact region 120 of both gate structures 110A' and 110B'; therefore, at the location of the cleaving line CD, gate structures 110A' and 110B' have substantially equal widths along the x-direction. Figure 2C In, similar to Figure 2A As discussed above, due to the spacing d', the polysilicon layer 200 disposed between the gate structures 110A' and 110B' is characterized by a skin layer 240.

[0037] In some embodiments, a cross-sectional view of the memory cell 100C along the contact region 120 of the adjacent polysilicon line 110 looks similar to Figure 2C .

[0038] In some embodiments, Figure 2A and Figure 2C This refers to the precursor structure (e.g., the initial structure) used for the embodiments described herein, which can be equivalently applied to memory cell layouts 100A / B / C and their variations. For simplicity and without departing from the spirit and scope of this disclosure, the embodiments described herein will be described with respect to memory cell 100A.

[0039] Figure 3 Based on some embodiments Figure 1A The flowchart describes a manufacturing method 300 based on the patterning process near the contact region 120 between the gate structures 110A and 110B. Other manufacturing operations may be performed between the various operations of method 300, and may be omitted only for clarity and ease of description. These various operations are within the spirit and scope of this disclosure. Furthermore, not all operations are required to perform the disclosure provided herein. Some operations may be performed simultaneously, or in combination with… Figure 3 The operations are executed in different orders as shown. In some embodiments, one or more other operations may be performed in addition to or in place of the currently described operations. (Refer to...) Figures 4 to 9C Description method 300.

[0040] refer to Figure 3 Method 300 begins with operation 310 and in a gate structure separated by a polysilicon layer (such as one consisting of...). Figure 2AThe process of forming oxide and nitride layers on the separate gate structures 110A and 110B of the polysilicon layer 200 shown. In some embodiments, the nitride layer is formed after the oxide layer is formed. The oxide and nitride layers together form a hard mask stack, which facilitates the patterning process of the polysilicon layer 200. By way of example and not limitation, the oxide layer 400 may be silicon oxide (SiO2) thermally grown at about 680ºC to a thickness between about 30 nm and about 40 nm. The nitride layer 410 may include silicon nitride (Si3N4) or silicon oxynitride (SiON) grown at about 400ºC and to a thickness between about 10 nm and 20 nm. In some embodiments, the nitride layer 410 is deposited by a basic conformal process, such as chemical vapor deposition (CVD). The foregoing materials, thicknesses, and growth conditions are not limited, and other materials, thicknesses, and growth conditions are also possible. These other materials, thicknesses, and growth conditions are within the spirit and scope of this disclosure.

[0041] Figure 4 Gate structures 110A and 110B are shown according to some embodiments after depositing an oxide layer 400 and a nitride layer 410 according to operation 310. In some embodiments, such as Figure 4 As shown, oxide layer 400 and nitride layer 410 cover the sidewalls and bottom surface of skin layer 240, but do not fill skin layer 240.

[0042] refer to Figure 3 Method 300 continues with operation 320 and the process of forming a patterned photoresist layer on the nitride layer 410. In some embodiments, a bottom anti-reflective coating (BARC) is inserted between the photoresist layer and the nitride layer 410 before depositing the photoresist layer. The BARC layer suppresses light reflection during the patterning of the photoresist layer. Furthermore, the BARC layer minimizes the generation of undesirable standing waves during photoresist patterning. Standing waves increase the edge and sidewall roughness of the resulting patterned photoresist structure. Additionally, the BARC layer fills small defects in underlying layers (such as skin 240) by acting as a filler, thereby forming a flat surface on which the photoresist layer can be formed. By way of example and not limitation, the BARC layer can be an organic compound comprising carbon, hydrogen, and oxygen. In some embodiments, the BARC layer is spin-coated to a thickness of approximately 160 nm on... Figure 4 The gate structures 110A and 110B shown are on the gate structures. Figure 5A The resulting structure is shown after forming a BARC layer 500 and a patterned photoresist layer 510 on a nitride layer 410. In some embodiments, the patterned photoresist layer 510 has a thickness of approximately 120 nm. The aforementioned thicknesses of the BARC layer 500 and the photoresist layer 510 are not limiting, and other thicknesses are also within the spirit and scope of this disclosure.

[0043] In some embodiments, the formation of the oxide layer 400 and the nitride layer 410 (as described with respect to operation 310) and the formation of the BARC layer 500 and the patterned photoresist layer 510 (as described with respect to operation 320) are not limited to the contact region 120. In other words, the aforementioned oxide, nitride, and photoresist layers (e.g., the BARC layer 500 and the patterned photoresist layer 510) can be formed simultaneously over the entire chip area (including the entire area of ​​the memory cell and the logic area of ​​the chip). For example, Figure 5B It shows according to Figure 2B The formation of oxide layer 400, nitride layer 410, BARC layer 500, and patterned photoresist layer 510 on the structure shown (e.g., the region within the memory cell outside contact region 120) for operations 310 and 320. Therefore, Figure 5C The diagram shows an oxide layer 400, a nitride layer 410, a BARC layer 500, and a photoresist layer 510 deposited in the logic region of a chip outside the memory cells. (See diagram for reference.) Figure 5C As shown, and during operation 320, according to some embodiments, the photoresist layer 510 on the logic region of the chip is not patterned. This is intentional because no components are formed in the logic region during subsequent operations.

[0044] refer to Figure 3 Method 300 continues with operations 330 and etching the BARC layer to form opening 600, thereby exposing a portion of the nitride layer 220 on the polysilicon layer 200, as... Figure 6A As shown. In some embodiments, additional openings (e.g., similar to opening 600) may be formed simultaneously at other locations of the memory cell outside the contact area 120—for example, as Figure 6B As shown, an opening 600' is formed between gate structures 110C and 110D. In some embodiments, due to the finite spacing d' between gate structures 110A and 110B, opening 600 can have a shorter width 600w in the x-direction compared to other openings (e.g., 600') formed outside the contact region 120. For example, Figure 6A The 600w shown (e.g., within contact area 120) can be equal to or less than the 600'w formed in different areas of the memory cell outside contact area 120. Figure 6B ).also, Figure 6A The opening 600 shown exposes the sidewall and bottom surface portions of the skin 240, which may be more challenging in subsequent operations. Conversely, Figure 6B The opening 600' in the middle only exposes the bottom surface portion of the skin layer 240', which may pose less of a challenge for etching in subsequent operations.

[0045] In some embodiments, during the formation of openings 600 and 600' in the memory cell region, the logic region of the chip is still masked by the BARC layer 500 and the photoresist layer 510, such as Figure 5C As shown. Therefore, during operation 330 of method 300, no opening is formed in the logic region of the chip.

[0046] refer to Figure 3 and Figure 7A Method 300 continues with operation 340 and the process of removing exposed portions of the nitride layer 410 and the underlying oxide layer 400 through opening 600 to expose the polysilicon layer 200 between gate structures 110A and 110B. In some embodiments, during operation 340, exposed portions of the nitride layer 410 and oxide layer 400 are also removed at other locations where openings (such as opening 600') have been formed in the memory cell—for example, as... Figure 6B As shown. With opening 600' exposing a portion of a single horizontal surface within the cortex 240'. Figure 6B on the contrary, Figure 7A Etching the nitride layer 410 and oxide layer 400 near the contact region 120, as shown, may be more challenging because the opening 600 exposes a combination of vertical and horizontal surfaces in the skin layer 240. In some embodiments, such as Figure 7A As shown, etching the nitride layer 410 and the underlying oxide layer 400 through the opening 600 results in unetched portions of the oxide layer 400. This is undesirable because the presence of residual oxide layers in the skin layer 240 can be detrimental to the subsequent removal of the polysilicon layer 200. For example, residual oxide layers in the skin layer 240 can lead to polysilicon residues (e.g., unetched portions of the polysilicon layer 200), bridging (e.g., electrical short circuits), or a combination thereof. In some embodiments, such as Figure 7B As shown, operation 340 completely removes the exposed portion of the nitride layer 410 and the underlying oxide layer 400 through the opening 600' in the memory cell region outside the contact region 120.

[0047] In some embodiments, the etching process used in operation 340 includes a dry etching process optimized to sufficiently remove the nitride layer 410 and the oxide layer 400 from the skin 240. In some embodiments, the etching process includes a mixture of difluoromethane (CH2F2), sulfur hexafluoride (SF6), helium (He), nitrogen (N2), etc. In some embodiments, the addition of N2 to the etching chemicals can improve the silicon-nitride selectivity—for example, from about 1:1 to about 1:6. Therefore, the nitride layer 410 is effectively removed during etching, and less polysilicon is etched when exposed to the etching chemicals. By way of example, and not limitation, the oxide-nitride selectivity is about 1:2.

[0048] According to some embodiments, the CH2F2 flow rate is approximately 50 sccm, the SF6 flow rate is approximately 20 sccm, the He flow rate is approximately 100 sccm, and the N2 flow rate is approximately 20 sccm to approximately 100 sccm. In some embodiments, the etching process lasts for approximately 32 s, and is based on the selectivity of silicon-nitride and oxide-nitride. In some embodiments, the duration of the etching process is adjusted such that 80% of the exposed oxide layer 400 is removed. In some embodiments, a bias voltage of approximately 80 volts is applied to the substrate 230 during the etching process. Furthermore, the etching process can be performed in a temperature range between approximately 40ºC and approximately 60ºC. The foregoing etching conditions are not limiting, and other etching conditions are possible. These other etching conditions are within the spirit and scope of this disclosure.

[0049] According to some embodiments, for N2 flow rates below approximately 20 sccm, the selectivity of silicon-nitride is poor, and the polysilicon will be etched along with the nitride. As a result, defects may form in the polysilicon layer 200. On the other hand, for N2 flow rates greater than approximately 100 sccm, polymers generated during etching prematurely stop the etching process, and the nitride cannot be adequately removed.

[0050] Subsequently, the photoresist layer 510 and the BARC layer 500 are removed using "ashing" (e.g., a high-temperature oxidation process), and the gate structures 110A and 110B are subjected to a wet etching process with diluted hydrofluoric acid (DHF) for approximately 20 seconds to ensure that unetched portions of the oxide layer 400 within the skin layer 240 are removed. In some embodiments, the water-HF ratio in the aforementioned DHF solution is approximately 100:1.

[0051] During the wet etching process, the nitride layer 410 is not etched, and therefore the oxide layer 400, which is "masked" (e.g., covered) by the nitride layer 410 (e.g., on the gate structures 110A / B and EG), is not removed. Figure 8A As shown. In some embodiments, due to the isotropic etching of the wet etching process, the exposed edge 800 of the oxide layer 400 is laterally recessed (e.g., forming an "undercut"). Undercuts in the oxide layer 400 may also occur at other locations in the memory cell where the edge of the oxide layer 400 is exposed beneath the nitride layer 410. The amount of undercut can be controlled by the DHF dilution ratio and the exposure time (e.g., duration) of the wet etching process. In some embodiments, similar undercuts can be formed in other memory cell regions outside the contact region 120 where the oxide layer 400 is exposed in the wet etching process, such as... Figure 8BThe exposed edge 800' of the oxide layer 400 in the figure is shown.

[0052] In some embodiments, Figure 3 Following operation 340 of method 300 as shown, additional photolithography and etching operations are performed in other areas of the chip (e.g., in logic regions) to remove a portion of the nitride layer 410 and oxide layer 400, as... Figure 8C As shown. During these photolithography and etching operations, the entire memory cell region is... Figure 8A and Figure 8B The fresh BARC and photoresist layer are not shown in the image. Subsequently, in... Figure 3 Before operation 350 of method 300 shown, these BARC and photoresist layers are removed using an ashing process.

[0053] refer to Figure 3 Method 300 continues with operation 350 and the etching of the exposed polysilicon layer 200 to form a gap or spacing 900 between the gate structures 110A and 110B, as... Figure 9A As shown. Before polysilicon etching, remove as... Figure 8A and Figure 8B The nitride layer 410 is shown. Removal of the nitride layer 410 is achieved, for example, using a selective dry etching process. By way of example and not limitation, the dry etching process may include organofluorine chemicals such as tetrafluoromethane (CF4), fluoroform (CHF3), 1,1-difluoroethane (CH3CHF2), or combinations thereof having hydrogen or oxygen. Other chemicals may also be used, and they are also within the spirit and scope of this disclosure.

[0054] like Figure 9A and Figure 9BAs shown, once the nitride layer 410 is removed, a dry etching process is used to remove (e.g., etch) portions of the polysilicon layer 200 not covered by the oxide layer 400. In some embodiments, the dry etching process is anisotropic, allowing control over the lateral etching of the polysilicon layer 200 (e.g., in the x-direction). Furthermore, the dry etching process is selective for the polysilicon layer 200. By way of example, and not limitation, the dry etching chemicals may have a selectivity greater than approximately 100:1 between the polysilicon layer 200 and the oxide layer 400. In some embodiments, the etching chemicals include mixtures of CH2F2, SF6, He, N2, etc. By way of example, and not limitation, the CH2F2 flow rate may be approximately 60 sccm, the SF6 flow rate may be approximately 45 sccm, the He flow rate may be approximately 150 sccm, and the N2 flow rate may be approximately 68 sccm. However, the foregoing conditions are not limiting, and other conditions may be used. These other conditions are within the spirit and scope of this disclosure. In some embodiments, the etching process ends when the dielectric layer 210 beneath the polysilicon layer 200 is exposed by the gap or spacing 900.

[0055] In some embodiments, such as Figure 9A and Figure 9B The diagram shows spacers or pitches 900 and 900', respectively. By way of example and not limitation, spacer or pitch 900 has a width W between approximately 50 nm and approximately 100 nm and a height H between approximately 100 nm and approximately 120 nm. Figure 9A As shown, the spacing d' between gate structures 110A and 110B is greater than the width W of the spacing or spacing 900 (e.g., d' > W). Therefore, as Figure 9B As shown, the spacing d between gate structures 110C and 110D is greater than the width W' of the interval or spacing 900' (e.g., d > W'). In some embodiments, the interval or spacing 900 and 900' are formed such that a portion of the polysilicon layer 200 remains as shown in the figure. Figure 9A The inner wall of the gate structure 110A shown, and as shown in the figure Figure 9B On the inner sidewalls of the gate structures 110C and 110D shown. The aspect ratio of the spacing or pitch 900 can be, for example, between about 1 and about 2.4.

[0056] In some embodiments, the polysilicon etching process in operation 350 can form polysilicon openings, including contact openings or other spaced openings, in a chip region outside the memory cell—for example, in a logic region of the chip. Figure 9C As shown.

[0057] In some embodiments, after operation 350, the oxide layer 400 is removed—for example, by using a wet etching process with DHF—and contacts can be formed on the contact region 120 of the gate structure 110B. This is by way of example and not limitation. Figure 10A This illustrates the process after the contact 1000 is formed on the widest portion of 110B (e.g., on contact area 120). Figure 9A The structure is as follows. As an example, and not a limitation, the contact 1000 can be formed by first depositing a dielectric layer 1010 to surround the gate structures 110A / 110B and filling the spacer or pitch 900, and then forming contact openings in the dielectric layer 1010 on the contact region 120 of the gate structure 110B through a patterned process. The contact openings can then be filled with a conductive material, such as a metal (e.g., tungsten (W), cobalt (Co), etc.). In some embodiments, prior to forming the dielectric layer 1010, a non-conductive material can be deposited on the gate structures 110A / 110B and the spacer or pitch 900. Figure 10A The etch stop layer shown facilitates the formation of contact openings for contact 1000. During the formation of contact 1000, additional contacts may be formed on other portions of the memory cell or other areas of the chip. For example, additional contacts may be formed on other portions of the memory cell or other areas of the chip. Figure 10B A contact 1000' is formed between the gate structures 110C and 110D shown. Subsequently, metallization layers or wiring layers can be formed on the gate structures 110A, 110B, 110C, and 110D. These are not... Figure 10A and Figure 10B The additional metallization layer or wiring layer shown can be electrically coupled to the CG of the gate structure 110B and the source and drain regions of the substrate 230 via contacts 1000 and 1000'.

[0058] A patterning process for strip regions of a memory cell is described according to various embodiments of this disclosure, which removes excess material between polysilicon lines and reduces (or eliminates) residues left by the removal process. In some embodiments, residue removal (or elimination) is achieved by introducing photolithography and etching operations that facilitate the removal of excess material between closely spaced polysilicon lines. In some embodiments, the patterning process includes hard mask photolithography and hard mask etching processes that remove a hard mask layer from a skin layer in the polysilicon layer between the polysilicon lines. In some embodiments, the etching process includes a dry etching process targeting the nitride and oxide layers of the hard mask, followed by a wet etching process targeting the oxide layer of the hard mask.

[0059] In some embodiments, a method includes: forming a first polysilicon line having a first width and a second polysilicon line having a second width on a substrate, wherein the first polysilicon line and the second polysilicon line are spaced apart by a polysilicon layer, and each of the first polysilicon line and the second polysilicon line includes a contact region greater than the first width and the second width. The method further includes: depositing a mask layer on the first polysilicon line, the contact region of the second polysilicon line, and the polysilicon layer; and etching the mask layer from the polysilicon layer using a dry etching process to remove a portion of the mask layer and expose a first portion of the polysilicon layer. Additionally, an unremoved portion of the mask layer is etched from the polysilicon layer using a wet etching process to expose a second portion of the polysilicon layer larger than the first portion, wherein the second portion is narrower than the polysilicon layer inserted between the contact region of the second polysilicon line and the first polysilicon line. The method further includes: removing the exposed second portion of the polysilicon layer to form a gap between the contact region of the second polysilicon line and the first polysilicon line.

[0060] In the above method, etching the mask layer includes: removing a nitride mask layer disposed on an oxide mask layer, wherein the oxide mask layer is disposed on a first polysilicon line; and removing the contact area of ​​the oxide mask layer, the second polysilicon line, and a portion of the polysilicon layer.

[0061] In the above method, the unremoved portion of the etched mask layer includes: etching the oxide mask layer disposed on the contact area of ​​the first polysilicon line, the second polysilicon line, and the polysilicon layer.

[0062] In the above method, depositing a mask layer on a polysilicon layer includes covering the sidewalls and bottom surface of a skin layer formed on the top surface of the polysilicon layer with the mask layer.

[0063] In the above method, etching the mask layer using a dry etching process includes: patterning a photoresist layer on the mask layer to expose a region of the mask layer above the polysilicon layer, wherein the exposed region of the mask layer is narrower than that of the polysilicon layer.

[0064] In the above method, etching the unremoved portion of the mask layer using a wet etching process includes forming an undercut in the unetched portion of the mask layer.

[0065] In the above method, the deposition mask layer includes: depositing an oxide layer on the contact region of the first polysilicon line and the second polysilicon line and on the polysilicon layer; and depositing a nitride layer on the oxide layer.

[0066] In some embodiments, a method includes: depositing a first hard mask layer in a skin formed on top of a polysilicon layer inserted between a first polysilicon gate structure and a second polysilicon gate structure; and depositing a second hard mask layer on the first hard mask layer, wherein the first hard mask layer and the second hard mask layer cover the sidewalls and bottom surface of the skin layer. The method further includes: performing a first etch to remove the second hard mask layer and a portion of the first hard mask layer from a first sidewall of the skin layer; performing a second etch to remove the first hard mask layer from the first sidewall and the bottom surface of the skin layer; and performing a third etch to remove a polysilicon layer not covered by the first hard mask layer and the second hard mask layer to form a gap between the first polysilicon gate structure and the second polysilicon gate structure.

[0067] The above method also includes forming a contact on the second polysilicon structure.

[0068] In the above method, depositing the first hard mask layer includes depositing an oxide layer on top of the polysilicon layer.

[0069] In the above method, depositing the second hard mask layer includes depositing a nitride layer on the first hard mask layer.

[0070] In the above method, performing the first etching includes performing etching with difluoromethane (CH2F2), sulfur hexafluoride (SF6), helium (He), and nitrogen (N2).

[0071] In the above method, performing the first etching includes using etching chemicals comprising a nitrogen gas flow between about 20 sccm and about 100 sccm to give a silicon-nitrogen etching selectivity of about 1 to 6.

[0072] In the above method, performing the second etching includes performing a wet etching process with diluted hydrofluoric acid (HF) for about 20 seconds.

[0073] In the above method, performing the third etching includes performing a dry etching process that is selective for polysilicon.

[0074] In the above method, performing the third etching includes forming a gap that is narrower than the distance between the first polysilicon gate structure and the second polysilicon gate structure.

[0075] In some embodiments, a structure includes: a first polysilicon line and a second polysilicon line disposed parallel to each other on a substrate. The first and second polysilicon lines include contact regions and non-contact regions, wherein each contact region is wider than each non-contact region, and wherein the contact region of the first polysilicon line is offset relative to the contact region of the second polysilicon line. The structure further includes: a polysilicon layer disposed on a sidewall of the non-contact region of the first polysilicon line and opposite to the contact region of the second polysilicon line; and a space between the polysilicon layer and the contact region of the second polysilicon line. The structure further includes: a contact element disposed on the contact region of the second polysilicon line.

[0076] In the above structure, the aspect ratio of the space is between approximately 1 and approximately 2.4.

[0077] In the above structure, the bottom surface of the space does not contain a polycrystalline silicon layer.

[0078] In the above structure, the second polysilicon line in the contact region includes a contact gate and one or more floating gates.

[0079] It should be understood that the detailed description section, and not the summary, is intended to explain this disclosure. The summary section may illustrate one or more, but not all, of the contemplated exemplary embodiments, and is therefore not intended to limit this disclosure.

[0080] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for patterning, comprising: A first polysilicon line having a first width and a second polysilicon line having a second width are formed on a substrate, wherein the first polysilicon line and the second polysilicon line are separated by a polysilicon layer, and each of the first polysilicon line and the second polysilicon line includes a contact region wider than the first width and the second width. A mask layer is deposited on the contact region of the first polysilicon line, the second polysilicon line, and the polysilicon layer, the polysilicon layer including a skin layer located on the top surface of the polysilicon layer; Depositing the mask layer includes: An oxide layer is deposited on the contact region of the first polysilicon line, the second polysilicon line, and the polysilicon layer; and A nitride layer is deposited on the oxide layer; The mask layer is etched from the polysilicon layer through an opening using a dry etching process to remove a portion of the mask layer and expose a first portion of the polysilicon layer, wherein etching the mask layer through the opening results in an unremoved portion of the oxide layer, the unremoved portion including a first unremoved portion located on a first sidewall of the skin layer and a second unremoved portion located on the bottom surface of the skin layer; The unremoved portion of the oxide layer is etched from the polysilicon layer using a wet etching process to expose a second portion of the polysilicon layer that is larger than the first portion, wherein the second portion is narrower than the polysilicon layer inserted between the contact region of the second polysilicon line and the first polysilicon line; and Remove the exposed second portion of the polysilicon layer to form a gap between the contact area of ​​the second polysilicon line and the first polysilicon line.

2. The method according to claim 1, wherein, Etching the mask layer includes: Remove the nitride mask layer disposed on the oxide mask layer, wherein the oxide mask layer is disposed on the first polysilicon line; and Remove the oxide mask layer, the contact area of ​​the second polysilicon line, and a portion of the polysilicon layer.

3. The method according to claim 1, wherein, Etching the unremoved portion of the mask layer includes etching an oxide mask layer disposed on the contact area of ​​the first polysilicon line, the second polysilicon line, and the polysilicon layer.

4. The method according to claim 1, wherein, Depositing the mask layer on the polysilicon layer includes covering the sidewalls and bottom surface of the skin layer with the mask layer.

5. The method according to claim 1, wherein, Etching the mask layer using the dry etching process includes: patterning a photoresist layer on the mask layer to expose a region of the mask layer over the polysilicon layer, wherein the exposed region of the mask layer is narrower than the polysilicon layer.

6. The method according to claim 1, wherein, Etching the unremoved portion of the mask layer using the wet etching process includes forming an undercut in the unetched portion of the mask layer.

7. The method according to claim 1, wherein, The first unremoved portion does not extend beyond the first sidewall.

8. A method for patterning, comprising: A first hard mask layer is deposited in a skin layer formed on top of a polysilicon layer inserted between a first polysilicon gate structure and a second polysilicon gate structure. A second hard mask layer is deposited on the first hard mask layer, wherein the first hard mask layer and the second hard mask layer cover the sidewalls and bottom surface of the skin layer; A first etching is performed to remove a portion of the second hard mask layer and the first hard mask layer from a first sidewall of the skin layer through an opening, wherein performing the first etching through the opening results in the first hard mask layer having a first unremoved portion and a second unremoved portion, the first unremoved portion being located on the first sidewall of the skin layer and the second unremoved portion being located on the bottom surface of the skin layer; Perform a second etching to remove the first unremoved portion and the second unremoved portion of the first hard mask layer; and A third etch is performed to remove the polysilicon layer not covered by the first hard mask layer and the second hard mask layer, so as to form a gap between the first polysilicon gate structure and the second polysilicon gate structure.

9. The method according to claim 8, further comprising: Contacts are formed on the second polysilicon gate structure.

10. A memory structure, comprising: Substrate; A first polysilicon line and a second polysilicon line are disposed parallel to each other on the substrate. Each of the first polysilicon line and the second polysilicon line includes a contact region and a non-contact region, wherein each contact region is wider than each non-contact region, and wherein the contact region of the first polysilicon line is offset relative to the contact region of the second polysilicon line. A polysilicon layer is disposed on the sidewall of the non-contact region of the first polysilicon line and opposite to the contact region of the second polysilicon line; The space between the contact area of ​​the polysilicon layer and the second polysilicon line; and A contact element is disposed on the contact area of ​​the second polysilicon line. The second polysilicon line in the contact region adjacent to the non-contact region includes a contact gate and a first floating gate and a second floating gate located below the contact gate and spaced apart from each other.

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