Semiconductor device and preparation method thereof

Abstract

The invention provides a preparation method of a semiconductor device, and the method comprises the steps: forming a bottom layer structure which at least comprises a substrate layer, a channel layer located above the substrate layer, and a barrier layer located on the upper surface of the channel layer, and forming a material layer of a gate structure above the barrier layer; forming a first dielectric layer on the upper surface of a material layer preset region of the gate structure, and forming a side wall on at least one side of the first dielectric layer; removing the first dielectric layer, and etching the material layer of the gate structure by taking the side wall as a mask to form the gate structure; and forming a source electrode structure and a drain electrode structure on two sides of the gate electrode structure respectively. According to the invention, the gate structure is formed by performing dry etching on the multi-layer medium to form the side wall, so that the short gate structure is formed, the limit of the precision of photoetching equipment on a production line is broken through, a shorter channel length is formed, and the channel resistance of the device is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing technology, and in particular relates to a semiconductor device and its preparation method. Background Technology

[0002] As market demands for smaller size and higher energy efficiency in power devices increase, wide-bandgap GaN devices have become widely used in high-frequency power conversion systems due to their lower power loss and faster switching capabilities. Compared to silicon metal-oxide-semiconductor field-effect transistors (MOSFETs), wide-bandgap GaN high electron mobility transistors (HEMTs) offer better quality factors and more promising performance in high-power and high-frequency applications.

[0003] For low- and medium-voltage wide-bandgap GaN devices, the access regions of the gate and drain are very short, and the channel resistance accounts for a large portion of the overall device resistance. To further reduce the channel resistance of wide-bandgap GaN devices, advanced photolithography techniques are typically used to reduce the gate length, i.e., the channel length. However, higher photolithography precision also means higher costs. How to further improve the performance of wide-bandgap GaN devices without increasing manufacturing costs—that is, how to manufacture wide-bandgap GaN devices with shorter gate lengths (i.e., lower channel resistance) without replacing them with more advanced photolithography machines—is a pressing problem that needs to be solved. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device and a method for fabricating the same, so as to solve the problem of manufacturing a wide bandgap semiconductor GaN device with shorter gate length (i.e., lower channel resistance) that breaks through the existing photolithography precision without more advanced photolithography equipment.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device. The method includes: forming an underlying structure, the underlying structure including at least a substrate layer and a channel layer above the substrate layer, and a barrier layer on the upper surface of the channel layer; forming a material layer of a gate structure above the barrier layer; forming a first dielectric layer on the upper surface of a predetermined region of the material layer of the gate structure; forming a sidewall on at least one side of the first dielectric layer; removing the first dielectric layer; using the sidewall as a mask, etching the material layer of the gate structure to form a gate structure; and forming a source structure and a drain structure on both sides of the gate structure, respectively.

[0006] Preferably, when sidewalls are formed on both sides of the first dielectric layer, the gate structure includes a first gate structure and a second gate structure, the source structure includes a first source structure and a first drain structure, the drain structure includes a second source structure and a second drain structure, the first source structure and the first drain structure are respectively located on both sides of the first gate structure, and the second source structure and the second drain structure are respectively located on both sides of the second gate structure.

[0007] Preferably, the method of forming the sidewall includes: forming a second dielectric layer covering the upper surface of the gate structure material layer and the first dielectric layer; and fully etching the second dielectric layer to form at least one sidewall.

[0008] Preferably, the etching ratio of the second dielectric layer to the first dielectric layer is greater than 3:1.

[0009] Preferably, the material layer of the gate structure includes: a P-type doped group III-V compound material layer covering the upper surface of the barrier layer and a metal layer covering the upper surface of the P-type doped group III-V compound material layer.

[0010] Preferably, the underlying structure further includes a cap layer formed on the upper surface of the barrier layer.

[0011] Preferably, the material layer of the gate structure includes: a gate dielectric layer covering the upper surface of the cap layer and a metal layer covering the upper surface of the gate dielectric layer.

[0012] Preferably, the method for forming the source structure and the drain structure includes: removing the sidewalls; forming a first passivation layer above the underlying structure, the first passivation layer covering the gate structure; etching the first passivation layer to form source contact holes and drain contact holes on both sides of the gate structure; and filling the source contact holes and drain contact holes with metal to form the source structure and the drain structure.

[0013] Preferably, the method for forming the first source structure, the first drain structure, the second source structure, and the second drain structure includes: removing the two sidewalls; forming a first passivation layer over the underlying structure, the first passivation layer covering the first gate structure and the second gate structure; etching the first passivation layer to form a first source contact hole and a first drain contact hole on both sides of the first gate structure and a second source contact hole and a second drain contact hole on both sides of the second gate structure; and filling the first source contact hole, the first drain contact hole, the second source contact hole, and the second drain contact hole with metal to form the first source structure, the first drain structure, the second source structure, and the second drain structure.

[0014] Preferably, both the first source contact hole and the second source contact hole are located between the first gate structure and the second gate structure.

[0015] Preferably, the first source contact hole and the second source contact hole share a single source contact hole.

[0016] Preferably, the source contact hole and the drain contact hole extend at least to the upper surface of the barrier layer.

[0017] Preferably, the method further includes: forming a second passivation layer on the upper surface of the first passivation layer, the second passivation layer covering the first source structure, the first drain structure, the second source structure, and the second drain structure; forming a first metal interconnect structure, the first metal interconnect structure extending from the upper surface of the second passivation layer to the upper surfaces of the gate structure, the source structure, and the drain structure.

[0018] Preferably, the fabrication method further includes: forming a first source structure and a first drain structure on both sides of the first gate structure, and forming a second source structure and a second drain structure on both sides of the second gate structure; and forming a third source structure and a third drain structure on the same side other than the first gate structure and the second gate structure, wherein the third source structure and the third drain structure are formed synchronously with the first source structure, the first drain structure, the second source structure, and the second drain structure.

[0019] Preferably, the preparation method further includes forming a third gate structure between the third source structure and the third drain structure.

[0020] Preferably, the method for forming the third gate structure includes: forming a second passivation layer on the upper surface of the first passivation layer, the second passivation layer covering the first source structure, the first drain structure, the second drain structure, the third source structure, and the third drain structure; etching the first passivation layer and the second passivation layer to form a contact hole for the third gate structure, forming a gate dielectric layer on at least the sidewalls and bottomwalls of the contact hole for the third gate structure; and filling the gate dielectric layer with metal to form the third gate structure.

[0021] Preferably, the method further includes: forming a third passivation layer on the upper surface of the second passivation layer, the third passivation layer covering the third gate structure; forming a second metal interconnect structure, the second metal interconnect structure extending from the upper surface of the third passivation layer to the upper surfaces of the gate structure, the source structure and the drain structure.

[0022] Secondly, this application provides a semiconductor device, the device comprising: a bottom layer, the bottom layer comprising at least a substrate layer and a channel layer above the substrate layer, and a barrier layer on the upper surface of the channel layer; a first passivation layer above the bottom layer; a first gate structure and a second gate structure above the bottom layer; a first source structure and a first drain structure on both sides of the first gate structure; and a second source structure and a second drain structure on both sides of the second gate structure; wherein the first passivation layer covers the first source structure, the first drain structure, and the first gate structure, and covers the second source structure, the second drain structure, and the second gate structure, and exposes the upper surfaces of the first source structure, the first drain structure, the second source structure, and the second drain structure.

[0023] Preferably, the first gate structure and the second gate structure include: a P-type doped group III-V compound material layer located on the upper surface of the barrier layer and a metal layer located on the upper surface of the P-type doped group III-V compound material layer.

[0024] Preferably, the underlying structure further includes a cap layer located on the upper surface of the barrier layer, wherein the material of the cap layer includes a group III-V compound.

[0025] Preferably, the first gate structure and the second gate structure include: a gate dielectric layer located on the upper surface of the cap layer and a gate metal layer located on the upper surface of the gate dielectric layer.

[0026] Preferably, the first source structure, the first drain structure, the second source structure, and the second drain structure extend at least to the upper surface of the barrier layer.

[0027] Preferably, the device further includes: a third source structure and a third drain structure located on the same side outside the first gate structure and the second gate structure; and a third gate structure located between the third source structure and the third drain structure.

[0028] Preferably, the device further includes an isolation region located between the second drain structure and the third source structure; the isolation region extends from the upper surface of the barrier layer at least into the interior of the channel.

[0029] As described above, the semiconductor device and its fabrication method of the present invention are methods for forming short-gate-length GaN devices using a top-sidewall process. This application overcomes the precision limitations of photolithography equipment on the production line by forming shorter channels through comprehensive dry etching of multiple dielectric layers, thereby reducing the channel resistance of the device. Specifically, in this application, a top-sidewall hard mask layer is formed by combining the deposition and etching processes of multiple dielectric layers. The size of this sidewall mask layer depends on the deposition thickness of the dielectric layers, and this size can be made very small. Furthermore, using this top sidewall as a mask, a shorter gate length can be formed. This application overcomes the precision limitations of photolithography equipment on the production line by employing a sidewall mask process to form a shorter channel length, thereby reducing the under-gate channel resistance of the device. Attached Figure Description

[0030] Figure 1A-1M The diagram shows the structural steps of a HEMT device according to one embodiment of the present invention.

[0031] Figure 2A-2G The diagram shows the structural steps of a HEMT device according to one embodiment of the present invention.

[0032] Figures 3A-3E The diagram shows the structural steps of a HEMT device according to one embodiment of the present invention. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] Firstly, such as Figure 1A-1M As shown, Figure 1A-1M The diagram shows the structural steps of the HEMT device according to Embodiment 1 of the present invention. The application provides a method for fabricating a semiconductor device, the method comprising: forming an underlying structure, the underlying structure including at least a substrate layer and a channel layer above the substrate layer, and a barrier layer on the upper surface of the channel layer; forming a material layer of a gate structure above the barrier layer; forming a first dielectric layer on the upper surface of a predetermined region of the material layer of the gate structure; forming a sidewall on at least one side of the first dielectric layer; removing the first dielectric layer; using the sidewall as a mask, etching the material layer of the gate structure to form a gate structure; and forming a source structure and a drain structure on both sides of the gate structure, respectively.

[0035] In this embodiment, a bottom layer structure is formed, which includes at least a substrate layer, a channel layer above the substrate layer, and a barrier layer on the upper surface of the channel layer. A material layer for a gate structure is formed above the barrier layer. The bottom layer structure 10 includes a substrate layer 101, a channel layer 103 on the substrate layer 101, and a barrier layer 104 on the surface of the channel layer 103. A 2DEG is formed at the contact surface between the channel layer 103 and the barrier layer 104. Further, in this embodiment, the bottom layer structure 10 also includes a buffer layer 102 located between the substrate layer 101 and the channel layer 103, and corresponding to the material of the channel layer 103, to release the stress caused by lattice mismatch and thermal mismatch between the channel layer 103 and the substrate layer 101 during epitaxial growth. Specifically, the substrate layer 101 can be made of materials such as silicon substrate, sapphire substrate, silicon carbide substrate, or diamond substrate. The channel layer 103 can be made of group III nitride materials such as gallium nitride (GaN), aluminum nitride (AlN), and indium nitride (InN). The barrier layer 104 can be made of a material corresponding to that of the channel layer 103, such as an AlGaN barrier layer, an InGaN barrier layer, or an InAlN barrier layer. When the channel layer 103 is a GaN channel layer, the buffer layer 102 can be made of materials such as Al... x Ga 1-x N buffer layer, etc., and in Al x Ga 1-x The molar content (x) of Al in the N buffer layer can gradually decrease along the growth direction of the buffer layer 102. The specific materials and thicknesses of the base layer 101, the buffer layer 102, the channel layer 103, and the barrier layer 104 are not limited here and can be selected as needed.

[0036] In this embodiment, the HEMT device can be a depletion-mode HEMT device or an enhancement-mode HEMT device. When the HEMT device is an enhancement-mode HEMT device, the gate structure includes a P-type doped III-V compound material layer covering the upper surface of the barrier layer and a metal layer covering the upper surface of the P-type doped III-V compound material layer. Specifically, a material layer for forming the gate structure is formed above the barrier layer. The material layer for the gate structure includes a P-type doped III-V compound material layer covering the upper surface of the barrier layer and a metal layer covering the upper surface of the P-type doped III-V compound material layer. The III-V compound material is one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium nitride (InAlN). The metal layer can be a gate metal suitable for HEMT devices, such as a TiN or Ni / Au stack structure constituting a Schottky contact, but is not limited to these. When the HEMT device is a depletion-type HEMT device, the gate structure includes a gate dielectric layer located on the upper surface of the barrier layer and a metal layer covering the upper surface of the gate dielectric layer. The cap layer is made of a III-V compound material, and the gate dielectric layer can be made of materials such as silicon nitride (SiN), other insulating materials such as silicon dioxide (SiO2), or a stack of nitride insulating materials and oxide insulating materials. The metal layer can use existing gate metals suitable for HEMT devices, such as TiN or Ni / Au stacks that form Schottky contacts, but is not limited to these.

[0037] In this embodiment, a first dielectric layer 301 is formed on the upper surface of a predetermined region of the material layer of the gate structure. The material of the first dielectric layer 301 can be a nitride insulating material, such as silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or a stack of nitride insulating materials and oxide insulating materials. A sidewall 402 is formed on at least one side of the first dielectric layer 301. In this embodiment, the sidewall 402 can be formed on one side (e.g., the left side), on one side (e.g., the right side), or on both sides of the first dielectric layer 301.

[0038] In this embodiment, the first dielectric layer 301 is removed. The method of removing the first dielectric layer 301 can be dry etching or wet etching. There is no limitation on the method of removing the first dielectric layer 301.

[0039] In this embodiment, the sidewall 402 is used as a mask to etch the material layer of the gate structure to form the gate structure 20. The etching method for the material layer of the gate structure can be dry etching or wet etching, which is not limited here. After etching, the gate structure is formed. The gate structure 20 includes a P-type gate 203 located in the lower layer and a gate metal layer 204 located in the upper layer. A source structure 602 and a drain structure 601 are formed on both sides of the gate structure. The source structure 602 and the drain structure 601 are located on opposite sides of the gate structure 20 and are spaced apart from the gate structure 20. The source structure 602 is preferably an ohmic contact source structure, and the drain structure 601 is preferably an ohmic contact drain structure. The source structure 602 and the drain structure 601 extend at least to the upper surface of the barrier layer 104. For example, as Figure 1K As shown, the source structure 602 and the drain structure 601 are both located on the surface of the barrier layer 104. In other embodiments, the source structure 602 and the drain structure 601 extend into the barrier layer 104. In other embodiments, the source structure 602 and the drain structure 601 extend into the channel layer 103.

[0040] like Figure 1A-1M As shown, Figure 1A-1M The diagram shows the structural steps of the HEMT device according to Embodiment 2 of the present invention. This embodiment uses an enhancement-mode HEMT device as an example for illustration. Unlike Embodiment 1, in this embodiment, sidewalls are formed on both sides of the first dielectric layer. Specifically, as shown... Figure 1A As shown, a bottom layer structure 10 is formed, the bottom layer structure 10 including at least a base layer 101 and a channel layer 103 located above the base layer 101, and a barrier layer 104 located on the upper surface of the channel layer 103, and a 2DEG is formed at the contact surface between the channel layer 103 and the barrier layer 104. Figure 1B As shown, a material layer for a gate structure is formed above the barrier layer 104. The material layer for the gate structure includes a lower P-type doped group III-V compound material layer 201 and an upper metal layer 202. In this embodiment, the P-type doped group III-V compound material layer 201 and the metal layer 202 can be formed by deposition or other methods, which are not limited here. The above steps are consistent with those in Embodiment 1 and will not be repeated here.

[0041] like Figure 1CAs shown, a first dielectric layer 301 is formed on the upper surface of a predetermined region of the metal layer 202. The material of the first dielectric layer 301 can be a nitride insulating material, such as silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or a stack of nitride insulating materials and oxide insulating materials, etc.

[0042] like Figure 1D As shown, a second dielectric layer 401 is formed on the upper surface of the gate structure material layer and the first dielectric layer 301. The material of the second dielectric layer 301 can be a nitride insulating material, such as silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or a stack of nitride insulating materials and oxide insulating materials. However, the first dielectric layer 301 and the second dielectric layer 401 are different dielectric layers, and the etching selectivity ratio between the two dielectric layers is greater than 3:1.

[0043] like Figure 1E As shown, the second dielectric layer 401 is fully etched to form sidewalls 402 on both sides of the first dielectric layer 301.

[0044] like Figure 1F As shown, the first dielectric layer 301 is removed. The method of removing the first dielectric layer 301 can be dry etching or wet etching. There is no restriction on the method of removing the first dielectric layer 301.

[0045] like Figure 1G As shown, the material layers of the gate structure are etched using the two sidewalls 402 as hard masks, namely, the P-type doped III-V compound material layer 201 and the metal layer 202. The remaining P-type doped III-V compound material layer 203 and the metal layer 204 are used to form two gate structures, which we refer to as the first gate structure 20 and the second gate structure 21, respectively.

[0046] like Figure 1H As shown, the two top side 402 walls are removed; the two top side 402 walls can be removed by dry etching or wet etching, and the method of removing the top side walls 402 is not limited here.

[0047] like Figure 1I As shown, a first passivation layer 501 is formed, which is located above the bottom structure 10. In this embodiment, the first passivation layer 501 is located above the first barrier layer 104, and the first passivation layer 501 covers the first gate structure 20 and the second gate structure 21.

[0048] like Figure 1JAs shown, a first source structure 602 and a first drain structure 601 are formed on both sides of the first gate structure 21, and a second source structure 604 and a second drain structure 603 are formed on both sides of the second gate structure 21. The method for forming the first source structure 602 and the second source structure 604 is preferably an ohmic contact source structure, and the method for forming the first drain structure 601 and the second drain structure 603 is preferably an ohmic contact drain structure. The first source structure 602 and the second source structure 604, as well as the first drain structure 601 and the second drain structure 603, are formed simultaneously. Specifically, the first passivation layer 501 is etched to form two source contact holes and two drain contact holes. The two source contact holes are designated as a first source contact hole and a second source contact hole, and the two drain contact holes are designated as a first drain contact hole and a second drain contact hole. The first source contact hole and the first drain contact hole are located on opposite sides of the first gate structure 20, and the second source contact hole and the second drain contact hole are located on opposite sides of the second gate structure 21, with both the first source contact hole and the second source contact hole situated between the first gate structure 20 and the second gate structure 21. Metal is then filled into the source contact holes and the drain contact holes to form a first source structure 602 and a first drain structure 601, as well as a second source structure 604 and a second drain structure 603. In this embodiment, the first source contact hole and the second source contact hole are shared source contact holes; that is, the first source structure 602 and the second source structure 604 are shared source structures.

[0049] In this embodiment, the method further includes: forming a first metal interconnect structure 80. Specifically, as shown... Figure 1K As shown, after removing the excess first passivation layer 501, that is, after removing a portion of the first passivation layer 501 above the first gate structure 20 and the second gate structure 21, a first passivation layer 502 with a flat upper surface is obtained, as shown. Figure 1L As shown, a second passivation layer 701 is then formed on the smooth upper surface of the first passivation layer 502. The second passivation layer 701 covers the upper surface of the first passivation layer 502 and encapsulates the upper surfaces of the first source structure 602, the first drain structure 601, the second source structure 604, and the second drain structure 603. Figure 1MAs shown, a first metal interconnect structure 80 is formed, wherein the first metal interconnect structure 80 extends from the upper surface of the second passivation layer 701 to the upper surfaces of the first gate structure 20, the first source structure 602, the first drain structure 602, the second gate structure 21, the second source structure 604, and the second drain structure 603, and the first metal interconnect structure 80 contacts the first gate structure 20, the first source structure 602, the first drain structure 602, the second gate structure 21, the second source structure 604, and the second drain structure 603, respectively, and the contact here is an electrical connection contact. Specifically, the method for forming the first metal interconnect structure 80 includes: etching the second passivation layer 701 to form a plurality of vias, the plurality of vias exposing the upper surfaces of the first source structure 602, the first drain structure 601, the second source structure 604, and the second drain structure 603, respectively; etching the second passivation layer 701 and the first passivation layer 502 to form two vias, the two vias exposing the upper surfaces of the first gate structure 20 and the second gate structure 21, respectively; and filling these vias with metal to form the first metal interconnect structure.

[0050] In this application, the gate structure is formed by etching the gate structure material layer using the top sidewall as a hard mask. The top sidewall is formed by dry etching, which eliminates the need for high-precision photolithography to form the gate structure. Furthermore, the top length formed by dry etching is very short, resulting in a very small gate length for the gate structure formed using the top sidewall as a mask. This application breaks through the precision limits of photolithography equipment on the production line by forming a shorter channel length through anisotropic dry etching of multilayer dielectrics, thereby reducing the channel resistance of the device.

[0051] like Figures 2A-2E As shown, Figures 2A-2E The diagram shown illustrates the structural steps of the HEMT device according to Embodiment 3 of the present invention. Unlike Embodiment 2, this embodiment uses a depletion-mode HEMT device as an example for explanation. Figure 2A As shown, a bottom layer structure 10 is formed. This bottom layer structure is consistent with the bottom layer structure in Embodiment 2, and will not be described again here.

[0052] like Figure 2BAs shown, the underlying structure further includes a cap layer 205 formed on the upper surface of the barrier layer. The cap layer 205 can be one or more of group III nitride materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium nitride (InAlN). A gate structure material layer is formed on the upper surface of the cap layer, comprising a gate dielectric layer 206 covering the upper surface of the cap layer 205 and a metal layer 207 covering the upper surface of the gate dielectric layer 206. The gate dielectric layer 206 can be made of materials such as silicon nitride (SiN), other insulating materials such as silicon dioxide (SiO2), or a stack of nitride and oxide insulating materials. The metal layer 207 can be a gate metal suitable for HEMT devices, such as a TiN or Ni / Au stack forming a Schottky contact, but is not limited to these.

[0053] like Figure 2C As shown, a first dielectric layer 301 is formed on the upper surface of a predetermined region of the metal layer 207. The material of the first dielectric layer 301 can be a nitride insulating material, such as silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or a stack of nitride insulating materials and oxide insulating materials, etc.

[0054] like Figure 2D As shown, a second dielectric layer 401 is formed on the upper surface of the gate structure material layer and the first dielectric layer 301. The material of the second dielectric layer 301 can be a nitride insulating material, such as silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or a stack of nitride insulating materials and oxide insulating materials. However, the first dielectric layer 301 and the second dielectric layer 401 are different dielectric layers, and there is an etching selectivity between them.

[0055] like Figure 2E As shown, the second dielectric layer 401 is fully etched to form sidewalls 402 on both sides of the first dielectric layer 301.

[0056] like Figure 2F As shown, the first dielectric layer 301 is removed. The method of removing the first dielectric layer 301 can be dry etching or wet etching. There is no restriction on the method of removing the first dielectric layer 301.

[0057] like Figure 2GAs shown, the gate structure metal layer is etched using the two sidewalls 402 as hard masks, that is, the metal layer 202 is etched, the gate dielectric 206 and the remaining metal layer 204 are used to form two gate structures, which we refer to as the first gate structure and the second gate structure, respectively.

[0058] In this embodiment, the method further includes forming a first source structure and a first drain structure on both sides of the first gate structure, and forming a second source structure and a second drain structure on both sides of the second gate structure. It also includes forming a metal interconnect structure. The processes for forming the first source structure, the first drain structure, the second source structure, and the second drain structure, as well as the process for forming the metal interconnect structure, are consistent with those in Embodiment 2 and will not be repeated here.

[0059] like Figures 3A-3E As shown, Figures 3A-3E The diagram shows the structure of each step of the HEMT device according to Embodiment 4 of the present invention. This embodiment uses a monolithically integrated HEMT device as an example for illustration. Figure 1A-1I As shown, the process of forming the first gate structure 20 and the second gate structure is consistent with the steps of forming the first gate structure and the second gate structure in Embodiment 2, and will not be repeated here. Furthermore, as... Figure 3A As shown, a first source structure 602 and a first drain structure 601 are formed on both sides of the first gate structure 20, and a second source structure 604 and a second drain structure 603 are formed on both sides of the second gate structure 21, respectively. In this embodiment, the first source structure 602 and the second source structure 604 share a single source structure. Furthermore, a third source structure 605 and a third drain structure 606 are formed on the same side outside the first gate structure 20 and the second gate structure 21, as shown... Figure 3A As shown, in this embodiment, the third source structure 605 and the third drain structure 606 are formed on the right side outside the first gate structure 20 and the second gate structure 21. In other embodiments, the third source structure 605 and the third drain structure 606 can also be formed together on the left side outside the first gate structure 20 and the second gate structure 21. The third source structure 605 and the third drain structure 606 are formed simultaneously with the first source structure 602 and the first drain structure 601, as well as the second source structure 604 and the second drain structure 603.

[0060] like Figure 3B As shown, after removing the uneven portion at the top of the first passivation layer 501, that is, after removing the portion of the first passivation layer 501 located above the first gate structure 20 and the second gate structure 21, a first passivation layer 502 with a relatively flat upper surface is obtained, as shown. Figure 3CAs shown, a second passivation layer 701 is then formed on the flat upper surface of the first passivation layer 502. The second passivation layer 701 covers the upper surface of the first passivation layer 502 and encapsulates the upper surfaces of the first source structure 602, the first drain structure 601, the second source structure 604, the second drain structure 603, the third source structure 605, and the third drain structure 606.

[0061] like Figure 3D As shown, a third gate structure 22 is formed. Specifically, the first passivation layer 502 and the second passivation layer 701 are etched to form a third gate structure contact hole. A gate dielectric layer (not shown) is formed at least on the sidewalls and bottom walls of the third gate structure contact hole. In this embodiment, the gate dielectric layer located on the sidewalls and bottom walls of the third gate structure contact hole is also located on the upper surface of the second passivation layer 701. In this embodiment, the gate dielectric layer located on the sidewalls and bottom walls of the third gate structure contact hole is also located on the upper surface of the second passivation layer 701 near the portion of the third gate structure contact hole.

[0062] Referring again to the 3D diagram, an isolation region 909 is formed between the first drain structure 601 and the third source structure 605. The isolation region extends from the upper surface of the barrier layer 104 into the channel layer 103 at least to block the 2DEG at the contact surface between the channel layer 103 and the barrier layer 104.

[0063] like Figure 3EAs shown, the method further includes forming a second metal interconnect structure 90. Specifically, a third passivation layer 901 is formed on the upper surface of the second passivation layer 701, the third passivation layer 901 covering the third gate structure 22; the third passivation layer 901 and the second passivation layer 701 are etched to form a plurality of vias, these vias exposing the upper surfaces of the first source structure 602, the first drain structure 601, the second source structure 604, the second drain structure 603, the third source structure 605, and the third drain structure 606, respectively; the third passivation layer 901, the second passivation layer 701, and the first passivation layer 502 are etched to form two vias, these two vias exposing the upper surfaces of the first gate structure 20 and the second gate structure 21, respectively; the third passivation layer 901 is etched to form a via, this via exposing the upper surface of the third gate structure 22. Metal is filled into these vias to form the second metal interconnect structure. The second metal interconnect structure 90 extends from the upper surface of the third passivation layer 901 to the upper surfaces of the gate structure, the source structure, and the drain structure. Furthermore, the second metal interconnect structure 90 contacts the first gate structure 20, the first source structure 602, the first drain structure 602, the second gate structure 21, the second source structure 604, the second drain structure 603, the third gate structure 22, the third source structure 605, and the third drain structure 606, respectively; these contacts are electrical connections.

[0064] Secondly, such as Figure 1K As shown, Figure 1M The diagram shown is a HEMT device structure diagram according to Embodiment 5 of the present invention. This embodiment provides a semiconductor device, which includes a bottom layer 10. The bottom layer includes at least a substrate layer 101 and a channel layer 103 located above the substrate layer 101, and a barrier layer 104 located on the upper surface of the channel layer 103; it also includes a first passivation layer 502 located above the bottom layer 10, a first gate structure 20 and a second gate structure 20 located above the bottom layer 10, and a first gate structure 20 and a second gate structure 20 located on both sides of the first gate structure 20. The system includes a source structure 602, a first drain structure 602, and a second source structure 604 and a second drain structure 603 located on both sides of the second gate structure 21. The first passivation layer 502 covers the first source structure 602, the first drain structure 601, and the first gate structure 20, and also covers the second source structure 604, the second drain structure 603, and the second gate structure 21. The first passivation layer 502 exposes the upper surfaces of the first source structure 602, the first drain structure 601, the second source structure 604, and the second drain structure 603.

[0065] Continue to refer to Figure 1KThe HEMT device is an enhancement-mode HEMT device. The gate structure includes a p-type doped group III-V compound layer 203 located on the upper surface of the barrier layer 104 and a metal layer 204 located on the upper surface of the group III-V compound layer 203. In this embodiment, the material 203 of the group III-V compound layer is one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium nitride (InAlN). The metal layer 204 can use existing gate metals suitable for HEMT devices, such as TiN or Ni / Au stacked structures that form Schottky contacts, but is not limited to these.

[0066] Continue to refer to Figure 1K In this embodiment, the first source structure 602, the first drain structure 601, the second source structure 604, and the second drain structure 603 extend at least to the upper surface of the barrier layer 104. In other embodiments, both the source structure 602 and the drain structure 601 extend into the barrier layer 104. In still other embodiments, both the source structure 602 and the drain structure 601 extend into the channel layer 103.

[0067] like Figure 1M As shown, the HEMT device further includes a first metal interconnect structure 80 and a second passivation layer 701 located on the upper surface of the first passivation layer 502. The second passivation layer 701 covers the upper surface of the first passivation layer 502 and encapsulates the upper surfaces of the first source structure 602, the first drain structure 601, the second source structure 604, and the second drain structure 603. The first metal interconnect structure 80 extends from the upper surface of the second passivation layer 701 to the upper surfaces of the first gate structure 20, the first source structure 602, the first drain structure 602, the second gate structure 21, the second source structure 604, and the second drain structure 603, respectively. The first metal interconnect structure 80 contacts the first gate structure 20, the first source structure 602, the first drain structure 602, the second gate structure 21, the second source structure 604, and the second drain structure 603; these contacts are electrical connections.

[0068] like Figure 2E As shown, Figure 2EThe diagram shown is a HEMT device structure according to Embodiment Six of the present invention. Unlike Embodiment Five, the HEMT device in this embodiment is a depletion-type HEMT device. In this embodiment, the underlying structure further includes a cap layer 205 located on the upper surface of the barrier layer 104, wherein the material of the cap layer 205 includes a III-V compound. The material 203 of the III-V compound layer is one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium nitride (InAlN). In this embodiment, the first gate structure and the second gate structure differ from the gate structure in Embodiment Five. Specifically, the gate structure in this embodiment includes a gate dielectric layer 206 located on the upper surface of the cap layer 205 and a gate metal layer 208 located on the upper surface of the gate dielectric layer 206. The gate dielectric layer 206 can be made of materials such as silicon nitride (SiN), other insulating materials such as silicon dioxide (SiO2), or a stack of nitride and oxide insulating materials. The gate metal layer 208 can use existing gate metals suitable for HEMT devices, such as TiN or Ni / Au stacks that form Schottky contacts, but is not limited to these.

[0069] like Figure 3E As shown, Figure 3E The diagram shown is a HEMT device structure diagram according to Embodiment 7 of the present invention. Unlike Embodiment 5, the HEMT device in this embodiment is a monolithically integrated HEMT device. This monolithically integrated HEMT device further includes: a third source structure 605 and a third drain structure 606 located on the same side outside the first gate structure 20 and the second gate structure 21; and a third gate structure 22 located between the third source structure 605 and the third drain structure 606. In this embodiment, the third source structure 605 and the third drain structure 606 have the same structure as the first source structure 602, the first drain structure 602, the second source structure 604, and the second drain structure 603 in Embodiment 5, and are formed in the same step. However, in this embodiment, the third gate structure 22 differs from the second gate structure 21 and the first gate structure 20 in Embodiment 5. In Embodiment 5, the second gate structure 21 and the first gate structure 20 are enhancement-mode gate structures, while in this embodiment, the third gate structure 22 is a depletion-mode gate structure.

[0070] like Figure 3EAs shown, the monolithically integrated HEMT device further includes an isolation region 909 located between the second drain structure 601 and the third source structure 605; wherein the isolation region 909 extends from the upper surface of the barrier layer 104 to at least the interior of the channel 103, and the isolation region 909 is used to block 2DEG at the contact surface between the channel layer 103 and the barrier layer 104.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A substructure is formed, the substructure comprising at least a base layer, a channel layer above the base layer, and a barrier layer on the upper surface of the channel layer. A material layer with a gate structure is formed above the barrier layer; A first dielectric layer is formed on the upper surface of a predetermined region of the material layer of the gate structure. A sidewall is formed on at least one side of the first dielectric layer; Remove the first dielectric layer. Using the sidewall as a mask, the material layer of the gate structure is etched to form the gate structure; A source structure and a drain structure are formed on both sides of the gate structure, respectively.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, When sidewalls are formed on both sides of the first dielectric layer, the gate structure includes a first gate structure and a second gate structure, the source structure includes a first source structure and a second source structure, and the drain structure includes a first drain structure and a second drain structure. The first source structure and the first drain structure are respectively located on both sides of the first gate structure, and the second source structure and the second drain structure are respectively located on both sides of the second gate structure.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method of forming the sidewall includes: A second dielectric layer is formed covering the upper surfaces of the gate structure material layer and the first dielectric layer; The second dielectric layer is fully etched to form at least one sidewall.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching ratio of the second dielectric layer to the first dielectric layer is greater than 3:

1.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material layer of the gate structure includes: a P-type doped group III-V compound material layer covering the upper surface of the barrier layer and a metal layer covering the upper surface of the P-type doped group III-V compound material layer.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The underlying structure also includes a cap layer formed on the upper surface of the barrier layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The material layers of the gate structure include: a gate dielectric layer covering the upper surface of the cap layer and a metal layer covering the upper surface of the gate dielectric layer.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, Methods for forming source and drain structures include: Remove the sidewalls; A first passivation layer is formed above the underlying structure, and the first passivation layer covers the gate structure; The first passivation layer is etched to form source contact holes and drain contact holes on both sides of the gate structure, and metal is filled in the source contact holes and drain contact holes to form source structure and drain structure.

9. The method for fabricating a semiconductor device according to claim 2, characterized in that, Methods for forming the first source structure, the first drain structure, the second source structure, and the second drain structure include: Remove the two side walls mentioned above; A first passivation layer is formed on top of the underlying structure, and the first passivation layer covers the first gate structure and the second gate structure. The first passivation layer is etched to form a first source contact hole and a first drain contact hole on both sides of the first gate structure and a second source contact hole and a second drain contact hole on both sides of the second gate structure. Metal is filled in the first source contact hole, the first drain contact hole, the second source contact hole, and the second drain contact hole to form a first source structure, a first drain structure, a second source structure, and a second drain structure.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, Both the first source contact hole and the second source contact hole are located between the first gate structure and the second gate structure.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The first source contact hole and the second source contact hole share a single source contact hole.

12. The method for fabricating a semiconductor device according to claim 8 or 11, characterized in that, The source contact hole and the drain contact hole extend at least to the upper surface of the barrier layer.

13. The method for fabricating a semiconductor device according to claim 8 or 11, characterized in that, The method further includes: A second passivation layer is formed on the upper surface of the first passivation layer, and the second passivation layer covers the first source structure, the first drain structure, the second source structure, and the second drain structure. A first metal interconnect structure is formed, which extends from the upper surface of the second passivation layer to the upper surfaces of the gate structure, the source structure, and the drain structure.

14. The method for fabricating a semiconductor device according to claim 2, characterized in that, The preparation method further includes: A first source structure and a first drain structure are formed on both sides of the first gate structure, and a second source structure and a second drain structure are formed on both sides of the second gate structure. as well as A third source structure and a third drain structure are formed on the same side outside the first gate structure and the second gate structure. The third source structure and the third drain structure are formed synchronously with the first source structure, the first drain structure, the second source structure, and the second drain structure.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The preparation method further includes: A third gate structure is formed between the third source structure and the third drain structure.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, Methods for forming the third gate structure include: A second passivation layer is formed on the upper surface of the first passivation layer, and the second passivation layer covers the first source structure, the first drain structure, the second drain structure, the third source structure, and the third drain structure. The first and second passivation layers are etched to form the third gate structure contact hole. A gate dielectric layer is formed on at least the sidewall and bottom wall of the third gate structure contact hole; A third gate structure is formed by filling the gate dielectric layer with metal.

17. The method for fabricating a semiconductor device according to claim 16, characterized in that, The method further includes: A third passivation layer is formed on the upper surface of the second passivation layer, and the third passivation layer covers the third gate structure; A second metal interconnect structure is formed, which extends from the upper surface of the third passivation layer to the upper surfaces of the gate structure, the source structure, and the drain structure.

18. A semiconductor device, characterized in that, The device includes: The underlying structure includes at least a base layer and a channel layer located above the base layer, and a barrier layer located on the upper surface of the channel layer; The first passivation layer is located above the underlying structure. The first gate structure and the second gate structure are located above the underlying structure. The first source structure and the first drain structure are located on both sides of the first gate structure, and the second source structure and the second drain structure are located on both sides of the second gate structure. The first passivation layer covers the first source structure, the first drain structure, and the first gate structure, as well as the second source structure, the second drain structure, and the second gate structure, and exposes the upper surfaces of the first source structure, the first drain structure, the second source structure, and the second drain structure.

19. The semiconductor device according to claim 18, characterized in that: The first gate structure and the second gate structure include: The barrier layer consists of a P-type doped group III-V compound material layer on its upper surface and a metal layer on its upper surface.

20. The semiconductor device according to claim 18, characterized in that: The underlying structure also includes a cap layer located on the upper surface of the barrier layer, wherein the material of the cap layer includes a group III-V compound.

21. The semiconductor device according to claim 20, characterized in that: The first gate structure and the second gate structure include: The gate dielectric layer is located on the upper surface of the cap layer, and the gate metal layer is located on the upper surface of the gate dielectric layer.

22. The semiconductor device according to claim 18, characterized in that: The first source structure, the first drain structure, the second source structure, and the second drain structure extend at least to the upper surface of the barrier layer.

23. The semiconductor device according to claim 18, characterized in that: The device also includes: A third source structure and a third drain structure located on the same side outside the first gate structure and the second gate structure; And a third gate structure located between the third source structure and the third drain structure.

24. The semiconductor device according to claim 23, characterized in that: The device also includes: The isolation region located between the second drain structure and the third source structure; The isolation zone extends from the upper surface of the barrier layer at least into the interior of the channel.

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