Nitride semiconductor transistor

Abstract

The present disclosure provides a nitride semiconductor transistor capable of improving distortion characteristics. The nitride semiconductor transistor includes: a nitride semiconductor layer having a channel layer and a barrier layer overlapping each other and having a first polarization in a first direction; a source electrode, a drain electrode, and a gate electrode in contact with the nitride semiconductor layer; a ferroelectric layer between the gate electrode and the drain electrode in plan view and having a second polarization in a second direction opposite to the first direction; the field plate is electrically connected to the source electrode and located above the nitride semiconductor layer, and the ferroelectric layer is located between the nitride semiconductor layer and the field plate.

Description

Technical Field

[0001] This disclosure relates to nitride semiconductor transistors. Background Technology

[0002] Previously, a high electron mobility transistor (HEMT) with a field plate connected to the source electrode was proposed.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: U.S. Patent Application Publication No. 2022 / 0302291

[0006] In recent years, there has been an increasing demand for further improvements in distortion characteristics. The distortion characteristics mentioned here refer to the distortion of the output amplitude relative to the input amplitude when a transistor is used as an amplifier (amplitude modulation: AM-AM characteristic). Summary of the Invention

[0007] The purpose of this disclosure is to provide a nitride semiconductor transistor that can improve distortion characteristics.

[0008] The nitride semiconductor transistor disclosed herein comprises: a nitride semiconductor layer having an overlapping channel layer and a barrier layer, and having a first polarization in a first direction; a source electrode, a drain electrode, and a gate electrode in contact with the nitride semiconductor layer; a ferroelectric layer located between the gate electrode and the drain electrode when viewed from above, and having a second polarization in a second direction opposite to the first direction; and a field plate electrically connected to the source electrode and located above the nitride semiconductor layer, wherein the ferroelectric layer is located between the nitride semiconductor layer and the field plate.

[0009] Invention Effects

[0010] According to this disclosure, distortion characteristics can be improved. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view showing the nitride semiconductor transistor of the first embodiment.

[0012] Figure 2 This is a diagram illustrating an example of the band structure of a nitride semiconductor transistor according to the first embodiment.

[0013] Figure 3 This is one of the diagrams illustrating the characteristics of a nitride layer semiconductor transistor.

[0014] Figure 4 This is Figure 2, which illustrates the characteristics of nitride layer semiconductor transistors.

[0015] Figure 5 This is a cross-sectional view (one of) showing a method for manufacturing a nitride semiconductor transistor according to the first embodiment.

[0016] Figure 6 This is a cross-sectional view (part two) showing the manufacturing method of the nitride semiconductor transistor according to the first embodiment.

[0017] Figure 7 This is a cross-sectional view (part 3) showing the manufacturing method of the nitride semiconductor transistor according to the first embodiment.

[0018] Figure 8 This is a cross-sectional view (fourth in a series) showing the manufacturing method of the nitride semiconductor transistor according to the first embodiment.

[0019] Figure 9 This is a cross-sectional view (part 5) showing the manufacturing method of the nitride semiconductor transistor according to the first embodiment.

[0020] Figure 10 This is a cross-sectional view showing the nitride semiconductor transistor of the second embodiment.

[0021] Figure 11 This is a cross-sectional view showing the nitride semiconductor transistor of the third embodiment.

[0022] Explanation of reference numerals in the attached figures:

[0023] 1, 2, 3: Nitride semiconductor transistors;

[0024] 10: Substrate;

[0025] 20: Nitride semiconductor layer;

[0026] 20A: Top surface;

[0027] 20D, 20S: concave part;

[0028] 21: Buffer layer;

[0029] 22: Channel layer;

[0030] 23: Barrier layer;

[0031] 25: Two-dimensional electron gas;

[0032] 31, 32: Insulating film;

[0033] 31D, 31F, 31G, 31S, 32F: Openings;

[0034] 42D: Drain electrode;

[0035] 42S: Source electrode;

[0036] 43: Gate electrode;

[0037] 45: Field board;

[0038] 45A: Part One;

[0039] 45B: Part Two;

[0040] 45C: Part Three;

[0041] 50: Ferroelectric layer;

[0042] E: Electric field;

[0043] P1, P2: Polarization. Detailed Implementation

[0044] [Description of embodiments of this disclosure]

[0045] First, the implementation plan disclosed herein will be listed for illustration.

[0046] (1) A nitride semiconductor transistor of one aspect of the present disclosure has: a nitride semiconductor layer having an overlapping channel layer and a barrier layer and having a first polarization in a first direction; a source electrode, a drain electrode and a gate electrode in contact with the nitride semiconductor layer; a ferroelectric layer located between the gate electrode and the drain electrode when viewed from above and having a second polarization in a second direction opposite to the first direction; and a field plate electrically connected to the source electrode and located above the nitride semiconductor layer, wherein the ferroelectric layer is located between the nitride semiconductor layer and the field plate.

[0047] A ferroelectric layer is positioned between the nitride semiconductor layer and the field plate. The nitride semiconductor layer has a first polarization, and the ferroelectric layer has a second polarization in the opposite direction to the first polarization. Therefore, when viewed from above, the depletion layer easily expands in the region between the gate and drain electrodes. Even if the source-drain current increases, the capacitance between the gate and drain electrodes and the capacitance between the drain and source electrodes do not easily increase. This improves the distortion characteristics (AM-AM characteristic) of the output amplitude relative to the input amplitude.

[0048] (2) In (1), the nitride semiconductor transistor may also have: a first insulating film on the nitride semiconductor layer, having a first opening extending to the nitride semiconductor layer; and a second insulating film on the first insulating film, having a second opening extending to the first insulating film, wherein the gate electrode contacts the nitride semiconductor layer via the first opening, and the ferroelectric layer contacts the first insulating film via the second opening. In this case, the gate electrode and the ferroelectric layer are easily and stably formed.

[0049] (3) In (1) or (2), the ferroelectric layer may also be a nitride layer comprising aluminum and at least one selected from the group consisting of scandium, boron and yttrium. In this case, large remanent polarization is readily obtained in the ferroelectric layer.

[0050] (4) In (3), the ferroelectric layer may also be an aluminum scandium nitride layer, wherein the ratio of the number of scandium atoms to the total number of aluminum atoms and the scandium atoms in the aluminum scandium nitride layer is less than or equal to 40%. In this case, the aluminum scandium nitride layer is more likely to have a wurtzite-type crystal structure.

[0051] (5) In (3), the ferroelectric layer may also be an aluminum yttrium nitride layer, wherein the ratio of the number of yttrium atoms to the total number of aluminum atoms and the total number of yttrium atoms is less than or equal to 80%. In this case, the aluminum yttrium nitride layer is more likely to have a wurtzite-type crystal structure.

[0052] (6) In (1) or (2), the ferroelectric layer may also be a hafnium oxide layer comprising at least one selected from the group consisting of zirconium, yttrium, lanthanum, and silicon. In this case, large remanent polarization is readily obtained in the ferroelectric layer.

[0053] (7) In (1) or (2), the ferroelectric layer may also be an oxide layer comprising at least one selected from the group consisting of barium, bismuth, lead, and titanium, and having a perovskite-type crystal structure. In this case, large remanent polarization is readily obtained in the ferroelectric layer.

[0054] (8) In any of (1) to (7), the nitride semiconductor layer may have a first surface for contact with the gate electrode, the first surface having metallic polarity. In this case, the nitride semiconductor layer is easily and stably formed.

[0055] [Details of the embodiments disclosed herein]

[0056] The embodiments of this disclosure will now be described in detail, but this disclosure is not limited thereto. It should be noted that in this specification and accompanying drawings, sometimes repeated descriptions are omitted by using the same reference numerals to denote constituent elements having substantially the same functional configuration. In this disclosure, "top view" refers to viewing an object from above. In this disclosure, the direction in which the nitride semiconductor layer is located when viewed from the substrate is defined as upward.

[0057] (First Implementation)

[0058] The first embodiment relates to a nitride semiconductor transistor. A nitride semiconductor transistor is, for example, a gallium nitride-based high electron mobility transistor (HEMT). Figure 1 This is a cross-sectional view showing the nitride semiconductor transistor of the first embodiment.

[0059] like Figure 1 As shown, the nitride semiconductor transistor 1 of the first embodiment has a substrate 10, a nitride semiconductor layer 20, a ferroelectric layer 50, an insulating film 31, an insulating film 32, a gate electrode 43, a source electrode 42S, a drain electrode 42D, and a field plate 45.

[0060] The substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the substrate 10 is a SiC substrate, the upper surface of the substrate 10 is a silicon (Si) polar surface.

[0061] The nitride semiconductor layer 20 has a buffer layer 21, a channel layer 22, and a barrier layer 23. The nitride semiconductor layer 20 may also have a nucleation layer between the substrate 10 and the buffer layer 21. The nitride semiconductor layer 20 has an upper surface 20A. The upper surface 20A has metallic polarity. The upper surface 20A is an example of a first surface.

[0062] A buffer layer 21 is located on the substrate 10. The buffer layer 21 is, for example, a gallium nitride (GaN) layer. The thickness of the buffer layer 21 is, for example, greater than or equal to 100 nm and less than or equal to 2000 nm.

[0063] The channel layer 22 is situated above the buffer layer 21. The channel layer 22 has an upper surface with metallic polarity. The channel layer 22 is, for example, a gallium nitride (GaN) layer. The thickness of the channel layer 22 is, for example, greater than or equal to 5 nm and less than or equal to 40 nm. The conductivity type of the channel layer 22 is, for example, n-type or undoped (i-type). Alternatively, the buffer layer 21 and the channel layer 22 may not be distinguished.

[0064] Barrier layer 23 is situated above channel layer 22. Channel layer 22 and barrier layer 23 overlap each other. Barrier layer 23 has an upper surface with metallic polarity. Barrier layer 23 is, for example, an aluminum gallium nitride (AlGaN) layer. The electron affinity of barrier layer 23 is weaker than that of channel layer 22. The band gap of barrier layer 23 is larger than that of channel layer 22. The thickness of barrier layer 23 is, for example, greater than or equal to 5 nm and less than or equal to 40 nm. The composition of barrier layer 23 is, for example, Al. Y Ga 1－Y N (0.15≤Y≤0.55). That is, in the AlGaN layer, the ratio of the number of Al atoms to the total number of Al atoms and Ga atoms (Al composition ratio) is greater than or equal to 15% and less than or equal to 55%. The conductivity type of the barrier layer 23 is, for example, n-type or undoped (i-type).

[0065] The nitride semiconductor layer 20 has a polarization P1 extending from the upper surface 20A to the lower surface. Polarization P1 is an example of a first polarization.

[0066] An active electrode recess 20S and a drain electrode recess 20D are formed in the nitride semiconductor layer 20. The recesses 20S and 20D penetrate the barrier layer 23. The recesses 20S and 20D may also further penetrate the channel layer 22. The bottom of the recesses 20S and 20D may be located in the channel layer 22 or in the buffer layer 21.

[0067] An insulating film 31 is situated above the barrier layer 23. The insulating film 31 is, for example, a silicon nitride (SiN) film. The thickness of the insulating film 31 is, for example, greater than or equal to 5 nm and less than or equal to 100 nm. An opening 31S for the active electrode, an opening 31D for the drain electrode, and an opening 31G for the gate electrode are formed on the insulating film 31. Opening 31S is connected to a recess 20S, and opening 31D is connected to a recess 20D. When viewed from above, opening 31G is located between openings 31S and 31D. Opening 31G reaches the barrier layer 23. The insulating film 31 is an example of a first insulating film, and opening 31G is an example of a first opening.

[0068] The source electrode 42S is located above the channel layer 22 or the buffer layer 21 within the recess 20S. The drain electrode 42D is located above the channel layer 22 or the buffer layer 21 within the recess 20D. The source electrode 42S and the drain electrode 42D are in contact with the nitride semiconductor layer 20. The source electrode 42S and the drain electrode 42D are in ohmic contact with the nitride semiconductor layer 20.

[0069] When viewed from above, the gate electrode 43 is positioned between the source electrode 42S and the drain electrode 42D. The gate electrode 43 rests on the insulating film 31 and contacts the barrier layer 23 through the opening 31G.

[0070] A cap layer may also exist above the barrier layer 23. In the case where a cap layer exists above the barrier layer 23, the insulating film 31 is located above the cap layer, and the gate electrode 43 is in contact with the cap layer via the opening 31G. The cap layer is, for example, a gallium nitride (GaN) layer.

[0071] An insulating film 32 is situated above the insulating film 31, the source electrode 42S, the drain electrode 42D, and the gate electrode 43. The insulating film 32 covers the insulating film 31, the source electrode 42S, the drain electrode 42D, and the gate electrode 43. The insulating film 32 is, for example, a silicon nitride (SiN) film. The thickness of the insulating film 32 is, for example, greater than or equal to 5 nm and less than or equal to 100 nm. An opening 32F is formed in the insulating film 32, extending to the insulating film 31. When viewed from above, the opening 32F is located between the gate electrode 43 and the drain electrode 42D. Alternatively, an opening extending to the source electrode 42S, an opening extending to the drain electrode 42D, and an opening extending to the gate electrode 43 may also be formed in the insulating film 32.

[0072] The ferroelectric layer 50 is in contact with the insulating film 31 via an opening 32F. For example, the ferroelectric layer 50 is located inside the opening 32F. The ferroelectric layer 50 has a polarization P2 that extends from the lower surface to the upper surface. That is, the polarization P2 is oriented in the opposite direction to the polarization P1. When viewed from above, the ferroelectric layer 50 is located between the gate electrode 43 and the drain electrode 42D. Polarization P2 is an example of a second polarization.

[0073] Field plate 45 is positioned above insulating film 32 and ferroelectric layer 50, above nitride semiconductor layer 20. Field plate 45 has a first portion 45A, a second portion 45B, and a third portion 45C. First portion 45A overlaps with gate electrode 43 when viewed from above. Second portion 45B overlaps with ferroelectric layer 50 when viewed from above. Third portion 45C is located between first portion 45A and second portion 45B when viewed from above, connecting first portion 45A and second portion 45B. Field plate 45 is electrically connected to source electrode 42S. Ferroelectric layer 50 is located between nitride semiconductor layer 20 and field plate 45.

[0074] Here, an example of the band structure of a nitride semiconductor transistor 1 is described. Figure 2 This is a diagram showing an example of the band structure of the nitride semiconductor transistor 1 according to the first embodiment. Figure 2 The image shows the Fermi level EF and the lower end of the conduction band EC. In Figure 2 In the diagram, the horizontal axis represents the position of the portion containing the ferroelectric layer 50 in the direction from the upper surface to the lower surface of the nitride semiconductor transistor 1, and the vertical axis represents the energy referenced to the Fermi level EF.

[0075] In nitride semiconductor transistor 1, such as Figure 1 and Figure 2As shown, a two-dimensional electron gas (2DEG) 25 is generated near the upper surface of the channel layer 22. However, the ferroelectric layer 50 is located between the nitride semiconductor layer 20 and the field plate 45. The nitride semiconductor layer 20 has a polarization P1, and the ferroelectric layer 50 has a polarization P2 in the opposite direction to the polarization P1. Therefore, part of the polarization is canceled out, thereby reducing the two-dimensional electron gas 25 near the ferroelectric layer 50. As a result, the depletion layer tends to expand in the region between the gate electrode 43 and the drain electrode 42D when viewed from above. Even if the source-drain current Ids increases, the capacitance Cgd between the gate electrode 43 and the drain electrode 42D and the capacitance Cds between the drain electrode 42D and the source electrode 42S do not easily increase. Therefore, the distortion characteristics of the output amplitude relative to the input amplitude (AM-AM characteristic) can be improved. That is, the nonlinearity of the output power deviating from the proportional relationship due to saturation with respect to large input power can be reduced.

[0076] Figure 3 and Figure 4 The diagram illustrates the characteristics of two nitride-layer semiconductor transistors. The first example is an example following the first embodiment. The second example is an example from the first embodiment where no opening 32F is formed in the insulating film 32, no ferroelectric layer 50 is present, and the insulating film 32 is located between the nitride semiconductor layer 20 and the field plate 45. Figure 3 In the diagram, the horizontal axis represents the current Ids, and the vertical axis represents the capacitance Cgd. Figure 4 In the diagram, the horizontal axis represents the current Ids, and the vertical axis represents the capacitance Cds.

[0077] like Figure 3 and Figure 4 As shown, in the first example, compared to the second example, the capacitances Cgd and Cds do not easily increase when the current Ids increases. Therefore, according to the first example, the distortion characteristics can be improved compared to the second example.

[0078] The ferroelectric layer 50 is, for example, a nitride layer, a hafnium oxide layer, or an oxide layer with a perovskite crystal structure, having a wurtzite-type crystal structure.

[0079] Examples of nitride layers include aluminum (Al) and at least one element selected from the group consisting of scandium (Sc), boron (B), and yttrium (Y). In this case, a large remanent polarization is readily obtained in the ferroelectric layer 50. When the ferroelectric layer 50 is an aluminum scandium nitride layer, the aluminum scandium nitride layer tends to have a wurtzite-type crystal structure when the ratio of the number of Sc atoms in the aluminum scandium nitride layer to the total number of Al atoms and Sc atoms (Sc composition ratio) is less than or equal to 40%. When the ferroelectric layer 50 is an aluminum yttrium nitride layer, the aluminum yttrium nitride layer tends to have a wurtzite-type crystal structure when the ratio of the number of Y atoms in the aluminum yttrium nitride layer to the total number of Al atoms and Y atoms (Y composition ratio) is less than or equal to 80%. The ferroelectric layer 50 may further include gallium (Ga) or indium (In). When the ferroelectric layer 50 includes gallium, the coercive electric field of the ferroelectric layer 50 can be reduced.

[0080] The Sc and Y composition ratios can be determined, for example, by transmission electron microscope-energy dispersive X-ray spectroscopy (TEM-EDX), secondary ion mass spectrometry (SIMS), or X-ray photoelectron spectroscopy.

[0081] Examples of hafnium oxide layers include those composed of at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), lanthanum (La), and silicon (Si). In this case, large remanent polarization is readily obtained in the ferroelectric layer 50.

[0082] Examples of oxide layers with a perovskite-type crystal structure include oxide layers comprising at least one element selected from the group consisting of barium (Ba), bismuth (Bi), lead (Pb), and titanium (Ti). In this case, large remanent polarization is readily obtained in the ferroelectric layer 50.

[0083] The ferroelectric layer 50 may further comprise at least one element selected from the group consisting of indium (In), selenium (Se), molybdenum (Mo), and tellurium (Te).

[0084] It should be noted that the polarization direction of the ferroelectric layer 50 can be determined by measuring the electric field inside the ferroelectric layer 50 using a transmission electron microscope (TEM).

[0085] Next, the manufacturing method of the nitride semiconductor transistor 1 according to the first embodiment will be described. Figures 5-9 This is a cross-sectional view showing a method for manufacturing the nitride semiconductor transistor 1 according to the first embodiment.

[0086] First, such as Figure 5 As shown, for example, a buffer layer 21, a channel layer 22, and a barrier layer 23 are sequentially formed on a substrate 10 using metal-organic chemical vapor deposition (MOCVD). At this point, the upper surfaces of the buffer layer 21, the channel layer 22, and the barrier layer 23 possess metallic polarity, and a two-dimensional electron gas 25 is generated near the upper surface of the channel layer 22. The nitride semiconductor layer 20 has a polarization P1 extending from the upper surface 20A to the lower surface. Next, an insulating film 31 is formed on the barrier layer 23.

[0087] Next, as Figure 6 As shown, an opening 31S for the source and an opening 31D for the drain are formed in the insulating film 31, and a recess 20S for the source and a recess 20D for the drain are formed in the nitride semiconductor layer 20. The opening 31S, opening 31D, recess 20S, and recess 20D can be formed, for example, by using reactive ion etching (RIE) with a mask (not shown).

[0088] Next, a source electrode 42S is formed on the channel layer 22 or buffer layer 21 within the recess 20S, and a drain electrode 42D is formed on the channel layer 22 or buffer layer 21 within the recess 20D. In the formation of the source electrode 42S and the drain electrode 42D, firstly, a metal layer (not shown) constituting the source electrode 42S and the drain electrode 42D is formed. During the formation of the metal layer, for example, a growth mask (not shown) with openings in the region where the metal layer is formed is used for film deposition, and then the growth mask and the metal layer (not shown) formed thereon are removed together. That is, a stripping process is performed.

[0089] Next, an opening 31G for the gate is formed on the insulating film 31. The opening 31G can be formed, for example, using a RIE (Relative Insulation Layer) with a mask (not shown). Then, a gate electrode 43 is formed on the insulating film 31, contacting the barrier layer 23 via the opening 31G. During the formation of the gate electrode 43, for example, a metal layer is deposited using a growth mask (not shown) with an opening formed in the region where the gate electrode 43 is formed, and then the growth mask and the metal layer (not shown) formed thereon are removed together. That is, a stripping process is performed.

[0090] Next, as Figure 7As shown, an insulating film 32 is formed on the insulating film 31, the source electrode 42S, the drain electrode 42D, and the gate electrode 43. Next, an opening 32F is formed on the insulating film 32. The opening 32F is formed, for example, using a RIE (Rear-Insulated Electrode) with a mask (not shown). Next, a ferroelectric layer 50 is formed that contacts the insulating film 31 via the opening 32F. The ferroelectric layer 50 can be formed, for example, by sputtering, CVD, electron beam epitaxy (MBE), or atomic layer deposition (ALD). At this point, the polarization of the ferroelectric layer 50 can be oriented in any direction.

[0091] Next, as Figure 8 As shown, a field plate 45 having a first portion 45A, a second portion 45B, and a third portion 45C is formed on the insulating film 32 and the ferroelectric layer 50. At this point, the field plate 45 is electrically insulated from the source electrode 42S. In the formation of the field plate 45, firstly, a metal layer (not shown) constituting the field plate 45 is formed. During the formation of the metal layer, for example, a growth mask (not shown) with openings formed in the region where the metal layer is formed is used for film formation, and then the growth mask and the metal layer (not shown) formed thereon are removed together. That is, a stripping process is performed.

[0092] Next, as Figure 9 As shown, by applying an electric field E greater than or equal to the coercive electric field of the ferroelectric layer 50, the ferroelectric layer 50 is made to have a polarization P2 in the opposite direction to the polarization P1. For example, the electric field E can be applied to the ferroelectric layer 50 by applying a voltage between the source electrode 42S and the field plate 45. Alternatively, the ferroelectric layer 50 can be heated to a temperature of about 500°C or less when controlling the polarization P2.

[0093] Next, the field plate 45 is electrically connected to the source electrode 42S. For example, a metal layer is formed that is connected to the field plate 45 and the source electrode 42S.

[0094] In this way, nitride semiconductor transistors can be manufactured.

[0095] The gate electrode 43 is in contact with the nitride semiconductor layer 20 through the opening 31G, and the ferroelectric layer 50 is in contact with the insulating film 31 through the opening 32F, thereby facilitating the stable formation of the gate electrode 43 and the ferroelectric layer 50.

[0096] The upper surface 20A of the nitride semiconductor layer 20 has metallic polarity, thereby facilitating the stable formation of the nitride semiconductor layer 20. The upper surface 20A of the nitride semiconductor layer 20 may also have nitrogen polarity.

[0097] It should be noted that there are no particular limitations on the method and timing for controlling the polarization of the ferroelectric layer 50. Furthermore, an insulating film 32 may be formed after the ferroelectric layer 50 is formed.

[0098] The depth of opening 32F is not particularly limited. Opening 32F may not penetrate the insulating film 32, or it may extend into the interior of the insulating film 31.

[0099] (Second Implementation)

[0100] The second embodiment differs from the first embodiment mainly in the composition of the ferroelectric layer 50. Figure 10 This is a cross-sectional view showing the nitride semiconductor transistor of the second embodiment.

[0101] like Figure 10 As shown, in the nitride semiconductor transistor 2 of the second embodiment, the ferroelectric layer 50 is not only located inside the opening 32F, but also on the upper surface of the insulating film 32.

[0102] The other configurations of the nitride semiconductor transistor 2 are the same as those of the nitride semiconductor transistor 1.

[0103] The same effect as that of nitride semiconductor transistor 1 can be achieved by using nitride semiconductor transistor 2.

[0104] (Third implementation method)

[0105] The third embodiment differs from the first embodiment mainly in the composition of the insulating film. Figure 11 This is a cross-sectional view showing the nitride semiconductor transistor of the third embodiment.

[0106] like Figure 11 As shown, in the nitride semiconductor transistor 3 of the third embodiment, an opening 31F is formed in the insulating film 31. When viewed from above, the opening 31F is located between the gate electrode 43 and the drain electrode 42D. The ferroelectric layer 50 contacts the barrier layer 23 via the opening 31F. For example, the ferroelectric layer 50 is located inside the opening 31F. Furthermore, the opening 32F is not formed in the insulating film 32.

[0107] The other configurations of the nitride semiconductor transistor 3 are the same as those of the nitride semiconductor transistor 1.

[0108] The same effect as that of nitride semiconductor transistor 1 can be achieved by using nitride semiconductor transistor 3.

[0109] During the formation of the nitride semiconductor transistor 3, the ferroelectric layer 50 can be formed after the insulating film 31 is formed, or the insulating film 31 can be formed after the ferroelectric layer 50 is formed. In addition, the opening 31F may not penetrate the insulating film 31, and the ferroelectric layer 50 may not be in contact with the barrier layer 23.

[0110] The embodiments have been described in detail above, but this disclosure is not limited to specific embodiments, and various modifications and alterations can be made within the scope of the claims.

Claims

1. A nitride semiconductor transistor, comprising: A nitride semiconductor layer having an overlapping channel layer and a barrier layer, and having a first polarization in a first direction; The source electrode, drain electrode, and gate electrode are in contact with the nitride semiconductor layer; The ferroelectric layer, when viewed from above, is located between the gate electrode and the drain electrode, and has a second polarization in a second direction opposite to the first direction; as well as The field plate, electrically connected to the source electrode, is located above the nitride semiconductor layer. The ferroelectric layer is located between the nitride semiconductor layer and the field plate.

2. The nitride semiconductor transistor according to claim 1, wherein, The nitride semiconductor transistor has: A first insulating film is disposed above the nitride semiconductor layer and has a first opening that reaches the nitride semiconductor layer; as well as A second insulating film is situated above the first insulating film and has a second opening extending into the first insulating film. The gate electrode contacts the nitride semiconductor layer via the first opening. The ferroelectric layer is in contact with the first insulating film through the second opening.

3. The nitride semiconductor transistor according to claim 1 or 2, wherein, The ferroelectric layer is a nitride layer comprising aluminum and at least one selected from the group consisting of scandium, boron and yttrium.

4. The nitride semiconductor transistor according to claim 3, wherein, The ferroelectric layer is an aluminum scandium nitride layer. In the aluminum scandium nitride layer, the ratio of the number of scandium atoms to the total number of aluminum atoms and the scandium atoms is less than or equal to 40%.

5. The nitride semiconductor transistor according to claim 3, wherein, The ferroelectric layer is an aluminum yttrium nitride layer. In the aluminum yttrium nitride layer, the ratio of the number of yttrium atoms to the total number of aluminum atoms and the total number of yttrium atoms is less than or equal to 80%.

6. The nitride semiconductor transistor according to claim 1 or 2, wherein, The ferroelectric layer is a hafnium oxide layer comprising at least one selected from the group consisting of zirconium, yttrium, lanthanum, and silicon.

7. The nitride semiconductor transistor according to claim 1 or 2, wherein, The ferroelectric layer is an oxide layer comprising at least one selected from the group consisting of barium, bismuth, lead and titanium, and having a perovskite-type crystal structure.

8. The nitride semiconductor transistor according to claim 1 or 2, wherein, The nitride semiconductor layer has a first surface for contact with the gate electrode. The first surface has metallic polarity.

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