LDMOS transistor architecture

Abstract

The invention relates to an LDMOS transistor architecture. A transistor is disclosed. The transistor includes a source region and a drain region having a first conductivity type. The transistor also includes a channel region adjacent to the source region and having a second conductivity type. The transistor also includes a drift region between the drain region and the channel region, the drift region having a drift region width less than a drain region width of the drain region. Further, the transistor includes a trench region on the first side and the second side of the drift region near the drift region.

Description

Technical Field

[0001] This disclosure relates in general to integrated circuit technology, and more particularly to laterally diffused metal-oxide-semiconductor transistors. Background Technology

[0002] Power electronic devices are used to control the conversion and distribution of electricity in many applications. Power transistors, such as laterally diffused metal-oxide-semiconductor transistors (LDMOS), are used in power electronic devices to handle voltages higher than those typically used in complementary MOS (CMOS) circuits. The breakdown voltage of an LDMOS transistor can be measured as the drain-source breakdown voltage with the gate and source shorted together.

[0003] The inventors of the embodiments disclosed herein have recognized that conventional techniques for increasing the breakdown voltage of power transistors (such as LDMOS transistors) can result in large footprint, additional processing costs, and / or reduced reliability. Embodiments of this disclosure can address one or more of these challenges. Attached Figure Description

[0004] A more complete understanding of this embodiment can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features.

[0005] Figure 1 A top view of a transistor according to an embodiment of the present disclosure is shown.

[0006] Figure 2 A perspective cross-sectional view of a transistor according to an embodiment of the present disclosure is shown.

[0007] Figure 3 A perspective cross-sectional view of a transistor according to an embodiment of the present disclosure is shown.

[0008] Figure 4 A top cross-sectional view of adjacent transistors according to an embodiment of the present disclosure is shown.

[0009] Figure 5 A top view of a transistor according to an embodiment of the present disclosure is shown.

[0010] Figure 6 A method for forming a transistor according to an embodiment of the present disclosure is shown. Detailed Implementation

[0011] Details of one or more embodiments are set forth in the following description and accompanying drawings. Other features will be apparent from the description, the drawings, and the claims. The disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended to be an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that embodiment.

[0012] Figure 1 A top view of a transistor 100 according to an embodiment of the present disclosure is shown. (As shown) Figure 1 As shown, transistor 100 can be a laterally diffused MOS (LDMOS) transistor, and therefore may also be referred to as an LDMOS or LDMOS transistor. As described in detail below, in some embodiments, transistor 100 can be an n-type metal-oxide-semiconductor transistor (NMOS transistor). In other embodiments, transistor 100 can be a p-type metal-oxide-semiconductor transistor (PMOS transistor).

[0013] Transistor 100 may include a body region 110, a source region 120, a gate 130, a channel region 140, an accumulation region 145, a drift region 150, and a drain region 160. The source region 120 and drain region 160 may have a first conductivity type. For example, in an embodiment where transistor 100 is an NMOS transistor, the source region 120 and drain region 160 may be n-type regions. And in an embodiment where transistor 100 is a PMOS transistor, the source region 120 and drain region 160 may be p-type regions. The source region 120 and drain region 160 may be disposed in a well region 104 having a second conductivity type opposite to the first conductivity type (e.g., ...). Figure 2 (As shown in the perspective view).

[0014] The body region 110 can also be disposed within the well region 104 and can have a higher doping type of the second conductivity than the well region 104. In an embodiment where transistor 100 is an NMOS transistor, the well region 104 and the body region 110 can be p-type regions. And in an embodiment where transistor 100 is a PMOS transistor, the well region 104 and the body region 110 can be n-type regions. Figure 1 As shown, in some embodiments, the body region 110 may be located near the source region 120. In other embodiments, the body region 110 may be located in the well region 104 at a distance from the source region 120. In some embodiments, the body region 110 and the source region 120 may be coupled together by one or more contacts and / or metal layers to couple the body of the transistor 100 to the source of the transistor 100.

[0015] Channel region 140 can be located near source region 120. For example, as... Figure 1 As shown, gate 130 may be formed on a portion of well region 104 adjacent to source region 120. Gate 130 may include a polysilicon layer and a gate dielectric formed on well region 104. A portion of well region 104 below gate 130 may form channel region 140. Therefore, channel region 140 may have a second conductivity type opposite to the first conductivity type. For example, in an embodiment where transistor 100 is an NMOS transistor, channel region 140 may be a p-type region. And in an embodiment where transistor 100 is a PMOS transistor, channel region 140 may be an n-type region.

[0016] During the fabrication of transistor 100, drift layer doping can be applied to well region 104 to form drift region 150. For example... Figure 1 As shown, drift region 150 can be located between drain region 160 and channel region 140. In some embodiments, drift layer doping can be applied not only to drift region 150 but also to the portion of well region 104 below gate 130. Therefore, drift layer doping can also form an accumulation region 145 below a portion of gate 130, and this accumulation region is located between channel region 140 and drift region 150. Drift layer doping can be of the same conductivity type but has a lower doping concentration than the doping of source region 120 and drain region 160. Therefore, accumulation region 145 and drift region 150 can have a first conductivity type with a lower doping concentration than source region 120 and drain region 160. Specifically, in embodiments where transistor 100 is an NMOS transistor, accumulation region 145 and drift region 150 can be n-type regions with a lower n-type doping concentration than source region 120 and drain region 160. Furthermore, in an embodiment where transistor 100 is a PMOS transistor, accumulation region 145 and drift region 150 may be p-type regions with a p-type doping concentration lower than that of source region 120 and drain region 160.

[0017] Although some implementation schemes may include, Figure 1 The accumulation region 145 is shown, but in other embodiments, the drift layer doped region may extend from the drift region 150 to the edge of the gate 130, but not beyond that edge. In such other embodiments, the accumulation region 145 may be omitted, and the channel region 140 may extend to the edge of the gate 130 and directly adjacent to the drift region 150. In such embodiments with or without the accumulation region 145, the drift region 150 may be referred to as being located between the drain region 160 and the channel region 140.

[0018] like Figure 1As shown in the top view, the drift region 150 can extend laterally from the accumulation region 145 below the gate 130 to the drain region 160. In the above-described embodiment without an accumulation region, the drift region 150 can extend laterally from the channel region 140 to the drain region 160. In some embodiments, the drift region 150 may have a drift region width 151 smaller than the drift region length 152. Furthermore, as... Figure 1 As shown, the drift region 150 may have a drift region width 151 smaller than the drain region width 161 of the drain region 160. For example, the drift region width 151 may be 75%, 50%, 25%, 10% or less of the drain region width 161. In some embodiments, the drift region width 151 may also be smaller than the source region width 121 of the source region 120 and smaller than the channel region width 141 of the channel region 140. For example, in some embodiments, the source region width 121, the channel region width 141 and the drain region width 161 may be equal to each other at a width greater than the drift region width 151 of the drift region 150.

[0019] like Figure 1 As shown in the top view, regions not occupied by active regions (such as body region 110, source region 120, channel region 140, accumulation region 145, drift region 150, and drain region 160) can be occupied by trench region 106. For example, trench region 106 may surround other features at the semiconductor surface of transistor 100, including body region 110, source region 120, channel region 140, accumulation region 145, drift region 150, and drain region 160. Particularly with respect to drift region 150, trench region 106 may be located near drift region 150 on a first side 154 and a second side 155 of drift region 150.

[0020] In some embodiments, trench region 106 may be formed of a dielectric material. For example, trench region 106 may comprise silicon dioxide. See below for reference. Figure 3 and Figure 4To explain further in detail, dielectric materials such as silicon dioxide can provide a more uniform electric field distribution than, for example, semiconductor materials such as silicon, silicon carbide, or gallium nitride. By confining the drift region 150 on a first side 154 and a second side 155 using trench region 106, such that the drift region 150 has a smaller drift region width 151 than the drain region width 161 of the drain region 160, the electric field distribution across the drift region 150 can be controlled by the silicon dioxide surrounding the trench region 106 during operation of transistor 100. Therefore, the electric field generated by the drift region 150 during operation of transistor 100 can be more uniformly distributed, thereby enhancing the breakdown voltage of transistor 100 for a given area. Furthermore, by confining the sides of the drift region 150 using trench region 106, transistor 100 can conduct in a straight path from source region 120 through channel region 140 and drift region 150 to drain region 160. Therefore, an enhanced breakdown voltage of transistor 100 can be achieved without sacrificing a significant increase in the on-resistance of transistor 100.

[0021] Figure 2 A perspective cross-sectional view of a transistor 100 according to an embodiment of the present disclosure is shown. Figure 2 As shown, the well region 104 can be formed in a semiconductor substrate including the epitaxial region 102. The semiconductor substrate and the epitaxial region 102 included therein can be formed of any suitable semiconductor material such as silicon, silicon carbide, or gallium nitride. And as referenced above... Figure 1 Each of the main region 110, source region 120, channel region 140, drift region 150 and drain region 160 can be disposed in the well region 104.

[0022] like Figure 2 As shown in the perspective view of the transistor 100, the trench region 106 may have a trench depth 107 greater than the drift region depth 157 of the drift region 150. Therefore, the trench region 106 can confine the drift region 150 to a first side 154 and a second side 155 of the drift region 150 over the entire drift region depth 157. Furthermore, by extending below the drift region depth 157 of the drift region 150, the trench region 106 can electrically isolate the transistor 100 from adjacent instances of transistors 100 and / or other circuit elements disposed in other adjacent regions of the well region 104.

[0023] Figure 3 A perspective cross-sectional view of a transistor 100 according to an embodiment of the present disclosure is shown. To open the view of the electric field lines 159, from... Figure 3 The perspective view of transistor 100 in the figure omits certain features of transistor 100. For example, Figure 3 The material of gate 130 and trench region 106 is omitted.

[0024] As described above, the breakdown voltage of a transistor such as transistor 100 can be measured as the drain-source breakdown voltage when the gate and source are shorted together. For example, in an embodiment where transistor 100 is an NMOS transistor, the breakdown voltage of transistor 100 can be measured as the drain voltage at which transistor 100 breaks down when the gate and source of transistor 100 are shorted together and grounded. When the gate and source of transistor 100 are shorted together, transistor 100 can remain in the off state, and there is no drain-to-source conduction. When a voltage is applied to the drain under these off-state conditions, this voltage will cause an electric field to emanate from the drain. For example, Figure 3 The diagram illustrates the electric field emanating from the drain region 160 when transistor 100 is an NMOS transistor, a voltage of 20 volts is applied to the drain of transistor 100, and both the source and gate of transistor 100 are kept at 0 volts. Each electric field line 159 can represent a 1-volt voltage drop in the electric field emanating from the drain region 160.

[0025] Dielectric materials such as silicon dioxide can provide a more uniform electric field distribution than, for example, semiconductor materials such as silicon, silicon carbide, or gallium nitride. For example, while semiconductor materials such as silicon can dissipate the electric field across a distance in a more exponential manner, dielectric materials such as silicon dioxide can dissipate the electric field across a distance in a more linear manner. By utilizing trench region 106 to confine the sides of drift region 150, such that drift region 150 has a smaller drift region width 151 than the drain region width 161 of drain region 160, the distribution of the electric field emanating from drain region 160 and across drift region 150 can be controlled by the silicon dioxide surrounding trench region 106. Therefore, due to the relative widths of drain region 160 and drift region 150, and the presence of trench region 106 confining the sides of drift region 150, Figure 3 The electric field lines 159 shown can be distributed more uniformly. By uniformly dissipating the electric field, congestion can be avoided, and the breakdown voltage of transistor 100 can be enhanced for a given area. Furthermore, by utilizing trench region 106 to confine the sides of drift region 150, transistor 100 can conduct along a straight path from source region 120 through channel region 140 and drift region 150 to drain region 160. Thus, an enhanced breakdown voltage of transistor 100 can be achieved without sacrificing a significant increase in on-resistance.

[0026] Figure 4 A top cross-sectional view of adjacent transistors according to an embodiment of the present disclosure is shown. Each of the first transistor 100a and the second transistor 100b can represent the above reference. Figures 1 to 3 An example of transistor 100 is described. For example... Figure 4As shown, the trench region 106 can separate the first transistor 100a and the second transistor 100b, and surround the various features of those respective transistors.

[0027] Figure 4 The diagram illustrates the electric field emanating from the drain region 160a when the first transistor 100a and the second transistor 100b are NMOS transistors, 20 volts are applied to the drain of the first transistor 100a, and both the source and gate of the first transistor 100a are kept at 0 volts, and the drain, source, and gate of the second transistor 100b are also kept at 0 volts. Each electric field line 159 can represent a 1-volt voltage drop in the electric field emanating from the drain region 160a.

[0028] As referenced above Figure 3 By utilizing the trench region 106 to confine the sides of the drift region 150a, the drift region 150a has a smaller drift region width than the drain region width of the drain region 160a. The distribution of the electric field emanating from the drain region 160a and across the drift region 150a can be controlled by the silicon dioxide surrounding the trench region 106. Therefore, due to the relative widths of the drain region 160a and the drift region 150a, and the presence of the trench region 106 confining the sides of the drift region 150a, the electric field lines 159 can be distributed more uniformly. By distributing the electric field lines 159 more uniformly from the drain region 160a along the direction of the drift region 150a, the distribution of these electric field lines 159 can also be more uniformly distributed in the direction toward the second transistor 100b. Therefore, in addition to enhancing the breakdown voltage of the first transistor 100a for a given area, the pitch of the first transistor 100a and the second transistor 100b can also be improved. Therefore, in power applications that require multiple instances of transistor 100, the total die area consumed by those instances of transistor 100 can be reduced.

[0029] Figure 5 A top view of a transistor 500 according to an embodiment of the present disclosure is shown. Figure 5 As shown, transistor 500 can be a laterally diffused MOS (LDMOS) transistor, and therefore may also be referred to as an LDMOS or LDMOS transistor. As described in detail below, in some embodiments, transistor 500 can be an NMOS transistor. In other embodiments, transistor 100 can be a PMOS transistor.

[0030] Transistor 500 may include a body region 510, a source region 520, a gate 530, a channel region 540, an accumulation region 545, a drift region 550, and a drain region 560. The source region 520 and drain region 560 may have a first conductivity type. For example, in an embodiment where transistor 500 is an NMOS transistor, the source region 520 and drain region 560 may be n-type regions. And in an embodiment where transistor 500 is a PMOS transistor, the source region 520 and drain region 560 may be p-type regions. The source region 520 and drain region 560 may be located in a well region having a second conductivity type opposite to the first conductivity type. For example, the source region 520 and drain region 560 may be located in a well region such as those referenced above. Figure 2 In the described well region 104.

[0031] The body region 510 can be located in the same well region as the source region 520 and drain region 560. The body region 510 can have a higher doping type of the second conductivity than the well region. In an embodiment where transistor 500 is an NMOS transistor, the body region 510 and the well region can be p-type regions. And in an embodiment where transistor 500 is a PMOS transistor, the body region 510 and the well region can be n-type regions. Figure 5 As shown, in some embodiments, the body region 510 may be located near the source region 520. In other embodiments, the body region 510 may be located in the well region at a distance from the source region 520. In some embodiments, the body region 510 and the source region 520 may be coupled together by one or more contacts and / or metal layers to couple the body of the transistor 500 to the source of the transistor 500.

[0032] Channel region 540 can be located near source region 520. For example, as Figure 5 As shown, gate 530 can be formed on a portion of the well region adjacent to source region 520. Gate 530 may include a polysilicon layer and a gate dielectric formed on the well region. The portion of the well region below gate 530 can thus form channel region 540. Therefore, channel region 540 may have a second conductivity type opposite to the first conductivity type. For example, in an embodiment where transistor 500 is an NMOS transistor, channel region 540 may be a p-type region. And in an embodiment where transistor 500 is a PMOS transistor, channel region 540 may be an n-type region.

[0033] During the fabrication of transistor 500, drift layer doping can be applied to the well region to form multiple drift region fingers, such as drift region fingers 550a, 550b, and 550c. Figure 5 As shown, transistor 500 may include a plurality of drift region fingers 550a, 550b, and 550c arranged in parallel between drain region 560 and channel region 540. Although in Figure 5 An embodiment of transistor 500 with three drift region fingers 550a, 550b, and 550c is shown, but other embodiments of transistor 500 may include any suitable number of drift region fingers to increase or decrease the cumulative width of the drift region fingers according to the current carrying capacity and on-state resistance requirements of a given application. For example, in applications requiring higher current carrying capacity and / or lower on-resistance, transistor 500 may include a larger number of drift region fingers, such as 4, 10, 20, 100, or more.

[0034] In some embodiments, drift layer doping can be applied not only to the plurality of drift region fingers 550a, 550b, and 550c, but also to the portion of the well region below the gate 530. Therefore, drift layer doping can also form an accumulation region 545 below a portion of the gate 530, and this accumulation region is located between the channel region 540 and each of the plurality of drift region fingers 550a, 550b, and 550c. The drift layer doping can be of the same conductivity type, but has a lower doping concentration than the doping of the source region 520 and the drain region 560. Therefore, the accumulation region 145 and each of the drift region fingers 550a, 550b, and 550c can have a first conductivity type with a lower doping concentration than the source region 520 and the drain region 560. Specifically, in an embodiment where transistor 500 is an NMOS transistor, the accumulation region 545 and the drift region fingers 550a, 550b, and 550c can be n-type regions with a lower n-type doping concentration than the source region 520 and the drain region 560. And in an embodiment where transistor 500 is a PMOS transistor, the accumulation region 545 and the drift region fingers 550a, 550b, and 550c can be p-type regions with a lower p-type doping concentration than the source region 520 and the drain region 560.

[0035] Although some implementations of transistor 500 may include such Figure 5 The accumulation region 545 is shown, but in other embodiments, the drift layer doped region may extend from the drift region fingers 550a, 550b, and 550c to the edge of the gate 530, but not beyond that edge. In such other embodiments, the accumulation region 545 may be omitted, and the channel region 540 may extend to the edge of the gate 530 and directly adjacent to the drift region fingers 550a, 550b, and 550c. In either embodiment with or without the accumulation region 545, the drift region fingers 550a, 550b, and 550c may be referred to as being located between the drain region 560 and the channel region 540.

[0036] like Figure 5As shown in the top view, drift region fingers 550a, 550b, and 550c can extend laterally from the accumulation region 545 below the gate 530 to the drain region 560. In the above-described embodiment without an accumulation region, drift region fingers 550a, 550b, and 550c can extend laterally from the channel region 540 to the drain region 560. In some embodiments, each of the plurality of drift region fingers 550a, 550b, and 550c may have a finger width 551 smaller than the finger length 552 of the drift region fingers. Furthermore, each of the plurality of drift region fingers 550a, 550b, and 550c may have a finger width 551 smaller than the drain region width 561 of the drain region 560. In some embodiments, the cumulative width of each of the plurality of drift region fingers 550a, 550b, and 550c may also be smaller than the drain region width 561 of the drain region 560. For example, the cumulative width of each of the plurality of drift region fingers 551, 550b and 550c may be 75%, 50%, 25%, 10% or less of the drain region width 561 of the drain region 560.

[0037] like Figure 5 As shown in the top view, regions not occupied by active regions (such as body region 510, source region 520, channel region 540, accumulation region 545, drift region 550, and drain region 560) may be occupied by trench region 506. For example, trench region 506 may surround other features at the semiconductor surface of transistor 500, including body region 510, source region 520, channel region 540, accumulation region 545, drift region 550, and drain region 560. With respect to the plurality of drift region fingers 550a, 550b, and 550c, trench region 506 may be located near each drift region finger on a first and second side of each drift region finger. Furthermore, trench region 506 may have a trench region depth greater than the drift region depth of each of the plurality of drift region fingers 550a, 550b, and 550c.

[0038] In some embodiments, trench region 506 may be formed of a dielectric material. For example, trench region 506 may comprise silicon dioxide. Similar to the reference above. Figure 3 and Figure 4As described, dielectric materials such as silicon dioxide can provide a more uniform electric field distribution than, for example, semiconductor materials such as silicon, silicon carbide, or gallium nitride. By limiting the drift region finger width of each of the plurality of drift region fingers 550a, 550b, and 550c using the drain region width 561 of the trench region 506 relative to the drain region 560, the electric field distribution across each of the plurality of drift region fingers 550a, 550b, and 550c during operation of the transistor 500 can be controlled by the silicon dioxide surrounding the trench region 506. Therefore, the electric field generated by the plurality of drift region fingers 550a, 550b, and 550c during operation of the transistor 500 can be more uniformly distributed, thereby enhancing the breakdown voltage of the transistor 500 for a given area.

[0039] Figure 6 A method 600 for forming a transistor according to an embodiment of the present disclosure is shown. Method 600 can be used with... Figure 6 The steps shown in the diagram can be performed in fewer or more steps. Furthermore, steps in method 600 can be omitted, repeated, performed in parallel, or combined with... Figure 6 The steps of method 600, though shown in order, may be executed sequentially or recursively. One or more steps of method 600, although shown in order, may be executed simultaneously or in a reordered manner.

[0040] Step 602 may include forming a well in the semiconductor substrate. For example, as referenced above. Figure 2 The well region 104 may be formed in a semiconductor substrate including the epitaxial region 102.

[0041] Step 604 may include forming a drift region in the well region between the channel region and the drain region. For example, as referenced above. Figure 1 and Figure 2 The drift region doping can be applied to form a drift region 150 in the well region 104. According to the further process steps described below, the drift region 150 can be formed between the region where the channel region 140 will be formed and the region where the drain region 160 will be formed.

[0042] Step 606 may include forming a trench region near the drift region on a first side and a second side of the drift region, wherein the trench region restricts the drift region on the first side and the second side of the drift region such that the drift region has a drift region width smaller than the drain region width of the drain region. For example, as referenced above. Figure 1 and Figure 2The trench region 106 may be located near the drift region 150 on a first side 154 and a second side 155 of the drift region 150, such that the drift region 150 has a drift region width 151 smaller than the drain region width 161 of the drain region 160. The trench region 106 can be formed by etching a semiconductor substrate region including the epitaxial region 102 and filling the etched region with silicon dioxide. In some embodiments, the trench region may be etched to a depth greater than the doping depth of the drift region. Therefore, the trench region 106 may have a trench depth greater than the drift region depth of the drift region 150.

[0043] Step 608 may include forming a gate over a portion of the well region. For example, as referenced above. Figure 1 and Figure 2 The gate 130 may be formed over a portion of the well region 104. The gate 130 may include a polysilicon layer and a gate dielectric formed over the well region 104. The portion of the well region 104 below the gate 130 may therefore serve as a channel region 140.

[0044] Step 610 may include forming a source region and a drain region in the well region. For example, as referenced above. Figure 1 and Figure 2 The source region 120 and drain region 160 may be formed in the well region 104. The source region 120 and drain region 160 may be formed of a first conductivity type opposite to the second conductivity type of the well region 104. For example, in an embodiment where transistor 100 is an NMOS transistor, the well region 104 may be formed as a p-type region, and the source region 120 and drain region 160 may be formed as n-type regions. And in an embodiment where transistor 100 is a PMOS transistor, the well region 104 may be formed as an n-type region, and the source region 120 and drain region 160 may be formed as p-type regions.

[0045] Step 612 may include forming a main region in the trap region. For example, as referenced above. Figure 1 and Figure 2 The body region 110 can be formed in the well region 104. In some embodiments, the body region 110 can be disposed in the well region 104 and can have a second conductivity type doping higher than that of the well region 104. Figure 1 As shown, the body region 110 may be formed adjacent to the source region 120. In other embodiments, the body region 110 may be formed at a distance from the source region 120 in the well region 104. In some embodiments, the body region 110 and the source region 120 may be coupled together by one or more contacts and / or metal layers to couple the body of the transistor 100 to the source of the transistor 100.

[0046] Although examples have been described above, other modifications and variations can be made from this disclosure without departing from the spirit and scope of these examples. The description of the various embodiments above exemplifies the principles of the invention. Based on the above disclosure, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to encompass all such variations and modifications.

Claims

1. A transistor, the transistor comprising: A source region having a first conductivity type; A channel region located near the source region and having a second conductivity type; Drain region, the drain region having the first conductivity type; A drift region is located between the drain region and the channel region, and the drift region has a drift region width smaller than the drain region width of the drain region. and The trench area is located near the drift area on the first and second sides of the drift area.

2. The transistor of claim 1, wherein the drift region has the first conductivity type and is at a lower doping concentration than the source region and the drain region.

3. The transistor of claim 1, wherein the trench region comprises silicon dioxide.

4. The transistor of claim 1, wherein the transistor is an NMOS transistor.

5. The transistor of claim 1, wherein the transistor is a PMOS transistor.

6. The transistor of claim 1, wherein the trench region has a trench depth greater than the drift region depth of the drift region.

7. The transistor of claim 1, wherein the width of the drift region is less than the length of the drift region.

8. The transistor of claim 1, further comprising an accumulation region located between the channel region and the drift region.

9. A transistor, the transistor comprising: A source region having a first conductivity type; A channel region located near the source region and having a second conductivity type; Drain region, the drain region having the first conductivity type; Multiple drift region fingers are arranged in parallel between the drain region and the channel region; and The groove region is located on the first and second sides of each drift region finger near each drift region finger.

10. The transistor of claim 9, wherein each of the plurality of drift region fingers has the first conductivity type and is at a lower doping concentration than the source region and the drain region.

11. The transistor of claim 9, wherein the trench region comprises silicon dioxide.

12. The transistor of claim 9, wherein the transistor is an NMOS transistor.

13. The transistor of claim 9, wherein the transistor is a PMOS transistor.

14. The transistor of claim 9, wherein the trench region has a trench depth greater than the drift region depth of each of the plurality of drift region fingers.

15. The transistor of claim 9, wherein each of the plurality of drift region fingers has a finger width smaller than the finger length of the drift region fingers.

16. The transistor of claim 9, further comprising an accumulation region located between the channel region and each of the plurality of drift region fingers.

17. A method for forming a transistor, the method comprising: A well region is formed in the semiconductor substrate; A drift region is formed in the well region between the channel region and the drain region; A trench region is formed on a first side and a second side of the drift region near the drift region, wherein the trench region defines the drift region on the first side and the second side of the drift region, such that the drift region has a drift region width smaller than the drain region width of the drain region; A gate is formed over a portion of the well region; as well as A source region and a drain region are formed in the well region.

18. The method of claim 17, wherein the width of the drift region is less than the length of the drift region.

19. The method of claim 17, wherein forming the trench region comprises etching a region of the semiconductor substrate and filling the region with silicon dioxide.

20. The method of claim 17, wherein the trench region has a trench depth greater than the drift region depth of the drift region.

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