Composite dielectric buried layer MOS structure and preparation method thereof

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a composite dielectric buried layer MOS structure which sequentially comprises a drain electrode, an epitaxial layer, a grid electrode and a composite dielectric from bottom to top, and the interior of the epitaxial layer comprises an N substrate layer located on the lower portion and an N diffusion layer located on the upper portion. An N well layer, a P well layer and a P + layer are formed on the left side and the right side of the interior of the N diffusion layer through ion implantation, the N well layer is located above the P well layer, the P + layer is located on the outer sides of the N well layer and the P well layer, and the composite medium covers the surface of the grid electrode and the upper surface of the epitaxial layer; and a metal layer is deposited and formed inside the composite medium and above the N well layer and the P + layer. According to the composite dielectric buried layer MOS structure, the composite dielectric covering the grid electrode and the upper surface of the epitaxial layer is introduced, and the metal layer is formed in the composite dielectric buried layer MOS structure in an embedded mode, so that three-dimensional isolation and integration of the grid electrode and the active region are achieved.

Description

Technical Field

[0001] This invention relates to the field of MOS semiconductor technology, and in particular to a composite dielectric buried MOS structure and its fabrication method. Background Technology

[0002] In existing MOS device structures, the gate and active region are typically isolated by a single dielectric layer, resulting in large parasitic capacitance. Furthermore, the source metal contact is usually positioned above the dielectric layer, leading to a longer current path and higher contact resistance. Simultaneously, to achieve electrical isolation between devices, shallow trench isolation or deep well regions are often required, which not only occupies valuable chip area but may also introduce latch-up effects and signal interference problems.

[0003] In addition, traditional lateral conductive structures have limitations such as high conduction loss and uneven heat dissipation in high voltage and high current applications, making it difficult to simultaneously meet the requirements of high integration, high performance and high reliability. Summary of the Invention

[0004] This invention provides a composite dielectric buried MOS structure and its fabrication method to solve existing technical problems, thereby solving the problem of excessive contact resistance caused by the source metallization path in the prior art.

[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a composite dielectric buried layer MOS structure, which includes, from bottom to top, a drain, an epitaxial layer, a gate, and a composite dielectric. The epitaxial layer includes an N-substrate layer located below and an N-diffusion layer located above. An N-well layer, a P-well layer, and a P+ layer are formed on the left and right sides of the interior of the N-diffusion layer by ion implantation. The N-well layer is located above the P-well layer, and the P+ layer is located outside the N-well layer and the P-well layer. The composite dielectric covers the surface of the gate and the upper surface of the epitaxial layer.

[0006] A metal layer is deposited inside the composite medium and above the N-well layer and the P+ layer; A hole is etched on the surface of the composite dielectric above the gate and the metal layer, and a source wiring layer and a gate wiring layer are deposited in the hole respectively; the source wiring layer is in direct contact with the metal layer, and the gate wiring layer is in direct contact with the gate.

[0007] Furthermore, an independent N- layer is formed inside the N-diffusion layer and below the P-well layer and P+ layer by ion implantation, and the independent N- layer is in direct contact with the P-well layer and P+ layer.

[0008] Furthermore, the N-diffusion layer is also a covering N-layer, which is located below the P-well layer and the P+ layer.

[0009] Furthermore, the N-substrate layer is in direct contact with the composite medium, which divides the N-layer into two parts, left and right.

[0010] Furthermore, the N-substrate layer has N+ layers formed on both sides by ion implantation.

[0011] Furthermore, the top end of the N+ layer penetrates and covers the N- layer before directly contacting the P+ layer, and the bottom end of the N+ layer penetrates the N substrate layer before directly contacting the drain.

[0012] Furthermore, the N-diffusion layer is also a covering N+ layer, which is located below the P-well layer and the P+ layer.

[0013] Furthermore, the N-substrate layer is in direct contact with the composite medium, which divides the N+ layer into two parts, left and right.

[0014] A method for fabricating a composite dielectric buried MOS structure specifically includes the following steps: S1. An N-type diffusion layer is formed on the surface of an N-type substrate by epitaxial growth; S2. Inside the N diffusion layer, on the left and right sides, a P well layer, an N well layer above the P well layer, and a P+ layer outside the N well layer and the P well layer are formed sequentially by ion implantation. S3. A gate is formed on the upper surface of the epitaxial layer by deposition and patterning processes; S4. Deposit a composite dielectric on the gate surface and the upper surface of the epitaxial layer to cover the entire structure surface; S5. A metal layer is formed inside the composite medium, at the position corresponding to the N-well layer and above the P+ layer, by deposition and etching processes. S6. Contact holes are formed by etching on the surface of the composite dielectric, at the positions corresponding to the gate and the metal layer; S7. Deposit conductive materials in the contact holes to form a source wiring layer electrically connected to the metal layer and a gate wiring layer electrically connected to the gate. S8. A drain is formed on the back side of the N substrate to complete the fabrication of the composite dielectric buried MOS structure.

[0015] The present invention provides a composite dielectric buried layer MOS structure and its fabrication method. Compared with the prior art, the advantages achieved by this method are as follows: 1. The composite dielectric buried MOS structure in this invention achieves three-dimensional isolation and integration between the gate and the active region by introducing a composite dielectric covering the gate and the upper surface of the epitaxial layer, and embedding a metal layer inside it. This structure effectively reduces the parasitic capacitance from the gate to the substrate, and significantly reduces the contact resistance by shortening the source metallization path, thereby improving the high-frequency response and switching efficiency of the device, and enhancing the overall integration density and operational reliability.

[0016] 2. By flexibly configuring doped regions such as independent N-layers, covered N-layers, or covered N+ layers in different embodiments, this invention allows the structure to adjust the drift region resistance and electric field distribution according to application requirements. This design improves breakdown voltage and withstand voltage stability while significantly reducing on-resistance by optimizing the vertical current path, thus balancing the needs of high-voltage applications and low-loss performance, and expanding the applicability of the device in power and high-frequency fields.

[0017] 3. The deep trench isolation design of the composite dielectric in this invention replaces the traditional shallow trench or well isolation process, which not only saves chip area but also effectively suppresses latch-up effects and signal crosstalk between devices. Combined with the vertical conductive channel formed by the N+ layers, this structure further improves the uniformity of current distribution and heat dissipation performance, and enhances the reliability and stability of the device under high temperature and high power conditions.

[0018] 4. This invention achieves efficient and controllable fabrication of the composite dielectric buried MOS structure through the orderly integration of steps such as epitaxial growth, ion implantation, dielectric deposition, and embedded metallization. The process flow is clear and compatible with existing semiconductor production lines, enabling consistent and repeatable device performance while ensuring structural accuracy and interface quality, which is conducive to the industrial application and promotion of this technology. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the metal layer and source wiring layer in this invention; Figure 3 This is a schematic diagram of the structure of Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of the structure of Embodiment 3 of the present invention; Figure 5 This is a schematic diagram of the structure of Embodiment 4 of the present invention; Figure 6 This is a schematic diagram of the structure of Embodiment 5 of the present invention.

[0020] In the figure: 1. Drain; 2. Gate; 3. Metal layer; 4. Source wiring layer; 5. Gate wiring layer; 6. Composite dielectric; 7. N-substrate layer; 8. N-diffusion layer; 9. N-well layer; 10. P-well layer; 11. P+ layer; 12. Independent N- layer; 13. Through N+ layer; 801. Covered N- layer; 802. Covered N+ layer. Detailed Implementation

[0021] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Example 1 like Figure 1 , Figure 2 As shown, according to one aspect of the present invention, a composite dielectric buried layer MOS structure is provided, which includes, from bottom to top, a drain 1, an epitaxial layer, a gate 2 and a composite dielectric 6. The epitaxial layer includes an N substrate layer 7 located below and an N diffusion layer 8 located above. An N well layer 9, a P well layer 10 and a P+ layer 11 are formed on the left and right sides of the interior of the N diffusion layer 8 by ion implantation. The N well layer 9 is located above the P well layer 10, and the P+ layer 11 is located outside the N well layer 9 and the P well layer 10. The composite dielectric 6 covers the surface of the gate 2 and the upper surface of the epitaxial layer. A metal layer 3 is deposited inside the composite dielectric 6 and above the N-well layer 9 and the P+ layer 11; a hole is etched on the surface of the composite dielectric 6 and above the gate 2 and the metal layer 3, and a source wiring layer 4 and a gate wiring layer 5 are deposited inside the hole respectively; the source wiring layer 4 is in direct contact with the metal layer 3, and the gate wiring layer 5 is in direct contact with the gate 2.

[0023] The composite dielectric 6 not only covers the surface of the gate 2, but also completely covers the upper surface of the epitaxial layer, and a metal layer 3 is embedded inside it, above the corresponding N-well layer 9 and P+ layer 11. The principle of its implementation is: by introducing the composite dielectric 6 as an integrated isolation and buried layer structure between the gate 2 and the subsequent wiring layer, and above the active region, and pre-depositing the metal layer 3 for source connection inside the dielectric, three-dimensional isolation and integration of the gate and source regions are achieved.

[0024] The advantages of this structure are that the composite dielectric 6, acting as a unified insulating layer, effectively reduces the parasitic capacitance between the gate 2 and the substrate, while the buried metal layer 3 shortens the current path of the source and reduces the contact resistance. The source wiring layer 4 and the gate wiring layer 5 are connected to the metal layer 3 and the gate 2 respectively through independent contact holes, simplifying the wiring design and improving the device's integration density and operational reliability.

[0025] Example 2 like Figure 3As shown, according to one aspect of the present invention, a composite dielectric buried MOS structure is provided, which includes, from bottom to top, a drain 1, an epitaxial layer, a gate 2 and a composite dielectric 6. The epitaxial layer includes an N substrate layer 7 located below and an N diffusion layer 8 located above. An N well layer 9, a P well layer 10 and a P+ layer 11 are formed on the left and right sides of the interior of the N diffusion layer 8 by ion implantation, wherein the N well layer 9 is located above the P well layer 10 and the P+ layer 11 is located outside the N well layer 9 and the P well layer 10.

[0026] In this embodiment, an independent N-layer 12 is formed inside the N-diffusion layer 8 and below the P-well layer 10 and P+ layer 11 by ion implantation. The independent N-layer 12 is in direct contact with the P-well layer 10 and P+ layer 11.

[0027] An additional independent N-layer 12 is formed inside the N-diffusion layer 8 and below the P-well layer 10 and P+ layer 11 through ion implantation. The principle behind this is that this independent N-layer 12, as a lightly doped drift region, is located below the P-type body region and can withstand a higher reverse voltage. Through its direct contact with the P-well layer 10 and P+ layer 11, the electric field distribution between the body region and the drift region is optimized.

[0028] The advantage of this improvement is that the independent N-layer 12 effectively widens the depletion region, significantly improving the device's breakdown voltage. Simultaneously, it helps alleviate the electric field concentration at the edge of the P-well layer 10, improving the device's breakdown voltage characteristics and high-temperature stability, making it more suitable for high-voltage operating environments.

[0029] Example 3 like Figure 4 As shown, according to one aspect of the present invention, a composite dielectric buried MOS structure is provided, which includes, from bottom to top, a drain 1, an epitaxial layer, a gate 2 and a composite dielectric 6. The epitaxial layer includes an N substrate layer 7 located below and an N diffusion layer 8 located above. An N well layer 9, a P well layer 10 and a P+ layer 11 are formed on the left and right sides of the interior of the N diffusion layer 8 by ion implantation, wherein the N well layer 9 is located above the P well layer 10 and the P+ layer 11 is located outside the N well layer 9 and the P well layer 10.

[0030] In this embodiment, the N-diffusion layer 8 is also a covering N-layer 801, which is located below the P-well layer 10 and the P+ layer 11. The N-substrate layer 7 is in direct contact with the composite medium 6, which divides the covering N-layer 801 into left and right parts.

[0031] The N-diffusion layer 8 is essentially a N-layer 801, which is physically divided into two independent parts in the middle region by the composite dielectric 6 above. The principle behind this is that the composite dielectric 6 extends downwards and directly contacts the N-substrate layer 7, thereby laterally dividing the originally continuous lightly doped N-type epitaxial layer, i.e., the N-layer 801, into two parts, forming two electrically isolated active regions.

[0032] The advantage of this structure lies in the high aspect ratio isolation achieved through composite dielectric 6, which replaces traditional shallow trench isolation or deep well isolation processes, greatly saving chip area. The devices on the left and right sides are electrically independent, effectively suppressing latch-up effects and mutual interference, making it particularly suitable for high-density, high-reliability integrated circuit designs.

[0033] Example 4 like Figure 5 As shown, according to one aspect of the present invention, a composite dielectric buried MOS structure is provided, which includes, from bottom to top, a drain 1, an epitaxial layer, a gate 2 and a composite dielectric 6. The epitaxial layer includes an N substrate layer 7 located below and an N diffusion layer 8 located above. An N well layer 9, a P well layer 10 and a P+ layer 11 are formed on the left and right sides of the interior of the N diffusion layer 8 by ion implantation, wherein the N well layer 9 is located above the P well layer 10 and the P+ layer 11 is located outside the N well layer 9 and the P well layer 10.

[0034] In this embodiment, the N-diffusion layer 8 is also a covering N-layer 801, which is located below the P-well layer 10 and the P+ layer 11. The N-substrate layer 7 is in direct contact with the composite medium 6, which divides the covering N-layer 801 into left and right parts.

[0035] In this embodiment, N+ layers 13 are formed on the left and right sides of the N substrate layer 7 by ion implantation. The top end of the N+ layer 13 penetrates and covers the N- layer 801 and then directly contacts the P+ layer 11, and the bottom end of the N+ layer 13 penetrates the N substrate layer 7 and then directly contacts the drain electrode 1.

[0036] N+ layers 13 are introduced on both sides of the N substrate 7. The principle of implementation is as follows: the N+ layers 13 are formed by high-concentration ion implantation. Starting from the back drain 1, they penetrate the N substrate 7, cover the N- layer 801, and finally make ohmic contact with the P+ layer 11, thus establishing a low-resistance vertical path for the source current from the P+ layer 11 to the back drain 1.

[0037] The core advantage of this design lies in its replacement of the traditional lateral source-drain current path with a vertical one. This vertical current path, running through layer N+13 as a low-resistance current channel, significantly reduces the device's on-resistance, thereby minimizing conduction losses. Simultaneously, the vertical current path facilitates heat dissipation and current distribution uniformity, enhancing the device's power handling capability and switching performance.

[0038] Example 5 like Figure 6 As shown, according to one aspect of the present invention, a composite dielectric buried MOS structure is provided, which includes, from bottom to top, a drain 1, an epitaxial layer, a gate 2 and a composite dielectric 6. The epitaxial layer includes an N substrate layer 7 located below and an N diffusion layer 8 located above. An N well layer 9, a P well layer 10 and a P+ layer 11 are formed on the left and right sides of the interior of the N diffusion layer 8 by ion implantation, wherein the N well layer 9 is located above the P well layer 10 and the P+ layer 11 is located outside the N well layer 9 and the P well layer 10.

[0039] In this embodiment, the N-diffusion layer 8 is also a covering N+ layer 802, which is located below the P-well layer 10 and the P+ layer 11. The N-substrate layer 7 is in direct contact with the composite medium 6, which divides the covering N+ layer 802 into left and right parts.

[0040] The lightly doped N- layer 801 is replaced with a heavily doped N+ layer 802, which is also divided into left and right parts by the composite dielectric 6. The principle behind this is that a highly doped N-type epitaxial layer is used as the N+ layer 802, directly connected to the N-substrate layer 7, significantly reducing the resistance of the entire drift region. The deep trench isolation effect of the composite dielectric 6 remains effective, ensuring lateral isolation of the device.

[0041] The main advantage of this change is that the extremely low bulk resistance of the N+ layer 802 further optimizes the vertical current flow, resulting in even lower on-resistance, making it particularly suitable for high-frequency or high-current applications where extremely low loss is required. At the same time, the heavily doped layer also helps improve the device's saturation current characteristics and electrostatic discharge immunity.

[0042] Example 6 like Figure 1 , Figure 2 As shown, a method for fabricating a composite dielectric buried MOS structure specifically includes the following steps: Step 1: An N-type diffusion layer 8 is formed on the surface of the N-type substrate 7 by epitaxial growth; An N-type single-crystal layer with controllable thickness and doping concentration is grown on an N-type substrate 7 using vapor phase epitaxy to form an N-diffusion layer 8, providing a foundation for subsequent well region and device fabrication. The advantages of this step are high crystal quality and uniform doping of the epitaxial layer, which effectively reduces defect density and improves overall device performance and consistency.

[0043] Step 2: On the left and right sides inside the N diffusion layer 8, a P well layer 10, an N well layer 9 above the P well layer, and a P+ layer 11 outside the N well layer and the P well layer are formed sequentially by ion implantation. A multi-masking and ion implantation process is employed to sequentially implant impurities such as boron and phosphorus, forming a well structure with vertical stacking and lateral spacing. The advantage of this step is that it allows for precise control of the depth, concentration, and profile of each well region, achieving excellent carrier isolation and electric field modulation, thus providing an optimized active region foundation for composite dielectric buried layer structures.

[0044] Step 3: Form gate 2 on the upper surface of the epitaxial layer through deposition and patterning processes; grow a gate dielectric layer on the cleaned silicon wafer surface, then deposit polysilicon or metal gate material, and define the gate 2 pattern through photolithography and etching processes.

[0045] The advantage of this step is that it forms a gate structure with excellent interface characteristics, provides a reliable control electrode for the device, and ensures good coverage and isolation with the subsequent composite dielectric 6.

[0046] Step 4: Deposit composite dielectric 6 on the surface of gate 2 and the upper surface of epitaxial layer to cover the entire structure surface; use chemical vapor deposition or other methods to sequentially deposit silicon oxide, silicon nitride or other high-k dielectric materials on the structure surface to form composite dielectric 6 with multilayer or gradient dielectric properties.

[0047] The advantage of this step is that the composite dielectric 6 not only provides excellent insulation and passivation effects and reduces the parasitic capacitance between the gate 2 and the substrate, but its buried layer design also creates space for the subsequent embedding of the metal layer 3, realizing the three-dimensional integration of the structure.

[0048] Step 5: Inside the composite dielectric 6, at the position corresponding to the N-well layer 9 and the P+ layer 11, a metal layer 3 is formed by deposition and etching processes; first, the composite dielectric 6 is etched to form a groove locally, and then conductive materials such as aluminum, copper or their alloys are deposited and planarized, so that the metal layer 3 is embedded inside the dielectric.

[0049] The advantage of this step is that by placing the source connection metal in front and embedding it in the dielectric, the path of current from P+ layer 11 to metal layer 3 is significantly shortened, effectively reducing contact resistance and parasitic inductance.

[0050] Step 6: On the surface of the composite dielectric 6, at the positions corresponding to the gate 2 and the metal layer 3, respectively, etch to form contact holes; using selective etching technology, precisely open vertical through holes in the composite dielectric 6 that reach the upper surface of the gate 2 and the upper surface of the metal layer 3 respectively.

[0051] The advantage of this step is that it enables independent, low-resistance contact windows between the gate and source metals, allowing for precise positioning of subsequent wiring layer connections and improving process alignment tolerance and connection reliability.

[0052] Step 7: Deposit conductive materials in the contact holes to form a source wiring layer 4 electrically connected to the metal layer 3 and a gate wiring layer 5 electrically connected to the gate 2; fill the contact holes with metal using a tungsten plug or copper damascene process, and pattern interconnect wires on the dielectric surface to form the source wiring layer 4 and the gate wiring layer 5, respectively.

[0053] The advantage of this step is that it achieves a low-resistance, high-reliability connection between the device electrodes and the external circuit, and the wiring layer is in direct contact with the embedded metal layer 3 and the gate 2, which further optimizes the current distribution and signal transmission performance.

[0054] Step 8: Drain 1 is formed on the back side of N substrate 7, completing the fabrication of the composite dielectric buried MOS structure. After thinning and cleaning the back side of the wafer, an ohmic contact metal layer is deposited or alloyed to form drain 1.

[0055] The advantage of this step is that it completes the construction of the vertical conductive path of the device, which allows the current path from the source to the drain 1 to be connected, and finally forms a composite dielectric buried layer MOS structure with low on-resistance, high voltage withstand and excellent isolation characteristics.

[0056] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A composite dielectric buried MOS structure, comprising, from bottom to top, a drain (1), an epitaxial layer, a gate (2), and a composite dielectric (6), wherein the epitaxial layer comprises an N-substrate layer (7) located below and an N-diffusion layer (8) located above, and an N-well layer (9), a P-well layer (10), and a P+ layer (11) formed on the left and right sides of the interior of the N-diffusion layer (8) by ion implantation, wherein the N-well layer (9) is located above the P-well layer (10), and the P+ layer (11) is located outside the N-well layer (9) and the P-well layer (10), characterized in that: The composite dielectric (6) covers the surface of the gate (2) and the upper surface of the epitaxial layer; A metal layer (3) is deposited inside the composite medium (6) and above the N-well layer (9) and the P+ layer (11). A hole is etched on the surface of the composite dielectric (6) above the gate (2) and the metal layer (3), and a source wiring layer (4) and a gate wiring layer (5) are deposited in the hole respectively; the source wiring layer (4) is in direct contact with the metal layer (3), and the gate wiring layer (5) is in direct contact with the gate (2).

2. The composite dielectric buried layer MOS structure according to claim 1, characterized in that: An independent N-layer (12) is formed inside the N-diffusion layer (8) and below the P-well layer (10) and P+ layer (11) by ion implantation. The independent N-layer (12) is in direct contact with the P-well layer (10) and P+ layer (11).

3. The composite dielectric buried layer MOS structure according to claim 1, characterized in that: The N-diffusion layer (8) is also a covering N-layer (801), which is located below the P-well layer (10) and the P+ layer (11).

4. The composite dielectric buried layer MOS structure according to claim 3, characterized in that: The N-substrate layer (7) is in direct contact with the composite medium (6), which divides the N-layer (801) into two parts, left and right.

5. The composite dielectric buried layer MOS structure according to claim 4, characterized in that: The N substrate layer (7) has N+ layers (13) formed on both sides by ion implantation.

6. The composite dielectric buried layer MOS structure according to claim 5, characterized in that: The top end of the N+ layer (13) penetrates and covers the N- layer (801) and then directly contacts the P+ layer (11), and the bottom end of the N+ layer (13) penetrates the N substrate layer (7) and then directly contacts the drain (1).

7. The composite dielectric buried layer MOS structure according to claim 1, characterized in that: The N-diffusion layer (8) is also a covering N+ layer (802), which is located below the P-well layer (10) and the P+ layer (11).

8. The composite dielectric buried layer MOS structure according to claim 7, characterized in that: The N substrate layer (7) is in direct contact with the composite medium (6), which divides the N+ layer (802) into two parts, left and right.

9. A method for fabricating a composite dielectric buried layer MOS structure, characterized in that, The composite dielectric buried layer MOS structure applied to claim 1, wherein the fabrication method of the composite dielectric buried layer MOS structure specifically includes the following steps: S1. An N-type diffusion layer (8) is formed on the surface of an N-type substrate (7) by epitaxial growth. S2. Inside the N diffusion layer (8), on the left and right sides, a P well layer (10), an N well layer (9) above the P well layer, and a P+ layer (11) outside the N well layer and the P well layer are formed sequentially by ion implantation. S3. A gate is formed on the upper surface of the epitaxial layer by deposition and patterning process (2). S4. Deposit composite dielectric (6) on the surface of gate (2) and the upper surface of epitaxial layer to cover the entire structure surface; S5. Inside the composite medium (6), at the position above the N-well layer (9) and the P+ layer (11), a metal layer (3) is formed by deposition and etching processes. S6. Contact holes are formed on the surface of the composite dielectric (6) at positions corresponding to the gate (2) and the metal layer (3); S7. Deposit conductive materials in the contact holes to form a source wiring layer (4) electrically connected to the metal layer (3) and a gate wiring layer (5) electrically connected to the gate (2). S8. A drain (1) is formed on the back side of the N substrate (7) to complete the fabrication of the composite dielectric buried MOS structure.

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