Thin film transistor, method of manufacturing same, and thin film transistor substrate and display device including same

Abstract

The invention relates to a thin film transistor, a method of manufacturing the same, and a thin film transistor substrate and a display device including the same. Another embodiment of the present invention seeks to provide a thin film transistor comprising: a source conductive layer and a drain conductive layer spaced apart from each other; the active layer is arranged between the source electrode conducting layer and the drain electrode conducting layer; and a gate electrode overlapping with the active layer, in which a direction from the drain conductive layer to the source conductive layer is referred to as a first direction, and a direction perpendicular to the first direction is referred to as a second direction, the active layer is disposed so as to stand in a direction not parallel to the first direction and the second direction, and the maximum length of the active layer in the second direction is longer than the minimum length of the active layer in the first direction.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0142981, filed on October 18, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a thin-film transistor and a method for manufacturing the same, as well as a thin-film transistor substrate and a display device including the thin-film transistor. Background Technology

[0004] Because thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching or driving elements in display devices such as liquid crystal displays or organic light-emitting devices.

[0005] Based on the material used to construct the active layer, thin-film transistors can be classified into amorphous silicon thin-film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin-film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin-film transistors in which oxide semiconductor is used as the active layer.

[0006] Recently, with the increase in pixel density of high-resolution or mobile displays, many pixels are crammed into confined spaces, and the area of ​​thin-film transistors (TFTs) is becoming increasingly smaller. In the past, as the area of ​​TFTs decreased, process costs increased due to limitations in patterning and etching processes, and they were potentially susceptible to the effects of large-area integration. Currently, ongoing research is underway to reduce the area of ​​TFTs while addressing these issues. Summary of the Invention

[0007] One object of the present invention is to provide a thin-film transistor having a short channel (including an active layer erected at an angle).

[0008] Another object of the present invention is to provide a thin-film transistor with improved reliability and mobility, comprising a source conductive layer and a drain conductive layer having different work functions.

[0009] Another object of the present invention is to provide a thin-film transistor with improved high junction stress (HJS) by providing multiple active layers with different mobility in the horizontal direction of a substrate.

[0010] Another object of the present invention is to provide a thin-film transistor with a reduced area.

[0011] Another object of the present invention is to provide a thin-film transistor substrate including such a thin-film transistor.

[0012] Another object of the present invention is to provide a display device including such a thin-film transistor.

[0013] An embodiment of the present invention for solving the above-mentioned technical problems provides a thin-film transistor, comprising: a source conductive layer and a drain conductive layer spaced apart from each other; an active layer disposed between the source conductive layer and the drain conductive layer; and a gate electrode overlapping the active layer, wherein the direction from the drain conductive layer to the source conductive layer is referred to as a first direction, and the direction perpendicular to the first direction is referred to as a second direction, the active layer is configured to stand (or stand upright) in a direction not parallel to the first direction and the second direction, and the maximum length of the active layer in the second direction is longer than the minimum length of the active layer in the first direction.

[0014] The active layer has a first side surface that contacts the source conductive layer and a second side surface that contacts the drain conductive layer. The first side surface and the second side surface are not parallel to the first direction and the second direction, but they can be parallel to each other.

[0015] The entire region of the active layer can overlap with the gate electrode.

[0016] The upper surface of the active layer, the upper surface of the source conductive layer, and the upper surface of the drain conductive layer can form a plane.

[0017] The thin-film transistor also includes a buffer layer, wherein the active layer is disposed on the buffer layer, and the lower surface of the active layer, the lower surface of the source conductive layer and the lower surface of the drain conductive layer can contact the buffer layer to form a plane.

[0018] The source conductive layer and the drain conductive layer can be made of different materials, and the work function of the source conductive layer can be less than the work function of the gate electrode, while the work function of the drain conductive layer can be greater than the work function of the gate electrode.

[0019] The active layer includes: a first active layer in contact with the source conductive layer; and a second active layer in contact with the drain conductive layer, wherein the second active layer does not contact the source conductive layer, and within a portion of the thickness of the active layer, any straight line parallel to the upper surface of the active layer can pass through both the first active layer and the second active layer.

[0020] The mobility of the second active layer can be greater than that of the first active layer.

[0021] The thin-film transistor also includes a gate insulating film located between the active layer and the gate electrode, and the upper surfaces of the first active layer and the second active layer can contact the gate insulating film.

[0022] The active layer also includes a third active layer located between the first active layer and the second active layer. The third active layer does not contact the source conductive layer, and within a portion of the thickness of the active layer, any straight line parallel to the upper surface of the active layer can pass through all the first active layer, the second active layer, and the third active layer.

[0023] The mobility of the third active layer can be greater than that of the first active layer but less than that of the second active layer.

[0024] The thin-film transistor also includes a gate insulating film between the active layer and the gate electrode, and the upper surfaces of the first active layer, the second active layer and the third active layer can contact the gate insulating film.

[0025] A groove is formed (or provided) on the upper surface of the active layer, and the thickness of the active layer may be less than the thickness of the source conductive layer and the thickness of the drain conductive layer.

[0026] A protrusion is formed (or disposed) on the upper surface of the active layer, and the thickness of the active layer may be greater than the thickness of the source conductive layer and the thickness of the drain conductive layer.

[0027] The upper surface of the active layer has a first length, and the lower surface of the active layer has a second length. The first length is shorter than the second length, and the first length and the second length can be measured along a direction parallel to the first direction.

[0028] At least a portion of the source conductive layer and at least a portion of the drain conductive layer may overlap with the gate electrode in a plane.

[0029] Another embodiment of the present invention provides a thin-film transistor substrate, comprising: a substrate (or base); a first thin-film transistor and a second thin-film transistor disposed on the substrate; the first thin-film transistor comprising: a first source conductive layer and a first drain conductive layer spaced apart from each other; a first sub-active layer disposed between the first source conductive layer and the first drain conductive layer; and a first gate electrode overlapping the first sub-active layer; and the second thin-film transistor comprising: a second source conductive layer and a second drain conductive layer spaced apart from each other; a second sub-active layer disposed between the second source conductive layer and the second drain conductive layer; and a second gate electrode overlapping the second sub-active layer, wherein the direction from the first drain conductive layer to the first source conductive layer is referred to as a first direction, and the direction perpendicular to the first direction is referred to as a second direction; the first sub-active layer and the second sub-active layer are configured to stand upright in a direction not parallel to the first direction and the second direction; the maximum length of the first sub-active layer in the second direction is greater than the minimum length of the first sub-active layer in the first direction, and the maximum length of the second sub-active layer in the second direction is greater than the minimum length of the second sub-active layer in the first direction.

[0030] The first source conductive layer and the second source conductive layer are integrally formed, and the first thin film transistor and the second thin film transistor can be connected in parallel.

[0031] The first sub-active layer has a third side surface in contact with the first source conductive layer, and the second sub-active layer has a fourth side surface in contact with the second source conductive layer. The third side surface and the fourth side surface may not be parallel to the first direction and the second direction, respectively.

[0032] The upper surfaces of the first drain conductive layer, the first sub-active layer, the first source conductive layer, the second source conductive layer, the second sub-active layer, and the second drain conductive layer can form a plane.

[0033] Another embodiment of the present invention provides a method for manufacturing a thin-film transistor, comprising the following steps: forming a buffer layer on a substrate; forming a first metal material layer on the buffer layer; forming an active material layer on the first metal material layer; forming a second metal material layer on the active material layer; performing a chemical mechanical polishing process to planarize the upper surfaces of the first metal material layer, the active material layer, and the second metal material layer, thereby forming a source conductive layer and a drain conductive layer spaced apart from each other, and an active layer disposed between the source conductive layer and the drain conductive layer; forming a gate insulating film on the source conductive layer, the drain conductive layer, and the active layer; forming a gate electrode on the gate insulating film, wherein the direction from the drain conductive layer to the source conductive layer is referred to as a first direction, and the direction perpendicular to the first direction is referred to as a second direction, the active layer is formed to stand upright in a direction not parallel to the first direction and the second direction, and the maximum length of the active layer in the second direction is longer than the minimum length of the active layer in the first direction.

[0034] The first metal layer and the second metal layer are made of different materials, and the work function of the second metal layer can be greater than that of the first metal layer.

[0035] Another embodiment of the present invention may provide a display device including the thin-film transistors described above. Attached Figure Description

[0036] The above and other objects, features and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0037] Figure 1 This is a plan view of a thin-film transistor according to an embodiment of the present invention.

[0038] Figure 2 This is a cross-sectional view of a thin-film transistor according to an embodiment of the present invention.

[0039] Figure 3This is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0040] Figure 4 This is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0041] Figure 5 This is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0042] Figure 6 This is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0043] Figure 7 This is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present invention.

[0044] Figure 8 for Figure 7 The circuit diagram of the thin-film transistor substrate is shown.

[0045] Figures 9A to 9H A process diagram illustrating the manufacturing process of a thin-film transistor substrate according to another embodiment of the present invention is provided.

[0046] Figure 10 This is a schematic diagram of a display device according to another embodiment of the present invention. Detailed Implementation

[0047] The advantages and features of this disclosure and its implementation methods will be illustrated by the embodiments described below with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0048] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to illustrate embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout this disclosure, similar reference numerals refer to similar elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where they are determined to unnecessarily obscure the focus of this disclosure.

[0049] When using the terms “comprising,” “having,” and “including” as described in this disclosure, an additional part may be added, unless only “only” is used. Singular terms may include plural forms unless otherwise stated.

[0050] When interpreting an element (or component), even if not explicitly described, the element (or component) is interpreted as including the error band.

[0051] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," or "near," one or more parts may be placed between two other parts, unless "only" or "directly (positively)" is used.

[0052] In this document, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used to readily describe the relationship between one element or group of elements shown in the figures and another element or group of elements. It should be understood that these terms are intended to cover different orientations of the devices other than those depicted in the figures. For example, if the devices shown in the figures are reversed, a device described as being “below” or “under” another device may be arranged “above” another device. Thus, the exemplary term “below or under” can include both “below or under” and “upper” orientations. Similarly, the exemplary term “upper” or “above” can include both “upper” and “below or under” orientations.

[0053] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” or “before,” discontinuous cases may be included unless “only” or “directly” is used.

[0054] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0055] It should be understood that the term "at least one" includes all combinations relating to any one item. For example, "at least one of the first element, the second element, and the third element" can include two or more elements selected from the first element, the second element, and the third element, as well as all combinations of each of the first element, the second element, and the third element.

[0056] As will be fully appreciated by those skilled in the art, the features of the various embodiments of this disclosure may be partially or completely coupled or combined with each other, and may interoperate with each other and be technically driven in various ways. Embodiments of this disclosure may be implemented independently of each other, or may be implemented together in an interdependent relationship.

[0057] Apart from the reference numerals for components in each figure describing embodiments of the present disclosure, the same components may have the same symbols as those that may be shown in other figures.

[0058] In the embodiments of this disclosure, for ease of description, the source electrode and the drain electrode are distinguished, and the source electrode and the drain electrode are interchangeable. A source electrode can be a drain electrode, and vice versa. Furthermore, the source electrode of any embodiment can be the drain electrode of another embodiment, and the drain electrode of any embodiment can be the source electrode of another embodiment.

[0059] In some embodiments of the present invention, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode; however, the embodiments of the present invention are not limited thereto. The source region can be the source electrode, and the drain region can be the drain electrode. Furthermore, the source region can be the drain electrode, and the drain region can be the source electrode.

[0060] Figure 1 This is a plan view of a thin-film transistor (100) according to an embodiment of the present invention. Figure 2 This is a cross-sectional view of a thin-film transistor (100) according to an embodiment of the present invention. Figure 3 This is a cross-sectional view of a thin-film transistor (200) according to an embodiment of the present invention. Figure 4 This is a cross-sectional view of a thin-film transistor (300) according to an embodiment of the present invention. Figure 5 This is a cross-sectional view of a thin-film transistor (400) according to an embodiment of the present invention. Figure 6 This is a cross-sectional view of a thin-film transistor (500) according to an embodiment of the present invention. Figures 2 to 6 It can correspond to along Figure 1 The cross-sectional view taken from line I-I'.

[0061] A thin-film transistor (100) according to an embodiment of the present invention includes: a source conductive layer (135) and a drain conductive layer (136) spaced apart from each other; an active layer (130); and a gate electrode (150).

[0062] According to one embodiment of the present invention, the source conductive layer (135), drain conductive layer (136), active layer (130) and gate electrode (150) of the thin film transistor (100) may be disposed on the substrate (110).

[0063] The components of the thin-film transistor (100) are described in detail below.

[0064] Glass or plastic can be used as the material for forming the substrate (110). Transparent plastics with flexible properties (e.g., polyimide) can be used as said plastic.

[0065] A light-blocking layer (not shown) may be disposed on a substrate (110). The light-blocking layer (not shown) blocks light incident from the substrate (110) and protects the active layer (130). If another structure is used as the light-blocking structure, the light-blocking layer (not shown) may be omitted.

[0066] According to one embodiment of the present invention, a buffer layer (120) may be disposed on a substrate (110).

[0067] The buffer layer (120) has insulating properties and protects the active layer (130). The buffer layer (120) may include at least one of insulating silicon oxide (SiOx), silicon nitride (SiNx), and metal oxide.

[0068] exist Figure 2 In this embodiment, the buffer layer (120) is shown as a single layer, but one embodiment of the invention is not limited thereto and may have multiple layers. In addition, another layer may be disposed between the substrate (110) and the buffer layer (120), and another layer may be disposed between the buffer layer (120) and the active layer (130).

[0069] According to one embodiment of the present invention, an active layer (130) is disposed on a buffer layer (120).

[0070] According to one embodiment of the present invention, the active layer (130) may be made of any of oxide semiconductor materials, low-temperature polycrystalline silicon (LTPS), and amorphous silicon (A-Si).

[0071] According to one embodiment of the present invention, source conductive layer (135) and drain conductive layer (136) spaced apart from each other may be disposed on buffer layer (120).

[0072] Figure 2 A configuration is shown in which the source conductive layer (135) and the drain conductive layer (136) are spaced apart from each other, and the active layer (130) is located between them.

[0073] According to one embodiment of the present invention, the direction from the drain conductive layer (136) to the source conductive layer (135) may be referred to as the first direction (X), and the direction perpendicular to the first direction (X) may be referred to as the second direction (Y).

[0074] For example, the first direction (X) may correspond to the horizontal direction of the substrate (110), and the second direction (Y) may correspond to the direction parallel to the straight line connecting the substrate (110) and the gate electrode (150) with the shortest distance.

[0075] According to one embodiment of the present invention, the active layer (130) may be configured to stand in a direction that is not parallel to the first direction (X) and the second direction (Y). Specifically, the active layer (130) may be configured to stand in a direction that is not parallel to either the first direction (X) or the second direction (Y).

[0076] For example, the maximum length of the active layer (130) in the second direction (Y) can be longer than the minimum length of the active layer (130) in the first direction (X). For example, the height of the active layer (130) can be greater than the length of the active layer (130). In this case, the height of the active layer (130) is measured in the second direction (Y), and the length of the active layer (130) is measured in the first direction (X).

[0077] According to one embodiment of the present invention, the active layer (130) is disposed at a certain angle to have a short channel. Therefore, the area of ​​the thin-film transistor can be reduced, and the manufacturing cost of the thin-film transistor can be reduced.

[0078] According to one embodiment of the present invention, the active layer (130) may have a first side surface (SS1) in contact with the source conductive layer (135) and a second side surface (SS2) in contact with the drain conductive layer (136).

[0079] For example, Figure 2 A first side surface (SS1) and a second side surface (SS2) are shown parallel to each other. The first side surface (SS1) refers to a surface in the active layer (130) that is not parallel to the first direction (X) while contacting the source conductive layer (135). Similarly, the second side surface (SS2) refers to a surface in the active layer (130) that is not parallel to the first direction (X) while contacting the drain conductive layer (136). For example, the first side surface (SS1) and the second side surface (SS2) may not be parallel to the first direction (X) and the second direction (Y).

[0080] According to one embodiment of the present invention, the active layer (130) may overlap with the gate electrode (150). According to one embodiment of the present invention, in a plan view, at least a portion of the source conductive layer (135) and at least a portion of the drain conductive layer (136) may overlap with the gate electrode (150). Alternatively, another portion of the source conductive layer (135) and another portion of the drain conductive layer (136) may not overlap with the gate electrode (150).

[0081] For example, Figure 1 and Figure 2 A view showing the entire region of the active layer (130) overlapping with the gate electrode (150) is shown. Figure 1 A view showing the entire region of the active layer (130) overlapping with the gate electrode (150) in a plan view is shown.

[0082] According to one embodiment of the present invention, the active layer (130) may have steps.

[0083] refer to Figure 2The steps of the active layer (130) can be regions formed by patterning the active layer (130). The steps of the active layer (130) can overlap with the gate electrode (150).

[0084] According to one embodiment of the present invention, the active layer (130) may have a top surface (TS1), a first side surface (SS1), a second side surface (SS2) and a bottom surface (BS1).

[0085] According to one embodiment of the present invention, the source conductive layer (135) may have an upper surface (TS2) and a lower surface (BS2).

[0086] According to one embodiment of the present invention, the drain conductive layer (136) may have an upper surface (TS3) and a lower surface (BS3).

[0087] refer to Figure 2 The upper surface (TS1) of the active layer (130), the upper surface (TS2) of the source conductive layer (135) and the upper surface (TS3) of the drain conductive layer (136) can form a plane.

[0088] For example, the plane formed by the upper surface (TS1) of the active layer (130), the upper surface (TS2) of the source conductive layer (135), and the upper surface (TS3) of the drain conductive layer (136) can be parallel to the first direction (X) and can be parallel to the upper surface of the substrate (110). For example, the upper surface (TS1) of the active layer (130), the upper surface (TS2) of the source conductive layer (135), and the upper surface (TS3) of the drain conductive layer (136) can contact the gate insulating film (140) to form a plane.

[0089] refer to Figure 2 The lower surface (BS1) of the active layer (130), the lower surface (BS2) of the source conductive layer (135), and the lower surface (BS3) of the drain conductive layer (136) can form a plane.

[0090] For example, the plane formed by the lower surface (BS1) of the active layer (130), the lower surface (BS2) of the source conductive layer (135), and the lower surface (BS3) of the drain conductive layer (136) can be parallel to the first direction (X) and can be parallel to the upper surface of the substrate (110). For example, the lower surface (BS1) of the active layer (130), the lower surface (BS2) of the source conductive layer (135), and the lower surface (BS3) of the drain conductive layer (136) can contact the buffer layer (120) to form a plane.

[0091] Specifically, the plane formed by the upper surface (TS1) of the active layer (130), the upper surface (TS2) of the source conductive layer (135), and the upper surface (TS3) of the drain conductive layer (136) can be parallel to the plane formed by the lower surface (BS1) of the active layer (130), the lower surface (BS2) of the source conductive layer (135), and the lower surface (BS3) of the drain conductive layer (136).

[0092] However, one embodiment of the invention is not limited thereto, and due to etching differences caused by material differences between the active layer (130), the source conductive layer (135), and the drain conductive layer (136), the active layer (130) may be over-etched or under-etched (see [reference]). Figure 5 and Figure 6 ).

[0093] According to one embodiment of the present invention, the source conductive layer (135) and the drain conductive layer (136) may each comprise at least one of gold (Au), nickel (Ni), copper (Cu), platinum (Pt), aluminum (Al), titanium (Ti), and chromium (Cr). However, one embodiment of the present invention is not limited thereto.

[0094] Specifically, the source conductive layer (135) and the drain conductive layer (136) can be made of different materials. For example, the work function of the source conductive layer (135) can be less than the work function of the gate electrode (150), and the work function of the drain conductive layer (136) can be greater than the work function of the gate electrode (150).

[0095] For example, when the work function of the gate electrode (150) is 4.7 eV, the work function of the source conductive layer (135) can be less than 4.7 eV, and the work function of the drain conductive layer (136) can be greater than 4.7 eV. In other words, the work function of the source conductive layer (135) and the work function of the drain conductive layer (136) can vary depending on the work function of the gate electrode (150). According to an embodiment of the present invention, the ranges of the work function values ​​of the source conductive layer (135) and the drain conductive layer (136) do not overlap.

[0096] For example, when the gate electrode (150) is made of copper (Cu), the source conductive layer (135) may include (or contain) at least one of aluminum (Al), titanium (Ti), nickel (Ni) and chromium (Cr), and the drain conductive layer (136) may include (or contain) at least one of gold (Au) and platinum (Pt).

[0097] When the work function of the source conductive layer (135) is less than the work function of the gate electrode (150), it becomes easier for carriers to be injected into the active layer (130), thereby improving the current characteristics of the thin film transistor.

[0098] Furthermore, when the work function of the drain conductive layer (136) is greater than that of the gate electrode (150), the carrier mobility from the active layer (130) to the drain conductive layer (136) is improved, thereby improving the current characteristics of the thin film transistor in the on state and improving the reliability of the thin film transistor.

[0099] Typically, for thin-film transistors, electrical contacts between the active layer and other components may require conductors. However, process errors can occur during the conductor-conducting process for the active layer.

[0100] According to the present invention, by directly contacting the active layer (130), the source conductive layer (135) and the drain conductive layer (136), a conductor-forming process can be eliminated, and therefore, process errors attributable to the conductor-forming process can be prevented.

[0101] According to one embodiment of the present invention, a gate insulating film (140) is disposed on the active layer (130). Specifically, the gate insulating film (140) is disposed between the active layer (130) and the gate electrode (150).

[0102] According to one embodiment of the present invention, the gate insulating film (140) may cover the entire upper surface of the active layer (130). Figure 2 A gate insulating film (140) covering the entire upper surface of multiple active layers (130) is shown.

[0103] The gate insulating film (140) may include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film (140) may have a single-film structure or a multilayer film structure. The gate insulating film (140) protects the active layer (130).

[0104] According to one embodiment of the present invention, the gate electrode (150) may be disposed on the gate insulating film (140).

[0105] According to one embodiment of the invention, the gate electrode (150) may overlap with the active layer (130). For example, see reference... Figure 2 The gate electrode (150) can overlap with the entire region of the active layer (130).

[0106] The gate electrode (150) may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode (150) may also have a multilayer film structure comprising at least two conductive films with different physical properties.

[0107] An interlayer insulating film (160) is disposed on the gate electrode (150). The interlayer insulating film (160) is an insulating layer made of insulating material. Specifically, the interlayer insulating film (160) can be made of organic material, inorganic material, or a laminate of organic and inorganic layers.

[0108] A source electrode (171) and a drain electrode (172) are disposed on an interlayer insulating film (160). The source electrode (171) and the drain electrode (172) are spaced apart from each other and are respectively connected to a source conductive layer (135) and a drain conductive layer (136). The source electrode (171) and the drain electrode (172) are connected to the source conductive layer (135) and the drain conductive layer (136) respectively through contact holes formed in the interlayer insulating film (160).

[0109] The source electrode (171) and drain electrode (172) may each comprise at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. The source electrode (171) and drain electrode (172) may each be formed using a single layer of metal or metal alloy, or may be formed using a multilayer comprising two or more layers.

[0110] According to one embodiment of the present invention, the active layer (130) may be formed of multiple layers. For example, the active layer (130) may include a first active layer (131) and a second active layer (132), such as Figure 3 As shown.

[0111] refer to Figure 3 The first active layer (131) may be in contact with the source conductive layer (135), and the second active layer (132) may be in contact with the drain conductive layer (136). For example, the second active layer (132) may not be in contact with the source conductive layer (135).

[0112] refer to Figure 3 Within a portion of the thickness of the active layer (130), any (or arbitrary) straight line parallel to the upper surface (TS1) of the active layer (130) may pass through both the first active layer (131) and the second active layer (132). For example, any (or arbitrary) straight line parallel to the upper surface of the substrate (110) may pass through both the first active layer (131) and the second active layer (132).

[0113] When a gate voltage is applied to the gate electrode (150), current can flow through the path of the active layer (130) closer to the gate electrode (150). According to one embodiment of the invention, the gate electrode (150) is disposed on the active layer (130). Therefore, when a gate voltage is applied to the gate electrode (150), current can flow through the upper region of the active layer (130), and can flow simultaneously through the upper regions of both the first active layer (131) and the second active layer (132).

[0114] According to one embodiment of the present invention, both the upper surface of the first active layer (131) and the upper surface of the second active layer (132) can be in contact with the gate insulating film (140). The upper surface (TS1) of the active layer (130) can be formed from the upper surface of the first active layer (131) and the upper surface of the second active layer (132).

[0115] According to one embodiment of the present invention, the mobility of the second active layer (132) may be greater than that of the first active layer (131). For example, the mobility of the second active layer (132) in contact with the drain conductive layer (136) may be greater than that of the first active layer (131) in contact with the source conductive layer (135).

[0116] Typically, high junction stress (HJS) refers to the stress that occurs when charge carriers move between two different media within a transistor, for example, between the source conductive layer (135) and the active layer (130) or between the active layer (130) and the drain conductive layer (136).

[0117] For example, when high junction stress (HJS) is applied to a thin-film transistor, mobility degradation may occur over time, which may degrade the current characteristics of the thin-film transistor.

[0118] When the mobility of the second active layer (132) is greater than that of the first active layer (131), the carrier movement in the second active layer (132) increases, thereby alleviating the high junction stress (HJS) in the thin-film transistor. Therefore, the current characteristics of the thin-film transistor can be improved.

[0119] For example, the mobility of the first active layer (131) can be as low as 1 cm. 2 / Vs to 10cm 2 Within the range of / Vs, and the mobility of the second active layer (132) can exceed 10 cm. 2 / Vs and equal to or less than 100cm 2 / Vs. However, embodiments of the present invention are not limited thereto.

[0120] According to one embodiment of the present invention, the active layer (130) may further include a third active layer (133) between the first active layer (131) and the second active layer (132), such as Figure 4 As shown.

[0121] refer to Figure 4 The second active layer (132) and the third active layer (133) may not be in contact with the source conductive layer (135). For example, the first active layer (131) may be disposed between the source conductive layer (135) and the third active layer (133), and the second active layer (132) may be disposed between the third active layer (133) and the drain conductive layer (136).

[0122] refer to Figure 4 Within a portion of the thickness of the active layer (130), any straight line parallel to the upper surface (TS1) of the active layer (130) can pass through all the first active layers (131), the second active layer (132), and the third active layer (133). For example, within a portion of the thickness of the active layer (130), any straight line parallel to the upper surface of the substrate (110) can pass through all the first active layers (131), the second active layer (132), and the third active layer (133).

[0123] When a gate voltage is applied to the gate electrode (150), current can flow through the active layer (130) along a path closer to the gate electrode (150). According to one embodiment of the invention, the gate electrode (150) is disposed on the upper portion of the active layer (130). Therefore, when a gate voltage is applied to the gate electrode (150), current can flow through the upper region of the active layer (130) and can flow simultaneously through the upper regions of the first active layer (131), the second active layer (132), and the third active layer (133).

[0124] According to one embodiment of the present invention, the upper surfaces of the first active layer (131), the second active layer (132), and the third active layer (133) can all be in contact with the gate insulating film (140). The upper surface (TS1) of the active layer (130) can be formed from the upper surfaces of the first active layer (131), the second active layer (132), and the third active layer (133).

[0125] The mobility of the third active layer (133) can be greater than that of the first active layer (131) and less than that of the second active layer (132). For example, the mobility can decrease in the order of the second active layer (132), the third active layer (133), and the first active layer (131).

[0126] According to one embodiment of the present invention, a groove (H1) may be formed (or disposed) on the upper surface (TS1) of the active layer (130), such as Figure 5 As shown. When the source conductive layer (135), active layer (130), and drain conductive layer (136) are etched, the active layer (130) may be over-etched due to the differences in material properties between the source conductive layer (135), active layer (130), and drain conductive layer (136). Therefore, a groove (H1) can be formed (or provided) on the upper surface (TS1) of the active layer (130).

[0127] refer to Figure 5 The shortest distance between the upper surface of the buffer layer (120) and the upper surface (TS1) of the active layer (130) can be shorter than the shortest distance between the upper surface of the buffer layer (120) and the upper surface (TS2) of the source conductive layer (135) or the upper surface (TS3) of the drain conductive layer (136).

[0128] For example, when a groove (H1) is formed (or provided) in the active layer (130), the thickness of the active layer (130) can be less than the thickness of the source conductive layer (135) and the drain conductive layer (136). In this case, the thickness can be measured along the second direction (Y).

[0129] refer to Figure 5 The groove (H1) formed (or set) on the upper surface (TS1) of the active layer (130) can be filled with the gate insulating film (140).

[0130] According to one embodiment of the present invention, a protrusion (H2) may be formed (or disposed) on the upper surface (TS1) of the active layer (130), such as Figure 6 As shown. When the source conductive layer (135), active layer (130), and drain conductive layer (136) are etched, the active layer (130) may be etched less due to the differences in material properties between the source conductive layer (135), active layer (130), and drain conductive layer (136). Therefore, a protrusion (H2) can be formed (or disposed) on the upper surface (TS1) of the active layer (130).

[0131] refer to Figure 6 The shortest distance between the upper surface of the buffer layer (120) and the upper surface (TS1) of the active layer (130) can be longer than the shortest distance between the upper surface of the buffer layer (120) and the upper surface (TS2) of the source conductive layer (135) or the upper surface (TS3) of the drain conductive layer (136).

[0132] For example, when a protrusion (H2) is formed (or disposed) in the active layer (130), the thickness of the active layer (130) can be greater than the thicknesses of the source conductive layer (135) and the drain conductive layer (136). In this case, the thickness can be measured along the second direction (Y).

[0133] According to one embodiment of the present invention, the upper surface (TS1) of the active layer (130) may have a first length (L1), and the lower surface (BS1) of the active layer (130) may have a second length (L2), such as Figure 2 As shown. Reference Figure 2 The second length (L2) can be longer than the first length (L1). In other words, the first length (L1) can be shorter than the second length (L2). For example, the first length (L1) can be in the range of 10 to 50 nm. (Reference) Figure 2 The first length (L1) of the upper surface (TS1) of the active layer (130) and the second length (L2) of the lower surface (BS1) of the active layer (130) can be narrower than the width of the gate electrode.

[0134] According to one embodiment of the present invention, the first length (L1) of the upper surface (TS1) and the second length (L2) of the lower surface (BS1) are each measured along a direction parallel to the first direction (X).

[0135] Figure 7 This is a cross-sectional view of a thin-film transistor substrate (600) according to another embodiment of the present invention. Figure 8 yes Figure 7 The circuit diagram of the thin-film transistor substrate (600) shown is shown.

[0136] According to an embodiment of the present invention, a thin-film transistor substrate (600) may include a substrate (110), a first thin-film transistor (T1) and a second thin-film transistor (T2) disposed on the substrate (110).

[0137] The first thin-film transistor (T1) includes: a first source conductive layer (135a) and a first drain conductive layer (136a) spaced apart from each other; a first sub-active layer (130a) disposed between the first source conductive layer (135a) and the first drain conductive layer (136a); and a gate electrode (151).

[0138] The second thin-film transistor (T2) includes: a second source conductive layer (135b) and a second drain conductive layer (136b) spaced apart from each other; a second sub-active layer (130b) disposed between the second source conductive layer (135b) and the second drain conductive layer (136b); and a gate electrode (152).

[0139] The descriptions of the first source conductive layer (135a) and the second source conductive layer (135b) are omitted because they are related to... Figure 2 The description of the source conductive layer (135) overlaps.

[0140] The descriptions of the first drain conductive layer (136a) and the second drain conductive layer (136b) are omitted because they are related to... Figure 2 The description of the drain conductive layer (136) overlaps.

[0141] The descriptions of the first sub-active layer (130a) and the second sub-active layer (130b) are consistent with... Figure 2 The description of the active layer (130) overlaps and is therefore omitted.

[0142] The descriptions of the first gate electrode (151) and the second gate electrode (152) are consistent with... Figure 2 The description of the gate electrode (150) overlaps and is therefore omitted.

[0143] also, Figure 7 The description of the substrate (110), buffer layer (120), gate insulating film (140), and interlayer insulating film (160) shown is omitted because they are related to... Figure 2 The descriptions of related components overlap.

[0144] According to one embodiment of the present invention, the first sub-active layer (130a) and the second sub-active layer (130b) are configured to stand in directions that are not parallel to the first direction (X) and the second direction (Y).

[0145] According to one embodiment of the present invention, the maximum length of the first sub-active layer (130a) and the second sub-active layer (130b) in the second direction (Y) may be longer than the minimum length of the first sub-active layer (130a) and the second sub-active layer (130b) in the first direction (X).

[0146] According to one embodiment of the present invention, the first source conductive layer (135a) and the second source conductive layer (135b) can be integrally formed. For example, see reference... Figure 7 and Figure 8 The first thin-film transistor (T1) and the second thin-film transistor (T2) can be formed in parallel (or in parallel). For example, the first source conductive layer (135a) of the first thin-film transistor (T1) and the second source conductive layer (135b) of the second thin-film transistor (T2) are connected together to the source electrode (171a). For example, the first drain electrode (172a) of the first thin-film transistor (T1) and the second drain electrode (172b) of the second thin-film transistor (T2) are respectively connected to the first drain conductive layer (136a) and the second drain conductive layer (136b).

[0147] According to one embodiment of the present invention, a first source conductive layer (135a) may be disposed between a first drain conductive layer (136a) and a second source conductive layer (135b), and the second source conductive layer (135b) may be disposed between a second drain conductive layer (136b) and a first source conductive layer (135a).

[0148] According to one embodiment of the present invention, the first sub-active layer (130a) may have a third side surface (SS3) in contact with the first source conductive layer (135a), and the second sub-active layer (130b) may have a fourth side surface (SS4) in contact with the second source conductive layer (135b).

[0149] For example, refer to Figure 7 The third side surface (SS3) and the fourth side surface (SS4) may not be parallel to each other and may have the same cone angle. For example, the third side surface (SS3) and the fourth side surface (SS4) may be symmetrically arranged with respect to the integrally formed first source conductive layer (135a) and second source conductive layer (135b). For example, the third side surface (SS3) and the fourth side surface (SS4) may not be parallel to the first direction (X) and the second direction (Y), respectively.

[0150] According to one embodiment of the present invention, the upper surface (TS4) of the first drain conductive layer 136a, the upper surface (TS5) of the first sub-active layer 130a, the upper surface (TS6) of the first source conductive layer 135a, the upper surface (TS7) of the second source conductive layer 135b, the upper surface (TS8) of the second sub-active layer 130b, and the upper surface (TS9) of the second drain conductive layer 136b can form a plane.

[0151] According to one embodiment of the present invention, the lower surface (BS4) of the first drain conductive layer (136a), the lower surface (BS5) of the first sub-active layer (130a), the lower surface (BS6) of the first source conductive layer (135a), the lower surface (BS7) of the second source conductive layer (135b), the lower surface (BS8) of the second sub-active layer (130b), and the lower surface (BS9) of the second drain conductive layer (136b) can form a plane.

[0152] Figures 9A to 9H This is a manufacturing process diagram of a thin-film transistor (100) according to another embodiment of the present invention. Details of the configuration already described above have been omitted.

[0153] refer to Figure 9A A buffer layer (120) can be formed on the substrate (110). The buffer layer (120) can be disposed on the entire substrate (110).

[0154] refer to Figure 9B A first metal material layer (135m) can be formed on the buffer layer (120). The first metal material layer (135m) is formed by patterning on the buffer layer (120). The first metal material layer (135m) may include at least one of gold (Au), nickel (Ni), copper (Cu), platinum (Pt), aluminum (Al), titanium (Ti), and chromium (Cr). However, embodiments of the present invention are not limited thereto.

[0155] refer to Figure 9C An active material layer (130m) can be formed on the first metal material layer (135m). The active material layer (130m) can be made of any of oxide semiconductor materials, low-temperature polycrystalline silicon (LTPS), and amorphous silicon (A-Si).

[0156] The material layer (130m) is formed by patterning on the first metallic material layer (135m).

[0157] refer to Figure 9D A second metallic material layer (136m) may be formed on the material layer (130m). The second metallic material layer (136m) may include at least one of gold (Au), nickel (Ni), copper (Cu), platinum (Pt), aluminum (Al), titanium (Ti), and chromium (Cr). However, embodiments of the present invention are not limited thereto.

[0158] According to one embodiment of the present invention, the first metal material layer (135m) and the second metal material layer (136m) may be formed of different materials. For example, the work function of the first metal material layer (135m) may be less than the work function of the gate electrode (150), and the work function of the second metal material layer (136m) may be greater than the work function of the gate electrode (150). For example, when the gate electrode (150) is formed of copper (Cu), the first metal material layer (135m) may include at least one of aluminum (Al), titanium (Ti), nickel (Ni), and chromium (Cr), and the second metal material layer (136m) may include at least one of gold (Au) and platinum (Pt).

[0159] refer to Figure 9E A chemical mechanical polishing (CMP) process can be performed to planarize the upper surfaces of the first metal material layer (135m), the active material layer (130m), and the second metal material layer (136m). Through the CMP process, a source conductive layer (135) and a drain conductive layer (136) spaced apart from each other, as well as an active layer (130) disposed between the source conductive layer (135) and the drain conductive layer (136), can be formed.

[0160] For example, the active material layer (130m) and the second metal material (136m) can be partially etched to planarize the upper surfaces of the first metal material layer (135m), the active material layer (130m), and the second metal material layer (136m). The first metal material layer (135m) can also be partially etched.

[0161] refer to Figure 9F A gate insulating film (140) can be formed on the source conductive layer (135), the drain conductive layer (136), and the active layer (130). The description of the gate insulating film (140) is omitted because it overlaps with the previous content.

[0162] refer to Figure 9G A gate electrode (150) can be formed on the gate insulating film (140). The description of the gate electrode (150) is omitted because it overlaps with the previous content. Figure 9G The grid electrode (150) is shown only on the right side of the figure.

[0163] refer to Figure 9H An interlayer insulating film (160), a source electrode (171), and a drain electrode (172) can be formed on the gate electrode (150). The description of the interlayer insulating film (160), the source electrode (171), and the drain electrode (172) is omitted because they overlap with the previous content.

[0164] Figure 10 A schematic diagram illustrating a display device (1000) according to yet another embodiment of the present disclosure.

[0165] like Figure 10 As shown, a display device (1000) according to another embodiment of the present disclosure may include a display panel (310), a gate driver (320), a data driver (330), and a controller (340).

[0166] The display panel (310) includes gate lines (GL) and data lines (DL), and pixels (P) are disposed in the intersection area of ​​the gate lines (GL) and data lines (DL). Images are displayed by driving the pixels (P). The gate lines (GL), data lines (DL), and pixels (P) can be disposed on a substrate (110).

[0167] The controller (340) controls the gate driver (320) and the data driver (330).

[0168] The controller (340) outputs a gate control signal (GCS) for controlling the gate driver (320) and a data control signal (DCS) for controlling the data driver (330) using signals supplied from an external system (not shown). Furthermore, the controller (340) samples input image data from the external system, re-registers the sampled data, and supplies the re-registered digital image data (RGB) to the data driver (330).

[0169] The gate control signal (GCS) includes the gate start pulse (GSP), gate shift clock (GSC), gate output enable signal (GOE), start signal (Vst), and gate clock (GCLK). Furthermore, control signals for controlling the shift register can be included within the gate control signal (GCS).

[0170] The data control signals (DCS) include the source start pulse (SSP), the source shift clock signal (SSC), the source output enable signal (SOE), and the polarity control signal (POL).

[0171] The data driver (330) supplies data voltage to the data line (DL) of the display panel (310). Specifically, the data driver (330) converts the image data (RGB) input from the controller (340) into analog data voltage and supplies the data voltage to the data line (DL).

[0172] According to one embodiment of this disclosure, the gate driver (320) can be packaged on the display panel (310). In this way, the structure in which the gate driver (320) is directly packaged on the display panel (310) will be referred to as a gate in panel (GIP) structure. In detail, in the gate in panel (GIP) structure, the gate driver (320) can be disposed on the substrate (110).

[0173] A display device (1000) according to one embodiment of the present disclosure may include the aforementioned thin-film transistor substrates (100, 200, 300, 400 and 500). According to one embodiment of the present disclosure, a gate driver (320) may include the aforementioned thin-film transistor substrates (100, 200, 300, 400 and 500).

[0174] The gate driver (320) may include a shift register (350).

[0175] Using a start signal and a gate clock sent from the controller (340), the shift register (350) sequentially supplies gate pulses to the gate line (GL) for one frame. In this case, one frame means a period of time during which an image is output through the display panel (310). The gate pulses have an on-state voltage capable of turning on the switching devices (thin-film transistors) located in the pixels (P).

[0176] Furthermore, for another time period within a frame (during which no gate pulse is supplied), the shift register (350) supplies a gate turn-off signal capable of turning off the switching device to the gate line (GL). Hereinafter, the gate pulse and the gate turn-off signal will be collectively referred to as the scan signal (SS or Scan).

[0177] The shift register (350) may include the aforementioned thin-film transistor substrates (100, 200, 300, 400 and 500).

[0178] The following advantages can be obtained according to this disclosure.

[0179] A thin-film transistor according to an embodiment of the present invention can have a short channel by including an active layer erected at an angle.

[0180] A thin-film transistor according to another embodiment of the present invention can have improved reliability and mobility by including a source conductive layer and a drain conductive layer with different work functions.

[0181] According to another embodiment of the present invention, a thin-film transistor can improve high junction stress (HJS) by providing multiple active layers with different mobility in the horizontal direction of the substrate.

[0182] In addition to the effects described above, other features and advantages of the present invention will be clearly understood by those skilled in the art from these descriptions and explanations.

[0183] It will be apparent to those skilled in the art that this disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications, and variations may be made in this disclosure without departing from the spirit or scope thereof. Therefore, the scope of this disclosure is defined by the appended claims, and it is intended that all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of this disclosure.

Claims

1. A thin-film transistor, comprising: Source conductive layers and drain conductive layers spaced apart from each other; An active layer disposed between the source conductive layer and the drain conductive layer; as well as The gate electrode overlapping the active layer, The direction from the drain conductive layer to the source conductive layer is referred to as the first direction, and the direction perpendicular to the first direction is referred to as the second direction. The active layer is configured to stand in a direction that is not parallel to the first direction and the second direction, and Wherein, the maximum length of the active layer in the second direction is longer than the minimum length of the active layer in the first direction.

2. The thin-film transistor according to claim 1, wherein, The active layer has a first side surface that contacts the source conductive layer and a second side surface that contacts the drain conductive layer, and The first side surface and the second side surface are not parallel to the first direction and the second direction, but are parallel to each other.

3. The thin-film transistor according to claim 1, wherein, The entire region of the active layer overlaps with the gate electrode.

4. The thin-film transistor of claim 1, wherein, The upper surface of the active layer, the upper surface of the source conductive layer, and the upper surface of the drain conductive layer form a plane.

5. The thin-film transistor of claim 1, further comprising a buffer layer, wherein the active layer is disposed on the buffer layer, and in, The lower surfaces of the active layer, the source conductive layer, and the drain conductive layer are in contact with the buffer layer to form a plane.

6. The thin-film transistor according to claim 1, wherein, The source conductive layer and the drain conductive layer are made of different materials. Wherein, the work function of the source conductive layer is less than the work function of the gate electrode, and The work function of the drain conductive layer is greater than the work function of the gate electrode.

7. The thin-film transistor according to claim 1, wherein, The active layer includes: The first active layer in contact with the source conductive layer; and The second active layer that is in contact with the drain conductive layer Wherein, the second active layer does not contact the source conductive layer, and Specifically, within a portion of the thickness of the active layer, any straight line parallel to the upper surface of the active layer passes through the first active layer and the second active layer.

8. The thin-film transistor according to claim 7, wherein, The mobility of the second active layer is greater than that of the first active layer.

9. The thin-film transistor of claim 7, further comprising a gate insulating film located between the active layer and the gate electrode, and in, The upper surfaces of the first active layer and the second active layer are in contact with the gate insulating film.

10. The thin-film transistor according to claim 7, wherein, The active layer further includes a third active layer located between the first active layer and the second active layer. Wherein, the third active layer does not contact the source conductive layer, and Wherein, within a portion of the thickness of the active layer, any straight line parallel to the upper surface of the active layer passes through the first active layer, the second active layer, and the third active layer.

11. The thin-film transistor of claim 10, wherein, The mobility of the third active layer is greater than that of the first active layer and less than that of the second active layer.

12. The thin-film transistor of claim 10, further comprising a gate insulating film located between the active layer and the gate electrode, and in, The upper surfaces of the first active layer, the second active layer, and the third active layer are in contact with the gate insulating film.

13. The thin-film transistor according to claim 1, wherein, A groove is formed on the upper surface of the active layer, and The thickness of the active layer is less than the thickness of the source conductive layer and the thickness of the drain conductive layer.

14. The thin-film transistor according to claim 1, wherein, Protrusions are formed on the upper surface of the active layer, and The thickness of the active layer is greater than the thickness of the source conductive layer and the thickness of the drain conductive layer.

15. The thin-film transistor according to claim 1, wherein, The upper surface of the active layer has a first length. The lower surface of the active layer has a second length. Wherein, the first length is shorter than the second length, and The first length and the second length are measured along a direction parallel to the first direction.

16. The thin-film transistor according to claim 1, wherein, At least a portion of the source conductive layer and at least a portion of the drain conductive layer overlap with the gate electrode in a plane.

17. A thin-film transistor substrate, comprising: Substrate; as well as The first thin-film transistor and the second thin-film transistor are disposed on the substrate. The first thin-film transistor includes: A first source conductive layer and a first drain conductive layer spaced apart from each other; A first sub-active layer disposed between the first source conductive layer and the first drain conductive layer; and The first gate electrode overlaps with the first sub-active layer; and The second thin-film transistor includes: A second source conductive layer and a second drain conductive layer spaced apart from each other; A second sub-active layer disposed between the second source conductive layer and the second drain conductive layer; and The second gate electrode overlapping the second sub-active layer, The direction from the first drain conductive layer to the first source conductive layer is referred to as the first direction, and the direction perpendicular to the first direction is referred to as the second direction. The first sub-active layer and the second sub-active layer are configured to stand in a direction that is not parallel to the first direction and the second direction, respectively. Wherein, the maximum length of the first sub-active layer in the second direction is longer than the minimum length of the first sub-active layer in the first direction, and Wherein, the maximum length of the second sub-active layer in the second direction is longer than the minimum length of the second sub-active layer in the first direction.

18. The thin-film transistor substrate according to claim 17, wherein, The first source conductive layer and the second source conductive layer are integrally formed, and The first thin-film transistor and the second thin-film transistor are connected in parallel.

19. The thin-film transistor substrate of claim 17, wherein, The first sub-active layer has a third side surface that contacts the first source conductive layer, and the second sub-active layer has a fourth side surface that contacts the second source conductive layer. The third side surface and the fourth side surface are not parallel to the first direction and the second direction, respectively.

20. The thin-film transistor substrate of claim 17, wherein, The upper surface of the first drain conductive layer, the upper surface of the first sub-active layer, the upper surface of the first source conductive layer, the upper surface of the second source conductive layer, the upper surface of the second sub-active layer, and the upper surface of the second drain conductive layer form a plane.

21. A method for manufacturing a thin-film transistor, comprising the following steps: A buffer layer is formed on the substrate. A first metallic material layer is formed on the buffer layer; An active material layer is formed on the first metallic material layer; A second metallic material layer is formed on the active material layer; A chemical mechanical polishing process is performed to planarize the upper surfaces of the first metal material layer, the active material layer, and the second metal material layer, thereby forming a source conductive layer and a drain conductive layer spaced apart from each other, as well as an active layer disposed between the source conductive layer and the drain conductive layer. A gate insulating film is formed on the source conductive layer, the drain conductive layer and the active layer; as well as A gate electrode is formed on the gate insulating film. The direction from the drain conductive layer to the source conductive layer is referred to as the first direction, and the direction perpendicular to the first direction is referred to as the second direction. The active layer is formed to stand in a direction that is not parallel to the first direction and the second direction, and Wherein, the maximum length of the active layer in the second direction is longer than the minimum length of the active layer in the first direction.

22. The method of manufacturing a thin-film transistor according to claim 21, wherein, The first metal layer and the second metal layer are made of different materials, and The work function of the second metal material layer is greater than that of the first metal material layer.

23. A display device comprising a thin-film transistor according to any one of claims 1 to 16.

Images