Transistor and display device including same

Abstract

A transistor and a display device including the same are disclosed. The transistor includes: an oxide semiconductor layer having a first source-drain region, a channel, and a second source-drain region in a first direction; an upper gate disposed over the oxide semiconductor layer and configured to overlap the channel, and a gate insulating film interposed between the upper gate and the channel; a lower gate disposed below the oxide semiconductor layer, configured to overlap at least the channel, and connected to the upper gate at a position configured to extend outward from the oxide semiconductor layer; a first source-drain electrode and a second source-drain electrode connected to the first source-drain electrode region and the second source-drain electrode region, respectively; and a voltage supply line connected to the lower gate and configured such that a positive constant voltage is supplied to the voltage supply line.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0143232, filed on October 18, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a transistor, and more specifically, to a transistor capable of easily controlling a threshold voltage, and a display device including the transistor. Background Technology

[0004] Display devices that display images in TVs, monitors, smartphones, tablet PCs, laptops, and other similar devices are being used in various ways and forms.

[0005] The display device includes multiple pixels for realizing an image and has transistors for controlling the operation of each pixel. Furthermore, transistors formed in the same process as those in the pixels are also disposed in an active region surrounding the multiple pixels.

[0006] In display devices, light-emitting display devices with light-emitting elements within the display panel without the need for a separate light source are considered competitive applications in order to achieve compactness and clear color display.

[0007] The transistors used for various functions of the display device require different characteristics, thus necessitating differences in their construction. Summary of the Invention

[0008] This invention describes a transistor structure comprising both an upper gate and a lower gate to achieve precise control of the threshold voltage in transistors used in display devices. By providing a bias voltage to the lower gate, the threshold voltage of the transistor (especially a transistor with a short and wide channel for driving current) can be adjusted to approximate the threshold voltage of a switching transistor with a different geometry. This configuration allows for tailored electrical performance without additional manufacturing steps or different material layers, thereby reducing power consumption and operational stress.

[0009] The solution utilizes a common oxide semiconductor layer and allows the lower gate to share existing circuitry, simplifying the manufacturing process. The ability to control the threshold voltage via a reference voltage line supports a range of transistor functions within each pixel, such as switching, driving, and sensing, contributing to improved display performance, energy efficiency, and long-term reliability.

[0010] For example, various embodiments of the present invention aim to provide a transistor and a display device including the transistor, which substantially overcomes one or more problems caused by the limitations and disadvantages of related technologies.

[0011] One aspect of the present invention is to achieve selective regulation of the threshold voltage of a transistor.

[0012] Another aspect of the invention is that even if transistors with different channel widths and lengths have different characteristics, by providing a reference voltage to compensate the threshold voltage of a transistor with a higher threshold voltage to be similar to the threshold voltage of a transistor with a lower threshold voltage, the threshold voltage of each transistor can be minimized.

[0013] Another aspect of the present invention is that by selectively compensating the threshold voltage of the transistor, it is possible to reduce the stress and power consumption of the transistor without affecting the characteristics of the transistor.

[0014] Another aspect of the present invention is the ability to realize transistors with different characteristics without any additional processes. Therefore, yet another aspect of the present invention is to provide a display device that can reduce greenhouse gases generated by additional manufacturing processes and achieve process optimization.

[0015] Additional advantages, aspects, and features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon studying the following, or may be learned from practice of the invention. Many aspects and other advantages of the invention can be realized and obtained by means of the structures specifically pointed out in the written description, its claims, and the accompanying drawings.

[0016] To achieve these and other advantages, according to the intent of the invention, as implemented and broadly described herein, a transistor includes: an oxide semiconductor layer having a first source-drain region, a channel, and a second source-drain region in a first direction; an upper gate disposed above the oxide semiconductor layer and configured to overlap the channel, and a gate insulating film interposed between the upper gate and the channel; a lower gate disposed below the oxide semiconductor layer, configured to overlap at least the channel, and connected to the upper gate at a location configured to extend outward from the oxide semiconductor layer; a first source-drain and a second source-drain respectively connected to the first source-drain region and the second source-drain region; and a voltage supply line connected to the lower gate and configured to provide a positive constant voltage to the voltage supply line.

[0017] In another aspect, a display device is provided, including a first transistor, a second transistor, and a voltage supply line. The first transistor is disposed on a substrate and includes a first oxide semiconductor layer and a first upper gate. The first oxide semiconductor layer includes a first channel, and the first upper gate is configured to overlap the first channel on the first oxide semiconductor layer. The second transistor is disposed on the substrate and spaced apart from the first transistor. The second transistor includes: a second oxide semiconductor layer having a second channel at a center and a first source-drain region and a second source-drain region located on both sides of the second channel; a second upper gate disposed above the second oxide semiconductor layer and configured to overlap the second channel, and a gate insulating film is interposed between the second upper gate and the second channel; and a lower gate disposed below the second oxide semiconductor layer, configured to overlap at least the second channel, and connected to the second upper gate at a location configured to extend outward from the second oxide semiconductor layer. The voltage supply line is connected to the lower gate.

[0018] It should be understood that the foregoing general description of the invention and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0019] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0020] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present invention.

[0021] Figure 2 This is a circuit diagram illustrating a sub-pixel according to an embodiment of the present invention;

[0022] Figure 3 This is a plan view illustrating a transistor according to an embodiment of the present invention;

[0023] Figure 4 It is along Figure 3 Cross-sectional views taken from lines I-I' and II-II';

[0024] Figure 5 It is a graph showing the variation of IV characteristics depending on the positive bias voltage applied to the lower gate of the transistor according to an embodiment of the present invention;

[0025] Figure 6 This is a circuit diagram illustrating a sub-pixel according to an embodiment of the present invention;

[0026] Figure 7 It is shown Figure 2 or Figure 6 A plan view of the first and second transistors;

[0027] Figure 8 It is along Figure 7 A cross-sectional view taken from line III-III';

[0028] Figure 9 This is a graph showing the IV characteristics of the first and second transistors of the present invention;

[0029] Figure 10 It is a graph showing the changes in threshold voltage and on-current as the voltage difference (Vgs) between the gate and source of the transistor changes.

[0030] Figure 11 This is a cross-sectional view of a display device according to an embodiment of the present invention. Detailed Implementation

[0031] In the following description, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

[0032] Reference will now be made in detail to preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. The same reference numerals will be used throughout the drawings to refer to the same or similar parts whenever possible. In the following description of the invention, detailed descriptions of known functions and constructions relevant herein will be omitted where such descriptions would obscure the subject matter of the invention. Furthermore, for clarity of description, the names of elements used in the following description have been chosen, and these names may differ from the names of elements in the actual product.

[0033] The shapes, dimensions, sizes (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, number of elements, etc. shown in the accompanying drawings to describe embodiments of the present invention are merely examples, and the present invention is not limited thereto.

[0034] The dimensions and thicknesses of each component shown in the accompanying drawings are for ease of description. The invention is not limited to the dimensions and thicknesses of the components shown, but please note that the relative sizes, positions, and thicknesses of the components shown in the submitted drawings are part of the invention.

[0035] In this specification, where terms such as “comprising,” “having,” or “including” are used, one or more components may be added, unless a term such as “only” is used. As used herein, the term “and / or” includes a single associated listed item and any and all combinations of two or more associated listed items.

[0036] Expressions such as "at least one" preceding the list of elements may modify the entire list of elements, but may not modify individual elements of the list. The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, "at least one of the first, second, and third elements" means: a combination of all three listed elements; a combination of any two of the three elements; and each of the first, second, and third elements individually.

[0037] The terminology used herein is for the purpose of describing specific aspects and is not intended to limit the invention. As used herein, terms used to describe elements in the singular are intended to include multiple elements. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context clearly indicates otherwise.

[0038] When interpreting components or values, components or values ​​are interpreted to include a range of errors or tolerances, even if no explicit description of such a range of errors or tolerances is provided.

[0039] In describing various exemplary embodiments of the invention, when using terms such as “above,” “over,” “below,” and “beside” to describe the positional relationship between two elements, at least one intermediate element may be present between the two elements unless “immediately,” “directly,” or “immediately following.” It will be understood that when an element or layer is referred to as being “connected to” or “joined to” another element or layer, it may be directly connected to or joined to the other element or layer, or one or more intermediate elements or layers may be present.

[0040] In describing various exemplary embodiments of the invention, when using terms such as “after,” “following,” “next,” and “before” to describe the temporal relationship between two events, another event may occur in between, unless more restrictive terms such as “exactly,” “immediately,” or “directly” are used.

[0041] As used herein, the term "connection" is intended to have the broadest possible meaning. Specifically, the phrase "A connected to B" encompasses both direct connection (where no intermediate parts or elements exist) and indirect connection (where one or more intermediate parts or elements exist between A and B). In other words, "A connected to B" includes both direct physical or electrical contact and indirect contact via one or more intermediate parts. Unless otherwise explicitly stated, these terms do not require direct physical or electrical contact. The term "connection" should be interpreted in the same manner.

[0042] In describing various exemplary embodiments of the present invention, terms such as "first" and "second" may be used to describe various components. These terms are intended to distinguish identical or similar components from one another and do not limit the components. Therefore, throughout the specification, unless otherwise specifically mentioned, a "first" component may be the same as a "second" component within the technical concept of the present invention.

[0043] Features of the various embodiments of the present invention may be partially or entirely combined with each other, and may be technically interoperable and driven with each other in various ways, as will be fully understood by those skilled in the art. Embodiments of the present invention may be implemented independently of each other, or may be implemented together in an interdependent relationship.

[0044] Figure 1 This is a plan view of a display device according to an embodiment of the present invention. Figure 2 This is a circuit diagram illustrating a sub-pixel according to an embodiment of the present invention.

[0045] Reference Figure 1 and Figure 2 A display device 1000 according to one embodiment of the present invention may include a display panel 110 and a housing (not shown) housing the side surfaces of the display panel 110 and the lower part of the display panel 110. The non-active area NA of the display panel 110 may be covered by the housing or by a separate light-shielding film. A printed circuit film and / or a battery may be disposed between the lower part of the display panel 110 and the housing.

[0046] The display panel 110 may include a substrate 111 and a driver connected to the substrate 111. The substrate 111 includes an active region AA and a non-active region NA surrounding the active region AA. The driver may be integrated with an array disposed in the active region AA within the substrate 111, and may be connected to the substrate 111 in a chip-on-glass (COG) manner, or may be connected to a printed circuit board on the substrate 111 in a chip-on-film (COF) manner via a film or connector. Optionally, the driver may include both a configuration integrated into the substrate 111 and a configuration external to the COG or COF.

[0047] The active area AA is the area where the image is displayed. Multiple subpixels SP are set in the active area AA of the display panel 110, and multiple subpixels SP can be used to display the image. The area other than the active area AA can be used as the non-active area NA.

[0048] The non-active area NA can be located in the edge region surrounding the active area AA of the displayed image. At least one driver for driving multiple sub-pixels SP can be located in the non-active area NA. The driver may include an in-panel gate (GIP). The in-panel gate (GIP) may be connected to multiple gate lines GL of the active area AA and sequentially supply gate voltage signals to the multiple gate lines GL.

[0049] Various additional components used to drive the sub-pixels SP in the active region AA can be further set in the non-active region NA.

[0050] like Figure 2 As shown, at least one of the multiple sub-pixels SP may include a first transistor T1, a second transistor T2, a storage capacitor Cst, a compensation circuit CC, and a light-emitting element ED.

[0051] For example, the first transistor T1 can be a switching transistor, and the second transistor T2 can be a driving transistor. The first transistor T1 and / or the second transistor T2 can be disposed at each of the plurality of sub-pixels located on the substrate 111.

[0052] The first electrode (e.g., drain) of the first transistor T1 is electrically connected to the data line DL, and the second electrode (e.g., source) of the first transistor T1 is electrically connected to the first node N1. The gate of the first transistor T1 is electrically connected to the gate line GL. The first transistor T1 transmits the data signal provided by the data line DL to the first node N1 in response to the scan signal provided by the gate line GL.

[0053] The storage capacitor Cst is electrically connected to the first node N1 and charges the first node N1 using the applied voltage. When the sub-pixel SP does not have the compensation circuit CC, the first node N1 can be connected to the first gate of the second transistor T2.

[0054] The first electrode (e.g., drain) of the second transistor T2 receives a high-potential drive voltage EVDD, and the second electrode (e.g., source) of the second transistor T2 is electrically connected to the first electrode (e.g., anode) of the light-emitting element ED at the second node N2. The second electrode (e.g., cathode) of the light-emitting element ED can receive a low-potential drive voltage EVSS. The second transistor T2 can control the amount of drive current Ids flowing to the light-emitting element ED according to the voltage difference Vgs between the gate and the source (see...). Figure 5 ).

[0055] like Figure 2As shown, the gate of the second transistor T2 may include a first gate connected to the compensation circuit CC or the first node N1 and a second gate connected to the reference voltage line RL. The second transistor T2 may further include a second gate to adjust the threshold voltage Vth. For example, when a positive bias voltage is applied to the second gate through the reference voltage line RL, the threshold voltage can be adjusted to a more negative value. A positive bias voltage is a constant positive voltage. When a positive bias voltage is selectively applied to the second gate through the reference voltage line RL, the threshold voltage can be reduced compared to when a single gate voltage is applied through the first gate. A reference voltage in a positive constant voltage state can be provided through the reference voltage line RL. The reference voltage line RL may be connected to the gate or an electrode (source) of a buffer transistor or a sensing transistor to control the gate or this electrode.

[0056] As another example, when a negative bias voltage is applied to the second gate of the second transistor T2 through the reference voltage line RL, the threshold voltage can be adjusted to rise to a more positive value.

[0057] Among the transistors placed in the sub-pixel SP, the switching transistors require high-speed driving for rapid switching operations and may also require high current output. The driving transistor achieves grayscale representation in the range from the initial gate voltage Vgsint (where the current value corresponding to the gate voltage applied to the gate changes at the initial gate voltage Vgsint) to the gate voltage reaching saturation (when sufficient current is reached). The gate voltage at which the transistor reaches saturation can be called the threshold voltage Vth. For example, the driving transistor that provides driving current to the light-emitting element ED (e.g., ...) Figure 2The second transistor T2 must be fixed to a certain extent or higher in the segment from the initial gate voltage Vgsint to the threshold voltage Vth (Vgsint-Vth), that is, the segment from the cutoff state to the saturation state in the IV curve used for grayscale representation (Vgsint-Vth). Additionally, in some cases, even if the driving transistor may require high current output to achieve high brightness performance of the light-emitting element (ED) below the sub-pixel area minimized due to integration. For this purpose, the channel width of the semiconductor layer of the driving transistor can be greater than the channel width of the semiconductor layer of the switching transistor, and the channel length of the semiconductor layer of the driving transistor can be less than the channel length of the semiconductor layer of the switching transistor. Therefore, the driving transistor can ensure a certain segment (where the current changes in the segment where the voltage changes from the initial gate voltage to the threshold voltage), thereby achieving rich grayscale representation. Furthermore, when the switching transistor capable of high-speed switching operation and the driving transistor capable of grayscale representation each comprise a semiconductor layer formed of the same material, the channels of these transistors can be configured to differ in at least one of width and length, and the slopes of their IV curves can be configured to differ as well. However, by applying a positive bias voltage to the lower gate of the driving transistor, the threshold voltage of the driving transistor with a smaller slope can be adjusted to the level of the lower threshold voltage of the switching transistor. Therefore, the driving transistor can have a smaller slope of its IV curve by adjusting the width / length of the channel, while simultaneously having a lower threshold voltage by applying a positive bias voltage to the lower gate.

[0058] Furthermore, since the driving transistor is the transistor that provides driving current to the light-emitting element (ED), a large amount of current must flow through it, requiring a large channel width. In this case, if the segment from the cutoff state to the saturation state in the IV curve of the driving transistor used for grayscale representation is fixed to a certain level or higher, the difference between the initial gate voltage Vgsint and the threshold voltage Vth becomes larger. That is, if the initial gate voltage Vgsint of the driving transistor is set to a level similar to that of a switching transistor, the threshold voltage of the driving transistor is high. When the threshold voltage of the driving transistor increases, the driving voltage can increase, thus increasing the power consumption for driving sub-pixels. At the same time, the stress level applied to the driving transistor itself can increase, thereby acting as a degradation factor for the driving transistor. Therefore, it is necessary for the driving transistor to reduce the threshold voltage Vth while maintaining the slope of the IV curve. In addition to the first gate configured to provide the gate voltage, the driving transistor of the present invention also has a second gate connected to the reference voltage line RL, thereby selectively providing the gate voltage through the second gate to shift the high threshold voltage in the negative direction, thereby reducing the driving voltage, reducing power consumption, and exhibiting a stress reduction effect. This improves the reliability of the driving transistor and ensures its robustness, so that the driving transistor does not deteriorate even after long-term driving.

[0059] A switching transistor is a transistor disposed in a sub-pixel to control the switching of the sub-pixel. Because switching transistors involve high-speed operation, their channel size can be smaller than that of the driving transistor. However, in the longitudinal direction of the channel, an effective channel length variation ΔL may occur due to diffusion during the conduction or doping processes in the source and drain regions of the semiconductor layer. In particular, the effective channel length variation ΔL can become more severe when the channel width decreases. Switching transistors used for high-resolution and high-speed operation have small channel sizes, and when the effective channel length is reduced due to conduction or doping processes, the threshold voltage can be very low, leading to leakage current in the off-state, and in severe cases, the switching transistor may not be in a stable off-state. Furthermore, when the semiconductor layer has high mobility, the switching transistor tends to exhibit increased dispersion as the threshold voltage decreases. Therefore, switching transistors require a high threshold voltage for operational stability.

[0060] In this way, due to their different operating characteristics, the aforementioned driving transistor and switching transistor require different channel widths and lengths, and have oppositely inclined threshold voltages. It is difficult to adjust the opposite tendencies of the threshold voltages of the driving transistor and switching transistor by simply adjusting the channel width and length. In addition to the first gate, the transistor according to one embodiment of the invention has a second gate that is selectively supplied with a gate voltage, thereby adjusting the threshold voltage of the transistor. Therefore, it is possible to adjust the threshold voltages of the switching transistor and the driving transistor to match or be similar.

[0061] The semiconductor layer of the first transistor T1 and / or the semiconductor layer of the second transistor T2 may include amorphous silicon (a-Si), crystalline silicon (such as polycrystalline silicon (poly-Si) or low-temperature polycrystalline silicon (poly-Si)) or oxide semiconductor.

[0062] If the first transistor T1 and / or the second transistor T2 comprises an oxide semiconductor, the oxide semiconductor has a small or almost no leakage current when off, thus providing stable characteristics during operation.

[0063] According to one embodiment of the invention, a transistor can have different characteristics by varying the width and length of its channel, and at least a second transistor T2 included in a sub-pixel may further include a second gate connected to a reference voltage line RL. In this case, the first transistor T1 in the sub-pixel may include a single gate. The second gate and the first gate may be located below and above the oxide semiconductor layer, respectively.

[0064] In a display device according to another embodiment of the present invention, a transistor has a semiconductor layer formed of an oxide semiconductor manufactured in the same process. A transistor with a single gate can be disposed in an active region surrounding a sub-pixel, and a transistor further including a second gate connected to the aforementioned reference voltage line can be configured to provide a drive current in each sub-pixel. Since transistors with different characteristics can have oxide semiconductor layers manufactured in the same process, the additional processes required to manufacture transistors with different stacks according to their characteristics, such as setting multiple metal layers and setting interlayer insulating films between multiple metal layers, can be omitted. Furthermore, among the transistors, transistors with a lower slope IV curve (e.g., driving transistors) can be provided with a second gate connected to a separate power supply voltage line or reference voltage line, thereby enabling a reduction in the threshold voltage of the transistor. In this case, the slope of the IV curve can be maintained to achieve grayscale performance, and the threshold voltage can be reduced to prevent increased power consumption and increased stress on the transistor.

[0065] The first transistor T1 and the second transistor T2 include the same oxide semiconductor layer, and at least one of the channel width and channel length disposed at the center of the oxide semiconductor layer can be changed to change the IV curve characteristics.

[0066] For example, the channel length of the first transistor T1 can be relatively long, and the channel width of the first transistor T1 can be relatively short. The first transistor T1 functions as a switching transistor, controlling a signal from the second transistor T2, which functions as a driving transistor within the sub-pixel SP. Therefore, the first transistor T1 can be integrated at high resolution, allowing its channel width and channel length to be set to process limits. Furthermore, the first transistor T1 can be designed such that its channel length is relatively long compared to its channel width, in order to prepare for the occurrence of channel length variations ΔL (the distance between the edge of the gate and the edge of the channel) in the channel length direction.

[0067] Compared to the first transistor T1, the second transistor T2 can have a shorter channel length and a larger channel width. This is because the second transistor T2 supplies current to the light-emitting element ED and can carry a large amount of current to achieve high brightness performance; therefore, the channel width of the second transistor T2 is increased to prepare for this.

[0068] The channel length can be determined as the distance between the source and drain regions on both sides of each transistor. The channel width can be determined in a direction that overlaps with the gate of each transistor and intersects with the channel length.

[0069] The second transistor T2 can provide a large amount of drive current to the light-emitting element ED by increasing the channel width. The second transistor T2 may have an IV curve that can represent grayscale by adjusting the channel width and length. According to one embodiment of the invention, the second transistor T2 has a second gate located below the oxide semiconductor layer, in addition to a first gate located above the oxide semiconductor layer. The second gate is connected to a power supply voltage line, and a positive bias voltage is applied to the second gate to adjust the threshold voltage in the negative direction, such that the threshold voltage of the second transistor T2 can be adjusted to a level similar to the threshold voltage of the first transistor T1. When a single gate is provided, the initial gate voltage Vgsint when the current value corresponding to the gate voltage changes is approximately 0V. Therefore, the second transistor T2, with a smaller slope IV curve, can have a higher threshold voltage than the first transistor T1. However, according to one embodiment of the invention, the second transistor T2 may additionally have a lower gate connected to a reference voltage line RL or a voltage supply line to which a power supply voltage is selectively applied, capable of applying a reverse bias voltage and shifting the IV curve in the negative direction. Therefore, the second transistor T2 according to one embodiment of the invention can reduce the threshold voltage and also reduce power consumption. Furthermore, the stress applied to the second transistor T2 can also be reduced.

[0070] Unlike the second transistor T2, the first transistor T1 may not have a lower gate. In another example, the first transistor T1 may have a lower gate connected to a line that provides a different voltage than the power supply voltage line connected to the second transistor T2, and the first transistor T1 regulates the threshold voltage differently from the second transistor T2, etc.

[0071] According to another embodiment of the present invention, the display device can shift the threshold voltage in the positive direction by applying a negative bias voltage as the gate voltage applied to the lower gate of any of the transistors located on the substrate.

[0072] Furthermore, according to another embodiment of the present invention, a display device may apply transistors having gates located above and below an oxide semiconductor layer to a region other than a sub-pixel in order to adjust a threshold voltage. The region other than the sub-pixel may be, for example, an active region of a substrate, and more specifically, an in-panel gate within an active region.

[0073] In a display device according to an embodiment of the present invention, each of the plurality of sub-pixels may further include a third transistor, the third transistor including a semiconductor layer, the semiconductor layer including a third channel having a width different from that of the second channel, and the third transistor may have characteristics different from those of the first transistor T1 and the second transistor T2.

[0074] The transistor and display device according to embodiments of the present invention include an oxide semiconductor layer in at least one of the transistors formed on a substrate 111, thereby enabling it to have excellent cutoff characteristics, be formed at a relatively low temperature compared to other materials, maintain amorphous properties, and have high mobility.

[0075] The light-emitting element (ED) outputs light corresponding to the driving current. The ED can output light corresponding to any one of the colors: red, green, blue, and white.

[0076] A light-emitting element (ED) may include an anode, an intermediate layer disposed on the anode, and a cathode providing a common voltage. The intermediate layer may include at least one light-emitting layer, and when an electric field is formed between the anode and the cathode, the intermediate layer may be configured to emit light of the same color, such as white light, for each sub-pixel SP, or may be configured to emit light of different colors, such as red, green, or blue light, for each sub-pixel SP. In addition to the light-emitting layer, the intermediate layer may also include various types of common layers and functional layers to effectively provide holes and electrons to the light-emitting layer.

[0077] The light-emitting element (ED) can be a top-emitting diode or a bottom-emitting diode.

[0078] A compensation circuit CC may be additionally provided in the sub-pixel SP to compensate for the threshold voltage of the second transistor T2, etc. In some cases, the compensation circuit CC may be omitted. The compensation circuit CC may be formed by one or more transistors. The compensation circuit CC may include one or more transistors and capacitors, and may be configured in various ways depending on the compensation method. The sub-pixel SP including the compensation circuit CC may include circuits with various structures having different numbers of transistors and / or capacitors, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0079] The in-panel gate (GIP) may be included in the non-active region NA. The in-panel gate outputs a gate signal to the gate line GL according to a gate control signal input from, for example, a timing controller. The in-panel gate (GIP) may include multiple transistors, and the multiple transistors may be formed in the same process as the transistors of the sub-pixel SP.

[0080] Furthermore, the transistors included in the gate within the panel may include transistors having an oxide semiconductor layer as the active layer and transistors having a semiconductor layer formed of crystalline silicon as the active layer.

[0081] In the following, a transistor according to one embodiment of the present invention will be described.

[0082] Figure 3 This is a plan view illustrating a transistor according to one embodiment of the present invention. Figure 4 It is along Figure 3 The cross-sectional views taken from lines I-I' and II-II', and Figure 5 This is a graph showing the variation of the IV characteristic depending on the positive bias voltage applied to the lower gate of the transistor according to an embodiment of the present invention.

[0083] like Figure 3 and Figure 4 As shown, a transistor according to one embodiment of the present invention may include: an oxide semiconductor layer AT having a first source-drain region SDA1, a channel CH, and a second source-drain region SDA2 in a first direction; an upper gate G disposed above the oxide semiconductor layer AT and configured to overlap with the channel CH, and a gate insulating film 125 interposed between the upper gate G and the channel CH; a lower gate BG disposed below the oxide semiconductor layer AT, configured to overlap at least with the channel CH, and connected to the upper gate G at a position extending outward from the oxide semiconductor layer AT; a first source-drain SD1 and a second source-drain SD2 respectively connected to the first source-drain region SDA1 and the second source-drain region SDA2; and a voltage supply line connected to the lower gate BG and configured to provide a positive bias voltage or a constant voltage to the voltage supply line.

[0084] The lower gate (BG) and the voltage supply line can be configured to be integrally formed together.

[0085] Here, the voltage supply line can be a reference voltage line RL. The voltage supply line can use one of the voltage lines set in the sub-pixel without forming an additional line.

[0086] In some cases, the voltage supply line can be formed as a separate line and connected to the lower gate BG.

[0087] The lower gate BG may have a width at least greater than the width W of the channel CH, and may be connected to the upper gate G via a third contact hole CT3 at a location offset from the oxide semiconductor layer AT. The upper gate G and the lower gate BG are connected at a location that does not overlap with the oxide semiconductor layer AT. At least one interlayer insulating film may be disposed between the oxide semiconductor layer AT and the lower gate BG. The third contact hole CT3 may be configured to penetrate the gate insulating film and at least one interlayer insulating film. The third contact hole CT3 may be spaced apart from the oxide semiconductor layer AT.

[0088] The channel CH of the oxide semiconductor layer AT has a length L in a first direction between the first source-drain region SDA1 and the second source-drain region SDA2, and a width W in a second direction intersecting the first direction.

[0089] like Figure 3 and Figure 4 As shown, the voltage supply line can be a reference voltage line RL. The reference voltage line RL can be connected to, for example, the source and drain of a sensing transistor included in a compensation circuit. When the reference voltage line RL provides a voltage to the lower gate BG, the voltage can be provided to the lower gate BG of the transistor through a circuit configuration included in the sub-pixel without the need to add a separate voltage line, thereby enabling process optimization.

[0090] The reference voltage line RL can be configured to be integrally formed with the lower gate BG, such as... Figure 4 As shown. In this case, the reference voltage line RL can be located in a layer below the oxide semiconductor layer AT. Therefore, in a transistor according to an embodiment of the invention, the lower gate of the transistor can receive a positive bias voltage or a positive constant voltage through a conductive connection between the reference voltage line connected to a transistor included in a sub-pixel and the lower gate BG, without the need for a separate voltage supply line.

[0091] According to one embodiment of the present invention, transistors may be disposed in each sub-pixel of substrate 111.

[0092] The substrate 111 may be formed of a flexible plastic material and may be flexible. The substrate 111 may include polyimide and may include a thin glass material that is flexible.

[0093] Substrate 111 may independently include a support substrate, such as polyethylene terephthalate (PET) and a polyimide film. Substrate 110 may include an adhesive film, such as a pressure-sensitive adhesive (PSA) film, to bond the polyimide film to the PET support substrate. Substrate 111 may have a structure of two organic film stacks with an inorganic interlayer film (not shown) interposed therebetween.

[0094] Multiple insulating films 120:121,122,123,124,125,126 and 127 are stacked on the active region AA and the non-active region NA of the substrate 111 so as to insulate the transistor electrodes from each other.

[0095] A first insulating film 121 is disposed on the active region AA and the non-active region NA on the substrate 111. The first insulating film 121 may be referred to as a buffer film and can perform the same function as buffer films known in the art. The first insulating film 121 may be disposed on the substrate 111 to protect moisture-sensitive structures on the substrate 111 from the effects of moisture permeating through the substrate 111, and the first insulating film 121 can planarize the surface of the substrate 111.

[0096] The first insulating film 121 may be disposed all the way to the edge of the substrate 111 to prevent moisture from penetrating from the edge of the substrate 111. The first insulating film 121 may be a single inorganic film, or may include multiple inorganic films stacked alternately.

[0097] For example, the first insulating film 121 may include at least one inorganic film selected from silicon oxide (SiOx) film, silicon nitride (SiNx) film and silicon nitride oxide (SiOxNy) film, or may include, for example, a multilayer film in which the above-mentioned inorganic films are stacked.

[0098] The second insulating film 122 may be disposed on the first insulating film 121. The second insulating film 122 may be used as a second buffer layer, and may also be used as a gate insulating film for a transistor (not shown) constituting a gate driver (not shown) disposed in the non-active region NA.

[0099] The second insulating film 122 may include an inorganic film, such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multilayer film thereof.

[0100] The third insulating film 123 may be disposed on the second insulating film 122. The third insulating film 123 may also be used as an interlayer insulating film constituting a transistor (not shown) of a gate driver (not shown) disposed in the non-active region NA.

[0101] The third insulating film 123 may include an inorganic material. The inorganic material may be, for example, a silicon nitride (SiNx) film.

[0102] The lower gate BG can be disposed on the third insulating film 123.

[0103] The lower gate (BG) may be formed of a conductive metal material. Specifically, the conductive metal material may include at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), silver-based metals (such as silver (Ag) or silver alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The lower gate (BG) may have a multilayer film structure comprising at least two conductive metal materials.

[0104] The lower gate BG and the reference voltage line RL can be disposed together on the third insulating film 123. The reference voltage line RL can be integrally formed with the lower gate BG.

[0105] The fourth insulating film 124 may be disposed on the third insulating film 123 on which the lower gate BG is disposed. The fourth insulating film 124 may serve as a buffer layer. The fourth insulating film 124 may include an oxide semiconductor layer AT disposed thereon for planarizing the upper surface of the substrate 111 to form the base of the transistor.

[0106] The fourth insulating film 124 may include an inorganic material. The inorganic material may include, for example, a silicon oxide (SiOx) film or a multilayer film in which inorganic films are stacked.

[0107] If the fourth insulating film 124 comprises a silicon oxide film, then no hydrogen particles are emitted during the heat treatment process during the manufacturing process, thereby preventing the reliability of the oxide semiconductor layer AT disposed adjacent to the fourth insulating film 124 from being reduced due to hydrogen particles.

[0108] The oxide semiconductor layer AT can be disposed on the fourth insulating film 124.

[0109] The oxide semiconductor layer AT includes: a channel CH overlapping with the upper gate G; and a first source-drain region SDA1 and a second source-drain region SDA2 connected to the first source-drain SD1 and the second source-drain SD2.

[0110] The channel CH can be the region where the oxide semiconductor layer AT overlaps with the upper gate G, i.e., the region where charge carriers move. The channel CH may be undoped.

[0111] In the oxide semiconductor layer AT, the first source-drain region SDA1 and the second source-drain region SDA2 can be regions excluding the channel CH, that is, conductive regions connected to the first source-drain SD1 and the second source-drain SD2. The first source-drain region SDA1 and the second source-drain region SDA2 can be disposed on both sides of the channel CH, with the channel inserted between them.

[0112] The first source-drain region SDA1 and the second source-drain region SDA2 may include conductive portions doped with impurities, etc. In some cases, the first source-drain region SDA1 and the second source-drain region SDA2 may include regions in which conductive regions implanted with impurities and non-conductive regions without impurities coexist. For example, the non-conductive region may be disposed between the conductive region and the channel CH.

[0113] The oxide semiconductor layer AT comprises an oxide semiconductor material. The oxide semiconductor material may be formed from oxides of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or from combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides.

[0114] More specifically, the oxide semiconductor material of the oxide semiconductor layer AT may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), etc.

[0115] Because the oxide semiconductor layer AT of the transistor contains oxide semiconductor material, the cutoff current is low and the effect of blocking leakage current is improved, thereby reducing power consumption.

[0116] The fifth insulating film 125 may be disposed on the oxide semiconductor layer AT. Since the oxide semiconductor layer AT is disposed on the fourth insulating film 124 in a patterned form, the fifth insulating film 125 is configured to cover the upper surface and side surface of the oxide semiconductor layer AT.

[0117] Since the fifth insulating film 125 is configured to cover an oxide semiconductor layer AT comprising an oxide semiconductor material, the fifth insulating film 125 can be formed of an inorganic material that does not contain hydrogen particles. For example, the fifth insulating film 125 may comprise a silicon oxide (SiOx) film or a multilayer film in which multiple inorganic films are stacked.

[0118] The fifth insulating film 125 can be used as a gate insulating film.

[0119] The upper gate G may be disposed on the fifth insulating film 125. The upper gate G may be used in response to a signal from... Figure 2The signal from the compensation circuit CC or capacitor Cst shown causes the second transistor T2 to be turned on or off. The upper gate G is insulated from the oxide semiconductor layer AT through the fifth insulating film 125 and is configured to overlap with at least a portion of the oxide semiconductor layer AT to form a channel CH in the oxide semiconductor layer AT. Here, the channel length L can be determined by the upper gate G overlapping the oxide semiconductor layer AT in the first direction, and the channel width W can be determined by the upper gate G overlapping the oxide semiconductor layer AT in the second direction.

[0120] The upper gate G may be formed of a conductive metal material. Specifically, the conductive metal material may include at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), silver-based metals (such as silver (Ag) or silver alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The upper gate G may have a multilayer film structure comprising at least two conductive metal materials.

[0121] The sixth insulating film 126 and the seventh insulating film 127 may be disposed on the upper gate G.

[0122] The sixth insulating film 126 covers the upper part and the side of the upper gate G to insulate the first source-drain SD1 and the second source-drain SD2 from the upper gate G.

[0123] The sixth insulating film 126 can be a single inorganic film or can be formed as a stack of multiple inorganic films. As an inorganic film, one or more inorganic materials are selected from silicon oxide (SiOx) films, silicon nitride (SiNx) films, and silicon nitride oxide (SiOxNy) films.

[0124] The seventh insulating film 127 disposed on the sixth insulating film 126 can be configured to planarize the upper part of the second transistor T2, including the patterned shape, such as the oxide semiconductor layer AT or the upper gate G.

[0125] The seventh insulating film 127 may be formed by a stack of organic materials, inorganic materials, or organic and inorganic films.

[0126] The first source-drain electrode SD1 and the second source-drain electrode SD2 can be disposed on the seventh insulating film 127. The first source-drain electrode SD1 and the second source-drain electrode SD2 can be arranged spaced apart from each other, and the upper gate G is inserted therebetween. In this case, as described above, the first source-drain electrode SD1, the second source-drain electrode SD2, and the upper gate G can be disposed in different layers.

[0127] The first source-drain electrode SD1 and the second source-drain electrode SD2 can be formed of a conductive metal material. Specifically, the conductive metal material may include at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), silver-based metals (such as silver (Ag) or silver alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first source-drain electrode SD1 and the second source-drain electrode SD2 may have a multilayer film structure comprising at least two conductive metal materials.

[0128] Each of the first source-drain electrode SD1 and the second source-drain electrode SD2 is connected to the oxide semiconductor layer AT. The first source-drain electrode SD1 is connected to the first source-drain region SDA1 of the oxide semiconductor layer AT through a first contact hole CT1 disposed in the fifth to seventh insulating films 125, 126 and 127, and the second source-drain electrode SD2 is connected to the second source-drain region SDA2 of the oxide semiconductor layer AT through a second contact hole CT2 disposed in the fifth to seventh insulating films 125, 126 and 127.

[0129] Figure 3 and Figure 4 An example is shown where the lower gate BG is connected to the upper gate G, which overlaps with the lower gate BG, via a third contact hole CT3 (which is disposed in the fourth insulating layer 124 and the fifth insulating layer 125 at a portion protruding from the plane of the oxide semiconductor layer AT). Here, the lower gate BG may be integrally formed with the reference voltage line RL, and the upper gate G and the lower gate BG may be at the same potential as the voltage supplied to the reference voltage line RL. Here, the voltage supplied to the reference voltage line RL is a positive bias voltage, and the value of the positive bias voltage may vary according to the magnitude of the threshold voltage to be adjusted.

[0130] For example, a reference voltage line RL may extend from the lower gate BG along a first direction. The extended reference voltage line RL may be connected to a sensing transistor or a buffer transistor in the compensation circuit CC.

[0131] In some cases, a positive constant voltage can be supplied to the lower gate BG through a line that is separated from the reference voltage line RL and is subject to rated voltage.

[0132] When the transistor is turned on, a reference voltage Vref or a power supply voltage can be selectively provided through the lower gate BG, and a positive constant voltage can also be provided to the upper gate G through the connection between the lower gate BG and the upper gate G via the third contact hole CT.

[0133] For example, when used as a driving transistor, Figure 3 and Figure 4The transistor shown may have a wide channel width W and a short channel length L, and can ensure a certain segment of the gate voltage (Vgsint-Vth) from the initial gate voltage Vgsint (the current value corresponding to the gate voltage applied to the gate changes at the initial gate voltage Vgsint) to the threshold voltage Vth that reaches saturation (where sufficient current is reached). However, the transistor including both the upper gate G and the lower gate BG according to one embodiment of the invention is not limited to a driving transistor. The transistor having the above structure can be applied to any transistor that requires adjustment of the threshold voltage.

[0134] Furthermore, the transistor of the present invention may have an upper gate G and a lower gate BG to address the increase in threshold voltage Vth when the gate voltage is provided by a single gate, and in the case where one of the transistors disposed on the substrate includes an oxide semiconductor layer with different characteristics, the threshold voltage Vth can be adjusted by the lower gate BG. Figure 5 As shown, as the magnitude of the positive bias voltage Vbg applied to the lower gate BG gradually increases, the IV curve gradually shifts in the negative direction. This means that as the magnitude of the positive bias voltage applied through the lower gate of the transistor increases, the threshold voltage of the transistor decreases.

[0135] For example, when Figure 3 and Figure 4 When the transistor is configured as a driving transistor, a specific segment in which the current changes can be ensured during the transition from the initial gate voltage to the threshold voltage, thereby achieving rich grayscale representation. Furthermore, when the switching transistor capable of high-speed switching and the driving transistor capable of grayscale representation are both made of the same semiconductor layer, the channel width / length of these transistors can be set differently, and the slope of their IV curves can be set differently. However, by applying a positive bias voltage to the lower gate of the driving transistor, the threshold voltage of the driving transistor with the smaller slope can be adjusted to the level of the lower threshold voltage of the switching transistor. Therefore, the driving transistor can have a smaller slope of its IV curve by adjusting the channel width / length, while simultaneously having a lower threshold voltage by applying a positive bias voltage to the lower gate.

[0136] According to another embodiment of the present invention, when the Figure 3 and Figure 4 When the transistor is configured as a switching transistor, the threshold voltage of the transistor can be adjusted to increase it by applying a negative bias voltage to the downward gate BG.

[0137] The following text will describe those with the same characteristics as... Figure 2 Sub-pixels with different circuit structures.

[0138] Figure 6This is a circuit diagram illustrating a sub-pixel according to an embodiment of the present invention.

[0139] like Figure 6 As shown, a sub-pixel SP according to one embodiment of the present invention includes: first to sixth transistors T1, T2, T3, T4, T5 and T6; a first capacitor Cs; a second capacitor Ca; and a light-emitting element ED.

[0140] Each of the first to sixth transistors T1, T2, T3, T4, T5, and T6 can be independently a p-type transistor or an n-type transistor. Figure 6 Examples of first to sixth transistors T1, T2, T3, T4, T5, and T6 being n-type transistors are shown.

[0141] When a high voltage is applied to the gate, each of the first to sixth transistors T1, T2, T3, T4, T5, and T6 is turned on. The first transistor T1 can be connected to the data line DL and acts as a switching transistor to provide data. The second transistor T2 can be connected to the first transistor T1 and acts as a driving transistor, and the sixth transistor T6 can act as an initialization transistor. The third transistor T3 can be connected to the reference voltage line RL and provides a reference voltage to one side of the first capacitor Cs. The fourth transistor T4 and the fifth transistor T5 can be connected to the first light-emitting control line EM1 and the second light-emitting control line EM2, respectively, to regulate the supply of driving current.

[0142] The gate of the first transistor T1 is connected to the first gate line SL1, the first electrode (e.g., drain) of the first transistor T1 is connected to the data line DL, and the second electrode (e.g., source) of the first transistor T1 is connected at the first node N1 to the first electrode of the first capacitor Cs and the gate of the second transistor T2.

[0143] The first electrode of the first capacitor Cs is connected to the first node N1, and the second electrode of the first capacitor Cs is connected to the second node N2.

[0144] The upper gate of the second transistor T2 is connected to the second electrode of the first transistor T1 at the first node N1, and the second transistor T2 is disposed between the fourth transistor T4 and the fifth transistor T5. The first electrode of the second transistor T2 is connected to the fourth transistor T4, which is provided with a high-potential drive voltage EVDD, and the second electrode of the second transistor T2 is connected to the first electrode of the fifth transistor T5 at the fourth node N4. The second transistor T2 also includes a lower gate, which is electrically connected to the reference voltage line RL at the third node N3.

[0145] The gate of the third transistor T3 is connected to the second gate line SL2, the first electrode (e.g., the drain) of the third transistor T3 is connected to the reference voltage line RL, and the second electrode (e.g., the source) of the third transistor T3 is connected at the first node N1 to one electrode of the first capacitor Cs and the gate of the second transistor T2. Here, the first electrode of the third transistor T3 is electrically connected to the lower gate of the second transistor T2 through the third node N3.

[0146] The gates of the fourth transistor T4 and the fifth transistor T5 are connected to the first light-emitting control line EM1 and the second light-emitting control line EM2, respectively.

[0147] The first electrode of the fourth transistor T4 is connected to the first power supply voltage line VDL, which is provided with a high-potential drive voltage EVDD, and the second electrode of the fourth transistor T4 is connected to the first electrode of the second transistor T2.

[0148] The first electrode of the fifth transistor T5 is connected to the second electrode of the second transistor T2 at the fourth node N4, and the second electrode of the fifth transistor T5 can be connected to the first electrode of the light-emitting element ED at the second node N2.

[0149] In addition, the gate of the sixth transistor T6 is connected to the third gate line SL3, the first electrode of the sixth transistor T6 is connected to the initialization line INL, the initialization voltage Vin is provided to the initialization line INL, and the second electrode of the sixth transistor T6 is connected to the first electrode of the fifth transistor T5 through the fourth node N4.

[0150] In addition, a second capacitor Ca is disposed between the second node N2 and the first power supply voltage line VDL.

[0151] The light-emitting element ED is positioned between the second node N2 and the second power supply voltage line VSL. A low-potential drive voltage EVSS is provided through the second power supply voltage line VSL.

[0152] Figure 6 The circuit operation will be described below.

[0153] When a first gate signal or a second gate signal is selectively applied to the gate of the first transistor T1 or the gate of the third transistor T3 via the first gate line SL1 or the second gate line SL2, the data signal provided by the first transistor T1 or the reference voltage signal Vref provided by the third transistor T3 is applied to the first electrode of the first capacitor Cs via the first node N1.

[0154] Based on the light emission control signals applied to the first light emission control line EM1 and the second light emission control line EM2, the second transistor T2 provides a drive current flowing between the fourth transistor T4 and the fifth transistor T5 to the first electrode of the light-emitting element ED through the second node N2. The lower gate of the second transistor T2 is connected to the reference voltage line RL through the third node N3, such that the reference voltage Vref is selectively provided to the lower gate of the second transistor T2 through the reference voltage line RL, and the threshold voltage of the second transistor T2 can be reduced when a positive bias voltage is applied as the reference voltage Vref.

[0155] The fourth transistor T4 can provide a voltage proportional to the high-potential drive voltage EVDD to the first electrode of the second transistor T2 via the light-emitting control signal provided by the first light-emitting control line EM1.

[0156] In addition, when the third gate signal is provided to the gate of the sixth transistor T6 through the third gate line SL3, a voltage proportional to the initialization voltage Vin transmitted to the initialization line INL can be transmitted to the first electrode of the fifth transistor T5 through the fourth node N4.

[0157] According to the light-emitting control signal provided to the second light-emitting control line EM2, the fifth transistor T5 can transmit a signal proportional to the high-potential driving voltage EVDD or a signal proportional to the initialization voltage Vin to the second node N2 through the fourth node N4. Therefore, the light-emitting element ED can be driven.

[0158] The second capacitor Ca is an auxiliary capacitor and is connected to the first power supply voltage line VDL, which is subjected to a high-potential drive voltage EVDD, thereby keeping the potential of the second node N2 higher than the low-potential drive voltage EVSS.

[0159] Therefore, when an initialization voltage Vin is applied to the first electrode of the light-emitting element ED, the light-emitting element ED is initialized; or, when a signal proportional to the high-potential drive voltage EVDD is applied to the first electrode of the light-emitting element ED, the light-emitting element ED emits light while current flows along the direction of the second power supply voltage line VSL. In one embodiment of the invention, the low-potential drive voltage EVSS provided to the second power supply voltage line VSL can be set to be lower than the high-potential drive voltage EVDD provided to the first power supply voltage line VDL.

[0160] Each light-emitting element (ED) can display one of the following colors: white, red, green, and blue.

[0161] In a display device according to one embodiment of the present invention, for example, the second transistor T2 may be formed having including Figure 3 and Figure 4 The structure of the aforementioned transistor with a lower gate is shown in the diagram.

[0162] The first transistor T1 and the third to sixth transistors T3, T4, T5, T6 can be configured as transistors without a lower gate, or can be configured such that the first transistor T1 and at least one of the third to sixth transistors T3, T4, T5, T6 have a lower gate, but have a different threshold voltage control than the second transistor T2.

[0163] Figure 7 It is shown Figure 2 or Figure 6 A planar view of the first and second transistors. Figure 8 It is along Figure 7 The cross-sectional view taken from line III-III'.

[0164] like Figure 7 and Figure 8 As shown, the first transistor T1 can be disposed on the substrate 111 and includes a first oxide semiconductor layer AT1 and a first upper gate G1. The first oxide semiconductor layer AT1 includes a first channel CH1, and the first upper gate G1 is disposed above the first oxide semiconductor layer AT1 and overlaps with the first channel CH1.

[0165] The first oxide semiconductor layer AT1 of the first transistor T1 may include a first source-drain region SDA11 and a second source-drain region SDA12 on both sides of the first channel CH1.

[0166] In addition, the first transistor T1 may include source-drain electrodes SD11 and SD12 connected to the first source-drain region SDA11 and the second source-drain region SDA12 through contact holes CT11 and CT12 disposed in the fifth to seventh insulating films 125, 126 and 127.

[0167] At least one light-shielding metal LS overlapping with the first channel CH1 may be disposed below the first oxide semiconductor layer AT1 to prevent light from being transmitted from below the substrate 111 to the first oxide semiconductor layer AT1. The light-shielding metal LS may have an area larger than that of the first upper gate G1, but is not limited thereto.

[0168] The light-shielding metal LS can be formed from a conductive metal material. Specifically, the conductive metal material can include at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), silver-based metals (such as silver (Ag) or silver alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The light-shielding metal LS can have a multilayer film structure comprising at least two conductive metal materials.

[0169] In some cases, the light-shielding metal LS can be connected to the first upper gate G1 located above the first oxide semiconductor layer AT1 to ensure high current or control threshold voltage.

[0170] The second transistor T2 can be disposed on the substrate 111 and spaced apart from the first transistor T1.

[0171] The second transistor T2 includes: a second oxide semiconductor layer AT2 having a second channel CH2 at its center and a first source-drain region SDA21 and a second source-drain region SDA22 on both sides of the second channel CH2; a second upper gate G2 disposed above the second oxide semiconductor layer AT2 and overlapping the second channel CH2, wherein a fifth insulating film 125 serves as a gate insulating film inserted between the upper gate G2 and the second channel CH2; and a lower gate BG disposed below the second oxide semiconductor layer AT2 and overlapping at least the second channel CH2, and connected to the upper gate G2 on the outside of the second oxide semiconductor layer AT2.

[0172] The first oxide semiconductor layers AT1 and AT2 of the first transistor T1 and the second transistor T2 can be located in the same layer and formed in the same process. A display device according to one embodiment of the invention defines the characteristics of the first transistor T1 and the second transistor T2 by the dimensions of the first channel CH1 and the second channel CH2 defined by the overlap region between the first upper gate G1 and the second upper gate G2 and the first oxide semiconductor layer AT1 and the second oxide semiconductor layer AT2. However, a lower gate BG is further included below the second oxide semiconductor layer AT2 of the second transistor T2 (which has a relatively high threshold voltage when a single gate is used), and a positive constant voltage is selectively provided to the lower gate BG. Therefore, as... Figure 5 As shown, the IV curve can be shifted in the negative direction to reduce the threshold voltage.

[0173] Therefore, the threshold voltage Vth of the second transistor T2, which has a wider channel width and a shorter channel length, can be adjusted to be similar to the threshold voltage Vth of the first transistor T1, which has a narrower channel width and a longer channel length.

[0174] The voltage supply line can be, for example, a reference voltage line RL to which a rated voltage is applied. The voltage supply line connected to the lower gate BG can be another power supply voltage line located in the sub-pixel, as long as a positive constant voltage can be applied. A positive constant voltage can be applied to the reference voltage line RL to provide a gate voltage to the second transistor T2 through the lower gate BG, thereby enabling a reduction in the threshold voltage of the second transistor T2.

[0175] For example, the second transistor T2 can be a driving transistor. In addition to a second upper gate G2 that provides the gate voltage, the second transistor T2 may have a lower gate BG connected to a reference voltage line RL, allowing the gate voltage to be selectively provided through the lower gate BG. This enables a high threshold voltage to be shifted in the negative direction, thereby reducing the driving voltage, reducing power consumption, and providing a stress reduction effect. This improves the reliability of the driving transistor and ensures its robustness, preventing degradation even after long-term driving.

[0176] The first transistor T1 can be a switching transistor that controls the switching of sub-pixels. Since the first transistor T1 involves high-speed operation, its channel size can be smaller than that of the driving transistor. Considering the effective channel length, the length of the channel of the first transistor T1 can be greater than its width. In some cases, the length of the channel of the first transistor T1 can be longer than the length of the channel of the second transistor T2, and the width of the channel of the first transistor T1 can be shorter than the width of the channel of the second transistor T2.

[0177] Due to their different operating characteristics, the first transistor (switching transistor) T1 and the second transistor (driving transistor) T2 require different channel widths and lengths, and have oppositely inclined threshold voltages. In a display device according to one embodiment of the present invention, in addition to the first gate, the second transistor T2 may also have a second gate that is selectively supplied with a gate voltage, such that the threshold voltage of the second transistor can be adjusted to be consistent with or similar to the threshold voltage of the first transistor T1.

[0178] The lower gate BG of the second transistor T2 can be connected to the voltage supply line and selectively receive signals applied to the voltage supply line. Whenever a gate signal is provided to the second upper gate G2, the second transistor T2 can receive a positive constant voltage (positive bias voltage) through the voltage supply line. Optionally, the supply cycle of the positive constant voltage to the voltage supply line can differ from the supply cycle of the gate signal. The threshold voltage Vth can be adjusted according to the amplitude and supply cycle of the positive constant voltage.

[0179] The substrate 111, which includes the first to seventh insulating films 121, 122, 123, 124, 125, 126 and 127, and the insulating film 120 have the same structure as in the above embodiments, and therefore their description will be omitted.

[0180] In the second transistor T2, the first source-drain electrode SD21 and the second source-drain electrode SD22 can be formed of conductive metal materials. Specifically, the conductive metal materials can include at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), silver-based metals (such as silver (Ag) or silver alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first source-drain electrode SD1 and the second source-drain electrode SD2 can have a multilayer film structure comprising at least two conductive metal materials.

[0181] The first source-drain electrode SD21 and the second source-drain electrode SD22 of the second transistor T2 are respectively connected to the first source-drain region SDA21 and the second source-drain region SDA22 on both sides of the second oxide semiconductor layer AT2. The first source-drain electrode SD21 is connected to the first source-drain region SDA21 of the second oxide semiconductor layer AT2 through the first contact hole CT21 disposed in the fifth to seventh insulating films 125, 126 and 127, and the second source-drain electrode SD22 is connected to the second source-drain region SDA22 of the second oxide semiconductor layer AT2 through the second contact hole CT22 disposed in the fifth to seventh insulating films 125, 126 and 127.

[0182] like Figure 7 and Figure 8 As shown, the lower gate BG can be connected to the overlapping second upper gate G2 via a contact hole GCT (which is disposed in the fourth insulating film 124 and the fifth insulating film 125 at the portion protruding outward from the oxide semiconductor layer AT2). Here, the lower gate BG can be integrally formed with the reference voltage line RL, and the second upper gate G2 and the lower gate BG can be at the same potential as the voltage supplied to the reference voltage line RL. Here, the voltage supplied to the reference voltage line RL is a positive bias voltage, and the value of the positive bias voltage can vary depending on the magnitude of the threshold voltage to be adjusted.

[0183] The light-shielding metal LS of the first transistor T1 can be connected to the first upper gate G1, or a separate ground signal can be applied to the light-shielding metal LS to further stabilize the characteristics of the first transistor T1.

[0184] The lower gate BG of the second transistor T2 is located below the second oxide semiconductor layer AT2, and can also be used to prevent light entering from below the substrate 111 from affecting the second oxide semiconductor layer AT2.

[0185] Figure 8 An example is shown where the light-shielding metal LS of the first transistor T1 and the lower gate BG of the second transistor T2 are located in different layers.

[0186] like Figure 8 As shown, if the vertical distance between the light-shielding metal LS of the first transistor T1 and the first oxide semiconductor layer AT1 is longer than the vertical distance between the lower gate BG of the second transistor T2 and the second oxide semiconductor layer AT2, then the first transistor T1 can further prevent the generation of parasitic capacitance with the first oxide semiconductor layer AT1 by applying a voltage to the light-shielding metal LS, and can be driven independently of the application of a voltage signal to the light-shielding metal LS.

[0187] For example, the reference voltage line RL can extend from the lower gate BG along a first direction. The extended reference voltage line RL can be connected to a sensing transistor or a buffer transistor, etc., in the compensation circuit CC.

[0188] In an embodiment of the present invention, in addition to the second upper gate G2 disposed above the second oxide semiconductor layer AT2, a lower gate BG is further disposed below the second oxide semiconductor layer AT2, thereby enabling individual voltage compensation through the lower gate BG, and thus selectively adjusting the threshold voltage of the second transistor T2.

[0189] One aspect of the embodiments of the present invention is that even if the first transistor T1 and the second transistor T2, which have different channel widths and lengths, have different characteristics, the threshold voltage of each transistor can be minimized by providing a reference voltage Vref to compensate the threshold voltage of the transistor with the higher threshold voltage to be similar to that of the transistor with the lower threshold voltage.

[0190] Another aspect of the embodiments of the present invention is that by selectively compensating the threshold voltage of the transistor, it is possible to reduce the stress and power consumption of the transistor without affecting the characteristics of the transistor.

[0191] Another aspect of the present invention is that, by adjusting the overlap region between the upper gate and the oxide semiconductor layer of the transistor and changing the arrangement of the lower gate or the light-shielding metal in the transistor comprising at least the oxide semiconductor layer, transistors with different characteristics can be realized without any additional processes. Therefore, a display device can be provided that can reduce greenhouse gases generated by additional manufacturing processes and achieve process optimization.

[0192] Figure 9 This is a graph showing the IV characteristics of the first and second transistors of the present invention. Figure 10 It is a graph showing the changes in threshold voltage and on-current as the voltage difference Vgs between the gate and source of the transistor changes.

[0193] like Figure 9As shown, when a positive bias voltage is applied through the lower gate of the second transistor T2, the initial gate voltage of the second transistor T2 is shifted more in the negative direction than that of the first transistor T1, so that the threshold voltage Vth of the first transistor T1 and the threshold voltage Vth of the second transistor T2 can be consistent with each other or become almost the same.

[0194] The gate on-state voltage of the first transistor T1 may be higher than that of the second transistor T2. The difference between the threshold voltage Vth of the first transistor T1 and the threshold voltage Vth of the second transistor T2 may be set to approximately 0.4V or less, thereby reducing the stress on each of the first transistor T1 and the second transistor T2 and reducing the power consumption of each of the first transistor T1 and the second transistor T2.

[0195] Figure 10 The results show that as the magnitude of the voltage applied to the lower gate increases, the threshold voltage Vth gradually decreases while the on-state current Ion gradually increases.

[0196] In other words, it can be confirmed that the second transistor T2, which is positively biased according to an embodiment of the present invention, ensures a lower threshold voltage Vth and a higher on-current Ion characteristic.

[0197] For example, such as Figure 7 and Figure 8 As shown, the first transistor T1 can be a switching transistor, and the second transistor T2 can be a driving transistor. In addition to a second upper gate G2 that provides the gate voltage, the second transistor T2 may also have a lower gate BG connected to a reference voltage line RL, allowing the gate voltage to be selectively provided via the lower gate BG, thereby shifting a high threshold voltage in the negative direction, thus reducing the driving voltage and decreasing power consumption and stress. This improves the reliability of the driving transistor and ensures its robustness, preventing degradation even after long-term driving.

[0198] The first transistor T1 can be a switching transistor that controls the switching of sub-pixels. Since the first transistor T1 involves high-speed operation, its channel size can be smaller than that of the driving transistor. Considering the effective channel length, the length of the channel of the first transistor T1 can be greater than its width. In some cases, the length of the channel of the first transistor T1 can be longer than the length of the channel of the second transistor T2, and the width of the channel of the first transistor T1 can be shorter than the width of the channel of the second transistor T2.

[0199] Due to their different operating characteristics, the first transistor (switching transistor) T1 and the second transistor (driving transistor) T2 require different channel widths and lengths, and have oppositely inclined threshold voltages. In a display device according to one embodiment of the present invention, in addition to the first gate, the second transistor T2 may also have a second gate that is selectively supplied with a gate voltage, such that the threshold voltage of the second transistor T2 can be adjusted to be consistent with or similar to the threshold voltage of the first transistor T1.

[0200] The following will describe a display device having the first transistor, the second transistor, and a light-emitting element as described above.

[0201] Figure 11 This is a cross-sectional view showing a display device according to an embodiment of the present invention.

[0202] like Figure 11 As shown, a display device 1000 according to one embodiment of the present invention may have the features described above. Figure 8 and Figure 9 The first transistor T1 and the second transistor T2 described are located on the substrate 111 and may include a planarization film 128, a dam 135, a light-emitting element 145 and an encapsulation layer 150 disposed on the first transistor T1 and the second transistor T2.

[0203] A planarization film 128 may be disposed on the first transistor T1 and the second transistor T2 to protect the first transistor T1 and the second transistor T2 and to mitigate the steps caused by the first transistor T1 and the second transistor T2.

[0204] The planarization film 128 may be disposed between the structure or elements of the first transistor T1, the second transistor T2, the wiring and the light-emitting element 145 to reduce the parasitic capacitance that occurs between the first transistor T1, the second transistor T2, the wiring and the light-emitting element 145.

[0205] A planarization film 128 may be disposed on an insulating film 120 to provide a flat surface.

[0206] The planarization film 128 may include an organic material. The organic material may include at least one material selected from the group consisting of acrylic resin, phenolic resin, polyimide resin, unsaturated polyester resin, polyamide resin, benzocyclobutene, polyphenylene resin, and polyphenylene sulfide resin.

[0207] The planarization film 128 can be configured as a composite stack of inorganic and organic insulating films. In addition to the insulating film 120 described above, various organic or inorganic materials can be further disposed between the substrate 111 and the planarization film 128.

[0208] The dam 135 is a pixel-defining film that exposes the first electrode E1 of each sub-pixel SP. The dam 135 may include an opaque material (e.g., black) to prevent optical interference between adjacent sub-pixels SP. In this case, the dam 135 may include a light-blocking material formed of at least one of colored pigments, organic black, and carbon.

[0209] The light-emitting element 145 is disposed on the planarization film 128 of the active region AA.

[0210] The light-emitting element 145 includes a first electrode E1, a light-emitting layer EL, and a second electrode E2. The light-emitting element 145 can be electrically connected to the second transistor T2 via a planarization film 128. The first electrode E1 of the light-emitting element 145 and the second source-drain SD22 of the second transistor T2 are electrically connected to each other.

[0211] The first electrode E1 can be used as the anode. The first electrode E1 can pass through the planarization film 128 and be connected to the second transistor T2.

[0212] The first electrode E1 may comprise a metallic material with high reflectivity. For example, the first electrode E1 may be formed as a multilayer structure, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and ITO (ITO / Al / ITO), an APC (Ag / Pd / Cu) alloy, a stacked structure of APC alloy and ITO (ITO / APC / ITO), or a stacked structure of silver (Ag) and molybdenum / titanium alloy (Ag / MoTI). Alternatively, the first electrode E1 may comprise a single-layer structure formed of one material selected from silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca), and barium (Ba), or an alloy of two or more materials selected from the above materials. The first electrode E1 may be referred to as a reflective electrode.

[0213] The light-emitting layer EL is disposed on the first electrode E1. The light-emitting layer EL may include a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer.

[0214] When a voltage is applied to the first electrode E1 and the second electrode E2, holes move to the organic light-emitting layer through the hole injection layer and the hole transport layer, and electrons move to the organic light-emitting layer through the electron injection layer and the electron transport layer, respectively. Holes and electrons recombine with each other in the organic light-emitting layer to form excitons, and the energy of the excitons decreases from the excited state to the ground state to emit light.

[0215] The light-emitting layer EL can be formed as a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, and a blue light-emitting layer that emits blue light. A red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer can be provided on the first electrode E1 for each sub-pixel SP.

[0216] The red emitting layer can be patterned in the red sub-pixel, the green emitting layer can be patterned in the green sub-pixel, and the blue emitting layer can be patterned in the blue sub-pixel. However, the red, green, and blue emitting layers are not limited to this. At least two or more of the organic emitting layers can be stacked and disposed in a sub-pixel SP.

[0217] The emitting layer EL can be a white emitting layer that emits white light. In this case, the emitting layer EL can be a common layer obtained by setting one or more layers together in the sub-pixel SP (instead of in a patterned manner).

[0218] As described above, the light-emitting layer EL can be disposed in a series structure of two or more stacked layers. In this case, each light-emitting element 145 may include a charge-generating layer disposed between the respective stacked layers. The charge-generating layer may be a common layer disposed on the entire surface of the active region AA.

[0219] The second electrode E2 is disposed on the light-emitting layer EL. The second electrode E2 can be used as a cathode.

[0220] The second electrode E2 can be disposed not only in the light-emitting area of ​​each sub-pixel SP, but also on the entire surface of the active area AA, but is not limited thereto. The second electrode E2 can be a common layer disposed on the sub-pixel SP and subjected to the same voltage. For this purpose, the second electrode E2 can be configured to extend from the active area AA to a portion of the non-active area NA.

[0221] The second electrode E2 can be a transmission electrode. The second electrode E2 can contain a transparent metallic material (i.e., a transparent conductive oxide (TCO) material), such as light-transmitting ITO or IZO; or a semi-transmitting metallic material (i.e., a semi-transmitting conductive material), such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode E2 is a semi-transmitting conductive material, the light extraction efficiency can be increased through the microcavity.

[0222] The top-emitting type has already been described above as an example of the light-emitting element 145. However, the light-emitting element 145 of the present invention is not limited thereto, and can be a bottom-emitting type in which light emitted from the light-emitting layer EL is emitted toward the substrate 111. In this case, the first electrode E1 can be formed of a transparent or translucent electrode material, and the second electrode E2 can be formed of a reflective electrode material.

[0223] An encapsulation layer 150 is disposed on the light-emitting element 145. The encapsulation layer 150 covers the active region AA and the non-active region NA to prevent oxygen or moisture from penetrating into the light-emitting element 145. If necessary, other layers, such as a capping layer, can be inserted between the encapsulation layer 150 and the second electrode E2.

[0224] The encapsulation layer 150 may include multiple layers. The encapsulation layer 150 may be formed as a structure in which inorganic films comprising inorganic insulating materials and organic films comprising organic insulating materials are stacked alternately. For example, the inorganic insulating materials may include at least one material, such as silicon oxide, silicon nitride, and / or silicon nitride.

[0225] Organic insulating materials may include at least one material selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate and hexamethyldisiloxane.

[0226] In the display device 1000, voltage can be selectively supplied to the second transistor T2 via a power supply voltage line connected to the lower gate BG, thereby reducing the threshold voltage and decreasing the stress applied to the second transistor T2 due to the reduced threshold voltage. Furthermore, when driving the second transistor T2, there is an effect of reducing power consumption.

[0227] In the display device 1000 of the present invention, when different first transistors T1 and second transistors T2 with different IV curves are provided, the second transistor T2 with a smaller slope IV curve has a lower gate BG and a reference voltage line RL is provided to be connected to the lower gate BG, such that the threshold voltage of the second transistor T2 can be adjusted to be similar to the threshold voltage of the first transistor T1 by selectively applying a positive bias voltage via the reference voltage line RL.

[0228] The first transistor T1 can be a switching transistor, and the second transistor T2 can be a driving transistor. In addition to a second upper gate G2 that provides the gate voltage, the second transistor T2 is separately provided with a lower gate BG connected to a reference voltage line RL. This allows the gate voltage to be selectively provided through the lower gate BG, thereby shifting a high threshold voltage in the negative direction, thus reducing the driving voltage and decreasing power consumption and stress. This improves the reliability of the driving transistor and ensures its robustness, preventing degradation even after long-term driving.

[0229] The first transistor T1 can be a switching transistor that controls the switching of sub-pixels. Since the first transistor T1 involves high-speed operation, its channel size can be smaller than that of the driving transistor. Considering the effective channel length, the length of the channel of the first transistor T1 can be greater than its width. In some cases, the length of the channel of the first transistor T1 can be longer than the length of the channel of the second transistor T2, and the width of the channel of the first transistor T1 can be shorter than the width of the channel of the second transistor T2.

[0230] Due to their different operating characteristics, the first transistor (switching transistor) and the second transistor (driving transistor) require different channel widths and lengths, and have oppositely inclined threshold voltages. In a display device according to one embodiment of the present invention, in addition to the first gate, the second transistor may have a second gate that is selectively supplied with a gate voltage, such that the threshold voltage of the second transistor can be adjusted to be consistent with or similar to the threshold voltage of the first transistor.

[0231] In a display device according to one embodiment of the present invention, a positive constant voltage can be selectively supplied to the second transistor (driving transistor) via a voltage supply line, and the threshold voltage of the second transistor can be shifted to be consistent with or similar to the threshold voltage of a first transistor (switching transistor) that is different from the second transistor. Therefore, the threshold voltages of the switching transistor and the driving transistor, which have different operating characteristics and functions, can be matched to each other by the voltage supplied to the voltage supply line.

[0232] The display device of the present invention can realize transistors with different characteristics without any additional processes by adjusting the overlap area between the upper gate of the transistor and the oxide semiconductor layer and changing the arrangement of the lower gate or the light-shielding metal in the transistor containing at least an oxide semiconductor layer.

[0233] The display device of the present invention can realize transistors with different characteristics without any additional processes, thereby reducing greenhouse gases generated by additional manufacturing processes, achieving process optimization, and achieving sustainable environmental / social / governance effects.

[0234] Currently, the development of transistors, including oxide semiconductors, for displays focuses on developing robust devices that do not degrade even after long-term operation.

[0235] Due to their low cutoff current characteristics, oxide semiconductor transistors are widely used as switching elements for low refresh rate drives. Additionally, the application of oxide semiconductor transistors as drive transistors for low-power displays is under investigation due to their fast saturation characteristics.

[0236] Since switching transistors and driving transistors require different driving characteristics, the channel widths and channel lengths of the semiconductor layers forming the switching transistors and driving transistors are different, resulting in switching transistors and driving transistors having different threshold voltages.

[0237] It is necessary to develop components with robust structures that have the margin to meet the operational requirements of various components. The transistor of this invention, while being implemented as a driving transistor, can additionally be provided with wiring that applies a positive bias voltage to the lower end of the active layer, allowing the threshold voltage of the driving transistor to be shifted in the negative direction, thereby reducing component stress and improving stability.

[0238] The driving transistor can only exhibit grayscale when the slope of the drive current change, which indicates a change in gate voltage in the IV curve, is gentle. Even if the slope of the IV curve is small, the transistor of the present invention can shift the threshold voltage, which has been shifted in the positive direction, back in the negative direction by providing a voltage via an additional lower gate, thereby changing the threshold voltage of the driving transistor to near 0V.

[0239] A driver transistor with a reduced threshold voltage can be driven at lower voltages, and the stress level applied to the driver transistor can be reduced, thereby suppressing device degradation. Additionally, a reduction in power consumption can be expected due to the lower drive voltage.

[0240] Furthermore, according to one embodiment of the present invention, the threshold voltage of the transistor can be selectively controlled by applying a reverse bias voltage to the lower end of the oxide semiconductor layer.

[0241] Transistors incorporating oxide semiconductors can increase process margins and reduce stress applied to the transistor by controlling the threshold voltage. Therefore, devices incorporating transistors with oxide semiconductors can increase reliability. Additionally, they have the effect of reducing power consumption when the transistor is driven.

[0242] A transistor according to one embodiment of the present invention may include: an oxide semiconductor layer having a first source-drain region, a channel, and a second source-drain region in a first direction; an upper gate disposed above the oxide semiconductor layer and configured to overlap the channel, and a gate insulating film interposed between the upper gate and the channel; a lower gate disposed below the oxide semiconductor layer, configured to overlap at least the channel, and connected to the upper gate at a location configured to extend outward from the oxide semiconductor layer; a first source-drain and a second source-drain respectively connected to the first source-drain region and the second source-drain region; and a voltage supply line connected to the lower gate and configured to provide a positive constant voltage to the voltage supply line.

[0243] In a transistor according to one embodiment of the present invention, the voltage supply line may be integrally formed with the lower gate.

[0244] In a transistor according to one embodiment of the present invention, the voltage supply line may be a reference voltage line.

[0245] In a transistor according to one embodiment of the invention, the positive constant voltage can be selectively provided via the voltage supply line. The threshold voltage of the transistor used as a driving transistor can be matched with the threshold voltage of the switching transistor. In other words, the threshold voltage of the transistor used as a driving transistor can be equal to or substantially equal to the threshold voltage of the switching transistor.

[0246] In a transistor according to one embodiment of the present invention, at least one interlayer insulating film may be disposed between the oxide semiconductor layer and the lower gate. The upper gate and the lower gate may be connected to each other via a contact hole configured to penetrate the gate insulating film and the at least one interlayer insulating film. The contact hole may be spaced apart from the oxide semiconductor layer.

[0247] In a transistor according to one embodiment of the present invention, one of the first source-drain and the second source-drain may be connected to an electrode of a light-emitting element, such that current is provided to the light-emitting element via the transistor.

[0248] A display device according to one embodiment of the present invention may include: a first transistor, a second transistor, and a voltage supply line. The first transistor is disposed on a substrate and may include a first oxide semiconductor layer and a first upper gate. The first oxide semiconductor layer includes a first channel, and the first upper gate is configured to overlap the first channel on the first oxide semiconductor layer. The second transistor is disposed on the substrate and spaced apart from the first transistor. The second transistor may include: a second oxide semiconductor layer having a second channel at a center and a first source-drain region and a second source-drain region located on both sides of the second channel; a second upper gate disposed above the second oxide semiconductor layer and configured to overlap the second channel, with a gate insulating film interposed between the second upper gate and the second channel; and a lower gate disposed below the second oxide semiconductor layer, configured to overlap at least the second channel, and connected to the second upper gate at a location configured to extend outward from the second oxide semiconductor layer. The voltage supply line may be connected to the lower gate.

[0249] In a display device according to one embodiment of the present invention, a positive constant voltage can be provided to the voltage supply line.

[0250] In a display device according to one embodiment of the present invention, the first transistor may be a switching transistor, and the second transistor may be a driving transistor. The threshold voltage of the first transistor and the threshold voltage of the second transistor can be matched to each other by the voltage supplied to the voltage supply line. In other words, the threshold voltage of the first transistor and the threshold voltage of the second transistor can be equal to or substantially equal to each other by the voltage supplied to the voltage supply line.

[0251] In a display device according to one embodiment of the present invention, the voltage supply line may be integrally formed with the lower gate of the second transistor.

[0252] In a display device according to one embodiment of the present invention, the voltage supply line may be a reference voltage line.

[0253] In a display device according to one embodiment of the present invention, the voltage supply line can selectively supply a positive constant voltage to the lower gate.

[0254] In a display device according to one embodiment of the present invention, at least one interlayer insulating film may be disposed between the second oxide semiconductor layer and the lower gate. The second upper gate and the lower gate may be connected to each other via a contact hole configured to penetrate the gate insulating film and the at least one interlayer insulating film. The contact hole may be spaced apart from the second oxide semiconductor layer.

[0255] In a display device according to one embodiment of the present invention, the width of the second channel of the second transistor may be larger than the width of the first channel of the first transistor.

[0256] In a display device according to one embodiment of the present invention, the first oxide semiconductor layer and the second oxide semiconductor layer may be located in the same layer.

[0257] In a display device according to one embodiment of the present invention, the first source-drain region may be connected to a first source-drain, and the second source-drain region may be connected to a second source-drain. One of the first source-drain and the second source-drain may be connected to a light-emitting element.

[0258] In a display device according to one embodiment of the present invention, the first transistor may be a switching transistor, and the second transistor may be a driving transistor. The first channel and the second channel may differ in at least one of their width and length. The gate on-state voltage of the first transistor may be higher than the gate on-state voltage of the second transistor. The threshold voltage of the first transistor and the threshold voltage of the second transistor may be the same or have a difference of 0.4V or less.

[0259] The display device according to one embodiment of the present invention may further include a light-shielding metal positioned below the first oxide semiconductor layer, overlapping the first channel, and disposed at a layer different from the lower gate.

[0260] In a display device according to an embodiment of the present invention, the first transistor may be a switching transistor, and the second transistor may be a driving transistor; the first transistor and the second transistor may be disposed at each of a plurality of sub-pixels located on the substrate.

[0261] In a display device according to one embodiment of the present invention, the first transistor may be a switching transistor, and the second transistor may be a driving transistor. The second transistor may be disposed at each of a plurality of sub-pixels located on the substrate. The first transistor may be disposed in a non-active region configured to surround the plurality of sub-pixels.

[0262] A display device according to one embodiment of the present invention may further include a third transistor at each of the plurality of sub-pixels, the third transistor including a semiconductor layer including a third channel having a different width from the second channel.

[0263] As is clear from the above description, the driving transistor of the present invention and the display device including the driving transistor have the following effects.

[0264] In addition to the upper gate disposed above the upper side of the semiconductor layer, the transistor of the present invention also has a lower gate disposed below the semiconductor layer, thereby enabling separate voltage compensation via the lower gate.

[0265] The transistor of the present invention has the following characteristics: the slope of the IV curve, which represents the voltage-current relationship from the off state to the on state for grayscale representation, is small, but the threshold voltage can be reduced by selectively applying a positive bias voltage to the lower gate.

[0266] The transistor of the present invention can reduce the threshold voltage by selectively providing voltage, and the stress applied to the transistor can be reduced due to the reduced threshold voltage. Additionally, it has the effect of reducing power consumption when the transistor is driven.

[0267] In the driving transistor and the switching transistor (which have IV curves with different slopes), the display device of the present invention can provide a positive bias voltage through a voltage supply line connected to the lower gate of the driving transistor, thereby shifting the threshold voltage of the driving transistor in the negative direction to match the threshold voltage of the switching transistor. This allows the threshold voltages of the switching transistor and the driving transistor, which have different operating characteristics and functions, to be matched with each other.

[0268] The display device of the present invention can adjust the threshold voltage of the driving transistor and the threshold voltage of the switching transistor to be similar to each other. This adjustment of the threshold voltage can be selectively performed so that even if the difference between the threshold voltage of the switching transistor and the threshold voltage of the driving transistor changes with time according to the driving action, this state can be adjusted to an initial state.

[0269] The display device of the present invention can realize transistors with different characteristics without any additional processes by adjusting the overlap area between the upper gate of the transistor and the oxide semiconductor layer and changing the arrangement of the lower gate or the light-shielding metal in the transistor that includes at least an oxide semiconductor layer.

[0270] The display device of the present invention can realize transistors with different characteristics without any additional processes, thereby reducing greenhouse gases generated by additional manufacturing processes, optimizing processes, and achieving sustainable environmental / social / governance effects.

[0271] From the above description, it will be clear to those skilled in the art that various changes and modifications are possible without departing from the spirit of the invention. Therefore, the scope of the invention should not be limited to the detailed description above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but rather should be interpreted to include all possible embodiments within the full scope of their equivalence.

Claims

1. A transistor, comprising: An oxide semiconductor layer having a first source-drain region, a channel, and a second source-drain region in a first direction; An upper gate is disposed above the oxide semiconductor layer and configured to overlap the channel, and a gate insulating film is interposed between the upper gate and the channel; A lower gate, disposed below the oxide semiconductor layer, configured to at least overlap the channel, and connected to the upper gate at a location configured to extend outward from the oxide semiconductor layer; The first source-drain and the second source-drain are respectively connected to the first source-drain region and the second source-drain region; as well as A voltage supply line, which is connected to the lower gate and configured to provide a positive constant voltage to the voltage supply line.

2. The transistor of claim 1, wherein the voltage supply line is integrally formed with the lower gate.

3. The transistor of claim 1, wherein the voltage supply line is a reference voltage line.

4. The transistor according to claim 1, wherein: The positive constant voltage is selectively provided through the voltage supply line. The threshold voltage of the transistor used as the driving transistor is matched with the threshold voltage of the switching transistor.

5. The transistor according to claim 1, wherein: At least one interlayer insulating film is disposed between the oxide semiconductor layer and the lower gate. The upper gate and the lower gate are connected to each other via a contact hole configured to penetrate the gate insulating film and the at least one interlayer insulating film. The contact hole is spaced apart from the oxide semiconductor layer.

6. The transistor of claim 1, wherein one of the first source-drain and the second source-drain is connected to an electrode of the light-emitting element such that current is provided to the light-emitting element via the transistor.

7. A display device, comprising: A first transistor is disposed on a substrate and includes a first oxide semiconductor layer and a first upper gate, the first oxide semiconductor layer including a first channel, and the first upper gate being configured to overlap the first channel on the first oxide semiconductor layer. A second transistor, disposed on the substrate and spaced apart from the first transistor, includes: a second oxide semiconductor layer having a second channel at its center and a first source-drain region and a second source-drain region located on both sides of the second channel; a second upper gate disposed above the second oxide semiconductor layer and configured to overlap the second channel, with a gate insulating film interposed between the second upper gate and the second channel; and a lower gate disposed below the second oxide semiconductor layer, configured to at least overlap the second channel, and connected to the second upper gate at a location configured to extend outward from the second oxide semiconductor layer; and A voltage supply line, which is connected to the lower gate.

8. The display device of claim 7, wherein a positive constant voltage is provided to the voltage supply line.

9. The display device according to claim 7, wherein: The first transistor is a switching transistor, and the second transistor is a driving transistor. The threshold voltage of the first transistor and the threshold voltage of the second transistor are matched to each other by the voltage supplied to the voltage supply line.

10. The display device of claim 7, wherein the voltage supply line is integrally formed with the lower gate of the second transistor.

11. The display device according to claim 7, wherein the voltage supply line is a reference voltage line.

12. The display device of claim 7, wherein the voltage supply line selectively provides a positive constant voltage to the lower gate.

13. The display device according to claim 7, wherein: At least one interlayer insulating film is disposed between the second oxide semiconductor layer and the lower gate. The second upper gate and the lower gate are connected to each other via a contact hole configured to penetrate the gate insulating film and the at least one interlayer insulating film. The contact hole is spaced apart from the second oxide semiconductor layer.

14. The display device of claim 7, wherein the width of the second channel of the second transistor is greater than the width of the first channel of the first transistor.

15. The display device according to claim 7, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are located in the same layer.

16. The display device according to claim 7, wherein: The first source-drain region is connected to the first source-drain region. The second source-drain region is connected to the second source-drain region. One of the first source-drain and the second source-drain is connected to the light-emitting element.

17. The display device according to claim 7, wherein: The first transistor is a switching transistor, and the second transistor is a driving transistor. The first channel and the second channel differ in at least one of their width and length. The gate on-state voltage of the first transistor is higher than that of the second transistor. The threshold voltage of the first transistor is the same as or has a difference of 0.4V or less with the threshold voltage of the second transistor.

18. The display device of claim 7, further comprising a light-shielding metal positioned below the first oxide semiconductor layer, overlapping the first channel, and disposed at a layer different from the lower gate.

19. The display device according to claim 18, wherein: The first transistor is a switching transistor, and the second transistor is a driving transistor. The first transistor and the second transistor are disposed at each of the plurality of sub-pixels located on the substrate.

20. The display device according to claim 18, wherein: The first transistor is a switching transistor, and the second transistor is a driving transistor. The second transistor is disposed at each of the plurality of sub-pixels located on the substrate. The first transistor is disposed in a non-active region, which is configured to surround the plurality of sub-pixels.

21. The display device of claim 20, further comprising a third transistor at each of the plurality of sub-pixels, the third transistor comprising a semiconductor layer having a third channel having a different width from the second channel.

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