Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device comprises a substrate; an epitaxial layer; a trench gate structure; the trench gate structure comprises a plurality of U-direction trench gates extending along a first direction and a plurality of V-direction trench gates extending along a second direction intersecting with the first direction, the plurality of U-direction trench gates are arranged in parallel along a direction perpendicular to the first direction, and the plurality of V-direction trench gates are arranged in parallel along a direction perpendicular to the first direction. The multiple V-direction trench gates are arranged in parallel in the direction perpendicular to the second direction, each V-direction trench gate is connected with two adjacent U-direction trench gates, and the multiple V-direction trench gates are alternately connected with the first side wall and the second side wall of the same U-direction trench gate. The trench gate structure is arranged to extend in a zigzag shape, the ratio of the width of the shielding region to the width between the two adjacent shielding regions is optimized, and then the on-resistance and the reverse characteristic are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] Third-generation semiconductor materials, represented by silicon carbide (SiC), enable devices to achieve higher power density and efficiency due to their excellent properties such as high frequency, high voltage, high temperature resistance, and radiation resistance. As a representative of switching devices made of this type of material, silicon carbide (SiC) power MOSFETs have been widely used in the field of power electronics due to their advantages of low switching loss and high operating frequency.

[0003] Currently, SiC power MOSFETs mainly employ two technical approaches: planar gate and trench gate. The trench gate structure, with its higher channel mobility and smaller cell size, offers superior conduction capability. To reduce the Rsp (resistance per unit area) of power semiconductor MOSFETs, one approach is to maximize the channel width within the same area. To achieve this, besides reducing the cell pitch, the cell type can also be changed. However, in traditional cell types, the trench width at the cell intersections (in trench MOSFETs) widens, resulting in a deterioration in reverse characteristics. Summary of the Invention

[0004] In view of the above problems, the purpose of this application is to provide a semiconductor device that improves on-resistance and reverse characteristics and provides good shielding by optimizing the trench gate structure and the ratio of the width of the shielding region to the width between two adjacent shielding regions.

[0005] According to one aspect of this application, a semiconductor device is provided, comprising: a substrate; an epitaxial layer located on a first surface of the substrate; and a trench gate structure located in the epitaxial layer and extending from the first surface of the epitaxial layer to a second surface; wherein the trench gate structure includes a plurality of U-shaped trench gates extending along a first direction and a plurality of V-shaped trench gates extending along a second direction intersecting the first direction, the plurality of U-shaped trench gates being arranged parallel to each other in a direction perpendicular to the first direction, the plurality of V-shaped trench gates being arranged parallel to each other in a direction perpendicular to the second direction, the V-shaped trench gates connecting two adjacent U-shaped trench gates, wherein the plurality of V-shaped trench gates are alternately connected to a first sidewall and a second sidewall of the same U-shaped trench gate.

[0006] Optionally, the plurality of V-direction trench gates include a plurality of first V-direction trench gates and a plurality of second V-direction trench gates. The first V-direction trench gates and the second V-direction trench gates connected to the same U-direction trench gate are respectively connected to the first sidewall and the second sidewall of the U-direction trench gate, and the first V-direction trench gates and the second V-direction trench gates are not collinear along the second direction.

[0007] Optionally, the semiconductor device further includes a shielding region located at the bottom of the node where the U-direction trench gate and the V-direction trench gate intersect.

[0008] Optionally, along the first direction, among the three adjacent shielding areas located below the same U-shaped trench grid, the first interval width between the middle shielding area and the first shielding area and the third interval width between the middle shielding area and the third shielding area are the same.

[0009] Optionally, along the first direction, the ratio of the first width of the shielding area to the first and / or third interval width between two adjacent shielding areas is greater than or equal to 1 / 5 and less than or equal to 1.

[0010] Optionally, along the direction perpendicular to the first direction, the ratio of the second width of the shielding area to the second interval width between two adjacent shielding areas is greater than or equal to 1 / 5 and less than or equal to 1.

[0011] Optionally, along a direction perpendicular to the first direction, the interval between two adjacent shielding areas is a second interval width; along the first direction, the interval between two adjacent shielding areas includes a first interval width and a third interval width; wherein, the second interval width is less than or equal to the first interval width, and the second interval width is less than or equal to the third interval width.

[0012] Optionally, at the node where the U-direction trench grid intersects with the V-direction trench grid, the shielding area covers the first sidewall, the second sidewall, and the bottom of the U-direction trench grid, and the shielding area covers the first sidewall, the second sidewall, and the bottom of the V-direction trench grid.

[0013] Optionally, at the node where the U-direction trench grid intersects with the V-direction trench grid, the shielding area covers the first or second sidewall of the U-direction trench grid and the bottom portion connected to the sidewall, and the shielding area covers the first sidewall, the second sidewall, and the bottom of the V-direction trench grid.

[0014] Optionally, the shielding area is projected onto the first surface of the epitaxial layer in the shape of a triangle.

[0015] Optionally, two vertices of the triangle are located at two intersecting nodes of the U-direction trench gate and the V-direction trench gate, respectively, and the other vertex of the triangle is located on the opposite sidewall of the U-direction trench gate, opposite to the sidewall where the intersecting node is located.

[0016] Optionally, the first direction is perpendicular to the second direction.

[0017] The semiconductor device provided in this application features a trench gate structure that extends in a zigzag pattern. Specifically, a second trench gate, connected to a first trench gate, is alternately connected on the first and second sidewalls of the first trench gate, forming a continuous zigzag path. This structure optimizes the ratio of the width of the shielding region to the width between two adjacent shielding regions. This structure effectively disperses electric field concentration, further optimizing the electric field distribution on the device surface, thereby improving the breakdown voltage. Simultaneously, this structure increases the channel width per unit area, which helps reduce on-resistance. By precisely controlling the ratio of the shielding region width to the spacing between adjacent shielding regions, the shielding effect and carrier migration efficiency are optimally matched. While ensuring good electric field shielding performance, interference with the current path is reduced, significantly improving the device's conduction and reverse recovery characteristics.

[0018] In addition, the zigzag extended trench gate structure is compatible with the existing silicon carbide device manufacturing process in terms of process implementation, which can effectively reduce process complexity and manufacturing cost, and is conducive to large-scale industrial application. Attached Figure Description

[0019] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0020] Figure 1 A three-dimensional structural schematic diagram of a semiconductor device according to a first embodiment of this application is shown;

[0021] Figure 2 A top view of a semiconductor device according to a first embodiment of this application is shown;

[0022] Figure 3 A semiconductor device according to a first embodiment of this application is shown. Figure 2 A schematic diagram of the cross-section of the dashed line AA;

[0023] Figure 4 A semiconductor device according to a first embodiment of this application is shown. Figure 2 A cross-sectional diagram of the dashed line BB;

[0024] Figure 5 A semiconductor device according to a first embodiment of this application is shown. Figure 2 A cross-sectional diagram of the dashed line CC;

[0025] Figure 6 A top view of a semiconductor device according to a second embodiment of this application is shown;

[0026] Figure 7 A top view of a semiconductor device according to a third embodiment of this application is shown;

[0027] Figure 8 A top view of a semiconductor device according to a fourth embodiment of this application is shown;

[0028] Figure 9 A top view of a semiconductor device according to a fifth embodiment of this application is shown;

[0029] Figure 10 A top view of a semiconductor device according to a sixth embodiment of this application is shown. Detailed Implementation

[0030] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0031] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0032] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".

[0033] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0034] The specific implementation methods of this application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0035] like Figures 1 to 10 As shown, to facilitate a clear description of the specific embodiments of this application, the first direction is defined as the U direction, the second direction as the V direction, and the third direction as the W direction.

[0036] Figure 1 A three-dimensional structural diagram of a semiconductor device according to a first embodiment of this application is shown; Figure 2 A top view of a semiconductor device according to a first embodiment of this application is shown; Figure 3 A semiconductor device according to a first embodiment of this application is shown. Figure 2 Cross-sectional view of the dashed line AA; Figure 4 A semiconductor device according to a first embodiment of this application is shown. Figure 2 Cross-sectional view of the dashed line BB; Figure 5 A semiconductor device according to a first embodiment of this application is shown. Figure 2 Cross-sectional view of the dashed line CC.

[0037] like Figures 1 to 5 As shown, the semiconductor device 100 of this application embodiment includes a substrate 110, an epitaxial layer 120, a trench gate structure 130, a source region 141, a body contact region 142, a body region 143, a shielding region 144, an interlayer dielectric layer 121, a source metal layer (not shown in the figure), and a drain metal layer 152.

[0038] The substrate 110 includes a first surface and a second surface opposite to each other, and the epitaxial layer 120 is located on the first surface of the substrate 110.

[0039] The substrate 110 may be made of elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon-germanium (SiGe), or binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP). However, the embodiments of this application are not limited thereto, and those skilled in the art may make other settings for the material of the substrate 110 as needed.

[0040] The crystal orientation of the substrate 110 may include the m-plane (1-100) or the a-plane (11-20).

[0041] The epitaxial layer 120 includes a first surface and a second surface opposite to each other, the second surface being adjacent to the first surface of the substrate 110, and the first surface of the epitaxial layer 120 being away from the first surface of the substrate 110. The epitaxial layer 120 may be made of the same or different semiconductor material as the substrate 110.

[0042] The epitaxial layer 120 is of the first doping type. The thickness and doping concentration of the epitaxial layer 120 can be designed according to the device's withstand voltage and on-resistance requirements.

[0043] The trench gate structure 130 is formed in the epitaxial layer 120 and extends from the first surface of the epitaxial layer 120 to the second surface. The trench gate structure 130 includes a gate dielectric layer 131 and a gate conductor 132 filled in the gate dielectric layer 131.

[0044] The gate dielectric layer 131 covers the sidewalls and bottom of the trench, and its material can be selected from silicon oxide, silicon nitride or high-k dielectric material to improve gate control capability and reduce leakage current.

[0045] The gate conductor 132 fills the space enclosed by the gate dielectric layer 131, and its material includes polysilicon or metal.

[0046] The gate dielectric layer 131 separates the gate conductor 132 from the epitaxial layer 120 to prevent leakage and ensure effective control of the channel by the gate.

[0047] The trench gate structure 130 includes a plurality of U-shaped trench gates 1301 and a plurality of V-shaped trench gates 1302. The plurality of U-shaped trench gates 1301 extend along a first direction and are arranged parallel to each other in a direction perpendicular to the first direction; the plurality of V-shaped trench gates 1302 extend along a second direction and are arranged parallel to each other in a direction perpendicular to the second direction.

[0048] Among them, such as Figure 2 As shown, the U-direction trench gate 1301 includes opposing first sidewalls S11 and second sidewalls S12, and the V-direction trench gate 1302 includes opposing first sidewalls S21 and second sidewalls S22. Multiple V-direction trench gates 1302 connected to the same U-direction trench gate 1301 are alternately connected to the first sidewalls S11 and second sidewalls S12 of the U-direction trench gate 1301, forming a continuous zigzag path.

[0049] The V-direction trench gate 1302 further includes a first V-direction trench gate 1302a and a second V-direction trench gate 1302b. In the second direction, the first V-direction trench gate 1302a and the second V-direction trench gate 1302b are not collinear, that is, the intersection points of the first V-direction trench gate 1302a and the second V-direction trench gate 1302b with the same U-direction trench gate 1301 do not overlap.

[0050] Alternatively, in some embodiments, it can be understood that the first V-direction trench gate 1302a and the second V-direction trench gate 1302b are parallel to each other and do not intersect.

[0051] Along the second direction, among the three adjacent U-shaped trench gates 1301, the plurality of V-shaped trench gates 1302 located between the middle U-shaped trench gate 1301 and the first U-shaped trench gate 1301 are all one of the first V-shaped trench gate 1302a and the second V-shaped trench gate 1302b. The plurality of V-shaped trench gates 1302 located between the middle U-shaped trench gate 1301 and the third U-shaped trench gate 1301 are all another of the first V-shaped trench gate 1302a and the second V-shaped trench gate 1302b. Furthermore, for the middle U-shaped trench gate 1301, the first V-shaped trench gate 1302a and the second V-shaped trench gate 1302b are alternately connected to the first sidewall S11 and the second sidewall S12 of the U-shaped trench gate 1301.

[0052] like Figure 2 In this embodiment, the first direction is not perpendicular to the second direction, the first direction is perpendicular to the third direction, and the second direction is perpendicular to the third direction.

[0053] In this embodiment, two adjacent U-direction trench gates 1301 and two adjacent V-direction trench gates 1302 in the middle together form a parallelogram grid unit on the first surface of the epitaxial layer 120. The grid unit is periodically arranged on the plane formed by the first direction and the second direction to form a complete trench gate array.

[0054] The source region 141 extends to a certain depth from the first surface of the epitaxial layer 120 to the second surface, and one sidewall of the source region 141 is adjacent to the sidewall of the trench gate structure 130. The source region 141 is of the first doping type, and its doping concentration is higher than that of the epitaxial layer 120.

[0055] In this embodiment, the depth of the source region 141 extending from the first surface of the epitaxial layer 120 to the second surface is less than the depth of the trench gate structure 130 extending from the first surface of the epitaxial layer 120 to the second surface.

[0056] The body contact region 142 extends a certain depth from the first surface of the epitaxial layer 120 to the second surface. The sidewall of the body contact region 142 is adjacent to the side of the source region 141 away from the trench gate structure 130. The body contact region 142 is of the second doping type. The first doping type is the opposite of the second doping type. The first doping type is one of P-type and N-type, and the second doping type is the other of P-type and N-type.

[0057] On the first surface of the epitaxial layer 120, the source region 141 is located between the bulk contact region 142 and the trench gate structure 130.

[0058] In this embodiment, the depth of the body contact region 142 extending from the first surface of the epitaxial layer 120 to the second surface is less than the depth of the trench gate structure 130 extending from the first surface of the epitaxial layer 120 to the second surface, but is substantially equal to the depth of the source region 141 extending from the first surface of the epitaxial layer 120 to the second surface.

[0059] Body region 143 extends from the second surface of source region 141 and body contact region 142 toward the second surface of epitaxial layer 120, and the sidewall of body region 143 is adjacent to the sidewall of trench gate structure 130. Body region 143 is of the second doping type, and its doping concentration is lower than that of body contact region 142.

[0060] In this embodiment, the first surface of the body region 143 is adjacent to the second surfaces of the source region 141 and the body contact region 142, but the second surface of the body region 143 is located between the second surfaces of the source region 141 and the body contact region 142 and the bottom surface of the trench gate structure 130, and does not extend to the bottom of the trench gate structure 130, so that part of the sidewall of the trench gate structure is adjacent to the epitaxial layer 120.

[0061] The shielding region 144 is located at the bottom of the node where the U-direction trench gate 1301 and the V-direction trench gate 1302 intersect. The shielding region 144 can effectively reduce the electric field concentration effect in the bottom region of the trench gate structure 130 and improve the breakdown voltage capability of the device. Among them, the shielding region 144 is a second doping type.

[0062] exist Figure 1 In the embodiment shown, the projection shape of the shielding region 144 on the first surface of the epitaxial layer 120 is square, and the projection of the node where the U-direction trench gate 1301 and the V-direction trench gate 1302 intersect on the first surface of the epitaxial layer 120 falls into the projection of the shielding region 144.

[0063] At the node where the U-direction trench gate 1301 and the V-direction trench gate 1302 intersect, the shielding area 144 covers the first sidewall S11, the second sidewall S12 and the bottom of the U-direction trench gate 1301, and the shielding area 144 covers the first sidewall S21, the second sidewall S22 and the bottom of the V-direction trench gate 1302, thereby completely covering the bottom corner of the connection area between the U-direction trench gate 1301 and the V-direction trench gate 1302, effectively mitigating electric field peaks and improving the stability and reliability of the device under high-frequency and high-voltage conditions.

[0064] Since the shielding area 144 is used to shield the nodes where the U-direction trench grid 1301 and the V-direction trench grid 1302 intersect, and the second direction in which the V-direction trench grid 1302 extends is not perpendicular to the first direction, the shielding areas 144 at both ends of the same V-direction trench grid 1302 are not collinear in the direction perpendicular to the first direction.

[0065] refer to Figure 2Multiple shielding zones 144 are arranged in an array along the first and second directions, with a certain distance between them, to adapt to the corresponding trench grid structure layout.

[0066] In some embodiments, along the first direction, the spaced-apart shielding areas 144 shield the bottom and sidewalls of the corresponding area of ​​the trench grid structure 130 and are adjacent to the second surface of the body area 143, so that current cannot flow through the area and a channel cannot be formed. At the same time, since the shielding area 144 is in direct contact with the bottom of the trench grid structure 130, the shielding area 144 in the area can effectively protect the bottom corner of the trench grid structure 130 from being penetrated.

[0067] Between two adjacent shielding regions 144, the bottom of the trench gate structure 130 is directly adjacent to the epitaxial layer 120, so that this part of the trench gate structure 130, together with the epitaxial layer 120 and the body region 143, forms an effective conductive channel to ensure that the charge carriers are smoothly conducted under the control of the gate.

[0068] Interlayer dielectric layer 121 is located on the first surface of epitaxial layer 120, which shields the trench gate structure 130 exposed on the first surface of epitaxial layer 120 and covers part of the surface of source region 141 adjacent to the sidewall of trench gate structure 130, forming an insulating protective layer.

[0069] The source metal layer (not shown in the figure) is located above the source region 141 and the body contact region 142, forming an ohmic contact with the source region 141 and the body contact region 142, and extends to cover the surface of the interlayer dielectric layer 121. The interlayer dielectric layer 121 serves as an insulating layer, effectively isolating the direct electrical connection between the source metal layer and the trench gate structure 130, preventing the risk of short circuits.

[0070] The drain metal layer 152 is located on the second surface of the substrate 110, forming an ohmic contact with the epitaxial layer 120 and the substrate 110 to enable current conduction in the vertical direction of the device. The drain metal layer withstands a high potential when the device is off, and it works in conjunction with the trench gate structure 130, the shielding region 144 and the body region 143 to optimize the electric field distribution and further improve the breakdown voltage and reliability of the device.

[0071] refer to Figure 2 and Figure 3 In the first direction, along Figure 2 In the cross section at the direction indicated by the dashed line AA, the U-shaped trench gate 1301 extends continuously, and the shielding area 144 periodically shields the bottom area of ​​the U-shaped trench gate 1301, so that the unshielded part directly contacts the epitaxial layer 120 to form a conductive path.

[0072] refer to Figure 2 and Figure 4 ,along Figure 2In the cross section at the direction indicated by the dashed line BB, V-shaped trench grids 1302 are arranged at intervals. Between the sidewalls of adjacent V-shaped trench grids 1302, an active region 141, a body contact region 142, and a body region 143 are formed. The body region 143 and the active region 141 are connected to the sidewalls of the V-shaped trench grids 1302. The body contact region 142 is located between two adjacent V-shaped trench grids 1302 and is surrounded by the active region 141 to separate the body contact region 142 from the V-shaped trench grids 1302.

[0073] refer to Figure 2 and Figure 5 ,along Figure 2 In the cross-section at the direction indicated by the dashed line CC, V-shaped trench gates 1302 extend at intervals, and a body region 143, a body contact region 142, and a source region 141 are formed between adjacent V-shaped trench gates 1302. In this cross-section, since the ends of the U-shaped trench gates 1301 and the V-shaped trench gates 1302 are connected, the shielding region 144, when covering the bottom corner areas of the ends of both sides of the V-shaped trench gates 1302, [is effective / effective]. Figure 5 This is manifested in the trench gate 130 extending from a position far from the corner at the bottom towards the end, while simultaneously extending downwards along the sidewall of the trench gate structure 130 for a certain width and upwards to adjoin the second surface of the body region 143. In the same continuously extending trench gate structure 130, the shielding region 144 is symmetrically distributed at the bottom corner, so the unshielded part at the bottom of the middle region of the trench gate structure 130 is in direct contact with the epitaxial layer 120, forming a conductive channel and realizing the effective transport of charge carriers.

[0074] Among them, reference Figure 2 In a single unit region (e.g., the trench gate structure 130 forming a parallelogram as shown by the dashed box M in Figure 2, and the source region 141 and the volume contact region 142 in the middle of the parallelogram), to more clearly describe the technical characteristics of the shielding region 144, the shielding region 144 at the node where the first V-direction trench gate 1302a intersects with the U-direction trench gate 1301 is defined as the first shielding region 1441, and the shielding region 144 at the node where the second V-direction trench gate 1302b intersects with the U-direction trench gate 1301 is defined as the second shielding region 1442. The first shielding region 1441 and the second shielding region 1442 have identical physical characteristics such as structure, shape, size, and doping.

[0075] It is understood that the above selection of unit region is just an example. Other unit regions can also be selected. For example, a unit consisting of two first shielding regions 1441 and a second shielding region 1442 can be selected. The final result obtained is consistent with the result obtained by the above selection of unit region.

[0076] Along the first direction, the shielding area 144 (including the first shielding area 1441 and the second shielding area 1442) has a first width Wa; with the first shielding area 1441 as a reference, among the three adjacent shielding areas 144, the second shielding area 1442 on the left and the first shielding area 1441 have a first interval width Wb, and the second shielding area 1442 on the right and the first shielding area 1441 have a third interval width We.

[0077] In some embodiments, the first spacing width Wb is equal to the third spacing width We, meaning that three adjacent shielding regions 144 are equally spaced. Due to the zigzag arrangement of the trench gate structure 130, the equally spaced distribution of three adjacent shielding regions 144 indicates that multiple shielding regions 144 are equally spaced along the first direction. The equally spaced shielding regions 144 make the electric field distribution at each trench gate node more uniform, effectively alleviating local electric field concentration and thus improving the breakdown voltage characteristics of the device. Simultaneously, the equally spaced arrangement simplifies mask design and process alignment, improving manufacturing consistency and yield.

[0078] In other embodiments, the first interval width Wb may not be equal to the third interval width We, that is, the three adjacent shielding areas 144 are not equally spaced.

[0079] In some embodiments, along the first direction, the ratio of the first width Wa of the shielding area 144 to one of the first interval width Wb or the third interval width We between two adjacent shielding areas 144 is greater than or equal to 1 / 5 and less than or equal to 1. Alternatively, the ratio of the first width Wa of the shielding area 144 to both the first interval width Wb and the third interval width We between two adjacent shielding areas 144 is greater than or equal to 1 / 5 and less than or equal to 1.

[0080] The smaller the ratio of the width of the shielding region 144 to the spacing width between two adjacent shielding regions 144, the better the Rsp (on-resistance) characteristics of the semiconductor device. However, if the ratio is too small, the width of the shielding region 144 may become too narrow, which may lead to poor shielding effect. Therefore, a ratio greater than or equal to 1 / 5 and less than or equal to 1 is configured to balance the voltage withstand capability and reliability of the semiconductor device while minimizing the Rsp (on-resistance) of the semiconductor device.

[0081] In some embodiments, along the first direction, the first width Wa of the shielding region 144 is greater than the width D2 of the V-direction trench gate 1302, so that the shielding region 144 can completely shield the corner at the connection between the U-direction trench gate 1301 and the V-direction trench gate 1302 in the first direction, optimize the electric field distribution, and improve the breakdown voltage and reliability of the device.

[0082] In some embodiments, along the first direction, at the node where the U-direction trench gate 1301 and the V-direction trench gate 1302 intersect, since the shielding area 144 covers the first sidewall S21, the second sidewall S22, and the bottom of the V-direction trench gate 1302, the second distance D3 between two adjacent V-direction trench gates 1302 is greater than the first spacing width Wb and the third spacing width We between two adjacent shielding areas 144 below the same U-direction trench gate 1301. Furthermore, the second distance D3 between two adjacent V-direction trench gates 1302 is greater than the sum of the first spacing width Wb and the third spacing width We between two adjacent shielding areas 144 below the same U-direction trench gate 1301.

[0083] In a unit region, along a direction perpendicular to the first direction, the shielding area 144 has a second width Wc, and there is a second spacing width Wd between two adjacent shielding areas 144.

[0084] In some embodiments, the second spacing width Wd is less than or equal to the first spacing width Wb, and the second spacing width Wd is less than or equal to the third spacing width We. Since the V-direction trench gate 1302 does not extend continuously in the second direction and in the direction perpendicular to the first direction, the second spacing width Wd between two adjacent shielding areas 144 in the direction perpendicular to the first direction only represents the distance between two adjacent shielding areas 144 located at the bottom of the continuously extending V-direction trench gate 1302. Of course, if the U-direction trench gates 1301 are arranged at equal intervals in the direction perpendicular to the first direction, then the second spacing width Wd between any two adjacent shielding areas 144 in the direction perpendicular to the first direction is equal, thereby forming a uniformly distributed electric field modulation region on the two-dimensional plane, effectively alleviating local electric field concentration.

[0085] In some embodiments, along a direction perpendicular to the first direction, the ratio of the second width Wc of the shielding region 144 to the second spacing width Wd between two adjacent shielding regions 144 is greater than or equal to 1 / 5 and less than or equal to 1. At this ratio, both the voltage withstand capability and reliability of the semiconductor device can be considered, while minimizing the Rsp (on-resistance) of the semiconductor device.

[0086] In some embodiments, the second width Wc of the shielding area 144 is greater than the width D1 of the U-direction trench gate 1301 in the direction perpendicular to the first direction, so that the shielding area 144 can shield the corner at the connection between the first trench gate and the second trench gate in the direction perpendicular to the first direction.

[0087] In some embodiments, along the direction perpendicular to the first direction, the first distance D4 between two adjacent U-direction trench gates 1301 is greater than the second spacing width Wd between two adjacent shielding areas 144 below the same V-direction trench gate 1302. Simultaneously, along the direction perpendicular to the first direction, the first distance D4 between two adjacent U-direction trench gates 1301 is greater than the third distance D5 between two adjacent shielding areas 144 below different V-direction trench gates 1302.

[0088] In this embodiment, since the projection of the shielding area 144 onto the first surface of the epitaxial layer 120 is a square, the first width Wa and the second width Wc of the shielding area 144 are equal, i.e., Wa=Wc; while the first interval width Wb and the second interval width Wd are set as needed, and can be equal or unequal, but both must meet the ratio range requirements in their respective directions.

[0089] The total width of a cell region in the first direction includes at least two first widths Wa, a first spacing width Wb and a third spacing width We, and the total width in the direction perpendicular to the first direction includes at least a second width Wc and a second spacing width Wd. When Wa=Wc and Wb=Wd, the cell region presents a rectangular symmetrical layout, which is beneficial to achieving a uniform electric field distribution in the two-dimensional direction of the device.

[0090] In the semiconductor device 100, since no conductive channel is formed at the shielding region 144, the narrower the first width Wa and the second width Wc of the shielding region 144, the more it helps to reduce the on-resistance Ron. However, no matter how the first width Wa and the second width Wc of the shielding region 144 change, they must still satisfy the requirement of shielding the corner at the connection between the U-direction trench gate 1301 and the V-direction trench gate 1302.

[0091] Figure 6 A top view of a semiconductor device according to a second embodiment of this application is shown.

[0092] In this embodiment, the various dimensions, distances, connections, and positional relationships are related to... Figure 2 The dimensions, distances, connections, and positional relationships are the same in the embodiments shown.

[0093] In this embodiment, the extension direction of the V-direction trench gate 1302 is perpendicular to the first direction, that is, the second direction is perpendicular to the first direction. Since the first direction is perpendicular to the second direction, the U-direction trench gate 1301 and the V-direction trench gate 1302 are perpendicular to each other.

[0094] In the second direction, two adjacent shielding areas 144 located at both ends of the same V-shaped trench grid 1302 are collinear in the second direction.

[0095] Among them, the shielding areas 144 located at both ends of the same V-direction trench grid 1302 are arranged in a straight line in the second direction. This layout is conducive to simplifying mask design and process alignment, reducing process complexity, and improving manufacturing consistency and yield.

[0096] Figure 7 A top view of a semiconductor device according to a third embodiment of this application is shown.

[0097] In this embodiment, the projection shape of the shielding area 144 on the first surface of the epitaxial layer 120 is triangular, and two adjacent shielding areas 144 located at the bottom of the same V-direction trench gate 1302 are not collinear in the direction perpendicular to the first direction.

[0098] refer to Figure 7 In some embodiments, the projection of the shielding region 144 onto the first surface of the epitaxial layer 120 is triangular. In this case, two of the three vertices of the shielding region 144 are located at the nodes where the U-direction trench gate 1301 and the V-direction trench gate 1302 intersect, and extend out of the intersecting nodes; the other is located on the other sidewall of the U-direction trench gate 1301 opposite to the sidewall where the intersecting node is located, and extends out of the sidewall.

[0099] At the intersection of the U-direction trench grid 1301 and the V-direction trench grid 1302, the shielding region 144 covers the first sidewall S11, the second sidewall S12, and the bottom of the U-direction trench grid 1301, and the shielding region 144 covers the first sidewall S21, the second sidewall S22, and the bottom of the V-direction trench grid 1302. However, among the first sidewall S11 and the second sidewall S12 of the U-direction trench grid 1301 covered by the shielding region 144, the sidewall where the intersection node is located is covered by a larger area of ​​the shielding region 144.

[0100] In this embodiment, since the projection of the shielding area 144 on the first surface of the epitaxial layer 120 is triangular, for the other side wall corresponding to the connection between the U-direction trench gate 1301 and the V-direction trench gate 1302, the shielding area 144 only shields the bottom corner of the side wall at the sharp corner. The shielding area is smaller than that of the square projection, but while ensuring the electric field control effect, it further releases the channel area space, which is beneficial to increasing the gate density per unit area.

[0101] In other embodiments, two vertices of the triangular shielding region 144 may overlap with the nodes where the U-direction trench gate 1301 and the V-direction trench gate 1302 intersect, i.e., these two vertices are located at the intersecting nodes but do not extend beyond the intersecting nodes; the other vertex may be located at the edge of the other sidewall of the U-direction trench gate 1301 opposite to the sidewall where the intersecting node is located, i.e., this vertex is located at the edge of the other sidewall but does not extend beyond the edge of that sidewall.

[0102] In one unit region, reference Figure 7To more clearly describe the technical characteristics of the shielding region 144, the shielding region 144 at the node where the first V-direction trench gate 1302a intersects with the U-direction trench gate 1301 is defined as the first shielding region 1441, and the shielding region 144 at the node where the second V-direction trench gate 1302b intersects with the U-direction trench gate 1301 is defined as the second shielding region 1442. The first shielding region 1441 and the second shielding region 1442 have identical physical characteristics such as structure, shape, size, and doping.

[0103] Along the first direction, the first width Wa of the shielding area 144 (including the first shielding area 1441 and the second shielding area 1442) is defined as the side length of the triangle in the first direction; with the first shielding area 1441 as a reference, among the three adjacent shielding areas 144, the first interval width Wb is defined as the distance between the nearest side of the second shielding area 1442 on the left and the first shielding area 1441 in the first direction, and the third interval width We is defined as the distance between the nearest side of the second shielding area 1442 on the right and the first shielding area 1441 in the first direction.

[0104] In some embodiments, the ratio of the first width Wa to either the first spacing width Wb or the third spacing width We remains greater than or equal to 1 / 5 and less than or equal to 1. Alternatively, the ratio of the first width Wa to both the first spacing width Wb and the third spacing width We remains greater than or equal to 1 / 5 and less than or equal to 1. At this ratio, both the voltage withstand capability and reliability of the semiconductor device can be balanced, while minimizing the Rsp (on-resistance) of the semiconductor device.

[0105] like Figure 7 As shown, in a single unit region, along the direction perpendicular to the first direction, the second width Wc of the shielding region 144 is defined as the side length of the triangle extending along the second direction. The first spacing width Wd between two adjacent shielding regions 144 is defined as the distance between the nearest edges of two adjacent triangles in the direction perpendicular to the first direction. At this point, the ratio of the second width Wc of the shielding region 144 to the second spacing width Wd between two adjacent shielding regions can be maintained at greater than or equal to 1 / 5 and less than or equal to 1. Under this ratio, both the voltage withstand capability and reliability of the semiconductor device can be considered, while minimizing the Rsp (on-resistance) of the semiconductor device.

[0106] Since the V-direction trench gate 1302 is not continuously extended in the second direction, the second interval width Wd between two adjacent shielding areas 144 only represents the distance between two adjacent shielding areas 144 located at the bottom of the continuously extending V-direction trench gate 1302 in the direction perpendicular to the first direction. Of course, if the U-direction trench gates 1301 are arranged at equal intervals in the second direction, the second interval width Wd between any two adjacent shielding areas 144 in the second direction is equal and satisfies the aforementioned ratio range, thereby forming a uniformly distributed electric field modulation region on the two-dimensional plane, effectively alleviating local electric field concentration.

[0107] In some embodiments, the first interval widths Wb and We may be different along the first direction.

[0108] In other embodiments, the first spacing width Wb and the third spacing width We can also be the same along the first direction. In this case, the first shielding area 1441 and the two second shielding areas 1442 on both sides are symmetrically arranged, thereby further optimizing the symmetry and uniformity of the electric field distribution, which helps to improve the breakdown voltage stability and reliability of the device, and also makes the layout design simpler and easier to implement, reducing the manufacturing difficulty while ensuring electrical performance.

[0109] In some embodiments, along the first direction, the first width Wa is greater than the width D2 of the V-direction trench gate 1302.

[0110] Among them, the second distance D3 is greater than the sum of the first interval width Wb and the third interval width We.

[0111] In some embodiments, the second interval width Wd can be configured to be less than or equal to the first interval width Wb.

[0112] In some embodiments, the second interval width Wd can be configured to be less than or equal to the third interval width We.

[0113] In some embodiments, along a direction perpendicular to the first direction, the second width Wc of the shielding region 144 is greater than the width D1 of the U-direction trench gate 1301.

[0114] In some embodiments, along a direction perpendicular to the first direction, the first distance D4 between two adjacent U-direction trench gates 1301 can be configured to be greater than the second spacing width Wd between two adjacent shielding areas 144 below the same V-direction trench gate 1302.

[0115] With other structural dimensions being the same, the first spacing width Wb and the second spacing width We between two adjacent shielding regions 144 in this embodiment are increased, making the ratio of the first width Wa of the shielding region 144 to the first spacing width Wb and the second spacing width We between two adjacent shielding regions 144 smaller. This further optimizes the compactness of the gate layout while ensuring a uniform distribution of the electric field, and reduces the loss of channel width while ensuring enhanced reverse characteristics.

[0116] Figure 8 A top view of a semiconductor device according to a fourth embodiment of this application is shown.

[0117] In this embodiment, the various dimensions, distances, connections, and positional relationships are related to... Figure 7 The dimensions, distances, connections, and positional relationships are the same in the embodiments shown.

[0118] In this embodiment, the extension direction of the V-shaped trench gate 1302 is perpendicular to the first direction, that is, the second direction is perpendicular to the first direction.

[0119] Since the first direction is perpendicular to the second direction, the U-direction trench gate 1301 and the V-direction trench gate 1302 are perpendicular to each other.

[0120] In the second direction, two adjacent shielding areas 144 located at both ends of the same V-shaped trench grid 1302 are collinear in the second direction.

[0121] Among them, the shielding areas 144 located at both ends of the same V-direction trench grid 1302 are arranged in a straight line in the second direction. This layout not only increases the space of the trench area, but also helps to simplify the mask design and process alignment, reduce the complexity of the process, and improve manufacturing consistency and yield.

[0122] Figure 9 A top view of a semiconductor device according to a fifth embodiment of this application is shown.

[0123] In this embodiment, the projection shape of the shielding area 144 on the first surface of the epitaxial layer 120 is rectangular, and two adjacent shielding areas 144 located at the bottom of the same V-direction trench gate 1302 are not collinear in the direction perpendicular to the first direction.

[0124] refer to Figure 9 In some embodiments, the projection of the shielding region 144 onto the first surface of the epitaxial layer 120 is rectangular. In this case, two of the four vertices of the shielding region 144 are located at the two intersecting nodes of the U-direction trench gate 1301 and the V-direction trench gate 1302, and extend out of the intersecting nodes; the other two are located at the bottom of the U-direction trench gate 1301, that is, a sidewall of the shielding region 144 extending along the first direction falls between the first sidewall and the second sidewall of the U-direction trench gate 1301.

[0125] At the node where the U-direction trench grid 1301 and the V-direction trench grid 1302 intersect, the shielding area 144 covers the first sidewall S11 or the second sidewall S12 of the U-direction trench grid 1301 and covers the bottom portion connected to the sidewall. The shielding area 144 also covers the first sidewall S21, the second sidewall S22 and the bottom of the V-direction trench grid 1302.

[0126] In this embodiment, since the projection of the shielding area 144 on the first surface of the epitaxial layer 120 is rectangular, and one sidewall of the rectangle falls between the first and second sidewalls of the U-direction trench gate 1301, the shielding area 144 does not shield the bottom corner of the other sidewall corresponding to the connection between the U-direction trench gate 1301 and the V-direction trench gate 1302. The shielding area is smaller than that of the square projection and the triangular projection, but while ensuring the electric field control effect, it further releases the channel area space, which is beneficial to improve the gate density per unit area.

[0127] In one unit region, reference Figure 9 To more clearly describe the technical characteristics of the shielding region 144, the shielding region 144 at the node where the first V-direction trench gate 1302a intersects with the U-direction trench gate 1301 is defined as the first shielding region 1441, and the shielding region 144 at the node where the second V-direction trench gate 1302b intersects with the U-direction trench gate 1301 is defined as the second shielding region 1442. The first shielding region 1441 and the second shielding region 1442 have identical physical characteristics such as structure, shape, size, and doping.

[0128] Along the first direction, the first width Wa of the shielding area 144 (including the first shielding area 1441 and the second shielding area 1442) is defined as the maximum distance of the rectangle in the first direction; with the first shielding area 1441 as a reference, among the three adjacent shielding areas 144, the first interval width Wb is defined as the distance between the nearest side of the second shielding area 1442 on the left and the first shielding area 1441 in the first direction, and the third interval width We is defined as the distance between the nearest side of the second shielding area 1442 on the right and the first shielding area 1441 in the first direction.

[0129] In some embodiments, the ratio of the first width Wa to either the first spacing width Wb or the third spacing width We remains greater than or equal to 1 / 5 and less than or equal to 1. Alternatively, the ratio of the first width Wa to both the first spacing width Wb and the third spacing width We remains greater than or equal to 1 / 5 and less than or equal to 1. At this ratio, both the voltage withstand capability and reliability of the semiconductor device can be balanced, while minimizing the Rsp (on-resistance) of the semiconductor device.

[0130] Within a single unit region, along the direction perpendicular to the first direction, the second width Wc of the shielding region 144 is defined as the width of a rectangle in the direction perpendicular to the first direction, and the first spacing width Wd between two adjacent shielding regions 144 is defined as the distance between the nearest edges of two adjacent rectangles in the direction perpendicular to the first direction. At this point, the ratio of the second width Wc of the shielding region 144 to the second spacing width Wd between two adjacent shielding regions remains greater than or equal to 1 / 5 and less than or equal to 1. This ratio balances the voltage withstand capability and reliability of the semiconductor device while minimizing the Rsp (on-resistance) of the semiconductor device.

[0131] Since the V-groove 1302 does not extend continuously in the second direction, the second interval width Wd between two adjacent shielding areas 144 only represents the distance between two adjacent shielding areas 144 located at the bottom of the continuously extending V-groove 1302 in the vertical direction of the first direction.

[0132] In some embodiments, the first interval width Wb and the third interval width We may be different along the first direction.

[0133] In other embodiments, the first spacing width Wb and the third spacing width We can also be the same along the first direction. In this case, the first shielding area 1441 and the two second shielding areas 1442 on both sides are symmetrically arranged, thereby further optimizing the symmetry and uniformity of the electric field distribution, which helps to improve the breakdown voltage stability and reliability of the device, and also makes the layout design simpler and easier to implement, reducing the manufacturing difficulty while ensuring electrical performance.

[0134] In some embodiments, along the first direction, the first width Wa of the shielding region 144 can be configured to be greater than the width D2 of the V-direction trench gate 1302.

[0135] Among them, the second distance D3 is greater than the sum of the first interval width Wb and the third interval width We.

[0136] In some embodiments, the second interval width Wd can be configured to be less than or equal to the first interval width Wb.

[0137] In some embodiments, the second interval width Wd can be configured to be less than or equal to the third interval width We.

[0138] In some embodiments, along the direction perpendicular to the first direction, the second width Wc of the shielding area 144 is smaller than the width D1 of the U-direction trench gate 1301, but the shielding area 144 still shields the corner at the connection between the V-direction trench gate 1302 and the U-direction trench gate 1301.

[0139] In some embodiments, along a direction perpendicular to the first direction, the first distance D4 between two adjacent U-direction trench gates 1301 can be configured to be greater than the second spacing width Wd between two adjacent shielding areas 144 below the same V-direction trench gate 1302.

[0140] In some embodiments, along the direction perpendicular to the first direction, the first distance D4 between two adjacent U-direction trench gates 1301 can be configured to be less than the third distance D5 between two adjacent shielding areas 144 below different V-direction trench gates 1302.

[0141] With other structural dimensions being the same, in this embodiment, one sidewall of the U-direction trench gate 1301 between two adjacent V-direction trench gates 1302 is completely released, thereby further optimizing the compactness of the gate layout while ensuring uniform electric field distribution, and reducing the loss of channel width while ensuring enhanced reverse characteristics.

[0142] Figure 10 A top view of a semiconductor device according to a sixth embodiment of this application is shown.

[0143] In this embodiment, the various dimensions, distances, connections, and positional relationships are related to... Figure 7 The dimensions, distances, connections, and positional relationships are the same in the embodiments shown.

[0144] In this embodiment, the extension direction of the V-direction trench gate 1302 is perpendicular to the first direction, that is, the second direction is perpendicular to the first direction. Since the first direction is perpendicular to the second direction, the U-direction trench gate 1301 and the V-direction trench gate 1302 are perpendicular to each other.

[0145] In the second direction, two adjacent shielding areas 144 located at both ends of the same V-shaped trench grid 1302 are collinear in the second direction.

[0146] Among them, the shielding areas 144 located at both ends of the same V-direction trench grid 1302 are arranged in a straight line in the second direction. This layout not only increases the space of the trench area, but also helps to simplify the mask design and process alignment, reduce the complexity of the process, and improve manufacturing consistency and yield.

[0147] Furthermore, the method for manufacturing a semiconductor device includes the following steps.

[0148] Step S10: Form an epitaxial layer on the first surface of the substrate.

[0149] In this step, an epitaxial layer 120 is formed on the first surface of the substrate 110 via an epitaxial process, which can employ metal-organic chemical vapor deposition or molecular beam epitaxy to ensure that the epitaxial layer 120 has excellent crystal quality and uniform and controllable thickness. Subsequently, doping is controlled to precisely set the conductivity type and carrier concentration of the epitaxial layer 120, providing a suitable electrical basis for the subsequent construction of the trench gate structure.

[0150] Step S20: Form a shielding region in the epitaxial layer.

[0151] In this step, doping elements are introduced into the epitaxial layer 120 through ion implantation to form a shielding region 144 with a predetermined shape and concentration distribution. The shielding region 144, which is projected as a triangle, is precisely controlled by a photolithography mask to ensure that its sharp corners are aligned with the bottom corners of the trench gate sidewalls. Subsequently, high-temperature annealing is used to activate the impurities and improve electrical activity.

[0152] The injection dosage and energy are optimized according to the target withstand voltage and electric field modulation requirements to ensure shielding effect and process compatibility.

[0153] Step S30: Form trenches in the epitaxial layer.

[0154] In this step, a dry etching process is used to etch trenches in the epitaxial layer 120. By controlling the depth and sidewall morphology of the trenches, it is ensured that they extend to a predetermined depth in the epitaxial layer 120. At the same time, during the etching process, a mask is used to distribute the trenches along a preset path, forming a continuous zigzag pattern.

[0155] Step S40: Form a trench grid structure within the trench.

[0156] In this step, a deposition process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, is used to grow a gate dielectric layer 131 in the trench. After the gate dielectric layer 131 is uniformly covered along the sidewalls and bottom of the trench, gate material is filled in the groove formed by the gate dielectric layer 131 along the trench to form a gate conductor 132.

[0157] The gate dielectric layer 131 is made of silicon oxide, silicon nitride, or a high dielectric constant material to balance interface quality and insulation strength. The gate conductor 132 is made of polysilicon or metal. The gate dielectric layer 131 separates the gate conductor 132 from the epitaxial layer 120, effectively suppressing leakage current and improving the device's switching characteristics. Simultaneously, by adjusting the thickness and dielectric constant of the gate dielectric layer 131, the threshold voltage and gate control capability are further optimized, achieving low on-resistance and fast response while ensuring high reliability.

[0158] Step S50: Form a volume region, a source region, and a volume contact region in the epitaxial layer.

[0159] In this step, a body region 143, a source region 141, and a body contact region 142 are sequentially formed in the epitaxial layer 120 by an ion implantation process.

[0160] In other embodiments, steps S40 and S50 can also be interchanged, that is, the body region, the source region and the body contact region are formed first, and then the trench gate structure is formed.

[0161] After step S50, the process also includes forming an oxide layer 121, a source metal layer, and a drain metal layer 152.

[0162] The semiconductor device provided in this application features a trench gate structure that extends in a zigzag pattern. Specifically, a second trench gate, connected to a first trench gate, is alternately connected on the first and second sidewalls of the first trench gate, forming a continuous zigzag path. This structure optimizes the ratio of the width of the shielding region to the width between two adjacent shielding regions. This structure effectively disperses electric field concentration, further optimizing the electric field distribution on the device surface, thereby improving the breakdown voltage. Simultaneously, this structure increases the channel width per unit area, which helps reduce on-resistance. By precisely controlling the ratio of the shielding region width to the spacing between adjacent shielding regions, the shielding effect and carrier migration efficiency are optimally matched. While ensuring good electric field shielding performance, interference with the current path is reduced, significantly improving the device's conduction and reverse recovery characteristics.

[0163] In addition, the zigzag extended trench gate structure is compatible with the existing silicon carbide device manufacturing process in terms of process implementation, which can effectively reduce process complexity and manufacturing cost, and is conducive to large-scale industrial application.

[0164] As described above, these embodiments of the present application do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, comprising: Substrate; An epitaxial layer is located on the first surface of the substrate; A trench gate structure is located in the epitaxial layer and extends from the first surface of the epitaxial layer to the second surface. The trench gate structure includes a plurality of U-shaped trench gates extending along a first direction, and a plurality of V-shaped trench gates extending along a second direction intersecting the first direction. The plurality of U-shaped trench gates are arranged parallel to each other in a direction perpendicular to the first direction, and the plurality of V-shaped trench gates are arranged parallel to each other in a direction perpendicular to the second direction. The V-shaped trench gates connect two adjacent U-shaped trench gates. In this configuration, multiple V-shaped trench gates are alternately connected to the first and second sidewalls of the same U-shaped trench gate.

2. The semiconductor device according to claim 1, wherein, The plurality of V-shaped trench gates includes a plurality of first V-shaped trench gates and a plurality of second V-shaped trench gates. The first V-direction trench gate and the second V-direction trench gate, which are connected to the same U-direction trench gate, are respectively connected to the first sidewall and the second sidewall of the U-direction trench gate. Furthermore, the first V-direction trench gate and the second V-direction trench gate are not collinear along the second direction.

3. The semiconductor device according to claim 2, wherein, The semiconductor device further includes a shielding region located at the bottom of the node where the U-direction trench gate and the V-direction trench gate intersect.

4. The semiconductor device according to claim 3, wherein, Along the first direction, among the three adjacent shielding areas located below the same U-shaped trench grid, the first interval width between the middle shielding area and the first shielding area and the third interval width between the middle shielding area and the third shielding area are the same.

5. The semiconductor device according to claim 3, wherein, Along the first direction, the ratio of the first width of the shielding area to the first interval width and / or the third interval width between two adjacent shielding areas is greater than or equal to 1 / 5 and less than or equal to 1.

6. The semiconductor device according to claim 3, wherein, In the direction perpendicular to the first direction, the ratio of the second width of the shielding area to the second interval width between two adjacent shielding areas is greater than or equal to 1 / 5 and less than or equal to 1.

7. The semiconductor device according to claim 3, wherein, Along the direction perpendicular to the first direction, the interval between two adjacent shielding areas is the second interval width; Along the first direction, the distance between two adjacent shielding zones includes a first interval width and a third interval width; Wherein, the second interval width is less than or equal to the first interval width, or / and the second interval width is less than or equal to the third interval width.

8. The semiconductor device according to any one of claims 3 to 7, wherein, At the node where the U-direction trench gate and the V-direction trench gate intersect, The shielding area covers the first sidewall, the second sidewall, and the bottom of the U-shaped trench grid. Furthermore, the shielding area covers the first sidewall, the second sidewall, and the bottom of the V-shaped trench grid.

9. The semiconductor device according to any one of claims 3 to 7, wherein, At the node where the U-direction trench gate and the V-direction trench gate intersect, The shielding area covers the first or second sidewall of the U-shaped trench grid, and the bottom portion connected to the sidewall. Furthermore, the shielding area covers the first sidewall, the second sidewall, and the bottom of the V-shaped trench grid.

10. The semiconductor device according to any one of claims 3 to 7, wherein, The shielding area is triangular in shape.

11. The semiconductor device according to claim 10, wherein, The two vertices of the triangle are located at the two intersecting nodes of the U-direction trench gate and the V-direction trench gate, respectively, and the other vertex of the triangle is located on the opposite sidewall of the U-direction trench gate, which is opposite to the sidewall where the intersecting node is located.

12. The semiconductor device according to any one of claims 1 to 7, wherein, The first direction is perpendicular to the second direction.

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