Packaging structure and packaging method of bidirectional blocking semiconductor device

Abstract

The invention provides a packaging structure and a packaging method of a bidirectional blocking semiconductor device, and the packaging structure comprises a first MOS tube chip and a second MOS tube chip, the back surface of the first MOS tube chip and the back surface of the second MOS tube chip are respectively provided with a first drain region and a second drain region, and the first drain region and the second drain region are directly bonded in a face-to-face manner to form a conductive bonding interface; the first MOS tube chip and the second MOS tube chip are stacked in the vertical direction, and the main current path of the semiconductor device in the conducting state is perpendicular to the conductive bonding interface; the front surface of the first MOS tube chip is bonded to the packaging substrate, and the first grid electrode and the first source electrode of the first MOS tube chip are electrically connected to the packaging substrate; and the connecting line is used for electrically connecting the second grid electrode and the second source electrode of the second MOS tube chip to the packaging substrate. A transverse current path is completely eliminated, the current path is only in the vertical direction, the contact resistivity of a bonding interface is greatly reduced, the on resistance of a device can be remarkably reduced, and the conduction loss of the packaging structure is greatly reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a packaging structure and packaging method for a bidirectional blocking semiconductor device. Background Technology

[0002] In power electronic devices, such as motor drives, photovoltaic inverters, energy storage converters, and on-board chargers, power semiconductor devices typically need to have bidirectional blocking and bidirectional conduction capabilities to achieve bidirectional current flow control and reliable shutdown under fault conditions.

[0003] In existing technologies, the mainstream approach to achieving bidirectional blocking functionality is to connect two MOSFETs back-to-back in series, meaning the drains of the two devices are connected together, and the two sources serve as switching ports. The circuit principle is as follows: Figure 1 As shown in the figure, the drains of the two MOSFETs are connected together. By controlling the two gates simultaneously, complete turn-off and turn-on in both directions can be achieved. Figure 2 This is the corresponding traditional chip layout diagram, where two chips (MOS1 and MOS2) are placed side by side in the same package, and the drains are electrically connected through the metal layer or lead frame on the back. Figure 3 It is along Figure 2 The cross-sectional view of section A and the current flow path are shown. The black arrows indicate the current flow in the conducting state.

[0004] However, the above-mentioned traditional packaging structure has the following technical drawbacks:

[0005] First, insufficient mechanical strength. To reduce the vertical on-resistance, the thickness of a single chip needs to be reduced to 20-50 micrometers. Ultra-thin chips are extremely prone to warping, cracking, or even shattering during packaging, transportation, and operation, severely affecting the reliability of the device.

[0006] Second, the packaging area utilization is low. The side-by-side layout results in a larger horizontal dimension for the devices, which is detrimental to the miniaturization of power modules and the integration of high power density, such as... Figure 2 As shown.

[0007] Third, the on-resistance is too high. Because the two chips are placed side-by-side, the current needs to flow vertically downwards from the source of one chip to its drain, then horizontally across a distance of several millimeters (typically 1-6 millimeters) via the back metal wiring, and then vertically upwards into the drain of the other chip. Figure 3 As shown, the additional resistance introduced by this horizontal current path accounts for 20% to 30% of the total on-resistance, significantly increasing the device's conduction losses.

[0008] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a packaging structure and packaging method for a bidirectional blocking semiconductor device, which solves the problems of low mechanical strength and integration and high on-resistance of the packaging structure of bidirectional blocking semiconductor devices in the prior art.

[0010] To achieve the above and other related objectives, the present invention provides a packaging structure for a bidirectional blocking semiconductor device. The packaging structure includes: a first MOS transistor chip and a second MOS transistor chip, wherein the back side of the first MOS transistor chip has a first drain region, and the back side of the second MOS transistor chip has a second drain region. The first drain region and the second drain region are directly bonded face-to-face to form a conductive bonding interface, so that the first MOS transistor chip and the second MOS transistor chip are stacked in a vertical direction, and the main current path of the semiconductor device in the on state is perpendicular to the conductive bonding interface; a packaging substrate, wherein the front side of the first MOS transistor chip is bonded to the packaging substrate, and the first gate and the first source of the first MOS transistor chip are electrically connected to the packaging substrate; and a connecting line for electrically connecting the second gate and the second source of the second MOS transistor chip to the packaging substrate.

[0011] Optionally, both the first MOSFET chip and the second MOSFET chip are vertically conductive field-effect transistors, and the first MOSFET chip and the second MOSFET chip have the same channel conductivity type.

[0012] Optionally, the conductive bonding interface is an atomic-level surface-activated bonding interface, where the semiconductor materials of the first drain region and the second drain region are directly bonded at the conductive bonding interface to form an ohmic contact, and the contact resistivity of the conductive bonding interface is less than 1×10⁻⁶. -6 Ω·cm 2 .

[0013] Optionally, the conductive bonding interface is a metal bonding interface formed by hot pressing or eutectic reaction. The metal bonding interface forms ohmic contacts with both the first and second drain regions, and the contact resistivity of the conductive bonding interface is less than 5 × 10⁻⁶. -6 Ω·cm 2 .

[0014] Optionally, the metal bonding interface includes an alloy or stack formed from one or more of copper, gold, tin, silver, nickel, titanium, and aluminum, and the thickness of the metal bonding interface is 10 nanometers to 2 micrometers.

[0015] Optionally, the thickness of the first MOSFET chip is 20 micrometers to 50 micrometers, and the thickness of the second MOSFET chip is 20 micrometers to 50 micrometers.

[0016] Optionally, the current path length of the package structure of the bidirectional blocking semiconductor device is less than 100 micrometers.

[0017] Optionally, the first gate and the second gate include either a trench gate structure or a trench shielded gate structure.

[0018] The present invention also provides a packaging method for a bidirectional blocking semiconductor device, comprising the steps of: providing a first MOS transistor chip having a first drain region on its back side and a first gate and a first source on its front side; providing a second MOS transistor chip having a second drain region on its back side and a second gate and a second source on its front side; vertically stacking the first MOS transistor chip and the second MOS transistor chip, and forming a conductive bonding interface between the first drain region and the second drain region by a surface activation bonding process or a metal bonding process; bonding the front side of the first MOS transistor chip to a packaging substrate to electrically connect the first gate and the first source of the first MOS transistor chip to the packaging substrate; and electrically connecting the second gate and the second source of the second MOS transistor chip to the packaging substrate by means of a connecting wire.

[0019] Optionally, the first drain region is bonded to the second drain region first, and then the front side of the first MOS transistor chip is bonded to the packaging substrate; or, the front side of the first MOS transistor chip is bonded to the packaging substrate first, and then the first drain region is bonded to the second drain region.

[0020] Optionally, the surface activation bonding process includes: activating the surfaces of the first drain region and the second drain region using plasma; stacking and contacting the surfaces of the first drain region and the second drain region; and annealing at a temperature of 20°C to 400°C to bond the surfaces of the first drain region and the second drain region.

[0021] Optionally, before vertically stacking the first MOS transistor chip and the second MOS transistor chip, the method further includes the step of performing chemical mechanical polishing on the surfaces of the first drain region and the second drain region to make the roughness of the surfaces of the first drain region and the second drain region less than 0.3 nanometers.

[0022] Optionally, the metal bonding process includes: depositing a metal layer on the surface of the first drain region and / or the surface of the second drain region; making the surfaces of the first drain region and / or the second drain region contact each other through the stacked metal layers; and performing hot-press bonding at a temperature of 200°C to 450°C.

[0023] As described above, the packaging structure and packaging method of the bidirectional blocking semiconductor device of the present invention have the following beneficial effects:

[0024] This invention directly bonds the drains of two transistor chips face-to-face, transforming the main current path from a mixed lateral and vertical path in traditional structures into a purely vertical path. This invention completely eliminates the lateral current path, leaving only a vertical current path. Simultaneously, the contact resistivity of the conductive bonding interface is significantly reduced. This structure can reduce the on-resistance of the device by 20% to 40%, substantially reducing the conduction loss of the packaging structure.

[0025] This invention vertically stacks two chips, increasing the overall thickness to 80-100 micrometers, which significantly increases the structural thickness of the device and thus effectively improves its mechanical strength.

[0026] This invention vertically stacks two chips, and the packaged horizontal projected area is only equivalent to the area of ​​a single chip, thereby significantly improving the power density of the device. Attached Figure Description

[0027] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0028] Figure 1 The diagram shows a circuit schematic of the package structure of a semiconductor device with bidirectional blocking function according to an embodiment of the present invention.

[0029] Figures 2-3 The diagram shows a package structure of a semiconductor device with bidirectional blocking function in the prior art. Figure 3 Displayed as Figure 2 A schematic diagram of the cross-sectional structure at mid-section A. Figure 3 The black arrow in the middle represents the path of the current.

[0030] Figures 4-6 The diagram shows the structural schematic of each step in a sealing method for a bidirectional blocking semiconductor device according to an embodiment of the present invention. Figure 6 The diagram shown is a schematic representation of the packaging structure of a bidirectional blocking semiconductor device according to an embodiment of the present invention.

[0031] Figures 7-9 The diagram shows the structural schematic of each step in another bidirectional blocking semiconductor device packaging method according to an embodiment of the present invention.

[0032] Figure 10 The diagram shows a schematic of the packaging structure of a bidirectional blocking semiconductor device bonded by a metal bonding process according to an embodiment of the present invention.

[0033] Figure 11The diagram shows a current path of the package structure of a bidirectional blocking semiconductor device according to an embodiment of the present invention.

[0034] Component designation explanation

[0035] 101 First MOSFET chip 102 Second MOSFET chip 103 Packaging substrate 104 Metal bonding interface 105 Gate interconnect 106 Source Connection Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0038] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0039] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0040] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0041] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] like Figure 9 and Figure 10 As shown in the figure, this embodiment provides a packaging structure for a bidirectional blocking semiconductor device. The packaging structure includes: a first MOS transistor chip 101 and a second MOS transistor chip 102. The back side of the first MOS transistor chip 101 has a first drain region, and the back side of the second MOS transistor chip 102 has a second drain region. The first drain region and the second drain region are directly bonded face to face to form a conductive bonding interface, so that the first MOS transistor chip 101 and the second MOS transistor chip 102 are stacked in a vertical direction, and the main current path of the semiconductor device in the on state is perpendicular to the conductive bonding interface; a packaging substrate 103, the front side of the first MOS transistor chip 101 is bonded to the packaging substrate 103, and the first gate and the first source of the first MOS transistor chip 102 are electrically connected to the packaging substrate 103; and connecting lines, which are used to electrically connect the second gate and the second source of the second MOS transistor chip 102 to the packaging substrate 103. The connecting lines may include a gate connection line 105 and a source connection line 106 that electrically connect the second gate and the second source of the second MOS transistor chip 102 to the packaging substrate 103.

[0044] In some embodiments, the packaging substrate 103 can be a PCB substrate, which has wiring structures and corresponding pads. The pads may include, for example, gate pads and source pads. The gate interconnect 105 connects the second gate of the second MOSFET chip 102 to the gate pad on the PCB substrate, and the source interconnect 106 connects the second source of the second MOSFET chip 102 to the source pad on the PCB substrate. The gate interconnect 105 and the source interconnect 106 may be made of, for example, gold, copper, aluminum, copper-aluminum alloy, etc., and are not limited to the examples listed herein. A molding layer may also be formed on the packaging substrate 103 to protect the first MOSFET chip 101 and the second MOSFET chip 102.

[0045] In some embodiments, the first MOS transistor chip 101 includes a first substrate. The front side of the first substrate has a first drift region, a first body region, a first source region, a first gate, and a first source, and the back side of the first substrate has a first drain region. The second MOS transistor chip 102 has a layer structure similar to that of the first MOS transistor chip 101. The second MOS transistor chip 102 includes a second substrate. The front side of the second substrate has a second drift region, a second body region, a second source region, a second gate, and a second source, and the back side of the second substrate has a second drain region.

[0046] In some embodiments, the first gate and the second gate can also be electrically connected to the same gate pad to achieve synchronous switching control of the first MOSFET chip 101 and the second MOSFET chip 102. With this configuration, the external controller only needs to provide one gate drive signal to synchronously control the switching state of the two transistors, which can effectively simplify system design and reduce drive power consumption and cost.

[0047] In some embodiments, the first gate and the second gate comprise either a trench gate structure or a trench-shielded gate structure. In this embodiment, the first MOS transistor chip 101 and the second MOS transistor chip 102 employ a trench-shielded gate structure. The trench extends downward from the source region surface, through the body region, and into the drift region. The lower part of the trench contains a shielding electrode, and the upper part contains a gate electrode. The shielding electrode and the gate electrode are isolated by an interlayer dielectric. The shielding electrode can be electrically connected to the source metal layer or the gate through a contact hole.

[0048] In some embodiments, the thickness of the first MOSFET chip 101 is 20 micrometers to 50 micrometers, and the thickness of the second MOSFET chip 102 is 20 micrometers to 50 micrometers. In a specific example, the thickness of both the first MOSFET chip 101 and the second MOSFET chip 102 is 40 micrometers, and the total thickness is 80 micrometers.

[0049] like Figure 9 As shown, in some embodiments, the conductive bonding interface is an atomic-level surface-activated bonding interface. The semiconductor materials of the first drain region and the second drain region are directly bonded at the conductive bonding interface to form an ohmic contact, and the contact resistivity of the conductive bonding interface is less than 1×10⁻⁶. -6 Ω·cm 2 In a specific example, the first drain region and the second drain region are directly bonded face-to-face, forming an atomic-level bonding interface. At this bonding interface, the semiconductor material of the first drain region (N-type silicon in this embodiment) is directly bonded to the semiconductor material of the second drain region (also N-type silicon), without any intermediary layer at the interface.

[0050] In some embodiments, both the first MOSFET chip 101 and the second MOSFET chip 102 are vertically conductive field-effect transistors, and both have the same channel conductivity type. In this embodiment, both the first MOSFET chip 101 and the second MOSFET chip 102 are N-type conductivity types.

[0051] In some embodiments, the current path of the semiconductor device in this embodiment is as follows: Figure 11As indicated by the black arrow: When both MOSFET chips are turned on, current flows vertically downwards from the second source through the second channel and the second drain region, across the conductive bonding interface, then into the first drain region and the first channel, finally reaching the first source and the package substrate. The entire path is vertical, resulting in a very short current path. In some embodiments, the current path length of the package structure of the bidirectional blocking semiconductor device is less than 100 micrometers.

[0052] like Figure 10 As shown, in some embodiments, the conductive bonding interface is a metal bonding interface 104 formed by hot pressing or eutectic reaction. The metal bonding interface 104 forms ohmic contacts with both the first drain region and the second drain region, and the contact resistivity of the conductive bonding interface 104 is less than 5 × 10⁻⁶. -6 Ω·cm 2 .

[0053] In some embodiments, the metal bonding interface comprises an alloy or stack formed of one or more of copper, gold, tin, silver, nickel, titanium, and aluminum, and the thickness of the metal bonding interface 104 is 10 nanometers to 2 micrometers. Specifically, a titanium-nickel-silver metal stack is prepared on the surface of the first drain region, with thicknesses of 50 nanometers, 100 nanometers, and 300 nanometers, respectively; a titanium-nickel-silver metal stack is prepared on the surface of the second drain region, with thicknesses of 50 nanometers, 100 nanometers, and 300 nanometers, respectively. The two metal stacks are hot-pressed and bonded at a certain temperature (e.g., 300°C to 500°C) and a certain pressure (e.g., 10 MPa to 30 MPa) for 10 to 30 minutes to form a homogeneous metal bonding layer, and the metal bonding layer forms ohmic contacts with both the first and second drain regions, with a total thickness of approximately 800 to 1000 nanometers.

[0054] like Figures 4-6 As shown, this embodiment also provides a packaging method for a bidirectional blocking semiconductor device, the packaging method including the following steps:

[0055] like Figure 4 As shown, step 1) is performed first, providing a first MOS transistor chip 101, which has a first drain region on the back and a first gate and a first source on the front.

[0056] like Figure 4 As shown, then step 2) is performed to bond the front side of the first MOS transistor chip 101 to the packaging substrate 103 so as to electrically connect the first gate and the first source of the first MOS transistor chip 101 to the packaging substrate 103.

[0057] like Figure 5As shown, then step 3) is performed, providing a second MOS transistor chip 102, which has a second drain region on the back and a second gate and a second source on the front. The first MOS transistor chip 101 and the second MOS transistor chip 102 are stacked vertically, and a conductive bonding interface is formed between the first drain region and the second drain region through a surface activation bonding process.

[0058] like Figure 6 As shown, then proceed to step 4), and electrically connect the second gate and the second source of the second MOS transistor chip to the packaging substrate via connecting lines.

[0059] In some embodiments, before vertically stacking the first MOS transistor chip 101 and the second MOS transistor chip 102, the method further includes: performing chemical mechanical polishing on the surface of the first drain region and the surface of the second drain region to make the roughness of the surface of the first drain region and the surface of the second drain region less than 0.3 nanometers.

[0060] In some embodiments, the surface activation bonding process includes:

[0061] The surfaces of the first and second drain regions were activated using plasma.

[0062] The surfaces of the first and second drain areas are stacked and in contact.

[0063] Annealing is performed at a temperature of 20℃ to 400℃ to bond the surfaces of the first and second drain regions.

[0064] Surface activation bonding processes include: in vacuum conditions below 1×10⁻⁶ -4 In the chamber of Pa, nitrogen or argon plasma is used to activate the surfaces of the first and second leak regions. The plasma power can be 50 W to 500 W and the treatment time can be 10 s to 300 s. Then, the surfaces of the first and second leak regions are brought into contact at a temperature of room temperature to 200 °C or without pressure. The pressure can be 1 MPa to 20 MPa to bond the surfaces of the first and second leak regions.

[0065] In some embodiments, such as Figure 10 As shown, a conductive bonding interface can also be formed between the first drain region and the second drain region through a metal bonding process. The metal bonding process includes:

[0066] A first bonding metal layer and / or a second bonding metal layer are deposited on the surface of the first drain region and / or the surface of the second drain region;

[0067] The surfaces of the first drain area and / or the second drain area are made in contact through a metal layer stack;

[0068] Hot pressing bonding is performed at a temperature of 200℃~450℃ to form a metal bonding interface 104.

[0069] In a specific example, the metal bonding process includes: depositing a first bonding metal layer and a second bonding metal layer on the first bonding surface and / or the second bonding surface, wherein the thickness of the bonding metal layer can be 20 nanometers to 1 micrometer; and then performing hot pressing bonding at a temperature of 200°C to 450°C, wherein the pressure can be 5 MPa to 50 MPa, and the bonding time can be 1 min to 60 min.

[0070] In this embodiment, the first MOS transistor chip 101 is first bonded to the packaging substrate, and then the first MOS transistor chip 101 and the second MOS transistor chip 102 are bonded together. The mechanical strength of the first MOS transistor chip 101 can be greatly increased by utilizing the packaging substrate.

[0071] like Figures 7-9 As shown, this embodiment also provides a packaging method for a bidirectional blocking semiconductor device, the packaging method including the following steps:

[0072] like Figure 7 As shown, step 1) is performed first, providing a first MOS transistor chip 101, which has a first drain region on the back and a first gate and a first source on the front.

[0073] like Figure 7 As shown, then proceed to step 2), providing a second MOS transistor chip 102, which has a second drain region on the back side and a second gate and a second source on the front side.

[0074] like Figure 7 As shown, then step 3) is performed, where the first MOS transistor chip 101 and the second MOS transistor chip 102 are stacked vertically, and a conductive bonding interface is formed between the first drain region and the second drain region by surface activation bonding process or metal bonding process.

[0075] like Figure 8 As shown, then step 4) is performed to bond the front side of the first MOS transistor chip 101 to the packaging substrate 103 so as to electrically connect the first gate and the first source of the first MOS transistor chip 101 to the packaging substrate 103.

[0076] like Figure 9 As shown, then step 5) is performed, and the second gate and the second source of the second MOS transistor chip 102 are electrically connected to the packaging substrate 103 via connecting lines.

[0077] In this embodiment, the first MOS transistor chip 101 and the second MOS transistor chip 102 are bonded together first, and then the front side of the first MOS transistor chip 101 is bonded to the packaging substrate. This can avoid the influence of the bonding process (such as temperature, pressure, etc.) between the first MOS transistor chip 101 and the second MOS transistor chip 102 on the packaging substrate.

[0078] As described above, the packaging structure and packaging method of the bidirectional blocking semiconductor device of the present invention have the following beneficial effects:

[0079] This invention directly bonds the drains of two transistor chips face-to-face, transforming the main current path from a mixed lateral and vertical path in traditional structures to a purely vertical path. In traditional structures, current must flow laterally for 1-6 mm across a metal layer on the back side, and the on-resistance of this lateral metal can account for 20%-30% of the total resistance. This invention completely eliminates the lateral current path, with the current path being solely vertical. Simultaneously, the contact resistivity of the bonding interface is significantly reduced. This structure can reduce the on-resistance of the device by 20%-40%, substantially reducing the conduction losses of the package structure.

[0080] In traditional bidirectional blocking structures, to reduce the on-resistance of the chip, the thickness of a single chip needs to be reduced to 20-50 micrometers, resulting in low mechanical strength. This invention vertically stacks two chips, increasing the overall thickness to 80-100 micrometers, significantly increasing the structural thickness of the device and thus effectively improving its mechanical strength.

[0081] In traditional side-by-side structures, two chips are arranged horizontally, occupying at least twice the area of ​​a single chip on the packaging substrate. This invention stacks two chips vertically, reducing the horizontal projected area of ​​the package to the equivalent of a single chip area, thereby significantly improving the device's power density.

[0082] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A packaging structure for a bidirectional blocking semiconductor device, characterized in that, The packaging structure includes: A first MOS transistor chip and a second MOS transistor chip, wherein the back side of the first MOS transistor chip has a first drain region and the back side of the second MOS transistor chip has a second drain region, and the first drain region and the second drain region are directly bonded face to face to form a conductive bonding interface, so that the first MOS transistor chip and the second MOS transistor chip are stacked in a vertical direction, and the main current path of the semiconductor device in the on state is perpendicular to the conductive bonding interface. The packaging substrate has the front side of the first MOS transistor chip bonded to the packaging substrate, and the first gate and the first source of the first MOS transistor chip are electrically connected to the packaging substrate. A connecting line is used to electrically connect the second gate and the second source of the second MOS transistor chip to the packaging substrate.

2. The packaging structure of the bidirectional blocking semiconductor device according to claim 1, characterized in that: Both the first MOS transistor chip and the second MOS transistor chip are vertically conductive field-effect transistors, and both have the same channel conductivity type.

3. The packaging structure of the bidirectional blocking semiconductor device according to claim 1, characterized in that: The conductive bonding interface is an atomic-level surface-activated bonding interface. The semiconductor materials of the first drain region and the second drain region are directly bonded at the conductive bonding interface to form an ohmic contact, and the contact resistivity of the conductive bonding interface is less than 1×10⁻⁶. -6 Ω·cm 2 .

4. The packaging structure of the bidirectional blocking semiconductor device according to claim 1, characterized in that: The conductive bonding interface is a metal bonding interface formed by hot pressing or eutectic reaction. The metal bonding interface forms ohmic contacts with both the first drain region and the second drain region, and the contact resistivity of the conductive bonding interface is less than 5 × 10⁻⁶. -6 Ω·cm 2 .

5. The packaging structure of the bidirectional blocking semiconductor device according to claim 1, characterized in that: The metal bonding interface comprises an alloy or stack formed from one or more of copper, gold, tin, silver, nickel, titanium, and aluminum, and the thickness of the metal bonding interface is 10 nanometers to 2 micrometers.

6. The packaging structure of the bidirectional blocking semiconductor device according to claim 1, characterized in that: The thickness of the first MOS transistor chip is 20 micrometers to 50 micrometers, and the thickness of the second MOS transistor chip is 20 micrometers to 50 micrometers.

7. The packaging structure of the bidirectional blocking semiconductor device according to claim 1, characterized in that: The current path length of the package structure of the bidirectional blocking semiconductor device is less than 100 micrometers.

8. The packaging structure of the bidirectional blocking semiconductor device according to claim 1, characterized in that: The first gate and the second gate include either a trench gate structure or a trench shielded gate structure.

9. A packaging method for a bidirectional blocking semiconductor device, characterized in that, Including the following steps: A first MOS transistor chip is provided, having a first drain region on the back side and a first gate and a first source on the front side; A second MOS transistor chip is provided, which has a second drain region on the back side and a second gate and a second source on the front side; The first MOS transistor chip and the second MOS transistor chip are stacked vertically, and a conductive bonding interface is formed between the first drain region and the second drain region by surface activation bonding process or metal bonding process. The front side of the first MOS transistor chip is bonded to the packaging substrate to electrically connect the first gate and the first source of the first MOS transistor chip to the packaging substrate. The second gate and second source of the second MOS transistor chip are electrically connected to the packaging substrate via connecting lines.

10. The packaging method for a bidirectional blocking semiconductor device according to claim 9, characterized in that: First, the first drain region is bonded to the second drain region, and then the front side of the first MOS transistor chip is bonded to the packaging substrate; or, the front side of the first MOS transistor chip is bonded to the packaging substrate first, and then the first drain region is bonded to the second drain region.

11. The packaging method for a bidirectional blocking semiconductor device according to claim 9, characterized in that: The surface activation bonding process includes: The surfaces of the first and second drain regions are activated using plasma. The surfaces of the first and second drain areas are stacked and in contact. Annealing is performed at a temperature of 20℃ to 400℃ to bond the surfaces of the first and second drain regions.

12. The packaging method for a bidirectional blocking semiconductor device according to claim 11, characterized in that: Before vertically stacking the first MOS transistor chip and the second MOS transistor chip, the method further includes the step of performing chemical mechanical polishing on the surfaces of the first drain region and the second drain region to make the roughness of the surfaces of the first drain region and the second drain region less than 0.3 nanometers.

13. The packaging method for a bidirectional blocking semiconductor device according to claim 9, characterized in that: The metal bonding process includes: Deposit a metal layer on the surface of the first drain region and / or the surface of the second drain region; The surfaces of the first drain area and / or the second drain area are made to contact each other through the stacked metal layers; Hot pressing bonding is performed at temperatures ranging from 200℃ to 450℃.

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