Semiconductor device and preparation method thereof
By setting a second part of the isolation dielectric layer that is higher than the top surface of the substrate in the isolation trench, the short circuit and over-etching problems during gate material removal are solved, and the stability and performance protection of semiconductor devices are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2026-01-26
- Publication Date
- 2026-04-21
AI Technical Summary
In the fabrication of semiconductor devices, especially in the fabrication of high dielectric constant metal gates, the top surface of the trench isolation structure is flush with the substrate surface. This makes it easy for the gate material to be over-etched and damaged during removal, resulting in film damage or residue, which affects device performance and may even lead to short circuits.
The second part of the isolation dielectric layer in the isolation trench is higher than the top surface of the substrate. After the gate material layer is formed, when the first and second gate structures are formed by etching, the higher position of the second part is used to contact the etching gas early to remove the gate material connection between the PMOS region and the NMOS region.
This avoids short circuits in the device, protects its performance, and prevents the impact of over-etching on performance, thus ensuring the stability and reliability of the device.
Smart Images
Figure CN121908627A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] In semiconductor device fabrication, especially in the fabrication of high-kJ metal gates (HKMGs), the top surface of the trench isolation structure and the surface of the substrate are generally flush. During the fabrication of the metal gate, gate material is deposited on the substrate, covering the PMOS region, NMOS region, and the surface of the trench isolation structure between the two regions; that is, the gate material extends from the PMOS region to the NMOS region. Then, an etching process removes the gate material on the trench isolation structure to form metal gates on the PMOS and NMOS regions respectively. However, when removing the gate material from the trench isolation structure, complete removal generally requires over-etching, which may damage the underlying film layer and affect device performance. Alternatively, insufficient etching time may leave gate material residue, causing short circuits and similarly affecting device performance. Summary of the Invention
[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method, so as to avoid short circuits affecting the device's performance.
[0004] To achieve the above objectives, the present invention provides a semiconductor device comprising:
[0005] The substrate includes a PMOS region, an NMOS region, and an isolation trench located between the PMOS region and the NMOS region;
[0006] The isolation dielectric layer includes:
[0007] The first part is located within the isolation trench and covers the sidewalls and bottom of the isolation trench;
[0008] The second part is located on the first part and in direct contact with the first part, and the second part is higher than the top surface of the substrate;
[0009] A germanium-silicon layer is located on the PMOS region;
[0010] A first gate structure is located on the germanium-silicon layer;
[0011] The second gate structure is located on the NMOS region.
[0012] Optionally, the top surface of the germanium-silicon layer is lower than the top surface of the substrate.
[0013] Optionally, the germanium-silicon layer and the gate oxide layer in the first gate structure are embedded in the substrate.
[0014] Optionally, the bottom surface of the germanium-silicon layer is in direct contact with the top surface of the substrate.
[0015] Optionally, the isolation medium layer further includes a third portion, which fills the isolation trench and is in direct contact with the second portion.
[0016] The present invention also provides a semiconductor device, comprising:
[0017] The substrate includes a PMOS region, an NMOS region, and an isolation trench located between the PMOS region and the NMOS region;
[0018] The isolation medium layer is located within the isolation trench;
[0019] A germanium-silicon layer is located on the PMOS region;
[0020] A first gate structure is located on the germanium-silicon layer;
[0021] The second gate structure is located on the NMOS region;
[0022] Wherein, the first gate structure and / or the second gate structure directly contact one end of the isolation dielectric layer, and the other end of the isolation dielectric layer is higher than the top surface of the substrate.
[0023] Optionally, the germanium-silicon layer and the gate oxide layer in the first gate structure are embedded in the substrate.
[0024] Optionally, the bottom surface of the germanium-silicon layer is in direct contact with the top surface of the substrate.
[0025] Optionally, the germanium-silicon layer and the first gate structure cover one end of the isolation dielectric layer, and the other end of the isolation dielectric layer is higher than the top surface of the substrate.
[0026] Optionally, the isolation medium layer includes a first part, a second part, and a third part. The first part is located within the isolation trench and covers the sidewalls and bottom of the isolation trench. The second part is located on the first part and is in direct contact with the first part. The third part fills the isolation trench and is in direct contact with the second part.
[0027] Optionally, the end of the isolation dielectric layer above the top surface of the substrate is one end of the second portion.
[0028] Optionally, the first gate structure or the second gate structure at least covers a portion of the second part at one end of the isolation dielectric layer.
[0029] This invention also provides a method for fabricating a semiconductor device, comprising:
[0030] A substrate is provided, the substrate including a PMOS region, an NMOS region, and an isolation trench located between the PMOS region and the NMOS region;
[0031] Forming an isolation medium layer, including:
[0032] The first part is located within the isolation trench and covers the sidewalls and bottom of the isolation trench;
[0033] The second part is located on the first part and is in direct contact with the first part;
[0034] The first portion and the substrate are etched so that the second portion is higher than the top surface of the substrate;
[0035] A germanium-silicon layer is formed on the PMOS region;
[0036] A gate material layer is formed to cover the PMOS region, the NMOS region, and the isolation dielectric layer, wherein the gate material layer at the top of the second portion is higher than the gate material layer at the top of the substrate;
[0037] The gate material layer is etched to form a first gate structure and a second gate structure, wherein the first gate structure is located on the germanium-silicon layer and the second gate structure is located on the NMOS region.
[0038] In the semiconductor device and its fabrication method provided by this invention, the substrate includes a PMOS region, an NMOS region, and an isolation trench located between the PMOS region and the NMOS region; the isolation dielectric layer includes: a first portion located within the isolation trench, covering the sidewalls and bottom of the isolation trench; a second portion located on the first portion and in direct contact with the first portion, the second portion being higher than the top surface of the substrate; a germanium-silicon layer located on the PMOS region, a first gate structure located on the germanium-silicon layer, and a second gate structure located on the NMOS region. By setting the second portion of the isolation dielectric layer higher than the top surface of the substrate, after the gate material layer is formed, during the etching process to form the first and second gate structures, the higher position of the second portion allows it to come into contact with the etching gas earlier and be etched away more quickly, blocking the connection between the gate materials of the PMOS region and the NMOS region, thereby preventing short circuits that could affect the device's performance. Furthermore, because the second portion is higher, etching on the second portion will not affect the device's performance. Attached Figure Description
[0039] Figures 1-6 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present invention.
[0040] Figures 7-10 This is a cross-sectional schematic diagram of a corresponding step in a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0041] The attached figures are labeled as follows:
[0042] 100 - Substrate; 110 - PMOS region; 120 - NMOS region; 200a - Isolation trench; 220 - Isolation dielectric layer; 210 - First section; 220 - Second section; 230 - Third section; 240 - Doped region; 300 - Germanium-silicon layer; 400a - First gate structure; 400b - Second gate structure; 410 - Gate oxide layer; 421 - First high dielectric constant dielectric layer; 422 - Second high dielectric constant dielectric layer; 430 - First metal layer; 440 - Conductive layer; 450 - Second metal layer; 460 - Third metal layer; 470 - Silicon nitride layer; 400 - Gate material layer; 500 - Sidewall; 600 - Mask layer. Detailed Implementation
[0043] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0044] Please refer to Figure 1 and Figure 2This embodiment provides a semiconductor device, including a substrate 100, an isolation dielectric layer 200, a germanium-silicon layer 300, a first gate structure 400a, and a second gate structure 400b. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto. The substrate 100 includes a PMOS region 110, an NMOS region 120, and an isolation trench 200a located in the PMOS region 110 and the NMOS region 120. The isolation dielectric layer 200 includes a first portion 210, a second portion 220, and a third portion 230. The first portion 210 is located within the isolation trench 200a and covers the sidewalls and bottom of the isolation trench 200a. The material of the first portion 210 may be silicon oxide. The second portion 220 is located on and in direct contact with the first portion 210. The second portion 220 is higher than the top surface of the substrate 100 (as shown in the dashed box, exhibiting a convex shape). This can be achieved by the second portion 220 on one sidewall of the isolation trench 200a being higher than the top surface of the substrate 100 (as shown in the dashed box, exhibiting a convex shape). (As shown in the figure), the second portion 220 of the two sidewalls of the isolation trench 200a can be higher than the top surface of the substrate 100, and the material of the second portion 220 can be silicon nitride; the third portion 230 fills the isolation trench 200a and is in direct contact with the second portion 220, and the top surface of the third portion 230 is approximately flush with the top surface of the substrate, and the material of the third portion 230 can be silicon oxide. The first portion 210 and the third portion 230 can be formed using different processes, for example, the first portion 210 can be formed using a thermal oxidation process, and the third portion 230 can be formed using a deposition process. In this embodiment, a doped region 240 can also be formed in the substrate 100, and the doped region can serve as the source region and the drain region, which are located in the substrate 100 on both sides of the gate structure.
[0045] Please continue to refer to this. Figure 1 The germanium-silicon layer 300 is located on the PMOS region 110. The top surface of the germanium-silicon layer 300 is lower than the top surface of the substrate 100. Specifically, the germanium-silicon layer 300 is embedded in the substrate 100, and the top surface of the germanium-silicon layer 300 is lower than the top surface of the substrate 100. Please refer to [reference needed]. Figure 2 The germanium-silicon layer 300 is located on the PMOS region 110, and the bottom surface of the germanium-silicon layer 300 is in direct contact with the top surface of the substrate 100.
[0046] The first gate structure 400a is located on the germanium-silicon layer 300, and the second gate structure 400b is located on the NMOS region 120. The first gate structure 400a includes a gate oxide layer 410, a first high dielectric constant dielectric layer 421, a first metal layer 430, a conductive layer 440, a second metal layer 450, a third metal layer 460, and a silicon nitride layer 470 (all of which are gate material layers) stacked from bottom to top. The second gate structure 400b includes a gate oxide layer 410, a second high dielectric constant dielectric layer 422, a first metal layer 430, a conductive layer 440, a second metal layer 450, a third metal layer 460, and a silicon nitride layer 470 (all of which are gate material layers) stacked from bottom to top. When the top surface of the germanium-silicon layer 300 is lower than the top surface of the substrate 100, the gate oxide layer 410 in the first gate structure 400a is located on and in direct contact with the germanium-silicon layer 300, and is embedded in the substrate 100. The width of the gate oxide layer 410 in the first gate structure 400a is greater than the width of other films in the first gate structure 400a. When the bottom surface of the germanium-silicon layer 300 is in direct contact with the top surface of the substrate 100, the width of the germanium-silicon layer 300 is approximately the same as the width of the films in the first gate structure 400a. In this embodiment, the gate oxide layer 410 can be made of silicon oxide, the first high dielectric constant dielectric layer 421 can be made of HfSiON and contain LaO, the second high dielectric constant dielectric layer 422 can be made of HfSiON and do not contain LaO, the first metal layer 430 can be made of titanium nitride, the conductive layer 440 can be made of SiP, the second metal layer 450 can be made of titanium nitride, and the third metal layer 460 can be made of tungsten.
[0047] Furthermore, sidewalls 500 are formed on the sides of the first gate structure 400a and the second gate structure 400b. The sidewalls 500 of the first gate structure 400a and the second gate structure 400b can be independent of each other (not connected, e.g.) Figure 1 (as shown), or the sidewall 500 of the first gate structure 400a sidewall and the sidewall 500 of the second gate structure 400b sidewall are connected (as shown). Figure 2 As shown, sidewall 500 covers the isolation dielectric layer 200 between PMOS region 110 and NMOS region 120. Sidewall 500 may be at least one of silicon oxide layer, silicon nitride layer and silicon oxynitride layer. In some embodiments, sidewall 500 may also extend to cover the top surface of silicon nitride layer 470.
[0048] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the different parts of each embodiment, and will not repeat the same parts. In addition, the same components in the different embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the different embodiments.
[0049] Please refer to Figures 3-6 In this embodiment, the first gate structure 400a and / or the second gate structure 400b directly contact one end of the isolation dielectric layer 200, and the other end of the isolation dielectric layer 200 is higher than the top surface of the substrate 100. The figure illustrates adjacent first gate structures 400a or second gate structures 400b directly contacting one end of the isolation dielectric layer 200, with the other end of the isolation dielectric layer 200 higher than the top surface of the substrate 100. In reality, there are multiple first gate structures 400a and second gate structures 400b. An isolation trench 200a is provided between the first gate structures 400a and second gate structures 400b. Non-adjacent first gate structures 400a and second gate structures 400b can directly contact one end of the isolation dielectric layer 200 adjacent to them.
[0050] Please continue to refer to this. Figure 3 and Figure 4 When the germanium-silicon layer 300 and the gate oxide layer 410 in the first gate structure 400a are embedded in the substrate 100, the second gate structure 400b can cover one end of the isolation dielectric layer 200, and the gate oxide layer 410 in the second gate structure 400b can directly contact one end of the isolation dielectric layer 200, while the other end of the isolation dielectric layer 200 is higher than the top surface of the substrate 100; or other film layers in the first gate structure 400a can cover one end of the isolation dielectric layer 200, and the first high dielectric constant dielectric layer 421 in the first gate structure 400a can directly contact one end of the isolation dielectric layer 200, while the other end of the isolation dielectric layer 200 is higher than the top surface of the substrate 100.
[0051] Please continue to refer to this. Figure 5 and Figure 6 When the bottom surface of the germanium-silicon layer 300 is in direct contact with the top surface of the substrate 100, the second gate structure 400b can cover one end of the isolation dielectric layer 200, and the gate oxide layer 410 in the second gate structure 400b can directly contact one end of the isolation dielectric layer 200, while the other end of the isolation dielectric layer 200 is higher than the top surface of the substrate 100; alternatively, the germanium-silicon layer 300 and the first gate structure 400a can cover one end of the isolation dielectric layer 200, and the germanium-silicon layer 300 can directly contact one end of the isolation dielectric layer 200, while the other end of the isolation dielectric layer 200 is higher than the top surface of the substrate 100.
[0052] The isolation dielectric layer 200 includes a first portion 210, a second portion 220, and a third portion 230. The first portion 210 is located within an isolation trench 200a and covers the sidewalls and bottom of the isolation trench 200a. The second portion 220 is located on the first portion 210 and is in direct contact with the first portion 210. The third portion 230 fills the isolation trench 200a and is in direct contact with the second portion 220. The top surface of the third portion 230 is flush with the top surface of the substrate. The end of the isolation dielectric layer 200 above the top surface of the substrate 100 is one end of the second portion 220. The first gate structure 400a or the second gate structure 400b at least covers the portion of the second portion 220 at one end of the isolation dielectric layer 200.
[0053] Figures 7-10 This is a cross-sectional schematic diagram of a corresponding step in the fabrication method of the semiconductor device provided in this embodiment. Figures 7-10 For preparation Figure 1 A cross-sectional schematic diagram of the corresponding steps in the fabrication of a semiconductor device illustrates how a second portion above the substrate is formed. This embodiment provides a method for fabricating a semiconductor device, including:
[0054] Please refer to Figure 7 A substrate 100 is provided, which includes a PMOS region 110, an NMOS region 120, and an isolation trench 200a located in the PMOS region 110 and the NMOS region 120.
[0055] Please continue to refer to this. Figure 7 An isolation dielectric layer 200 is formed, comprising a first portion 210, a second portion 220, and a third portion 230. The first portion 210 is located within an isolation trench 200a and covers the sidewalls and bottom of the isolation trench 200a, and the first portion 210 also extends to cover the top surface of the substrate 100. The second portion 220 is located on the first portion 210 and is in direct contact with the first portion 210. The third portion 230 fills the isolation trench 200a and is in direct contact with the second portion 220, and the top surface of the third portion 230 is flush with the top surface of the substrate.
[0056] Please refer to Figure 8 A mask layer 600 is formed on the NMOS region and part of the isolation dielectric layer 200; the first part 210 and the substrate 100 (PMOS region 110) are etched using the mask layer 600 as a mask, so that the exposed second part 220 is higher than the top surface of the substrate 100. Different etching gases are used to control the etching selectivity during etching to obtain the target morphology; the mask layer 600 is removed after etching.
[0057] Please refer to Figure 9A germanium-silicon layer 300 is formed on the PMOS region 110, and a gate oxide layer 410 in the first gate structure 400a is formed on the germanium-silicon layer 300, such that the germanium-silicon layer 300 and the gate oxide layer 410 in the first gate structure 400a are embedded in the substrate 100. Then, the first portion 210, a portion of the third portion 230, and a portion of the second portion 220 on the NMOS region 120 are removed.
[0058] Please refer to Figure 10 A gate oxide layer 410 in the second gate structure 400b is formed on the NMOS region 120, and the top surface of the second portion 220 is higher than the top surface of the gate oxide layer 410 in the second gate structure 400b; and a gate material layer is formed to cover the PMOS region 110, the NMOS region 120 and the isolation dielectric layer 200. The gate material layer includes a high dielectric constant dielectric layer (a first high dielectric constant dielectric layer 421 and a second high dielectric constant dielectric layer 422), a first metal layer 430, a conductive layer 440, a second metal layer 450, a third metal layer 460 and a silicon nitride layer 470 stacked sequentially from bottom to top. The gate material layer at the top of the second portion 220 is higher than the gate material layer 220 at the top of the substrate 100.
[0059] Please refer to the reference. Figure 1 A patterned photoresist layer (not shown in the figure) is formed on the gate material layer. The patterned photoresist layer covers part of the gate material layer, specifically the area where the first gate structure 400a and the second gate structure 400b are located. Using the patterned photoresist layer as a mask, the gate material layer is etched to form the first gate structure 400a and the second gate structure 400b. The first gate structure 400a is located on the germanium-silicon layer, and the second gate structure 400b is located on the NMOS region. Because the second part 220 is positioned higher, the gate material layer 400 at the top of the second part 220 will come into contact with the etching gas earlier during etching and will be etched away more quickly, blocking the connection between the gate materials of the PMOS region 110 and the NMOS region 120, thereby preventing short circuits that could affect the device's performance.
[0060] In summary, in the semiconductor device and its fabrication method provided by this invention, the substrate includes a PMOS region, an NMOS region, and an isolation trench located between the PMOS and NMOS regions; the isolation dielectric layer includes: a first portion located within the isolation trench, covering the sidewalls and bottom of the isolation trench; a second portion located on the first portion and in direct contact with the first portion, the second portion being higher than the top surface of the substrate; a germanium-silicon layer located on the PMOS region, a first gate structure located on the germanium-silicon layer, and a second gate structure located on the NMOS region. By setting the second portion of the isolation dielectric layer higher than the top surface of the substrate, after the gate material layer is formed, during the etching process to form the first and second gate structures, the higher position of the second portion allows it to come into contact with the etching gas earlier and be etched away more quickly, blocking the connection between the gate materials of the PMOS and NMOS regions. This prevents short circuits from affecting the device's performance. Furthermore, because the second portion is higher, etching on the second portion will not affect the device's performance.
[0061] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the scope of protection of the present invention.
Claims
1. A semiconductor device, characterized in that, include: The substrate includes a PMOS region, an NMOS region, and an isolation trench located between the PMOS region and the NMOS region; The isolation dielectric layer includes: The first part is located within the isolation trench and covers the sidewalls and bottom of the isolation trench; The second part is located on the first part and in direct contact with the first part, and the second part is higher than the top surface of the substrate; A germanium-silicon layer is located on the PMOS region; A first gate structure is located on the germanium-silicon layer; The second gate structure is located on the NMOS region.
2. The semiconductor device as claimed in claim 1, characterized in that, The top surface of the germanium-silicon layer is lower than the top surface of the substrate.
3. The semiconductor device as described in claim 2, characterized in that, The germanium-silicon layer and the gate oxide layer in the first gate structure are embedded in the substrate.
4. The semiconductor device as claimed in claim 1, characterized in that, The bottom surface of the germanium-silicon layer is in direct contact with the top surface of the substrate.
5. The semiconductor device as claimed in claim 1, characterized in that, The isolation medium layer also includes a third part, which fills the isolation trench and is in direct contact with the second part.
6. A semiconductor device, characterized in that, include: The substrate includes a PMOS region, an NMOS region, and an isolation trench located between the PMOS region and the NMOS region; The isolation medium layer is located within the isolation trench; A germanium-silicon layer is located on the PMOS region; A first gate structure is located on the germanium-silicon layer; The second gate structure is located on the NMOS region; Wherein, the first gate structure and / or the second gate structure are in direct contact with one end of the isolation dielectric layer, and the other end of the isolation dielectric layer is higher than the top surface of the substrate.
7. The semiconductor device as claimed in claim 6, characterized in that, The germanium-silicon layer and the gate oxide layer in the first gate structure are embedded in the substrate.
8. The semiconductor device as claimed in claim 6, characterized in that, The bottom surface of the germanium-silicon layer is in direct contact with the top surface of the substrate.
9. The semiconductor device as claimed in claim 8, characterized in that, The germanium-silicon layer and the first gate structure cover one end of the isolation dielectric layer, and the other end of the isolation dielectric layer is higher than the top surface of the substrate.
10. The semiconductor device as claimed in claim 6, characterized in that, The isolation medium layer includes a first part, a second part, and a third part. The first part is located in the isolation trench and covers the sidewalls and bottom of the isolation trench. The second part is located on the first part and is in direct contact with the first part. The third part fills the isolation trench and is in direct contact with the second part.
11. The semiconductor device as claimed in claim 10, characterized in that, The end of the isolation dielectric layer above the top surface of the substrate is one end of the second part.
12. The semiconductor device as claimed in claim 10, characterized in that, The first gate structure or the second gate structure at least covers a portion of the second part at one end of the isolation dielectric layer.
13. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a PMOS region, an NMOS region, and an isolation trench located between the PMOS region and the NMOS region; Forming an isolation medium layer, including: The first part is located within the isolation trench and covers the sidewalls and bottom of the isolation trench; The second part is located on the first part and is in direct contact with the first part; The first portion and the substrate are etched so that the second portion is higher than the top surface of the substrate; A germanium-silicon layer is formed on the PMOS region; A gate material layer is formed to cover the PMOS region, the NMOS region, and the isolation dielectric layer, wherein the gate material layer at the top of the second portion is higher than the gate material layer at the top of the substrate; The gate material layer is etched to form a first gate structure and a second gate structure, wherein the first gate structure is located on the germanium-silicon layer and the second gate structure is located on the NMOS region.