Back contact solar cell, laminated cell and photovoltaic module

Abstract

The invention provides a back contact solar cell, a laminated cell and a photovoltaic module, and the back contact solar cell comprises a semiconductor substrate, the second surface of the semiconductor substrate is provided with a first sub-region and second sub-regions located at the two sides of the first sub-region, and the first sub-region is internally provided with a plurality of first texture structures; a plurality of first polishing structures are arranged in the second sub-region, the second sub-region protrudes in the direction away from the first surface relative to the first sub-region, and the distance between the second sub-region and the bottom of the first texture structure in the first sub-region is 2-5 microns; the second surface of the semiconductor substrate is provided with a third sub-region and fourth sub-regions located on the two sides of the third sub-region, a plurality of second texture structures are arranged in the third sub-region, a plurality of second polishing structures are arranged in the fourth sub-regions, and the fourth sub-regions protrude in the direction away from the first surface relative to the third sub-region; and the distance between the bottom of the second texture structure in the fourth sub-region and the bottom of the second texture structure in the third sub-region is 2-5 microns.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a back-contact solar cell, a tandem cell, and a photovoltaic module. Background Technology

[0002] Photovoltaic cells are a type of clean power generation system that uses sunlight to generate electricity. Photovoltaic power generation systems are expected to meet future electricity needs without harming the environment. As a result, public attention has been focused on photovoltaic power generation systems. The core component of a photovoltaic power generation system is a solar cell, which can directly convert sunlight into electrical energy.

[0003] Back-contact solar cells are a type of solar cell technology that places both the positive and negative electrodes on the back of the cell. This design eliminates any grid lines obstructing the front of the cell, maximizing sunlight utilization, reducing optical losses, increasing the effective power generation area, and improving conversion efficiency. As research into back-contact solar cells progresses, further studies are needed to understand their structure and performance.

[0004] Improving the passivation and electrical contact performance of back-contact solar cells to enhance their photoelectric conversion efficiency is an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides a back-contact solar cell, a tandem cell, and a photovoltaic module, which can improve the passivation performance and electrical contact performance of the back-contact solar cell, thereby improving the photoelectric conversion efficiency of the back-contact solar cell.

[0006] In a first aspect, embodiments of this application provide a back-contact solar cell, comprising: A semiconductor substrate having a first surface and a second surface disposed opposite to each other; The second surface of the semiconductor substrate is provided with alternating first and second conductive regions. Within the first conductive region, the second surface of the semiconductor substrate has a first sub-region and a second sub-region located on both sides of the first sub-region. The first sub-region is provided with a plurality of first texture structures, and the second sub-region is provided with a plurality of first polishing structures. The second sub-region protrudes in a direction away from the first surface relative to the first sub-region. The distance between the bottom of the first texture structure in the second sub-region and the first sub-region is 2μm~5μm. Within the second conductive region, the second surface of the semiconductor substrate has a third sub-region and a fourth sub-region located on both sides of the third sub-region. The third sub-region is provided with a plurality of second texture structures, and the fourth sub-region is provided with a plurality of second polishing structures. The fourth sub-region protrudes in a direction away from the first surface relative to the third sub-region. The distance between the bottom of the second texture structure in the fourth sub-region and the third sub-region is 2μm~5μm. A first passivation layer and a first electrode are disposed within the first conductive region; A second passivation layer and a second electrode are disposed within the second conductive region.

[0007] Secondly, embodiments of this application provide a stacked battery, the stacked battery comprising a top battery and a bottom battery stacked together, the bottom battery being the back-contact solar cell described in the first aspect.

[0008] Thirdly, embodiments of this application provide a photovoltaic module, the photovoltaic module comprising: A battery string, wherein the battery string is formed by connecting multiple solar cells as described in the first aspect or stacked cells as described in the second aspect; An encapsulation layer that covers the surface of the battery string; A cover plate for covering the surface of the encapsulation layer away from the battery string.

[0009] The technical solution provided in this application can achieve the following beneficial effects: In the solar cell of this application, a first sub-region and a second sub-region located on both sides of the first sub-region are provided within a first conductive region. The first sub-region has multiple first textured structures, and the second sub-region has multiple first polished structures. The second sub-region protrudes relative to the first sub-region in a direction away from the first surface, i.e., there is a height difference between the first polished structures in the second sub-region and the first textured structures in the first sub-region, and the distance between the bottoms of the first textured structures in the second sub-region and the first sub-region is 2μm~5μm. A third sub-region and a fourth sub-region located on both sides of the third sub-region are provided within the second conductive region. The third sub-region has multiple second textured structures, and the fourth sub-region has multiple second textured structures. The polished structure features a fourth sub-region that protrudes away from the first surface relative to the third sub-region. Specifically, there is a height difference between the second polished structure in the fourth sub-region and the second textured structure in the third sub-region, and the distance between the bottoms of the second textured structures in the fourth and third sub-regions is 2μm to 5μm. This reduces the contact resistance between the electrode and the semiconductor substrate within both the first and second conductive regions. The presence of a first polished structure in the second sub-region and a second polished structure in the fourth sub-region effectively enhances the light absorption capacity of the non-electrode region and suppresses carrier recombination, achieving excellent passivation. This balances improved passivation performance with reduced contact resistance. The back-contact solar cell of this application effectively improves open-circuit voltage and short-circuit current, thereby increasing photoelectric conversion efficiency.

[0010] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a back-contact solar cell provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the semiconductor substrate provided in the embodiments of this application; Figure 3 A microscope image of the first conductive region provided in an embodiment of this application; Figure 4 A microscope image of the first texture structure provided in an embodiment of this application; Figure 5 A microscope image of the second conductive region provided in an embodiment of this application; Figure 6 Microscopic image of the second texture structure provided in the embodiments of this application; Figure 7 Microscopic image of the second polished structure provided in the embodiments of this application; Figure 8 Microscopic images of the third texture structure provided in the embodiments of this application; Figure 9 Another microscopic image of the first conductive region provided in the embodiments of this application; Figure 10 Another microscopic image of the second conductive region provided in the embodiments of this application; Figure 11 A microscope image of the first surface of a semiconductor substrate provided in an embodiment of this application; Figure 12 This is a schematic diagram of the structure of the stacked battery provided in the embodiments of this application; Figure 13 This is a schematic diagram of the structure of a photovoltaic module provided in an embodiment of this application.

[0012] Figure label: 1000 - Photovoltaic modules; 100-back contact solar cell; 10 - First conductive region; 101 - First sub-region; 102 - Second sub-region; 103 - First sidewall; 20 - Second conductive region; 201 - Third sub-region; 202 - Fourth sub-region; 203 - Second sidewall; 30 - Isolation Zone; 1-Semiconductor substrate; 11-First textured structure; 12-First polished structure; 13-Second textured structure; 14-Second polished structure; 15-Third textured structure; 16-Fourth textured structure; 161-First end; 162-Second end; 17-Fifth textured structure; 171-Third end; 172-Fourth end; 2-First passivation layer; 3-Second passivation layer; 4-Third passivation layer; 5-Antireflection layer; 6-First electrode; 7-Second electrode; 200 - First cover plate; 300 - First encapsulating adhesive layer; 400 - Second encapsulating adhesive layer; 500 - Second cover plate; 2000-Stacked Battery; 2001-Top Battery; 2002-bottom battery.

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0015] In the description of this application, unless otherwise expressly specified and limited, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; unless otherwise specified or explained, the term "multiple" refers to two or more; the terms "connected," "fixed," etc., should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, an integral connection, or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0016] In the description of this specification, it should be understood that the directional terms such as "upper" and "lower" used in the embodiments of this application are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this application. Furthermore, in the context, it should also be understood that when it is mentioned that an element is connected "upper" or "lower" to another element, it can be directly connected to the other element "upper" or "lower," or indirectly connected to the other element "upper" or "lower" through an intermediate element.

[0017] In this specification, the "~" between two numerical values ​​represents an endpoint value that includes both numerical values.

[0018] This application provides a back-contact solar cell 100. Figure 1 This is a schematic diagram of a back-contact solar cell 100. Figure 2 Please refer to the schematic diagram of a semiconductor substrate structure. Figure 1 and Figure 2 The back-contact solar cell 100 includes: Semiconductor substrate 1, semiconductor substrate 1 having a first surface and a second surface disposed opposite to each other; The second surface of the semiconductor substrate 1 is provided with alternating first conductive regions 10 and second conductive regions 20; Within the first conductive region 10, the second surface of the semiconductor substrate 1 has a first sub-region 101 and a second sub-region 102 located on both sides of the first sub-region 101. The first sub-region 101 is provided with a plurality of first texture structures 11, and the second sub-region 102 is provided with a plurality of first polishing structures 12. The second sub-region 102 protrudes in a direction away from the first surface relative to the first sub-region 101. The distance between the bottom of the first texture structure 11 in the second sub-region 102 and the first sub-region 101 is 2μm to 5μm. Within the second conductive region 20, the second surface of the semiconductor substrate 1 has a third sub-region 201 and a fourth sub-region 202 located on both sides of the third sub-region 201. The third sub-region 201 is provided with a plurality of second texture structures 13, and the fourth sub-region 202 is provided with a plurality of second polishing structures 14. The fourth sub-region 202 protrudes in a direction away from the first surface relative to the third sub-region 201. The distance between the bottom of the second texture structures 13 in the fourth sub-region 202 and the third sub-region 201 is 2μm to 5μm. A first passivation layer 2 and a first electrode 6 are disposed within the first conductive region 10; The second passivation layer 3 and the second electrode 7 are disposed within the second conductive region 20.

[0019] In the above-described scheme, the solar cell of this application includes a first sub-region 101 and a second sub-region 102 located on both sides of the first sub-region 101. The first sub-region 101 contains multiple first texture structures 11, and the second sub-region 102 contains multiple first polished structures 12. The second sub-region 102 protrudes relative to the first sub-region 101 in a direction away from the first surface, meaning there is a height difference between the first polished structures 12 of the second sub-region 102 and the first texture structures 11 of the first sub-region 101, and the distance between the bottoms of the first texture structures 11 in the second sub-region 102 and the first sub-region 101 is 2μm to 5μm. The second conductive region 20 includes a third sub-region 201 and a fourth sub-region 202 located on both sides of the third sub-region 201. The third sub-region 201 contains multiple second texture structures 13. The fourth sub-region 202 is provided with multiple second polished structures 14. The fourth sub-region 202 protrudes away from the first surface relative to the third sub-region 201, meaning there is a height difference between the second polished structures 14 in the fourth sub-region 202 and the second textured structures 13 in the third sub-region 201. The distance between the bottoms of the second textured structures 13 in the fourth sub-region 202 and the third sub-region 201 is 2μm to 5μm. Thus, within the first conductive region 10 and the second conductive region 20, the contact resistance between the electrode and the semiconductor substrate 1 can be reduced. Simultaneously, the first polished structure 12 in the second sub-region 102 and the second polished structure 14 in the fourth sub-region 202 effectively enhance the light absorption capacity of the non-electrode region and effectively suppress carrier recombination, achieving excellent passivation effects. This balances improved passivation performance with reduced contact resistance. The back-contact solar cell of this application can effectively improve open-circuit voltage and short-circuit current, thereby improving photoelectric conversion efficiency.

[0020] It should be noted that "texture structure" refers to a micro- or nano-sized structure that can scatter or reflect light to enhance light absorption. The texture structure of this application can be formed by processes such as chemical etching, laser etching, mechanical etching, or plasma etching on the semiconductor substrate 1.

[0021] It should be noted that "polished structure" refers to a relatively flat region with low roughness and no obvious texture undulations formed on the surface of semiconductor substrate 1 after polishing. The surface height difference in this region is typically less than 50 nm and does not have significant light-trapping capabilities. Polished structures can be formed through chemical mechanical polishing (CMP), wet chemical polishing (such as alkaline polishing or acid polishing), or plasma polishing.

[0022] In this application, the first conductive region 10 and the second conductive region 20 are alternately distributed on the second surface of the semiconductor substrate 1. The conductivity type of the dopant element in the first conductive region 10 is different from that in the second conductive region 20. Their main function is to separate and collect charge carriers, and then transfer the collected charge carriers to the first electrode 6 and the second electrode 7 on the second surface of the semiconductor substrate 1 to form a path with the external load. Therefore, the first conductive region 10 and the second conductive region 20 can be in direct contact. Otherwise, the collected charge carriers will form a short circuit by directly contacting each other on the second surface of the semiconductor substrate 1, which would prevent the charge carriers from being effectively collected. Therefore, an isolation region 30 is usually provided between the first conductive region 10 and the second conductive region 20.

[0023] In this application, the back-contact solar cell may also be referred to as a "back-contact battery" or a "battery".

[0024] In some embodiments, the isolation region 30 has a textured structure, which is beneficial for improving light reflection and scattering of the back-contact solar cell and increasing the parallel resistance, thereby improving the photoelectric conversion efficiency.

[0025] In some embodiments, a passivation layer (not shown in the figures) is provided in the isolation region 30 to improve the passivation effect of the back contact solar cell.

[0026] In some embodiments, an insulating layer (not shown in the figures) is provided within the isolation region 30 to improve the insulation of the first conductive region 10 and the second conductive region 20 in the back contact solar cell.

[0027] In some embodiments, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer), but it can also be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) is, for example, a polycrystalline silicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate. This application does not limit the specific type of the semiconductor substrate 1. Optionally, the semiconductor substrate 1 is an N-type crystalline silicon substrate.

[0028] In some embodiments, the thickness of the semiconductor substrate 1 is 60μm to 240μm, specifically it can be 60μm, 80μm, 90μm, 100μm, 120μm, 150μm, 200μm or 240μm, etc., and is not limited here.

[0029] Please continue reading. Figure 1 The semiconductor substrate 1 includes a first surface and a second surface disposed opposite to each other. For example, the first surface refers to the front surface (also called the light-receiving surface) of the semiconductor substrate 1, that is, the surface that receives sunlight, and the second surface refers to the surface opposite to the front surface, that is, the rear surface (also called the back-lighting surface).

[0030] In some embodiments, the first conductive region 10 is an N-type conductive region and the second conductive region 20 is a P-type conductive region. In other embodiments, the first conductive region 10 is a P-type conductive region and the second conductive region 20 is an N-type conductive region. The following description uses an example where the first conductive region 10 is an N-type conductive region and the second conductive region 20 is a P-type conductive region.

[0031] Figure 3 Please refer to a microscope image of the first conductive region 10. Figure 2 and Figure 3 The first sub-region 101 has multiple first texture structures 11, and the microscopic image of the first texture structure 11 is shown below. Figure 4 As shown, the second sub-region 102 is provided with a plurality of first polishing structures 12. The first sub-region 101 and the second sub-region 102 are not on the same plane, that is, the second surface of the semiconductor substrate 1. The first sub-region 101 and the second sub-region 102 have a height difference.

[0032] Correspondingly, Figure 5 Please refer to a microscope image of the second conductive region 20. Figure 2 and Figure 5 The third sub-region 201 has multiple second texture structures 13, and the microscopic image of the second texture structure 13 is shown below. Figure 6 As shown, the fourth sub-region 202 is provided with multiple second polishing structures 14, and the microscope image of the second polishing structure 14 is shown below. Figure 7 As shown, the third sub-region 201 and the fourth sub-region 202 are not on the same plane, that is, on the second surface of the semiconductor substrate 1, the third sub-region 201 and the fourth sub-region 202 have a height difference.

[0033] The semiconductor substrate 1 with the first conductive region 10 and the second conductive region 20 in the back-contact solar cell 100 can be cross-sectioned and observed under a measuring instrument (optical microscope, atomic force microscope, scanning electron microscope, transmission electron microscope, etc.). The observation angle is the angle after cross-section along the thickness direction of the semiconductor substrate 1. From the measuring instrument, it can be observed that there is a significant height difference between the first polished structure 12 of the second sub-region 102 and the first textured structure 11 of the first sub-region 101, and there is a significant height difference between the second polished structure 14 of the fourth sub-region 202 and the second textured structure 13 of the third sub-region 201.

[0034] In some implementations, continue as Figure 2 As shown, the distance between the bottom of the first texture structure 11 in the second sub-region 102 and the first sub-region 101 is denoted as h1, where h1 is 2μm to 5μm, specifically 2μm, 3μm, 4μm, 5μm or any value within the range of any two of the above values.

[0035] In some implementations, continue as Figure 2 As shown, the distance between the bottom of the second texture structure 13 within the fourth sub-region 202 and the third sub-region 201 is denoted as h2, where h2 is 2μm to 5μm, specifically 2μm, 3μm, 4μm, 5μm, or any value within the range of any two of the above values. For an example, please refer to [further details]. Figure 4 The distance between the bottom of the second texture structure 13 in the fourth sub-region 202 and the third sub-region 201 is 3.662 μm.

[0036] This application controls the distance between the bottom of the first textured structure 11 in the second sub-region 102 and the first sub-region 101, and the distance between the bottom of the second textured structure 13 in the fourth sub-region 202 and the third sub-region 201, within the aforementioned range. This not only reduces the contact resistance between the electrode and the semiconductor substrate 1 but also ensures the passivation effect of the second surface of the semiconductor substrate 1, thereby achieving a balance between improving passivation performance and reducing contact resistance. If the distance between the bottom of the first textured structure 11 in the second sub-region 102 and the first sub-region 101 is too large, or the distance between the bottom of the second textured structure 13 in the fourth sub-region 202 and the third sub-region 201 is too large, the passivation effect deteriorates. If the distance between the bottom of the first textured structure 11 in the second sub-region 102 and the first sub-region 101 is too small, or the distance between the bottom of the second textured structure 13 in the fourth sub-region 202 and the third sub-region 201 is too small, the contact resistance between the electrode and the semiconductor substrate 1 increases significantly.

[0037] In some embodiments, the back-contact solar cell 100 further includes a third textured structure 15 disposed on the first surface of the semiconductor substrate 1, and the microscopic image of the third textured structure 15 is shown below. Figure 8 As shown.

[0038] Figure 9 Another microscopic image of the first conductive region 10. Figure 10 Another microscopic image of the second conductive region 20. Figure 11 A microscope image of the first surface of semiconductor substrate 1, as shown below. Figures 9-11 As shown, the texture coverage of the first surface of the semiconductor substrate 1 is greater than the texture coverage of the first sub-region 101, and the texture coverage of the first surface of the semiconductor substrate 1 is greater than the texture coverage of the third sub-region 201.

[0039] This application provides a third texture structure 15 on the first surface of the semiconductor substrate 1, which is beneficial for improving the utilization rate of sunlight and reducing the reflectivity of the first surface. This application specifies that the texture coverage of the first surface of the semiconductor substrate 1 is greater than the texture coverage in the first sub-region 101, and the texture coverage of the first surface of the semiconductor substrate 1 is greater than the texture coverage in the third sub-region 201. This ensures that while reducing contact resistance, it further improves the passivation performance of the first sub-region 101 and the third sub-region 201, thereby improving the overall performance of the back contact solar cell.

[0040] It should be noted that "texture coverage" refers to the proportion of the total surface area of ​​the semiconductor substrate 1 to areas with height differences or undulations in shape.

[0041] In some embodiments, the texture coverage of the first surface of the semiconductor substrate 1 is 100%.

[0042] In some implementations, the texture coverage α within the first sub-region 101 satisfies 70% ≤ α < 100%, and α can specifically be 70%, 75%, 80%, 85%, 90%, 95%, 95%, or any value within the range of any two of the above values.

[0043] In some implementations, the texture coverage β in the third sub-region 201 satisfies 70%≤β<100%, and β can specifically be 70%, 75%, 80%, 85%, 90%, 95%, 95%, or any value within the range of any two of the above values.

[0044] In this application, the values ​​of texture coverage α and texture coverage β can be the same or different.

[0045] It should be noted that the texture coverage rate in this application is obtained using the following method: within any 50μm × 50μm field of view on the surface of the semiconductor substrate 1, the percentage of the area covered by the texture structure relative to the total area of ​​that field of view. This refers to the proportion of the total surface area of ​​a region on a certain surface of the semiconductor substrate 1 where there is a height difference or morphological undulation. The height difference or morphological undulation is formed by a texturing process, including but not limited to surface structures generated by etching, deposition, or machining. The texture coverage rate can be obtained by acquiring surface morphology data using an electron microscope (SEM), atomic force microscope (AFM), or laser confocal microscope, and then calculated using corresponding image or data analysis software.

[0046] In some implementations, please refer to [the relevant documentation]. Figure 3 A first sidewall 103 is provided between the first sub-region 101 and the second sub-region 102, and a plurality of fourth texture structures 16 are provided in the first sidewall 103.

[0047] Accordingly, please continue to refer to Figure 5 A second sidewall 203 is provided between the third sub-region 201 and the fourth sub-region 202, and a plurality of fifth texture structures 17 are provided in the second sidewall 203.

[0048] A first sidewall 103 exists between the first sub-region 101 and the second sub-region 102. The first sidewall 103 has a different crystal phase than the first sub-region 101 and the second sub-region 102. A second sidewall 203 exists between the third sub-region 201 and the fourth sub-region 202. The second sidewall 203 also has a different crystal phase than the third sub-region 201 and the fourth sub-region 202. Compared to other regions, the first sidewall 103 and the second sidewall 203 are more difficult to passivate. This application, by providing a fourth texture structure 16 on the first sidewall 103 and a fifth texture structure 17 on the second sidewall 203, helps to increase the specific surface area of ​​the second surface of the semiconductor substrate 1, reduce the contact resistance, and simultaneously enhance the light-trapping effect of the second surface of the solar cell, increase the light absorption of sunlight from the back side, and reduce the reflection of sunlight from the back side.

[0049] In some embodiments, at least one of the fourth texture structure 16 and the fifth texture structure 17 includes at least one of cylindrical and prismatic shapes.

[0050] Compared to the pyramid-shaped textured structures formed by texturing in related technologies, pyramid structures have a simple morphology, a large base area, and a pointed top. Located on the back side of the semiconductor substrate 1, they generally have poor back-side light reflection and are not conducive to subsequent film deposition. The fourth textured structure 16 and the fifth textured structure 17 of this application are non-pyramid morphologies. Compared to pyramid morphologies, these non-pyramid morphologies are easier to passivate, improving the passivation performance of the back-contact solar cell 100. Furthermore, long-wavelength light transmitted from the front side of the back-contact solar cell 100 through the semiconductor substrate 1 can also be absorbed by the fourth textured structure 16 and the fifth textured structure 17, further enhancing the overall light absorption efficiency of the cell, while not affecting the passivation effect of the first sidewall 103 and the second sidewall 203, thus improving the photoelectric conversion efficiency of the solar cell.

[0051] In some implementations, please refer to [the relevant documentation]. Figure 3 The fourth texture structure 16 includes a first end 161 and a second end 162 positioned opposite each other. The first end 161 extends into the first sub-region 101, and the second end 162 extends into the second sub-region 102. Please continue reading. Figure 5 The fifth texture structure 17 includes a third end 171 and a fourth end 172 that are arranged opposite to each other. The third end 171 extends into the third sub-region 201, and the fourth end 172 extends into the fourth sub-region 202.

[0052] In some implementations, the height of the first texture structure 11 is greater than or equal to the height of the second texture structure 13.

[0053] In some embodiments, the height of the first texture structure 11 is 300nm to 900nm, specifically 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm or any value within the range of any two of the above values.

[0054] In some embodiments, the height of the second texture structure 13 is 250nm to 850nm, specifically 250nm, 350nm, 400nm, 450nm, 550nm, 650nm, 700nm, 780nm, 800nm, 850nm, or any value within the range of any two of the above values.

[0055] It should be noted that the height of the first texture structure 11 refers to the distance from the top to the bottom of the first texture structure 11 along the thickness direction of the semiconductor substrate 1. This means that the top and bottom of the first texture structure 11 are positioned opposite each other, and the bottom of the first texture structure 11 is in contact with the first conductive region 10. Correspondingly, the height of the second texture structure 13 refers to the distance from the top to the bottom of the second texture structure 13 along the thickness direction of the semiconductor substrate 1.

[0056] In some embodiments, the bottom one-dimensional dimension of the first texture structure 11 is greater than or equal to the bottom one-dimensional dimension of the second texture structure 13.

[0057] In some embodiments, the bottom surface one-dimensional dimension of the first texture structure 11 is 2.0μm to 3.5μm, specifically it can be 2.0μm, 2.3μm, 2.5μm, 2.7μm, 3.0μm, 3.3μm, 3.5μm or any value within the range of any two of the above values.

[0058] In some embodiments, the bottom surface one-dimensional dimension of the second texture structure 13 is 1.3μm to 2.0μm, specifically it can be 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2.0μm or any value within the range of any two of the above values.

[0059] It should be noted that the one-dimensional dimension of the bottom of the first texture structure 11 refers to the length, width, diagonal length, and diameter of the circle on the bottom surface of the first texture structure 11, and is not limited here. The one-dimensional dimension of the bottom of the first texture structure 11 can be directly measured and calibrated on the film surface using measuring instruments (optical microscope, atomic force microscope, scanning electron microscope, transmission electron microscope, etc.). Correspondingly, the one-dimensional dimension of the bottom surface of the second texture structure 13 refers to the length, width, diagonal length, and diameter of the circle on the bottom surface of the second texture structure 13, and the one-dimensional dimension of the bottom surface of the second texture structure 13 can be determined using the aforementioned measuring instruments.

[0060] Compared to the first texture structure 11, the second texture structure 13 of this application has a smaller height and a smaller bottom dimension, which is beneficial for forming more uniform doping in the second conductive region 20, reducing the recombination current density at the electrode-semiconductor substrate 1 contact, improving the fill factor, and thus improving the conversion efficiency of the back contact solar cell 100.

[0061] In some embodiments, the one-dimensional dimension of the first polishing structure 12 is 5μm to 20μm, specifically it can be 5μm, 8μm, 10μm, 13μm, 15μm, 18μm, 20μm or any value within the range of any two of the above values.

[0062] The one-dimensional dimension of the second polishing structure 14 is 3μm to 18μm, specifically it can be 3μm, 5μm, 7μm, 9μm, 12μm, 15μm, 18μm or any value within the range of any two of the above values.

[0063] The one-dimensional dimension of the first polishing structure 12 in this application is larger than the one-dimensional dimension of the bottom surface of the first texture structure 11, and the one-dimensional dimension of the second polishing structure 14 is larger than the one-dimensional dimension of the bottom surface of the second texture structure 13. The larger dimensions of the first polishing structure 12 and the second polishing structure 14 are conducive to achieving a highly uniform doping distribution and a uniform metal-semiconductor interface, which is beneficial to reducing contact recombination loss.

[0064] In some embodiments, the morphology of the first texture structure 11 includes at least one of pyramids and pyramid-like structures, and the morphology of the second texture structure 13 includes at least one of pyramids and pyramid-like structures. Pyramid-like structures include, for example, truncated pyramids, domed pyramids, nanocones, inverted pyramids, frustums, cones, polygonal pyramids, irregular hill-like structures, etc.

[0065] In some embodiments, the top included angle of the first texture structure 11 is 90°~120°, and the top included angle of the second texture structure 13 is 90°~120°. Specifically, it can be 90°, 95°, 100°, 110°, 115°, 120° or any value within the range of any two of the above values.

[0066] In some implementations, the reflectivity of the first sub-region 101 is 12% to 18%, specifically 12%, 13%, 14%, 15%, 16%, 17%, 18%, or any value within the range of any two of the above values.

[0067] In some implementations, the reflectivity of the second sub-region 102 is 35% to 40%, specifically 35%, 36%, 37%, 38%, 39%, 40%, or any value within the range of any two of the above values.

[0068] In some implementations, the reflectivity of the third sub-region 201 is 13% to 20%, specifically 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, or any value within the range of any two of the above values.

[0069] In some implementations, the reflectivity of the fourth sub-region 202 is 37% to 43%, specifically 37%, 38%, 39%, 40%, 41%, 42%, 43%, or any value within the range of any two of the above values.

[0070] In some embodiments, the direction in which the first conductive region 10 points to the second conductive region 20 is referred to as the first direction. Please refer to the following document. Figure 2 The first direction is Figure 2 In the X direction, the length of the first conductive region 10 along the first direction is denoted as L1, and the length of the first sub-region 101 along the first direction is denoted as L2. L2 = 0.2L1~0.6L1. Specifically, L2 can be 0.2L1, 0.3L1, 0.4L1, 0.5L1, 0.6L1, or any value within the range of any two of the above values.

[0071] L1 = 20μm~40μm, and L1 can be 20μm, 25μm, 28μm, 30μm, 33μm, 36μm, 38μm, 40μm or any value within the range of any two of the above values.

[0072] L2 = 10μm~30μm, and L2 can specifically be 10μm, 12μm, 15μm, 18μm, 22μm, 25μm, 27μm, 30μm or any value within the range of any two of the above values.

[0073] In some implementations, please refer to [the relevant documentation]. Figure 2 The length of the second conductive region 20 along the first direction is denoted as L3, and the length of the third sub-region 201 along the first direction is denoted as L4. L4 = 0.2L3~0.6L3. Specifically, L4 can be 0.2L3, 0.3L3, 0.4L3, 0.5L3, 0.6L3, or any value within the range of any two of the above values.

[0074] L3 = 20μm~40μm. Specifically, L3 can be 20μm, 25μm, 28μm, 30μm, 33μm, 36μm, 38μm, 40μm, or any value within the range of any two of the above values.

[0075] L4 = 10μm~30μm. Specifically, L4 can be 10μm, 12μm, 15μm, 18μm, 22μm, 25μm, 27μm, 30μm, or any value within the range of any two of the above values.

[0076] This application controls the length ratio of the first sub-region 101 in the first conductive region 10 and the length ratio of the second sub-region 102 in the second conductive region 20, thereby reducing contact.

[0077] In some embodiments, the height of the third texture structure 15 is greater than the height of the first texture structure 11, and the height of the third texture structure 15 is 900nm~1500nm.

[0078] The third texture structure 15 of this application is disposed on the first surface of the semiconductor substrate 1, i.e. the front side, and the first texture structure 11 is disposed on the second surface of the semiconductor substrate 1, i.e. the back side. This application controls the height of the third texture structure 15 to be greater than the height of the first texture structure 11, and the height of the third texture structure 15 is 900nm~1500nm, which can reduce the reflectivity of the front side of the semiconductor substrate 1, enhance the light trapping effect of the first surface of the semiconductor substrate 1, and improve the utilization rate of sunlight.

[0079] In some embodiments, the material of the first passivation layer 2 includes at least one of hydrogen-containing silicon nitride, hydrogen-containing silicon oxynitride, hydrogen-containing silicon carbon oxynitride, and hydrogen-containing silicon carbon oxynitride.

[0080] In some embodiments, the material of the second passivation layer 3 includes at least one of hydrogen-containing silicon nitride, hydrogen-containing silicon oxynitride, hydrogen-containing silicon carbon oxynitride, and hydrogen-containing silicon carbon oxynitride.

[0081] Since the first sub-region 101 has a first texture structure 11 and the second sub-region 102 has a first polishing structure 12, and the bottom of the first texture structure 11 in the second sub-region 102 and the first sub-region 101 has a height difference, the thickness of the first passivation layer 2 in the first sub-region 101 and the second sub-region 102 is different; correspondingly, the thickness of the second passivation layer 3 in the third sub-region 201 and the fourth sub-region 202 is different.

[0082] In some embodiments, the thickness of the first passivation layer 2 located in the first sub-region 101 is 75nm to 85nm, specifically 75nm, 77nm, 79nm, 80nm, 82nm, 85nm, or any value within the range of any two of the above values.

[0083] In some embodiments, the thickness of the first passivation layer 2 located in the second sub-region 102 is 105nm to 115nm, specifically 105nm, 108nm, 110nm, 113nm, 115nm, or any value within the range of any two of the above values.

[0084] In some embodiments, the thickness of the second passivation layer 3 located in the third sub-region 201 is 75nm to 85nm, specifically 75nm, 77nm, 79nm, 80nm, 82nm, 85nm, or any value within the range of any two of the above values.

[0085] In some embodiments, the thickness of the second passivation layer 3 located in the fourth sub-region 202 is 105~115nm, specifically 105nm, 108nm, 110nm, 113nm, 115nm or any value within the range of any two of the above values.

[0086] In some implementations, please refer to [the relevant documentation]. Figure 1 The back contact solar cell 100 also includes a third passivation layer 4 located on the first surface of the semiconductor substrate 1. The third passivation layer 4 can reduce the minority carrier concentration on the first surface of the semiconductor substrate 1 by utilizing the passivation effect, suppress carrier recombination, thereby reducing the recombination rate on the first surface of the semiconductor substrate 1. At the same time, it can also reduce the series resistance and improve the electron transport capability.

[0087] In some embodiments, the material of the third passivation layer 4 includes at least one of hydrogen-containing silicon nitride, hydrogen-containing silicon oxynitride, hydrogen-containing silicon carbon oxynitride, and hydrogen-containing silicon carbon oxynitride. The third passivation layer 4 made of the above materials has excellent surface passivation properties.

[0088] In some embodiments, the thickness of the third passivation layer 4 is 10nm to 100nm, specifically 10nm, 20nm, 30nm, 42nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm or any value within the range of any two of the above values.

[0089] In some implementations, please refer to [the relevant documentation]. Figure 1 The back-contact solar cell 100 also includes an anti-reflection layer 5 located on the surface of the third passivation layer 4. The anti-reflection layer 5 is made of at least one of aluminum oxide, silicon nitride, and silicon oxynitride. The anti-reflection layer 5 can reduce the reflectivity of incident light on the front side of the back-contact solar cell 100 and improve the light utilization efficiency of the semiconductor substrate 1.

[0090] In some implementations, please refer to [the relevant documentation]. Figure 1 and Figure 2The back-contact solar cell 100 further includes a first electrode 6 located in a first conductive region 10 and a second electrode 7 located in a second conductive region 20. In some embodiments, the first electrode 6 penetrates the first passivation layer 2 and contacts at least a portion of the first textured structure 11, which helps to increase the contact area between the first electrode 6 and the semiconductor substrate 1, reduce contact resistance, and enhance the adhesion of the first electrode 6. The second electrode 7 penetrates the second passivation layer 3 and contacts at least a portion of the second textured structure 13, which helps to increase the contact area between the second electrode 7 and the semiconductor substrate 1, reduce contact resistance, and enhance the adhesion of the second electrode 7. In other embodiments, by processing the regions where the first passivation layer 2 and the second passivation layer 3 are located, the first electrode 6 does not penetrate the first passivation layer 2 and contacts at least a portion of the first textured structure 11; the second electrode 7 does not penetrate the second passivation layer 3 and contacts at least a portion of the first textured structure 11.

[0091] The first electrode 6 and the second electrode 7 are used to collect and summarize the current of the back-contact solar cell 100. It is understood that in some embodiments, the first electrode 6 and the second electrode 7 may not be provided on the rear surface of the back-contact solar cell 100.

[0092] In some embodiments, the metal paste used to prepare the first electrode 6 and the second electrode 7 can be one or more of aluminum, silver, gold, nickel, molybdenum or copper, and there is no limitation herein.

[0093] In some embodiments, the back contact solar cell 100 of this application is an IBC cell (Interdigitated Back Contact). The back contact solar cell 100 further includes: a first doped conductive layer in the first conductive region 10 and a second doped conductive layer in the second conductive region 20. The first doped conductive layer is located between the first passivation layer 2 and the semiconductor substrate 1, and the second doped conductive layer is located between the first passivation layer 2 and the semiconductor substrate 1. The doping elements of the first doped conductive layer and the doping elements of the second doped conductive layer have different conductivity types.

[0094] In some embodiments, the material of the first doped conductive layer includes at least one of polycrystalline semiconductor, amorphous semiconductor and microcrystalline semiconductor, and the doping element in the first doped conductive layer includes at least one of phosphorus, arsenic and tellurium; the material of the second doped conductive layer includes at least one of polycrystalline semiconductor, amorphous semiconductor and microcrystalline semiconductor, and the doping element in the second doped conductive layer includes at least one of boron, aluminum and gallium.

[0095] In some embodiments, the back contact solar cell 100 of this application is a TBC (Tunnel Oxide Passivated Contact Back Contact Cell). The back contact solar cell 100 further includes: a first tunneling layer and a third doped conductive layer sequentially stacked in the first conductive region 10, and / or a second tunneling layer and a fourth doped conductive layer located in the second conductive region 20.

[0096] In some embodiments, at least one of the first and second tunneling layers is made of at least one of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, and silicon oxynitride. At least one of the third and fourth doped conductive layers is made of at least one of polycrystalline semiconductors, amorphous semiconductors, and microcrystalline semiconductors, and the doping element in at least one of the third and fourth doped conductive layers includes at least one of phosphorus, arsenic, and tellurium.

[0097] In some embodiments, the back contact solar cell 100 of this application is an HBC (Tunnel Oxide Passivated Contact Back Contact Cell). The back contact solar cell 100 further includes: a first amorphous layer and a fifth doped conductive layer sequentially stacked in the first conductive region 10, and / or a second amorphous silicon layer and a six-doped conductive layer located in the second conductive region 20.

[0098] In some embodiments, at least one of the first and second amorphous silicon layers includes an amorphous silicon dielectric material. The first amorphous silicon layer may include an amorphous silicon material in which no doping elements have been actively introduced. For example, the amorphous silicon inevitably contains some doping elements (e.g., doping elements introduced during the fabrication of the fifth doped conductive layer diffuse into the first amorphous silicon layer, resulting in the first amorphous silicon layer containing the same doping elements), but this does not significantly alter the intrinsic conductivity of the amorphous silicon. In some embodiments, the amorphous silicon dielectric material may include one or more of amorphous silicon oxide, intrinsic amorphous silicon, amorphous silicon carbide, etc.

[0099] In some embodiments, the material of at least one of the fifth doped conductive layer and the sixth doped conductive layer includes at least one of doped amorphous silicon and doped microcrystalline silicon, and the doping element in at least one of the fifth doped conductive layer and the sixth doped conductive layer includes at least one of boron, aluminum and gallium.

[0100] Based on the same inventive concept, this application also provides a stacked battery 2000. Figure 12 For a schematic diagram of the tandem battery structure, please refer to [link / reference]. Figure 12The stacked solar cell 2000 includes a bottom cell 2002 and a top cell 2001 stacked sequentially along a preset direction; wherein the bottom cell 2002 includes the back-contact solar cell 100 provided in the above embodiments of the present invention. It should be noted that the stacked solar cell 2000 provided by the present invention has the technical effects of the back-contact solar cell 100 in the present invention, and the repeated parts will not be described again.

[0101] Based on the same inventive concept, this application also provides a photovoltaic module, which includes: A battery string is formed by connecting multiple back-contact solar cells or tandem cells prepared by the above-described preparation method. Encapsulation layer, which covers the surface of the battery string; Cover plate, used to cover the surface of the encapsulation layer away from the battery string.

[0102] Specifically, Figure 13 A schematic diagram of a photovoltaic module is shown below. Please refer to [link / reference]. Figure 13 The photovoltaic module 1000 includes a first cover plate 200, a first encapsulating layer 300, a solar cell string, a second encapsulating layer 400, and a second cover plate 500.

[0103] In some embodiments, the solar cell string includes multiple back-contact solar cells 100 or tandem cells 2000 as described above, connected by conductive strips. The connection between the back-contact solar cells 100 can be partial stacking or splicing. Similarly, the connection between the tandem cells 2000 can be partial stacking or splicing.

[0104] In some embodiments, the first cover plate 200 and the second cover plate 500 can be transparent or opaque covers, such as glass covers or plastic covers.

[0105] The first encapsulating adhesive layer 300 is in contact with and bonded to the first cover plate 200 and the battery string on both sides, respectively. The second encapsulating adhesive layer 400 is in contact with and bonded to the second cover plate 500 and the battery string on both sides, respectively. The first encapsulating adhesive layer 300 and the second encapsulating adhesive layer 400 can be ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene coelastomer (POE) film, or polyethylene terephthalate (PET) film, respectively.

[0106] The photovoltaic module 1000 can also be fully encapsulated on the sides, that is, the sides of the photovoltaic module 1000 are completely covered and encapsulated with encapsulating tape to prevent lamination shift during the lamination process.

[0107] The photovoltaic module 1000 also includes an edge sealing component, which is fixedly encapsulated on a portion of the edge of the photovoltaic module 1000. This edge sealing component can be fixedly encapsulated on the edge of the photovoltaic module 1000 near a corner. The edge sealing component can be a high-temperature resistant tape. This high-temperature resistant tape has excellent high-temperature resistance properties and will not decompose or detach during lamination, ensuring reliable encapsulation of the photovoltaic module 1000. The two ends of the high-temperature resistant tape are respectively fixed to the second cover plate 500 and the first cover plate 200. The two ends of the high-temperature resistant tape can be bonded to the second cover plate 500 and the first cover plate 200 respectively, while the middle portion can limit the side of the photovoltaic module 1000, preventing lamination displacement of the photovoltaic module 1000 during the lamination process.

[0108] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A back-contact solar cell, characterized in that, include: A semiconductor substrate having a first surface and a second surface disposed opposite to each other; The second surface of the semiconductor substrate is provided with alternating first and second conductive regions. Within the first conductive region, the second surface of the semiconductor substrate has a first sub-region and a second sub-region located on both sides of the first sub-region. The first sub-region is provided with a plurality of first texture structures, and the second sub-region is provided with a plurality of first polishing structures. The second sub-region protrudes in a direction away from the first surface relative to the first sub-region. The distance between the bottom of the first texture structure in the second sub-region and the first sub-region is 2μm~5μm. Within the second conductive region, the second surface of the semiconductor substrate has a third sub-region and a fourth sub-region located on both sides of the third sub-region. The third sub-region is provided with a plurality of second texture structures, and the fourth sub-region is provided with a plurality of second polishing structures. The fourth sub-region protrudes in a direction away from the first surface relative to the third sub-region. The distance between the bottom of the second texture structure in the fourth sub-region and the third sub-region is 2μm~5μm. A first passivation layer and a first electrode are disposed within the first conductive region; A second passivation layer and a second electrode are disposed within the second conductive region.

2. The back-contact solar cell according to claim 1, characterized in that, The back-contact solar cell further includes a third texture structure disposed on the first surface of the semiconductor substrate, wherein the texture coverage of the first surface of the semiconductor substrate is greater than the texture coverage of the first sub-region, and the texture coverage of the first surface of the semiconductor substrate is greater than the texture coverage of the third sub-region.

3. The back-contact solar cell according to claim 2, characterized in that, The texture coverage α of the first sub-region satisfies 70% ≤ α < 100%, and the texture coverage β of the third sub-region satisfies 70% ≤ β < 100%.

4. The back-contact solar cell according to claim 1, characterized in that, A first sidewall is provided between the first sub-region and the second sub-region, and a plurality of fourth texture structures are provided in the first sidewall; A second sidewall exists between the third sub-region and the fourth sub-region, and multiple fifth texture structures are provided within the second sidewall.

5. The back-contact solar cell according to claim 4, characterized in that, At least one of the fourth and fifth texture structures includes at least one of cylindrical and prismatic shapes.

6. The back-contact solar cell according to claim 4, characterized in that, The fourth texture structure includes a first end and a second end disposed opposite to each other, the first end extending into the first sub-region and the second end extending into the second sub-region; The fifth texture structure includes a third end and a fourth end that are disposed opposite to each other, the third end extending into the third sub-region and the fourth end extending into the fourth sub-region.

7. The back-contact solar cell according to claim 1, characterized in that, The height of the first texture structure is greater than or equal to the height of the second texture structure; The one-dimensional dimension of the bottom surface of the first texture structure is greater than or equal to the one-dimensional dimension of the bottom surface of the second texture structure.

8. The back-contact solar cell according to claim 7, characterized in that, The height of the first texture structure is 300nm~900nm; The height of the second texture structure is 250nm~850nm; The bottom surface of the first texture structure has a one-dimensional dimension of 2.0μm~3.5μm; The bottom surface of the second texture structure has a one-dimensional dimension of 1.3μm to 2.0μm.

9. The back-contact solar cell according to claim 1, characterized in that, The first polishing structure has a one-dimensional dimension of 5μm to 20μm, and the second polishing structure has a one-dimensional dimension of 3μm to 18μm.

10. The back-contact solar cell according to claim 1, characterized in that, The morphology of at least one of the first texture structure and the second texture structure includes at least one of pyramids and pyramid-like structures.

11. The back-contact solar cell according to claim 10, characterized in that, The included angle at the top of at least one of the first texture structure and the second texture structure is 90° to 120°.

12. The back-contact solar cell according to claim 1, characterized in that, The reflectivity of the first sub-region is 12%~18%, the reflectivity of the second sub-region is 35%~40%, the reflectivity of the third sub-region is 13%~20%, and the reflectivity of the fourth sub-region is 37%~43%.

13. The back-contact solar cell according to claim 1, characterized in that, The length of the first conductive region along the first direction is denoted as L1, and the length of the first sub-region along the first direction is denoted as L2, where L2 = 0.2L1~0.6L1; The length of the second conductive region along the first direction is denoted as L3, and the length of the third sub-region along the first direction is denoted as L4, where L4 = 0.2L3~0.6L3, and the first direction points from the first conductive region to the second conductive region.

14. The back-contact solar cell according to claim 13, characterized in that, L1=20μm~40μm, L2=10μm~30μm, L3=20μm~40μm, L4=10μm~30μm.

15. The back-contact solar cell according to claim 2, characterized in that, The height of the third texture structure is greater than the height of the first texture structure, and the height of the third texture structure is 900nm~1500nm.

16. The back-contact solar cell according to claim 1, characterized in that, The thickness of the first passivation layer located in the first sub-region is 75nm~85nm, and the thickness of the first passivation layer located in the second sub-region is 105~115nm; and / or The thickness of the second passivation layer located in the third sub-region is 75nm~85nm, and the thickness of the second passivation layer located in the fourth sub-region is 105nm~115nm.

17. A stacked battery, characterized in that, The stacked battery includes a top battery and a bottom battery stacked together, wherein the bottom battery is a back-contact solar cell as described in any one of claims 1 to 16.

18. A photovoltaic module, characterized in that, The photovoltaic module includes: A battery string, wherein the battery string is formed by connecting multiple solar cells as described in any one of claims 1 to 16 or stacked cells as described in claim 17; An encapsulation layer that covers the surface of the battery string; A cover plate for covering the surface of the encapsulation layer away from the battery string.

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