Visible light chip and infrared chip integrated wafer-level packaging structure and packaging method

Abstract

The invention discloses a visible light chip and infrared chip integrated wafer level packaging structure and a packaging method. The structure comprises a visible light wafer, an infrared wafer and a deep cavity frame wafer between the visible light wafer and the infrared wafer. The visible light wafer comprises a plurality of visible light chips capable of transmitting infrared spectrum; the deep cavity frame wafer comprises a plurality of deep cavity frame chips; each deep-cavity frame chip is of a hollow enclosure-shaped structure and comprises a deep-cavity frame, a connecting structure and a getter; the infrared wafer comprises a plurality of infrared chips; all visible light chips of the visible light wafer, all deep cavity frame chips of the deep cavity frame wafer and all infrared chips of the infrared wafer are in one-to-one correspondence, and each deep cavity frame chip, the corresponding visible light chip and the corresponding infrared chip form a vacuum chamber through two times of anodic bonding. Bonding alignment is facilitated, useless structures are removed in the subsequent scribing process, and efficient and low-cost integration is achieved through wafer-level vacuum packaging.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a wafer-level packaging structure and packaging method for integrating visible light chips and infrared chips. Background Technology

[0002] Currently, both visible light and infrared chips are limited in their application scenarios and scope due to the constraints of their spectral range. Ultra-wideband (UWB) chip integration combines the functions of both, solving these problems and improving their performance.

[0003] However, designing both visible light and infrared array structures in parallel on a single-layer chip significantly increases both the design and manufacturing complexity. Stacking and integrating visible light and infrared chips, on the other hand, is an effective method that is easier to mass-produce.

[0004] In the design of the stacked structure, it is necessary to consider how the visible light chip and the infrared chip can effectively receive the spectrum of their respective ranges.

[0005] Stacked packaging of single chips is inefficient and costly. How to form a vacuum chamber and how to achieve wafer-level stacked packaging of visible light and infrared chips are technical problems that urgently need to be solved by those skilled in the art.

[0006] The high vacuum requirement of infrared chips necessitates that the packaging equipment can achieve and maintain a high vacuum, as well as high-temperature exhaust and getter activation. However, the impact of excessively high temperatures on the performance of sensitive materials limits the packaging temperature.

[0007] Therefore, how to facilitate bonding and alignment while also removing unwanted structures during subsequent dicing, and how to achieve efficient and low-cost integration of visible light and infrared chips through wafer-level vacuum packaging, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0008] In view of the above-mentioned deficiencies of the prior art, the present invention provides a wafer-level packaging structure and packaging method for integrating visible light chips and infrared chips. The purpose is to facilitate bonding and alignment, as well as the removal of useless structures during subsequent dicing. The wafer-level vacuum packaging achieves efficient and low-cost integration of visible light chips and infrared chips.

[0009] To achieve the above objectives, the present invention discloses a wafer-level packaging structure integrating a visible light chip and an infrared chip, comprising a visible light wafer and an infrared wafer, wherein a deep cavity frame wafer is disposed between the visible light wafer and the infrared wafer;

[0010] The visible light wafer is an anode wafer that has undergone visible light processing and contains several visible light chips that can transmit the infrared spectrum;

[0011] The deep cavity frame wafer is a cathode wafer that completes the deep cavity process and contains several deep cavity frame chips.

[0012] Each of the aforementioned deep cavity frame chips includes a deep cavity frame, a connection structure, and a getter;

[0013] Each of the aforementioned deep cavity frames is a hollow wall-shaped structure;

[0014] Each pair of adjacent deep cavity frames is connected by a grooved connection structure;

[0015] The infrared wafer is an anode wafer that has undergone infrared processing and contains several infrared chips;

[0016] All the visible light chips of the visible light wafer, all the deep cavity frame chips of the deep cavity frame wafer, and all the infrared chips of the infrared wafer are in one-to-one correspondence with each other, and each deep cavity frame chip forms a vacuum chamber with the corresponding visible light chip and the corresponding infrared chip through two anodic bonding processes.

[0017] Before the first anodic bonding, the first side of the deep cavity frame wafer facing the visible light wafer is aligned and positioned with the corresponding back side of the visible light wafer through corresponding pillar-hole, tenon-groove or protrusion-groove structures. After covering the surface of the deep cavity frame wafer with a conductive wafer or conductive mold, it is fixed with a wafer-level bonding fixture, and a termination current of not less than 2mA is set in the first anodic bonding.

[0018] After the first anodic bonding is completed, the second side of the deep cavity frame wafer facing the visible light wafer is aligned with the corresponding side of the infrared wafer using a positioning machine, and fixed with a wafer-level bonding fixture. Then, the upper and lower electrodes are used to control the temperature to complete the degassing, activation of the getter, and the second anodic bonding.

[0019] Preferably, a thin film of the getter is prepared on the inner sidewall of each of the deep cavity frames.

[0020] Preferably, both anodic bonding operations are performed using a voltage not exceeding 600V and a limited upper current.

[0021] Preferably, a plurality of the visible light chips are arranged in an array structure on the visible light wafer, and on the outer side of the visible light wafer facing away from the deep cavity frame wafer, there are scribe lines forming a rectangular frame structure around the perimeter.

[0022] The lane marking area is the area outside the rectangular lane marking lines, that is, the gap area formed by the frames of adjacent lane marking lines.

[0023] On the back side of the visible light wafer facing the deep cavity framework wafer, there are bonding areas with a "well" shaped frame structure around the perimeter;

[0024] Each of the aforementioned visible light chips includes a visible light functional region and a visible light non-functional region;

[0025] Each of the aforementioned visible light non-functional regions is used for infrared spectrum transmission;

[0026] Each of the aforementioned visible light functional regions is used to detect and process the visible light spectrum;

[0027] The infrared chips in the stacked structure corresponding to each of the visible light chips are used to detect and process the infrared spectrum that penetrates the visible light chips.

[0028] More preferably, the visible light array structure in which a plurality of the visible light chips are arranged in an array on the visible light wafer has a period of 1.5 μm to 3.0 μm;

[0029] The area ratio of the visible light functional region to the visible light non-functional region in each of the visible light chips is 1:6;

[0030] The first side of the deep cavity frame wafer facing the visible light wafer is aligned and positioned with the corresponding back side of the visible light wafer by at least two pairs of corresponding pillar-hole, tenon-groove, or protrusion-groove structures.

[0031] Preferably, the grooved connection structures are all located on the second side of the deep cavity frame wafer facing the visible light wafer.

[0032] Preferably, the manufacturing process of the deep cavity framework wafer includes the following steps:

[0033] Step A1: Scan along the edge of each of the deep cavity frames with a pulsed laser to form spaced modified micropores, making them easier to etch;

[0034] Step A2: Clean the wafer to remove dust and particles generated during laser scanning;

[0035] Step A3: Align the first and second sides of the deep cavity framework wafer with photolithography.

[0036] Step A4: Wet etching, etching through all areas with the modified micropores, leaving the corresponding deep cavity frame;

[0037] Simultaneously, the pillar-hole, tenon-groove, or protrusion-groove structures required for positioning are etched onto the first surface of the deep cavity frame wafer.

[0038] Furthermore, the grooved connection structure is etched into the second surface of the deep cavity frame wafer;

[0039] Step A5: Remove adhesive and clean.

[0040] Step A6: Use a mask to block the upper and lower surfaces of the deep cavity framework wafer, and deposit a thin film of getter on the sidewall of the deep cavity framework wafer;

[0041] Step A7: Clean the wafer.

[0042] This invention also provides a packaging method for a wafer-level packaging structure integrating visible light chips and infrared chips, comprising the following steps:

[0043] Step B1: Position the visible light wafer with the back side facing the deep cavity frame wafer facing upwards, and the first side of the deep cavity frame wafer facing downwards, so that the first side of the deep cavity frame wafer and the back side of the visible light wafer are aligned and positioned through corresponding pillar-hole, tenon-groove or protrusion-groove structures.

[0044] Then, a conductive wafer or conductive mold is placed over the second side of the deep cavity frame wafer and fixed with a wafer-level bonding fixture;

[0045] The deep cavity frame wafer and the visible light wafer, which are fixed by the wafer-level bonding fixture, are introduced into the bonding chamber. The bonding temperature is set to be lower than the getter activation temperature and the temperature that the visible light chip can withstand. Pressure and voltage are applied, and the termination current is set to be lower than the upper limit current and not lower than 2mA to complete the first anodic bonding.

[0046] Step 2: Align the deep cavity frame wafer that has completed the first anodic bonding with the second side of the deep cavity frame wafer and the corresponding side of the infrared wafer in the visible light wafer using an alignment machine, and then isolate and fix it with the isolation plate and pressure claw on the wafer-level bonding fixture;

[0047] The deep cavity framework wafer, the visible light wafer, and the infrared wafer, which are fixed by the wafer-level bonding fixture, are then introduced into the bonding chamber.

[0048] The lower electrode of the bonding machine is brought into contact with the infrared wafer, and the temperature is set below the temperature that the infrared chip can withstand.

[0049] The upper electrode plate of the bonding machine is kept at a certain distance from the visible light chip, and a relatively high temperature is set so that the temperature radiated to the visible light chip is lower than the activation temperature of the getter and the temperature that the visible light chip can withstand, thus completing the degassing process.

[0050] Keep the temperature of the lower electrode plate constant and raise the temperature of the upper electrode plate so that the temperature radiated to the visible light chip is higher than the activation temperature of the getter but lower than the temperature that the visible light chip can withstand, thus completing the activation of the getter.

[0051] Lower the temperature of the upper electrode to the same temperature as the lower electrode, remove the isolation sheet on the wafer-level bonding fixture, so that the second side of the deep cavity frame wafer contacts the corresponding bonding area of ​​the infrared wafer, and lower the upper electrode to contact the front side of the visible light wafer, and apply heat, pressure and voltage to complete the second anodic bonding;

[0052] The end current is set as the end mark of the second anodic bonding. The set value is lower than the upper limit current and lower than the end current of the first anodic bonding, specifically 0.5mA to 1mA.

[0053] After the second anodic bonding, the second side of the deep cavity frame wafer forms a gap with the scribe line region of the corresponding side of the infrared wafer through a grooved connection structure;

[0054] Step 3: Draw the scribe line from the front side of the visible light wafer to the bottom of the groove of the deep cavity frame wafer, so that the connection between the visible light chip and the deep cavity frame chip is independent.

[0055] Remove the independent connection between the visible light chip and the deep cavity frame chip to expose the dicing path of the infrared wafer, and then scribe through the dicing mark line in the middle of the infrared chip to obtain a single effective chip;

[0056] Each of the effective chips is a visible light chip and an infrared chip connected through the deep cavity frame chip, and a vacuum chamber is formed between each deep cavity frame chip and the corresponding infrared chip.

[0057] Preferably, in step 1, the anode bonding voltage is -200V to -600V, the upper limit of the current is 3mA to 15mA, and the termination current is 2mA; in step 2, the anode bonding voltage is -200V to -600V, and the absolute value of the voltage is higher than the absolute value of the first anode bonding voltage, preferably 100V to 200V higher, the upper limit of the current is 3mA to 15mA, and the termination current is 0.5mA to 1mA.

[0058] More preferably, in step 1, the anode bonding voltage is -300V to -500V and the upper limit of the current is 5mA to 8mA; in step 2, the anode bonding voltage is -300V to -500V and the upper limit of the current is 5mA to 8mA.

[0059] The beneficial effects of this invention are:

[0060] This invention facilitates bonding and alignment, as well as the removal of unwanted structures during subsequent dicing processes, enabling efficient and low-cost integration of visible light and infrared chips through wafer-level vacuum packaging.

[0061] This invention makes the infrared chip slightly larger than the visible light chip, which facilitates the separate wiring; the getter is prepared on the side wall of the deep cavity frame, which does not occupy the effective area of ​​the visible light chip and the infrared chip, saving space, and the getter is distributed more widely and evenly, which is beneficial to vacuum maintenance.

[0062] The unique bonding process of this invention fully activates the getter while avoiding affecting the core functions of the visible light wafer and the infrared wafer.

[0063] The following will further explain the concept, specific structure, and technical effects of the present invention in conjunction with the accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Attached Figure Description

[0064] Figure 1 A schematic diagram of the structure of an embodiment of the present invention is shown, and Figure 2 Schematic diagram of the cross-sectional structure along the AA direction.

[0065] Figure 2 This invention is shown Figure 1 Schematic diagram of the CC-direction structure.

[0066] Figure 3 This invention is shown Figure 2 Schematic diagram of the BB-shaped structure.

[0067] Figure 4 A schematic diagram of the front structure of a visible light wafer is shown in one embodiment of the present invention.

[0068] Figure 5 A schematic diagram of the back side structure of a visible light wafer is shown in one embodiment of the present invention.

[0069] Figure 6 This diagram illustrates the structure of the second side of a deep cavity frame wafer in one embodiment of the present invention.

[0070] Figure 7 This invention is shown Figure 6 A magnified view of a portion of point D in the middle.

[0071] Figure 8 This invention is shown Figure 6 A magnified view of a portion of point E in the middle.

[0072] Figure 9 This invention is shown Figure 6 Schematic diagram of the HH-direction structure.

[0073] Figure 10 A schematic diagram of an infrared wafer structure is shown in one embodiment of the present invention.

[0074] Figure 11 This diagram illustrates the wafer position during the venting and activation process in the second bonding step according to an embodiment of the present invention.

[0075] Figure 12 This diagram illustrates the wafer position during the second bonding process in one embodiment of the present invention.

[0076] Figure 13 The diagram shows the temperature and pressure curves of the second bonding process in one embodiment of the present invention.

[0077] Figure 14 A schematic diagram of voltage and current curves is shown in one embodiment of the present invention.

[0078] Figure 15 This diagram illustrates a single chip structure after wafer-level packaging and dicing in one embodiment of the present invention.

[0079] Figure 16 A schematic diagram of the FF-direction structure in the present invention 15 is shown.

[0080] Figure 17 A schematic diagram of the GG-oriented structure in the present invention is shown. Detailed Implementation

[0081] Example

[0082] like Figures 1 to 12 ,and Figures 15 to 17 As shown, the wafer-level packaging structure integrating visible light and infrared chips includes a visible light wafer 1 and an infrared wafer 3; a deep cavity frame wafer 2 is provided between the visible light wafer 1 and the infrared wafer 3.

[0083] Visible light wafer 1 is an anode wafer that completes visible light processing and contains several visible light chips 19 that can transmit infrared spectrum;

[0084] The deep cavity frame wafer 2 is a cathode wafer that completes the deep cavity process and contains several deep cavity frame chips 29;

[0085] Each deep cavity frame chip 29 includes a deep cavity frame 24, a connection structure 23, and a getter 21;

[0086] Each deep cavity frame 24 is a hollow wall-shaped structure;

[0087] Each pair of adjacent deep cavity frames 24 are connected by a grooved connection structure 23;

[0088] Infrared wafer 3 is an anode wafer that completes the infrared process and contains several infrared chips 31;

[0089] All visible light chips 19 of visible light wafer 1, all deep cavity frame chips 29 of deep cavity frame wafer 2, and all infrared chips 31 of infrared wafer 3 correspond to each other one-to-one, and each deep cavity frame chip 29 forms a vacuum chamber 9 with the corresponding visible light chip 19 and the corresponding infrared chip 31 through two anodic bonding processes.

[0090] Before the first anodic bonding, the deep cavity frame wafer 2 is aligned and positioned with the first side of the visible light wafer 1 and the corresponding back side 12 of the visible light wafer 1 through the corresponding pillar-hole, tenon-groove or protrusion-groove structure 22. After covering the surface of the deep cavity frame wafer 2 with a conductive wafer or conductive mold, it is fixed with a wafer-level bonding fixture, and a termination current of not less than 2mA is set in the first anodic bonding.

[0091] After the first anodic bonding is completed, the second side of the deep cavity frame wafer 2 facing the visible light wafer 1 and the corresponding side of the infrared wafer 3 are aligned by an alignment machine, fixed by a wafer-level bonding fixture, and then the upper electrode plate 41 and the lower electrode plate 42 are used to control the temperature to complete the exhaust, activation of the getter 21 and the second anodic bonding.

[0092] In practical applications, temperature control via the upper electrode 41 and the lower electrode 42 can ensure chip performance while completing degassing, getter 21 activation, and second anodic bonding.

[0093] After two anodic bonding processes, each effective chip on the wafer stacked together consists of a visible light chip 19 and an infrared chip 31 connected by a deep cavity frame chip 29, with a vacuum chamber 9 formed between the three.

[0094] In some embodiments, a thin film of getter 21 is prepared on the inner sidewall of each deep cavity frame 24.

[0095] In some embodiments, both anodic bonding operations are performed using a voltage not exceeding 600V and with a limited upper current limit.

[0096] In some embodiments, a plurality of visible light chips 19 are arranged in an array structure on the visible light wafer 1, and on the outer side of the visible light wafer 1, which faces away from the deep cavity frame wafer 2, there are scribing marking lines in a rectangular frame structure around the perimeter.

[0097] The zone 15 is the area outside the rectangular zone marking lines, that is, the gap area formed by the frames of adjacent zone marking lines.

[0098] On the outer side of the visible light wafer 1 facing the deep cavity frame wafer 2, there are bonding areas 16 arranged in a "well" shaped frame structure around the perimeter.

[0099] Each visible light chip 19 includes a visible light functional area 13 and a visible light non-functional area 14;

[0100] Each visible light non-functional region 14 is used for infrared spectrum transmission;

[0101] Each visible light functional region 13 is used to detect and process the visible light spectrum;

[0102] The infrared chips 31 in the stacked structure corresponding to each visible light chip 19 are used to detect and process the infrared spectrum that passes through the visible light chip 19.

[0103] In some embodiments, the visible light array structure with a period of 1.5 μm to 3.0 μm is formed by arranging a plurality of visible light chips 19 in an array structure on a visible light wafer 1.

[0104] The period of the visible light array structure arranged in an array structure mentioned above refers to the period of the array structure inside each visible light chip;

[0105] In practical applications, visible light array structures with a period of 2.1μm to 2.4μm have better periodicity;

[0106] The area ratio of the visible light functional region 13 to the visible light non-functional region 14 in each visible light chip 19 is preferably 1:6.

[0107] The deep cavity frame wafer 2 is aligned and positioned with the first face of the visible light wafer 1 and the corresponding back face 12 of the visible light wafer 1 through at least two pairs of corresponding pillar-hole, tenon-groove or protrusion-groove structures 22.

[0108] In practical applications, the two pairs of corresponding pillar-hole, tenon-groove or protrusion-groove structures 22 are all set in the outer region of the deep cavity frame wafer 2 facing the visible light wafer 1, and are distributed in different regions of the deep cavity frame wafer 2 facing the visible light wafer 1.

[0109] In some embodiments, the grooved connection structure 23 is located on the second side of the deep cavity frame wafer 2 facing the visible light wafer 1.

[0110] In some embodiments, the manufacturing process of the deep cavity framework wafer 2 includes the following steps:

[0111] Step A1: Scan along the edge of each deep cavity frame 24 with a pulsed laser to form spaced modified small holes, making them easier to etch;

[0112] Step A2: Clean the wafer to remove dust and particles generated during laser scanning;

[0113] Step A3: Align the first and second sides of the deep cavity frame wafer 2 with the photolithography.

[0114] Step A4: Wet etching, etching through all areas with modified micropores, leaving the corresponding deep cavity frame 24;

[0115] Simultaneously, the pillar-hole, tenon-groove, or protrusion-groove structures 22 required for positioning are etched on the first surface of the deep cavity framework wafer 2.

[0116] Furthermore, a connection structure 23 containing grooves is etched on the second surface of the deep cavity framework wafer 2;

[0117] Step A5: Remove adhesive and clean.

[0118] Step A6: Use a mask to block the upper and lower surfaces of the deep cavity framework wafer 2, and deposit a thin film of getter 21 on the sidewall of the deep cavity framework wafer 2.

[0119] Step A7: Clean the wafer.

[0120] like Figures 11 to 14 As shown, the present invention also provides a packaging method for a wafer-level packaging structure integrating a visible light chip and an infrared chip, comprising the following steps:

[0121] Step 1: With the visible light wafer 1 facing upwards and the back side 12 of the deep cavity frame wafer 2 facing downwards, align and position the first side of the deep cavity frame wafer 2 with the back side 12 of the visible light wafer 1 through the corresponding pillar-hole, tenon-groove or protrusion-groove structure 22.

[0122] Next, a conductive wafer or conductive mold is placed over the second side of the deep cavity frame wafer 2 and fixed with a wafer-level bonding fixture;

[0123] The deep cavity frame wafer 2, which is fixed by a wafer-level bonding fixture, and the visible light wafer 1 are introduced into the bonding chamber. The bonding temperature is set to be lower than the activation temperature of the getter 21 and the temperature that the visible light chip 19 can withstand. Pressure and voltage are applied, and the termination current is set to be lower than the upper limit current and not lower than 2mA to complete the first anodic bonding.

[0124] like Figure 14 As shown, the upper limit current is the peak value of the current during the bonding process to prevent the bonding from being completed too quickly and forming defects, and to prevent excessive current from damaging the microstructure. After the set upper limit current is maintained for a period of time, the set voltage is reached, and the bonding current begins to gradually decrease. When it drops to the set end current, the power is automatically cut off and the process is terminated.

[0125] Step 2: Align the deep cavity frame wafer 2, which has completed the first anodic bonding, with the second side of the deep cavity frame wafer 2 in the visible light wafer 1 and the corresponding side of the infrared wafer 3 using an alignment machine, and then isolate and fix it using the isolation plate 43 on the wafer-level bonding fixture and the clamping claw.

[0126] The deep cavity framework wafer 2, visible light wafer 1, and infrared wafer 3, which are fixed by a wafer-level bonding fixture, are then introduced into the bonding chamber.

[0127] The lower electrode plate 42 of the bonding machine is brought into contact with the infrared wafer 3, and a lower temperature than that that the infrared chip 31 can withstand is set.

[0128] The upper electrode plate 41 of the bonding machine is kept at a certain distance from the visible light chip 19, and a relatively high temperature is set so that the temperature radiated to the visible light chip 19 is lower than the activation temperature of the getter 21 and the temperature that the visible light chip 19 can withstand, thus completing the degassing.

[0129] Keep the temperature of the lower electrode plate 42 constant and raise the temperature of the upper electrode plate 41 so that the temperature radiated to the visible light chip 19 is higher than the activation temperature of the getter 21 and lower than the temperature that the visible light chip 19 can withstand, thus completing the activation of the getter 21.

[0130] Lower the temperature of the upper electrode plate 41 to the same temperature as the lower electrode plate 42, remove the isolation sheet 43 on the wafer-level bonding fixture, so that the second side of the deep cavity frame wafer 2 contacts the corresponding bonding area 16 of the infrared wafer 3, and lower the upper electrode plate 41 to contact the front side 11 of the visible light wafer 1, and apply heat, pressure and voltage to complete the second anodic bonding.

[0131] Set the termination current to be lower than the upper limit current, with a preferred value of 0.5mA to 1mA;

[0132] After the second anodic bonding, the second surface of the deep cavity frame wafer 2 forms a gap with the bonding region 16 of the corresponding side of the infrared wafer 3 through the grooved connection structure 23;

[0133] Step 3: Draw the scribe line from the front side 11 of the visible light wafer 1 to the bottom of the groove of the deep cavity frame wafer 2, which are bonded together as a whole, so that the connection between the visible light chip 19 and the deep cavity frame chip 29 is independent.

[0134] Remove the independent connection between the visible light chip 19 and the deep cavity frame chip 29 to expose the dicing path of the infrared wafer 3, and then scribe through the dicing mark line in the middle of the infrared chip 31 to obtain a single effective chip.

[0135] Each effective chip is a visible light chip 19 and an infrared chip 31 connected by a deep cavity frame chip 29, and a vacuum chamber 9 is formed between each deep cavity frame chip 29 and the corresponding infrared chip 31.

[0136] In some embodiments, in step 1, the anode bonding voltage is -200V to -600V, the upper limit of the current is 3mA to 15mA, and the termination current is 2mA; in step 2, the anode bonding voltage is -200V to -600V, and the absolute value of the voltage is higher than the absolute value of the first anode bonding voltage, preferably 100V to 200V higher, the upper limit of the current is 3mA to 15mA, and the termination current is 0.5mA to 1mA.

[0137] In some embodiments, in step 1, the anode bonding voltage is -300V to -500V and the upper limit of the current is 5mA to 8mA; in step 2, the anode bonding voltage is -300V to -500V and the upper limit of the current is 5mA to 8mA.

[0138] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A wafer-level packaging structure integrating a visible light chip and an infrared chip, comprising a visible light wafer (1) and an infrared wafer (3); characterized in that, A deep cavity frame wafer (2) is provided between the visible light wafer (1) and the infrared wafer (3); The visible light wafer (1) is an anode wafer that has completed the visible light process and contains several visible light chips (19) that can transmit the infrared spectrum; The deep cavity frame wafer (2) is a cathode wafer that completes the deep cavity process and contains several deep cavity frame chips (29); Each of the deep cavity frame chips (29) includes a deep cavity frame (24), a connection structure (23), and a getter (21); Each of the aforementioned deep cavity frames (24) is a hollow wall-shaped structure; Each pair of adjacent deep cavity frames (24) are connected by a grooved connection structure (23); The infrared wafer (3) is an anode wafer that has completed infrared processing and contains several infrared chips (31); All the visible light chips (19) of the visible light wafer (1), all the deep cavity frame chips (29) of the deep cavity frame wafer (2), and all the infrared chips (31) of the infrared wafer (3) correspond to each other one by one, and each deep cavity frame chip (29) forms a vacuum chamber (9) with the corresponding visible light chip (19) and the corresponding infrared chip (31) through two anodic bonding. Before the first anodic bonding, the first side of the deep cavity frame wafer (2) facing the visible light wafer (1) is aligned and positioned with the corresponding back side (12) of the visible light wafer (1) through the corresponding pillar-hole, tenon-groove or protrusion-groove structure (22). After covering the surface of the deep cavity frame wafer (2) with a conductive wafer or conductive mold, it is fixed with a wafer-level bonding fixture, and a termination current of not less than 2mA is set in the first anodic bonding. After the first anodic bonding is completed, the second side of the deep cavity frame wafer (2) facing the visible light wafer (1) and the corresponding side of the infrared wafer (3) are aligned by a positioning machine, fixed by a wafer-level bonding fixture, and then the temperature is controlled by the upper electrode plate (41) and the lower electrode plate (42) respectively to complete the degassing, activation of the getter (21) and the second anodic bonding.

2. The wafer-level packaging structure integrating a visible light chip and an infrared chip according to claim 1, characterized in that, A thin film of the getter (21) is prepared on the inner wall of each of the deep cavity frames (24).

3. The wafer-level packaging structure integrating a visible light chip and an infrared chip according to claim 1, characterized in that, Both anodic bonding operations were performed using a voltage not exceeding 600V and with a limited upper current limit.

4. The wafer-level packaging structure integrating a visible light chip and an infrared chip according to claim 1, characterized in that, A number of visible light chips (19) are arranged in an array on the visible light wafer (1), and on the outside of the visible light wafer (1) facing away from the deep cavity frame wafer (2), there are dicing marking lines in a rectangular frame structure surrounding the dicing area (15). The marking area (15) is the area outside the rectangular marking lines, that is, the gap area formed by the frames of adjacent marking lines; On the outer side of the visible light wafer (1) facing the deep cavity frame wafer (2), there are bonding areas (16) arranged in a "well" shaped frame structure around the perimeter. Each of the visible light chips (19) includes a visible light functional region (13) and a visible light non-functional region (14); Each of the aforementioned visible light non-functional regions (14) is used for infrared spectral penetration; Each of the visible light functional regions (13) is used to detect and process the visible light spectrum; The infrared chip (31) in the stacked structure corresponding to each of the visible light chips (19) is used to detect and process the infrared spectrum that passes through the visible light chip (19).

5. The wafer-level packaging structure integrating a visible light chip and an infrared chip according to claim 4, characterized in that, The visible light chips (19) arranged in an array on the visible light wafer (1) have a visible light array structure period of 1.5 μm to 3.0 μm; The area ratio of the visible light functional region (13) to the visible light non-functional region (14) of each visible light chip (19) is 1:6; The deep cavity frame wafer (2) is aligned and positioned with the first side of the visible light wafer (1) facing the visible light wafer (1) and the corresponding back side (12) of the visible light wafer (1) by at least two pairs of corresponding pillar-hole, tenon-groove or protrusion-groove structures (22).

6. The wafer-level packaging structure integrating a visible light chip and an infrared chip according to claim 1, characterized in that, The grooved connection structure (23) is located on the second side of the deep cavity frame wafer (2) facing the visible light wafer (1).

7. The wafer-level packaging structure integrating a visible light chip and an infrared chip according to claim 1, characterized in that, The manufacturing process of the deep cavity framework wafer (2) includes the following steps: Step A1: Scan along the edge of each of the deep cavity frames (24) with a pulsed laser to form spaced modified small holes, making them easier to etch; Step A2: Clean the wafer to remove dust and particles generated during laser scanning; Step A3: Align the first and second surfaces of the deep cavity frame wafer (2) with the photolithography. Step A4: Wet etching, etching through all areas with the modified micropores, leaving the corresponding deep cavity frame (24); Simultaneously, the pillar-hole, tenon-groove, or protrusion-groove structure (22) required for positioning is etched on the first surface of the deep cavity frame wafer (2). Furthermore, the grooved connection structure (23) is etched on the second surface of the deep cavity frame wafer (2); Step A5: Remove adhesive and clean. Step A6: Use a mask to cover the upper and lower surfaces of the deep cavity frame wafer (2), and deposit a thin film of getter (21) on the sidewall of the deep cavity frame wafer (2); Step A7: Clean the wafer.

8. A packaging method for a wafer-level packaging structure integrating a visible light chip and an infrared chip, characterized in that, Includes the following steps: Step 1: Place the visible light wafer (1) with the back side (12) of the deep cavity frame wafer (2) facing upwards, and the first side of the deep cavity frame wafer (2) facing downwards, so that the first side of the deep cavity frame wafer (2) and the back side (12) of the visible light wafer (1) are aligned and positioned by corresponding pillar-hole, tenon-groove or protrusion-groove structure (22); Then, a conductive wafer or conductive mold is placed over the second side of the deep cavity frame wafer (2) and fixed with a wafer-level bonding fixture; The deep cavity frame wafer (2) and the visible light wafer (1) fixed by the wafer-level bonding fixture are introduced into the bonding chamber. The bonding temperature is set to be lower than the activation temperature of the getter (21) and the temperature that the visible light chip (19) can withstand. Pressure and voltage are applied, and the end current is set to be lower than the upper limit current and not lower than 2mA to complete the first anodic bonding. Step 2: Align the deep cavity frame wafer (2) that has completed the first anodic bonding with the second side of the deep cavity frame wafer (2) of the visible light wafer (1) and the corresponding side of the infrared wafer (3) through the alignment machine, and then isolate and fix it with the isolation plate (43) and the clamping claw on the wafer-level bonding fixture; The deep cavity framework wafer (2), the visible light wafer (1), and the infrared wafer (3), which are fixed by the wafer-level bonding fixture, are then introduced into the bonding chamber. The lower electrode plate (42) of the bonding machine is brought into contact with the infrared wafer (3), and the temperature is set below the temperature that the infrared chip (31) can withstand. The upper electrode plate (41) of the bonding machine is kept at a certain distance from the visible light chip (19), and a higher temperature is set so that the temperature radiated to the visible light chip (19) is lower than the activation temperature of the getter (21) and the temperature that the visible light chip (19) can withstand, thus completing the exhaust. Keep the temperature of the lower electrode plate (42) constant and raise the temperature of the upper electrode plate (41) so that the temperature radiated to the visible light chip (19) is higher than the activation temperature of the getter (21) and lower than the temperature that the visible light chip (19) can withstand, thus completing the activation of the getter (21). Lower the temperature of the upper electrode plate (41) to the same temperature as the lower electrode plate (42), remove the isolation sheet (43) on the wafer-level bonding fixture, so that the second side of the deep cavity frame wafer (2) contacts the corresponding bonding area (16) of the infrared wafer (3), and lower the contact between the upper electrode plate (41) and the front side (11) of the visible light wafer (1), and apply heat, pressure and voltage to complete the second anodic bonding; Set the termination current to be lower than the upper limit current, specifically 0.5mA to 1mA; After the second anodic bonding, the second side of the deep cavity frame wafer (2) forms a gap with the bonding area (16) of the corresponding side of the infrared wafer (3) through the grooved connection structure (23); Step 3: Draw the dicing marks from the front (11) of the visible light wafer (1) to the bottom of the groove of the deep cavity frame wafer (2), so that the connection between the visible light chip (19) and the deep cavity frame chip (29) is independent. Remove the independent connection between the visible light chip (19) and the deep cavity frame chip (29) to expose the dicing path of the infrared wafer (3), and then scribe through the dicing mark line in the middle of the infrared chip (31) to obtain a single effective chip; Each of the effective chips is a visible light chip (19) and an infrared chip (31) connected by the deep cavity frame chip (29), and a vacuum chamber (9) is formed between each of the deep cavity frame chips (29) and the corresponding infrared chip (31).

9. The packaging method for the wafer-level packaging structure integrating a visible light chip and an infrared chip according to claim 8, characterized in that, In step 1, the anode bonding voltage is -200V to -600V, the upper limit of the current is 3mA to 15mA, and the termination current is 2mA; in step 2, the anode bonding voltage is -200V to -600V, and the absolute value of the voltage is higher than the absolute value of the first anode bonding voltage, preferably 100V to 200V higher, the upper limit of the current is 3mA to 15mA, and the termination current is 0.5mA to 1mA.

10. The packaging method for the wafer-level packaging structure integrating a visible light chip and an infrared chip according to claim 9, characterized in that, In step 1, the anode bonding voltage is -300V to -500V and the upper limit of the current is 5mA to 8mA. In step 2, the anode bonding voltage is -300V to -500V and the upper limit of the current is 5mA to 8mA.

Images