Display device

Abstract

The display device includes: a substrate; a first electrode in the display area of the substrate; a light emitting layer on the first electrode; a pixel defining film on the light emitting layer; a second electrode on the pixel defining film; and a flow control layer including a first main trench in the non-display area of the substrate, a second main trench in the non-display area, and an auxiliary trench in the non-display area between the first main trench and the second main trench.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0142618, filed on October 18, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to aspects of display devices, electronic devices including display devices, and methods for manufacturing display devices. Background Technology

[0004] Organic light-emitting display devices include display elements with brightness that varies according to current, such as organic light-emitting diodes (OLEDs).

[0005] Organic light-emitting display devices consist of multiple pixels that provide different light from each other (e.g., different colors of light). Summary of the Invention

[0006] Embodiments of this disclosure may relate to a display device capable of controlling the flow of an encapsulated organic film, an electronic device including a display device, and a method for manufacturing a display device.

[0007] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first electrode in a display region of the substrate; a light-emitting layer on the first electrode; a pixel defining film on a portion of the first electrode; a second electrode on the pixel defining film; and a flow control layer including: a first main trench in a non-display region of the substrate; a second main trench in the non-display region; and an auxiliary trench between the first main trench and the second main trench in the non-display region.

[0008] In one embodiment, the width of the auxiliary trench may be different from the width of the first main trench.

[0009] In one embodiment, the width of the auxiliary trench may be smaller than the width of the first main trench.

[0010] In one embodiment, the width of the first main trench and the width of the second main trench can be the same as each other.

[0011] In an embodiment, the display device may further include: a first encapsulated inorganic film on a flow control layer; an encapsulated organic film on the first encapsulated inorganic film; and a second encapsulated inorganic film on the encapsulated organic film.

[0012] In an embodiment, the residual membrane encapsulating the organic membrane may be located in at least one of the first main trench, the second main trench, and the auxiliary trench of the flow control layer.

[0013] In an embodiment, the auxiliary trench may include a plurality of auxiliary trenches, and the residual membrane may include a plurality of residual membranes in the plurality of auxiliary trenches, the plurality of residual membranes being spaced apart from each other.

[0014] In an embodiment, the residual membrane located in at least one of the first main trench and the second main trench may have a different thickness than the residual membrane located in the auxiliary trench.

[0015] In an embodiment, the thickness of the residual film in the auxiliary trench may be greater than the thickness of the residual film in at least one of the first main trench and the second main trench.

[0016] In one embodiment, the cavity surrounded by the second encapsulating inorganic film may be located in an auxiliary trench.

[0017] In an embodiment, the pixel defining film may include: a first pixel defining film; and a second pixel defining film on the first pixel defining film.

[0018] In one embodiment, the flow control layer may be located at the same layer as the layer of the first pixel defining film.

[0019] In an embodiment, the second pixel defining film may also be located between the flow control layer and the first encapsulation inorganic film.

[0020] In an embodiment, the auxiliary trench may include multiple auxiliary trenches, and the multiple auxiliary trenches may have the same width as each other.

[0021] In one embodiment, the spacing between adjacent auxiliary trenches among the plurality of auxiliary trenches may be the same as the spacing between other adjacent auxiliary trenches among the plurality of auxiliary trenches.

[0022] In one embodiment, the auxiliary trench may include multiple auxiliary trenches, and the width of the multiple auxiliary trenches may increase as they move further away from the center of the display area.

[0023] In one embodiment, the auxiliary trench may include multiple auxiliary trenches, and the width of the multiple auxiliary trenches may decrease as they move further away from the center of the display area.

[0024] In an embodiment, the flow control layer may include: a substrate layer; and a plurality of protruding patterns protruding from the substrate layer to define a first main trench, a second main trench, and an auxiliary trench.

[0025] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: forming a flow control layer on a substrate, the flow control layer having a first main trench, a second main trench, and an auxiliary trench; forming a pixel defining film on the flow control layer; forming a first encapsulating inorganic film on the pixel defining film; forming an encapsulating organic film on the first encapsulating inorganic film; and forming a residual film in at least one of the first main trench, the second main trench, and the auxiliary trench by selectively removing a portion of the encapsulating organic film formed in a non-display area of ​​the substrate.

[0026] According to one or more embodiments of this disclosure, an electronic device includes a display device comprising a screen. The display device includes: a substrate; a first electrode in a display region of the substrate; a light-emitting layer on the first electrode; a pixel-defining film on a portion of the first electrode; a second electrode on the pixel-defining film; and a flow control layer including: a first main trench in a non-display region of the substrate; a second main trench in the non-display region; and an auxiliary trench between the first and second main trenches in the non-display region.

[0027] According to some embodiments of this disclosure, the flow of the encapsulated organic film can be controlled.

[0028] According to some embodiments of this disclosure, at least one auxiliary trench can be formed between the first and second main trenches of the flow control layer, and thus prevents or substantially prevents the raw materials of the encapsulating organic film from flowing to the edge of the substrate during the process of forming the encapsulating organic film. Therefore, the encapsulation state of the display panel can be improved.

[0029] According to some embodiments of this disclosure, the residual film disposed inside the auxiliary trench may not be connected to a residual film in another trench adjacent to the auxiliary trench, and may be kept in a state spaced apart from it (e.g., separated). Therefore, even when a portion of the encapsulating organic film is exposed at the edge of the display panel, the diffusion of external moisture into the encapsulating organic film disposed in the display area of ​​the display panel can be prevented or substantially prevented.

[0030] According to some embodiments of this disclosure, by examining the presence or absence of a residual film disposed in an auxiliary trench, it becomes easier to determine how far the raw material used to encapsulate the organic film has moved from the center of the display area. Furthermore, the auxiliary trench can be used as a ruler to examine the extent of diffusion of the raw material used to encapsulate the organic film.

[0031] However, this disclosure is not limited to the foregoing aspects and features, and the foregoing and additional aspects and features will be set forth in part in the detailed description below with reference to the accompanying drawings, and this disclosure may be partly apparent from its obviousness or may be learned by practicing one or more of the presented embodiments of this disclosure. Attached Figure Description

[0032] The above and other aspects and features of this disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0033] Figure 1 This is an exploded perspective view showing a display device according to an embodiment;

[0034] Figure 2 This is a block diagram illustrating a display device according to an embodiment;

[0035] Figure 3 This is an equivalent circuit diagram of the first pixel according to an embodiment;

[0036] Figure 4 This is a layout diagram showing an example of a display panel according to an embodiment;

[0037] Figure 5 This illustrates an embodiment. Figure 4 Layout diagram of the display area;

[0038] Figure 6 This illustrates an embodiment. Figure 4 Layout diagram of the display area;

[0039] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I1-I1';

[0040] Figure 8 yes Figure 4 A magnified view of region A;

[0041] Figure 9 It is along Figure 8 A cross-sectional view taken from line I2-I2';

[0042] Figure 10 This is a cross-sectional view of the display device according to an embodiment;

[0043] Figure 11 This is a cross-sectional view of the display device according to an embodiment;

[0044] Figures 12 to 14 These are diagrams illustrating some processes of a method for manufacturing a display device according to an embodiment;

[0045] Figure 15 This is a block diagram of an electronic device according to an embodiment;

[0046] Figure 16 Schematic diagrams of some electronic devices according to some embodiments are shown;

[0047] Figure 17Schematic diagrams of some electronic devices according to some embodiments are shown; and

[0048] Figure 18 Schematic diagrams of some electronic devices according to some embodiments are shown. Detailed Implementation

[0049] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments illustrated herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques that are not essential for a full understanding of the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore, redundant descriptions may not be repeated.

[0050] When a particular embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0051] Furthermore, unless otherwise stated or implied, as will be understood by those skilled in the art, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or in part or in whole with each other, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently or in combination with each other in any suitable manner.

[0052] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and ratios of elements, layers, and regions may be exaggerated and / or simplified. For ease of illustration, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below” or “below” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein should be interpreted accordingly.

[0053] Furthermore, it should be anticipated that the shapes shown in the accompanying drawings may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments of this disclosure should not be construed as limited to the specific shapes shown in the drawings, and should be interpreted to account for variations in shape that may occur, for example, due to manufacturing processes. Consequently, the shapes shown in the drawings may not depict the actual shape of an area of ​​the device, and this disclosure is not limited thereto.

[0054] In the accompanying drawings, the x-axis (first direction DR1), y-axis (second direction DR2), and z-axis (third direction DR3) are not limited to the three axes (directions) of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0055] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or segment from another element, component, area, layer, or segment. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first area, first layer, or first segment described below can be named a second element, second component, second area, second layer, or second segment. Furthermore, when an element is described as a “first” element, this may not require or imply the existence of a “second” element or other elements. As used herein, the terms “first” and “second,” etc., may also be used to distinguish elements of different categories or groups. For example, the terms “first” and “second,” etc., may respectively represent “first category (or first group)” and “second category (or second group),” etc.

[0056] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intermediary elements or layers may exist. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element and / or may be indirectly electrically connected with one or more intermediary layers, regions, or elements between the layer, region, or element and the other layer, region, or element. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intermediary elements or layers may exist.

[0057] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of this disclosure. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural forms. It will be further understood that, when used in this specification, the terms “comprises,” “includes,” and “has, have, having” indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. When preceding / following a column of elements, expressions such as “at least one of…” modify the entire column of elements and do not modify individual elements within the column. For example, the expressions “at least one of a, b and c” and “at least one of the group consisting of a, b and c” indicate only a, only b, only c, both a and b, both a and c, both b and c, all a, b and c, or variations thereof.

[0058] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for the inherent variation in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” means “one or more embodiments of this disclosure.” As used herein, the terms “use,” “using,” and “used” can be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0059] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their context in the relevant field and / or the meaning of this specification, and should not be interpreted in an idealized or overly formal sense.

[0060] Figure 1 This is an exploded perspective view showing a display device according to an embodiment. Figure 2 This is a block diagram illustrating a display device according to an embodiment.

[0061] refer to Figure 1 and Figure 2The display device 10 according to the embodiment is a means for displaying moving images and / or still images. The display device 10 according to the embodiment can be applied to or implemented as various suitable portable electronic devices, such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic managers, e-books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 according to the embodiment can be applied to or implemented as a display unit (e.g., a display screen) of various suitable electronic devices (such as televisions, laptops, monitors, billboards, or Internet of Things (IoT) terminals or devices). As another example, the display device 10 according to the embodiment can be applied to or implemented as a wearable electronic device, such as a smartwatch, a watch phone, and a head-mounted display (HMD) for realizing virtual reality and / or augmented reality.

[0062] The display device 10 according to an embodiment includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0063] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 that intersects or intersects the first direction DR1. In the display panel 100, the angle where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 meet each other may be a right angle or may be rounded with a suitable curvature (e.g., a predetermined curvature). However, the planar shape of the display panel 100 is not limited to a quadrilateral shape and may be a suitable shape similar to other polygonal shapes, circular shapes, or elliptical shapes. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0064] like Figure 2 As shown, the display panel 100 includes a display area DAA for displaying images and a non-display area NDA for not displaying images. It can be understood that, since the display panel 100 includes a substrate SSUB (e.g., see...), Figure 7 Therefore, the substrate SSUB includes the display area DAA and the non-display area NDA.

[0065] The display area DAA includes multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL), and multiple data lines (DL).

[0066] Multiple pixels (PX) can be arranged in a matrix along the first direction DR1 and the second direction DR2. Multiple scan lines (SL) and multiple emission control lines (EL) can extend along the first direction DR1 and are simultaneously positioned along the second direction DR2. Multiple data lines (DL) can extend along the second direction DR2 and are simultaneously positioned along the first direction DR1.

[0067] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. The multiple emit control lines EL include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0068] Each of the multiple unit pixels UPX comprises multiple pixels PX1, PX2, PX3. For example... Figure 3 As shown, each of the plurality of pixels PX1, PX2, and PX3 may include a plurality of pixel transistors T1 to T6 that can be formed by semiconductor processes and may be disposed on a semiconductor substrate SSUB (e.g., see Figure 7 (e.g., in or on a semiconductor substrate SSUB). For example, multiple pixel transistors and / or multiple data transistors of the data driver 700 may be formed of complementary metal-oxide-semiconductor (CMOS).

[0069] Each of the multiple pixels PX1, PX2, and PX3 can be connected to a corresponding one of the multiple write scan lines GWL, a corresponding one of the multiple control scan lines GCL, a corresponding one of the multiple bias scan lines GBL, a corresponding one of the multiple first emission control lines EL1, a corresponding one of the multiple second emission control lines EL2, and a corresponding one of the multiple data lines DL. Each of the multiple pixels PX1, PX2, and PX3 can receive the data voltage of the corresponding data line DL according to the write scan signal of the corresponding write scan line GWL, and can allow the light-emitting element to emit light according to the data voltage.

[0070] The non-display area NDA may include a scan driver 610, a transmit driver 620, and a data driver 700.

[0071] The scan driver 610 includes a plurality of scan transistors, and the emitter driver 620 includes a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors can be formed by semiconductor processes and are formed on a semiconductor substrate SSUB (e.g., see...). Figure 7 (e.g., in or on a semiconductor substrate SSUB). For example, multiple scan transistors and multiple light-emitting transistors can be formed as CMOS. Figure 2In this diagram, the scan driver 610 is shown positioned on the left side of the display area DAA, and the transmit driver 620 is shown positioned on the right side of the display area DAA; however, this disclosure is not limited thereto. For example, both the scan driver 610 and the transmit driver 620 may be positioned on the left or right side of the display area DAA.

[0072] The scan driver 610 may include a write scan signal output unit (e.g., a write scan signal output circuit) 611, a control scan signal output unit (e.g., a control scan signal output circuit) 612, and a bias scan signal output unit (e.g., a bias scan signal output circuit) 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal based on the scan timing control signal SCS from the timing control circuit 400, and may sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal based on the scan timing control signal SCS, and may sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal based on the scan timing control signal SCS, and may sequentially output the bias scan signal to the bias scan line GBL.

[0073] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal based on the transmit timing control signal ECS and can sequentially output the first transmit control signal to the first transmit control line EL1. The second transmit control driver 622 can generate a second transmit control signal based on the transmit timing control signal ECS and can sequentially output the second transmit control signal to the second transmit control line EL2.

[0074] The data driver 700 may include multiple data transistors. These multiple data transistors can be formed using semiconductor processes and can be formed on a semiconductor substrate SSUB (e.g., see...). Figure 7 (e.g., in or on a semiconductor substrate SSUB). For example, multiple data transistors can be formed as CMOS.

[0075] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, pixels PX1, PX2, and PX3 can be selected by the write scan signal of the scan driver 610, and the analog data voltage can be supplied to the selected pixels PX1, PX2, and PX3.

[0076] The heat dissipation layer 200 may overlap with the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100 (such as the rear surface as an example). The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite with high thermal conductivity or a metal layer made of silver (Ag), copper (Cu), or aluminum (Al).

[0077] Circuit board 300 can be electrically connected to the first pad unit PDA1 of display panel 100 using conductive adhesive components such as anisotropic conductive film (e.g., see...). Figure 4 Multiple first pads PD1 (e.g., see...) Figure 4 Circuit board 300 can be a flexible printed circuit board or a flexible film with a flexible material. Figure 1 In the diagram, circuit board 300 is shown as unbent, but it can be bent. In this case, one end of circuit board 300 may be disposed on the rear surface of display panel 100 and / or the rear surface of heat dissipation layer 200. This one end of circuit board 300 may be one of a plurality of first pads PD1 connected to the first pad unit PDA1 of display panel 100 using conductive adhesive components (e.g., see...). Figure 4 The other end of the ) is opposite to the other end.

[0078] The timing control circuit 400 can receive digital video data DATA and timing signals from an external source. Based on the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0079] The power supply circuit 500 can generate multiple panel power voltages based on an external source voltage. For example, the power supply circuit 500 can generate a common voltage VSS, a drive voltage VDD, and an initialization voltage VINT, and can supply the common voltage VSS, drive voltage VDD, and initialization voltage VINT to the display panel 100. See below for further details. Figure 3 The common voltage VSS, drive voltage VDD, and initialization voltage VINT are described in more detail.

[0080] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and can be attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the common voltage VSS, drive voltage VDD, and initialization voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0081] As another example, similar to scan driver 610, transmit driver 620, and data driver 700, each of timing control circuitry 400 and power supply circuitry 500 can be located in the non-display area NDA of display panel 100. In this case, timing control circuitry 400 may include multiple timing transistors, and power supply circuitry 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be formed using semiconductor processes and can be formed on a semiconductor substrate SSUB (e.g., see...). Figure 7 (e.g., in or on a semiconductor substrate SSUB). For example, multiple timing transistors and multiple power transistors can be formed as CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the data driver 700 with the first pad unit PDA1 (e.g., see...). Figure 4 )between.

[0082] Figure 3 This is an equivalent circuit diagram of the first pixel according to an embodiment.

[0083] refer to Figure 3 The first pixel PX1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Furthermore, combined with... Figure 2The first pixel PX1 can be connected to the common voltage line VSL to which the common voltage VSS corresponds to a low potential voltage, the driving voltage line VDL to which the driving voltage VDD corresponds to a high potential voltage, and the initialization voltage line VIL to which the initialization voltage VINT corresponds. In other words, the common voltage line VSL can be a low potential voltage line, the driving voltage line VDL can be a high potential voltage line, and the initialization voltage line VIL can be an initialization voltage line. In this case, the common voltage VSS can be a voltage lower than the initialization voltage VINT. The driving voltage VDD can be a voltage higher than the initialization voltage VINT.

[0084] The first pixel PX1 includes multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0085] The light-emitting element LE emits light according to the driving current flowing through the channel of the first transistor T1. The amount of light emitted from the light-emitting element LE can be proportional to the driving current. The light-emitting element LE can be disposed between the fourth transistor T4 and the common voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the common voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, and in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0086] The first transistor T1 may be a driving transistor in which the source-drain current (hereinafter referred to as the "drive current") flowing between the source and drain electrodes of the first transistor T1 is controlled according to the voltage applied to the gate electrode of the first transistor T1. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0087] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal to the write scan line GWL, thereby connecting one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0088] A third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal controlling the scan line GCL to connect the first node N1 to the second node N2. Therefore, the gate electrode and drain electrode of the first transistor T1 can be connected to each other, and thus, the first transistor T1 can operate like a diode. In other words, the third transistor T3 can enable the first transistor T1 to be diode-connected. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0089] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0090] A fifth transistor T5 can be disposed between the third node N3 and the initialization voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the initialization voltage line VIL. Therefore, the initialization voltage VINT of the initialization voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the initialization voltage line VIL.

[0091] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal via the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the drive voltage line VDL. Therefore, the drive voltage VDD of the drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0092] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0093] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the drive voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the drive voltage line VDL.

[0094] The first node N1 is the contact point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the contact point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the contact point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0095] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a P-type MOSFET, but this disclosure is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an N-type MOSFET. As another example, some of the first transistors T1 to the sixth transistor T6 can be P-type MOSFETs, and the others of the first transistors T1 to the sixth transistor T6 can be N-type MOSFETs.

[0096] exist Figure 3 In the diagram, the first pixel PX1 is shown as comprising six transistors T1 to T6 and two capacitors CP1 and CP2, but the equivalent circuit diagram of the first pixel PX1 is not limited to this. For example, the number of transistors and capacitors in the first pixel PX1 is not limited to... Figure 3 The quantities shown.

[0097] In addition, the second pixel PX2 (for example, see Figure 2 The equivalent circuit diagram of ) and the third pixel PX3 (for example, see Figure 2 The equivalent circuit diagram can be found in the reference above. Figure 3 The equivalent circuit diagram of the first pixel PX1 described is the same or substantially the same. Therefore, its redundant description need not be repeated.

[0098] Figure 4 This is a layout diagram showing an example of a display panel according to an embodiment.

[0099] refer to Figure 4 The display area DAA of the display panel 100 according to the embodiment includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to the embodiment includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad unit (e.g., a first pad area) PDA1, and a second pad unit (e.g., a second pad area) PDA2.

[0100] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. For example, the scan driver 610 can be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on the other side of the display area DAA in the first direction DR1. In other words, the scan driver 610 can be disposed on the left side of the display area DAA, and the transmit driver 620 can be disposed on the right side of the display area DAA. However, this disclosure is not limited thereto, and both the scan driver 610 and the transmit driver 620 can be disposed on either the first side or the second side of the display area DAA.

[0101] The first pad unit PDA1 may include a connection to the circuit board 300 via a conductive adhesive component (e.g., see...). Figure 1 Multiple first pads PD1 of pads or bumps. The first pad unit PDA1 can be disposed on the third side of the display area DAA. For example, the first pad unit PDA1 can be disposed on one side of the display area DAA in the second direction DR2.

[0102] The first pad unit PDA1 can be disposed on the outside of the data driver 700 on the second direction DR2. In other words, the first pad unit PDA1 can be disposed closer to the edge of the display panel 100 than the data driver 700.

[0103] The second pad unit PDA2 may include multiple second pads PD2 corresponding to inspection pads to check whether the display panel 100 is operating normally. The multiple second pads PD2 may be connected to a fixture or probe, or may be connected to a circuit board used for inspection during the inspection process. The circuit board used for inspection may be a printed circuit board made of a rigid material, or it may be a flexible printed circuit board made of a flexible material.

[0104] The first distribution circuit 710 distributes the data voltage applied through the first pad unit PDA1 to multiple data lines DL (e.g., see...). Figure 2 For example, the first distribution circuit 710 can distribute the data voltage applied through a first pad PD1 of the first pad unit PDA1 to P data lines DL (where P is a positive integer of 2 or greater), and thus, the number of first pads PD1 can be reduced. The first distribution circuit 710 can be arranged on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be provided on one side of the display area DAA in the second direction DR2. In other words, the first distribution circuit 710 can be provided on the lower side of the display area DAA.

[0105] The second distribution circuit 720 distributes the signal applied through the second pad unit PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad unit PDA2 and the second distribution circuit 720 can be components for checking the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 can be arranged on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be located on the other side of the display area DAA in the second direction DR2. In other words, the second distribution circuit 720 can be located on the upper side of the display area DAA.

[0106] Figure 5 This illustrates an embodiment. Figure 4 The layout diagram of the display area. Figure 6 This illustrates an embodiment. Figure 4 The layout diagram of the display area.

[0107] refer to Figure 5 Each of the multiple unit pixels UPX includes a first emission region EA1 corresponding to the emission region of the first pixel PX1, a second emission region EA2 corresponding to the emission region of the second pixel PX2, and a third emission region EA3 corresponding to the emission region of the third pixel PX3. In other words, a unit pixel UPX may include a unit emission region UEA, and the unit emission region UEA may include the aforementioned first emission region EA1, second emission region EA2, and third emission region EA3.

[0108] refer to Figure 6 Each of the multiple unit pixels UPX includes a first emission region EA1 corresponding to the emission region of the first pixel PX1, a second emission region EA2 corresponding to the emission region of the second pixel PX2, and a third emission region EA3 corresponding to the emission region of the third pixel PX3.

[0109] refer to Figure 5 and Figure 6 Each of the first launch area EA1, the second launch area EA2, and the third launch area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape in the plan view.

[0110] like Figure 5 As shown, the maximum length of the third transmission region EA3 in the first direction DR1 can be less than the maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1. The maximum lengths of the first transmission region EA1 and the second transmission region EA2 in the first direction DR1 can be the same as or substantially the same as each other.

[0111] The maximum length of the third transmission region EA3 in the second direction DR2 can be greater than the maximum length of the first transmission region EA1 in the second direction DR2 and the maximum length of the second transmission region EA2 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 can be greater than the maximum length of the second transmission region EA2 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 can be less than the maximum length of the third transmission region EA3 in the second direction DR2.

[0112] like Figure 6 As shown in the diagram, in the plan view, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a hexagonal shape comprising six straight lines, but this disclosure is not limited thereto. In the plan view, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a polygonal shape other than a hexagon, a circular shape, an elliptical shape, or an irregular shape.

[0113] like Figure 5As shown, in each of the plurality of unit pixels UPX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the second direction DR2. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different from each other.

[0114] As another example, such as Figure 6 As shown, the first transmission region EA1 and the second transmission region EA2 may be adjacent to each other in the first direction DR1. The second transmission region EA2 and the third transmission region EA3 may be adjacent to each other in the first oblique direction DD1, and the first transmission region EA1 and the third transmission region EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 is the direction between the first direction DR1 and the second direction DR2, and may refer to a direction inclined at 45° relative to the first direction DR1 and the second direction DR2. The second oblique direction DD2 may be a direction orthogonal to or substantially orthogonal to the first oblique direction DD1.

[0115] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. The first color of light can be blue, the second color of light can be green, and the third color of light can be red. For example, the blue band can indicate that the peak wavelength of the light is in the range of approximately 370 nm to approximately 460 nm, the green band can indicate that the peak wavelength of the light is in the range of approximately 480 nm to approximately 560 nm, and the red band can indicate that the peak wavelength of the light is in the range of approximately 600 nm to approximately 750 nm.

[0116] exist Figure 5 and Figure 6 In the diagram, each of the plurality of unit pixels (UPX) is shown as comprising three emission regions EA1, EA2, and EA3, but this disclosure is not limited thereto. In other words, each of the plurality of unit pixels (UPX) may comprise four emission regions.

[0117] Furthermore, the arrangement of the emission regions of multiple unit pixel UPXs is not limited to Figure 5 and Figure 6 The arrangement shown. For example, the emission regions of multiple unit pixels UPX can be in a strip structure in which the emission regions are arranged along a first direction DR1, or in a rhomboid structure in which the emission regions have a diamond-shaped arrangement (e.g., structure, (This is a formally registered trademark of Samsung Display Co., Ltd.)

[0118] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I1-I1'.

[0119] refer to Figure 7 The display panel 100 includes a semiconductor backplane (base plate) SBP, a light-emitting element backplane EBP, a display element layer EML, a packaging layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0120] The semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films (SINS1, SINS2, and SINS3) covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) may be as described above. Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0121] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be doped with type I impurities. Multiple well regions WA can be disposed on the upper surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with type II impurities. The type II impurity can be different from the type I impurity. For example, when the type I impurity is a P-type impurity, the type II impurity can be an N-type impurity. As another example, when the type I impurity is an N-type impurity, the type II impurity can be a P-type impurity.

[0122] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0123] The bottom insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side surface insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side surface insulating film (SINS) can be disposed on the bottom insulating film (BINS).

[0124] Each of the source region SA and the drain region DA can be a region doped with a type I impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third-direction DR3. The channel region CH can overlap with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE (e.g., opposite side).

[0125] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. Due to the bottom insulating film BINS, the first low-concentration impurity region LDD1 can be a region with an impurity concentration lower than that of the source region SA. Due to the bottom insulating film BINS, the second low-concentration impurity region LDD2 can be a region with an impurity concentration lower than that of the drain region DA. The distance between the source region SA and the drain region DA can be increased by the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the pixel transistors PTR can be increased, and thus, breakdown and hot carrier phenomena that might be caused by shorter channels can be prevented or substantially prevented.

[0126] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be formed as silicon carbonitride (SiCN) or silicon oxide (SiO). x This disclosure includes inorganic membranes, but is not limited thereto.

[0127] The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed as silicon oxide (SiO2). x This disclosure includes inorganic membranes, but is not limited thereto.

[0128] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of a corresponding pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and suitable alloys thereof.

[0129] A third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The upper surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) can be formed as silicon oxide (SiO2). x This disclosure includes inorganic membranes, but is not limited thereto.

[0130] In another embodiment, the semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as a polyimide substrate. In this case, the thin-film transistor (e.g., a pixel transistor PTR) can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, while the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0131] The backplane (EBP) for the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. The multiple insulating films INS1 to INS9 can be disposed between the first conductive layer ML1 to the eighth conductive layer ML8.

[0132] The first conductive layers ML1 to the eighth conductive layers ML8 are used to realize the first pixel PX1 by connecting multiple contact terminals CTE exposed from the semiconductor backplane SBP to each other (e.g., see...). Figure 3 The circuit can be configured such that, for example, only the first transistor T1 to the sixth transistor T6 can be formed in the semiconductor backplane SBP, and the connection between the first transistor T1 to the sixth transistor T6 and the formation of the first capacitor CP1 and the second capacitor CP2 can be performed through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE can also be performed through the first conductive layer ML1 to the eighth conductive layer ML8.

[0133] A first insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of a plurality of first vias VA1 may penetrate the first insulating film INS1 to connect to a corresponding contact terminal CTE exposed from the semiconductor backplane SBP. Each of a plurality of first conductive layers ML1 may be disposed on the first insulating film INS1 and connected to a corresponding first via VA1.

[0134] A second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the plurality of second vias VA2 can penetrate the second insulating film INS2 to connect to the corresponding exposed first conductive layer ML1. Each of the plurality of second conductive layers ML2 can be disposed on the second insulating film INS2 and can be connected to the corresponding second via VA2.

[0135] A third insulating film INS3 can be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the plurality of third vias VA3 can penetrate the third insulating film INS3 to connect to the corresponding exposed second conductive layer ML2. Each of the plurality of third conductive layers ML3 can be disposed on the third insulating film INS3 and can be connected to the corresponding third via VA3.

[0136] A fourth insulating film INS4 can be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the plurality of fourth vias VA4 can penetrate the fourth insulating film INS4 to connect to the corresponding exposed third conductive layer ML3. Each of the plurality of fourth conductive layers ML4 can be disposed on the fourth insulating film INS4 and can be connected to the corresponding fourth via VA4.

[0137] A fifth insulating film INS5 can be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the plurality of fifth vias VA5 can penetrate the fifth insulating film INS5 to connect to the corresponding exposed fourth conductive layer ML4. Each of the plurality of fifth conductive layers ML5 can be disposed on the fifth insulating film INS5 and can be connected to the corresponding fifth via VA5.

[0138] A sixth insulating film INS6 can be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the plurality of sixth vias VA6 can penetrate the sixth insulating film INS6 to connect to the corresponding exposed fifth conductive layer ML5. Each of the plurality of sixth conductive layers ML6 can be disposed on the sixth insulating film INS6 and can be connected to the corresponding sixth via VA6.

[0139] A seventh insulating film INS7 can be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the plurality of seventh vias VA7 can penetrate the seventh insulating film INS7 to connect to the corresponding exposed sixth conductive layer ML6. Each of the plurality of seventh conductive layers ML7 can be disposed on the seventh insulating film INS7 and can be connected to the corresponding seventh via VA7.

[0140] An eighth insulating film INS8 can be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the plurality of eighth vias VA8 can penetrate the eighth insulating film INS8 to connect to the corresponding exposed seventh conductive layer ML7. Each of the plurality of eighth conductive layers ML8 can be disposed on the eighth insulating film INS8 and can be connected to the corresponding eighth via VA8.

[0141] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 may be made of the same or substantially the same material. Each of the first conductive layers ML1 to ML8 and the first vias VA1 to VA8 may be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and suitable alloys thereof. The first insulating films INS1 to INS8 may be made of the same or substantially the same material. The first insulating films INS1 to INS8 may be formed as silicon oxide (SiO2). x This disclosure includes inorganic membranes, but is not limited thereto.

[0142] The thickness of each of the following layers can be greater than the thickness of each of the following: the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of each of the following: the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of each of the following: the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of each of the following: the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. For example, the thickness of the first conductive layer ML1 can be approximately... The thickness of each of the following layers can be approximated: the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. Furthermore, the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can each be approximated.

[0143] Each of the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. Each of the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thicknesses of the seventh via VA7 and the eighth via VA8. Each of the thicknesses of the seventh via VA7 and the eighth via VA8 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be the same as or substantially the same as each other. For example, each of the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately... The thickness of the seventh via VA7 and the thickness of the eighth via VA8 can each be approximated.

[0144] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be formed of silicon oxide (SiO2). x This disclosure includes inorganic membranes, but is not limited thereto.

[0145] Each of the plurality of ninth vias VA9 can penetrate the ninth insulating film INS9 to connect to the corresponding exposed eighth conductive layer ML8. Each of the plurality of ninth vias VA9 can be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and suitable alloys thereof. The thickness of the ninth via VA9 can be approximately...

[0146] The display element layer (EML) can be disposed on the light-emitting element backplane (EBP). The display element layer (EML) may include a reflective electrode layer (RL), a tenth insulating film (INS10) and an eleventh insulating film (INS11), a tenth via (VA10), light-emitting elements (LE), a pixel defining film (PDL), and multiple trenches (TRC). Each of the multiple light-emitting elements (LE) may include a first electrode (AND), a light-emitting stack (light-emitting layer) (ES), and a second electrode (CAT).

[0147] A reflective electrode layer RL can be disposed on the ninth insulating film INS9. The reflective electrode layer RL may include one or more reflective electrodes RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL may include... Figure 7The first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 are shown in the figure.

[0148] Each of the plurality of first reflective electrodes RL1 may be disposed on the ninth insulating film INS9 and may be connected to the corresponding ninth via VA9. Each of the plurality of first reflective electrodes RL1 may be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and suitable alloys or nitrides thereof. For example, each of the plurality of first reflective electrodes RL1 may include titanium nitride (TiN).

[0149] Each of the plurality of second reflective electrodes RL2 may be disposed on a corresponding first reflective electrode RL1. Each of the plurality of second reflective electrodes RL2 may be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and suitable alloys thereof. For example, each of the plurality of second reflective electrodes RL2 may include aluminum (Al).

[0150] Each of the plurality of third reflective electrodes RL3 may be disposed on a corresponding second reflective electrode RL2. Each of the plurality of third reflective electrodes RL3 may be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and suitable alloys or nitrides thereof. For example, each of the third reflective electrodes RL3 may include titanium nitride (TiN).

[0151] Each of the plurality of fourth reflective electrodes RL4 may be disposed on a corresponding third reflective electrode RL3. Each of the plurality of fourth reflective electrodes RL4 may be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and suitable alloys thereof. For example, each of the plurality of fourth reflective electrodes RL4 may include titanium (Ti).

[0152] Because the second reflective electrode RL2 is essentially the electrode that reflects light from the light-emitting element LE, its thickness can be greater than that of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately... Furthermore, the thickness of the second reflective electrode RL2 can be approximately...

[0153] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9. The tenth insulating film INS10 can be disposed horizontally between adjacent reflective electrode layers RL. In another embodiment, the tenth insulating film INS10 can be disposed on the reflective electrode layer RL in the third pixel PX3. The tenth insulating film INS10 can be formed of silicon oxide (SiO2). x This disclosure includes inorganic membranes, but is not limited thereto.

[0154] The eleventh insulating film INS11 can be disposed on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can be formed as silicon oxide (SiO2). x ( ) type inorganic film, but this disclosure is not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 may be optical auxiliary layers through which light emitted from the light-emitting element LE and reflected by the reflective electrode layer RL passes.

[0155] In another embodiment, in order to adjust the resonant distance of the light emitted from the light-emitting element LE of at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the tenth insulating film INS10 and the eleventh insulating film INS11 may not be disposed below the first electrode AND of the first pixel PX1. The first electrode AND of the first pixel PX1 may be disposed directly on the reflective electrode layer RL. The eleventh insulating film INS11 may be disposed below the first electrode AND of the second pixel PX2. The tenth insulating film INS10 and the eleventh insulating film INS11 may be disposed below the first electrode AND of the third pixel PX3.

[0156] Therefore, in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the distance between the first electrode AND and the reflective electrode layer RL can be different. In other words, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main peak wavelength of the light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, various modifications can be made to the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, in Figure 7In the third pixel PX3, the distance between the first electrode AND and the reflective electrode layer RL is shown to be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 and the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1. The distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 is also shown to be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1. However, this disclosure is not limited thereto.

[0157] Furthermore, although according to embodiments of this disclosure in Figure 7 The diagram shows a tenth insulating film INS10 and an eleventh insulating film INS11. However, in some embodiments, a twelfth insulating film may be further attached below the first electrode AND of the first pixel PX1. In this case, the eleventh insulating film INS11 and the twelfth insulating film may be disposed below the first electrode AND of the second pixel PX2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be disposed below the first electrode AND of the third pixel PX3.

[0158] Each of the plurality of tenth vias VA10 can penetrate the eleventh insulating film INS11 in the second pixel PX2 and the third pixel PX3 to connect to the corresponding exposed fourth reflective electrode RL4. Each of the plurality of tenth vias VA10 can be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and suitable alloys thereof. The thickness of the tenth via VA10 in the second pixel PX2 can be less than the thickness of the tenth via VA10 in the third pixel PX3.

[0159] The first electrode AND of each of the plurality of light-emitting elements LE can be disposed on the eleventh insulating film INS11 and can be connected to the corresponding tenth via VA10. The first electrode AND of each of the plurality of light-emitting elements LE can be located in the display area DAA of the semiconductor substrate SSUB (e.g., see...). Figure 4In the plurality of light-emitting elements (LEs), the first electrode AND of each LE can be connected to the drain region DA or source region SA of the corresponding pixel transistor PTR via a corresponding tenth via VA10, corresponding first reflective electrodes RL1 to fourth reflective electrodes RL4, corresponding first vias VA1 to ninth vias VA9, corresponding first conductive layers ML1 to eighth conductive layers ML8, and corresponding contact terminals CTE. The first electrode AND of each LE can be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and suitable alloys or nitrides thereof. For example, the first electrode AND of each LE can be made of titanium nitride (TiN).

[0160] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the plurality of light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the plurality of light-emitting elements (LEs). The PDL is used to separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0161] The first emitting region EA1 can be defined as an area in which a first electrode AND, a light-emitting stack ES, and a second electrode CAT are sequentially stacked in a first pixel PX1 to emit light. The second emitting region EA2 can be defined as an area in which a first electrode AND, a light-emitting stack ES, and a second electrode CAT are sequentially stacked in a second pixel PX2 to emit light. The third emitting region EA3 can be defined as an area in which a first electrode AND, a light-emitting stack ES, and a second electrode CAT are sequentially stacked in a third pixel PX3 to emit light.

[0162] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the plurality of light-emitting elements (LEs), the second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be formed of silicon oxide (SiO2). x This disclosure is not limited to inorganic films. The thickness of each of the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can be approximately...

[0163] When the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 form a single pixel-defining film, the height of this single pixel-defining film increases, making it possible for the first encapsulating inorganic film TFE1 to break due to step coverage. Step coverage refers to the ratio of the film thickness coated on the inclined portion to the film thickness coated on the flat portion. The lower the step coverage, the more likely the film is to be cut at the inclined portion.

[0164] Therefore, in order to prevent or substantially prevent the first encapsulated inorganic film TFE1 from breaking due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can have a cross-sectional structure with a step shape. For example, the width of the first pixel defining film PDL1 can be greater than the width of the second pixel defining film PDL2 and the width of the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 can be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to its length in the horizontal direction.

[0165] Each of the plurality of trench TRCs can penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Furthermore, each of the plurality of trench TRCs can penetrate the eleventh insulating film INS11. In each of the plurality of trench TRCs, the eleventh insulating film INS11 can have a shape in which a portion of the eleventh insulating film INS11 is slotted.

[0166] At least one trench TRC can be set between adjacent pixels PX1, PX2, and PX3. Figure 7 In the diagram, two trenches TRC are shown as being positioned between adjacent pixels PX1, PX2, and PX3, but this disclosure is not limited thereto.

[0167] An ES (Emitting Light Stack) can include multiple stacked layers. Figure 7 In the diagram, the light-emitting stack ES is shown as having a triple-tandem structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this disclosure is not limited thereto. For example, the light-emitting stack ES may have a double-tandem structure including two stacked layers.

[0168] In a three-tiered structure, the light-emitting stack ES can have a tiered structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different colors of light (e.g., different colors of light). For example, the light-emitting stack ES may include a first stacked layer IL1 for emitting light of a first color, a second stacked layer IL2 for emitting light of a third color, and a third stacked layer IL3 for emitting light of a second color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0169] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer for emitting light of a first color and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer for emitting light of a third color and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer for emitting light of a second color and a third electron transport layer are sequentially stacked.

[0170] A first charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer IL1 and a P-type charge generation layer for supplying holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0171] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0172] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and can be disposed on the bottom surface of each of the plurality of trench TRCs. Due to the trench TRCs, the first stacked layer IL1 can be disconnected between adjacent pixels PX1, PX2, and PX3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRCs, the second stacked layer IL2 can be disconnected between adjacent pixels PX1, PX2, and PX3. A cavity ESS or blank space can be disposed between the first stacked layer IL1 and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 can be not disconnected by the trench TRCs, and can be configured to cover the second stacked layer IL2 in each of the plurality of trench TRCs. In other words, in the three-in-series structure, each of the plurality of trench TRCs can be a structure for disconnecting the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between adjacent pixels PX1, PX2, and PX3. Furthermore, in the dual-series structure, each of the multiple trench TRCs can be a structure used to disconnect the charge-generating layer and the lower intermediate layer disposed between the lower stacked layer and the upper stacked layer.

[0173] To stably disconnect the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2, and PX3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. Other suitable structures can exist to replace the trench TRCs in order to disconnect the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2, and PX3. For example, a separator wall with an inverted tapered shape can be disposed on the pixel defining film PDL instead of a trench TRC.

[0174] The number of stacked layers IL1, IL2, and IL3 used to emit different lights is not limited to... Figure 7 The quantities shown are as indicated. For example, a light-emitting stack ES may include two stacked layers. In this case, either of the two stacked layers may be the same as or substantially the same as the first stacked layer IL1, and the other of the two stacked layers may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge-generating layer for supplying electrons to either stacked layer and holes to the other intermediate layer may be disposed between the two stacked layers.

[0175] exist Figure 7 In the diagram, the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are shown as being disposed entirely within the first emission region EA1, the second emission region EA2, and the third emission region EA3; however, this disclosure is not limited thereto. For example, the first stacked layer IL1 may be disposed within the first emission region EA1, but may not be disposed within the second emission region EA2 and the third emission region EA3. Furthermore, the second stacked layer IL2 may be disposed within the second emission region EA2, but may not be disposed within the first emission region EA1 and the third emission region EA3. Similarly, the third stacked layer IL3 may be disposed within the third emission region EA3, but may not be disposed within the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL can be omitted.

[0176] The second electrode CAT can be disposed on the third stacked layer IL3. The second electrode CAT can be disposed on the third stacked layer IL3 in each of the multiple trench TRCs. The second electrode CAT can be formed of a transparent conductive oxide (TCO) that can transmit light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency can be improved in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 due to the microcavity effect.

[0177] The encapsulation layer TFE can be disposed on the display element layer EML. To prevent or substantially prevent oxygen and / or moisture from penetrating into the display element layer EML, the encapsulation layer TFE may include at least one inorganic film TFE1 or TFE3 and at least one organic film TFE2. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1, a second encapsulation inorganic film TFE3, and an encapsulation organic film TFE2. The encapsulation organic film TFE2 may be disposed between the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3.

[0178] The first encapsulating inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulating inorganic film TFE1 can be formed in which silicon nitride (SiN) is alternately stacked. x ) layer, silicon oxynitride (SiON) layer and / or silicon oxide (SiO) layer x Multiple films consisting of two or more inorganic films in a layer. The first encapsulating inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0179] The encapsulating organic membrane TFE2 can be disposed on the first encapsulating inorganic membrane TFE1. The encapsulating organic membrane TFE2 can be an organic membrane made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc. The encapsulating organic membrane TFE2 may include monomers.

[0180] The second encapsulation inorganic film TFE3 can be disposed on the encapsulation organic film TFE2. The second encapsulation inorganic film TFE3 can be formed as titanium oxide (TiO2). x ) layer or aluminum oxide (AlO) x The second encapsulation inorganic film TFE3 may be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic film TFE3 may be less than the thickness of the first encapsulation inorganic film TFE1.

[0181] Organic film APL can be a layer used to increase the interfacial adhesion strength between the encapsulation layer TFE and the optical layer OPL. Organic film APL can be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0182] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be disposed on the organic film APL.

[0183] The first color filter CF1 can overlap with the first emission region EA1 of the first pixel PX1. The first color filter CF1 allows light of the first color (or in other words, light in the blue band) to pass through it. The blue band can be approximately 370 nm to approximately 460 nm. Therefore, the first color filter CF1 allows light of the first color emitted from the first emission region EA1 to pass through it.

[0184] The second color filter CF2 can overlap with the second emission region EA2 of the second pixel PX2. The second color filter CF2 allows light of the second color (or in other words, light in the green band) to pass through it. The green band can be approximately 480nm to approximately 560nm. Therefore, the second color filter CF2 allows light of the second color emitted from the second emission region EA2 to pass through it.

[0185] The third color filter CF3 can overlap with the third emission region EA3 of the third pixel PX3. The third color filter CF3 allows light of the third color (or in other words, light in the red band) to pass through it. The red band can be approximately 600nm to approximately 750nm. Therefore, the third color filter CF3 allows light of the third color emitted from the third emission region EA3 to pass through it.

[0186] Each of the plurality of lenses LNS can be disposed on a corresponding color filter among the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS can be used to increase the amount of light directed to the display device 10 (e.g., see [reference]). Figure 1 The structure of the light ratio on the front surface of the lens. Each of the multiple lenses (LNS) can have a cross-sectional shape that convexes in the upward direction.

[0187] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a suitable refractive index (e.g., a predetermined refractive index) such that light travels in the third direction (DR3) at the interface between the multiple lens lenses (LNS) and the filler layer FIL. Furthermore, the filler layer FIL can be a planarization layer. The filler layer FIL can be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0188] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin substrate. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used for adhesion to the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin substrate, it can be applied directly to the filler layer FIL.

[0189] The polarizer POL can be disposed on one surface of the CVL cover layer. The polarizer POL can be a structure used to reduce or prevent visibility degradation that may be caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but this disclosure is not limited thereto. However, the polarizer POL can be omitted if the visibility degradation caused by reflection of external light is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0190] Figure 8 yes Figure 4 A magnified view of region A. Figure 9 It is along Figure 8The cross-sectional view taken from line I2-I2'.

[0191] refer to Figure 8 and Figure 9 Display panel 100 (for example, see Figure 1 The flow control layer 1000 may be disposed on a substrate (semiconductor substrate) SSUB. The flow control layer 1000 may include a pixel defining film (e.g., a first pixel defining film PDL1, e.g., see [reference]). Figure 7 The flow control layer 1000 can be integrally formed with the pixel defining film (e.g., the first pixel defining film PDL1). The flow control layer 1000 can be disposed at the same layer as the pixel defining film (e.g., the first pixel defining film PDL1) (e.g., in the middle or on top).

[0192] The flow control layer 1000 may include a plurality of protruding patterns 900. For example, the flow control layer 1000 may include a substrate layer 800 and a plurality of protruding patterns 900 protruding from the substrate layer 800.

[0193] Multiple protruding patterns 900 may protrude from the substrate layer 800 along a direction from the substrate SSUB toward the flow control layer 1000 (e.g., third-direction DR3) (or may extend from the substrate layer 800 along a direction from the substrate SSUB toward the flow control layer 1000 (e.g., third-direction DR3)). Multiple protruding patterns 900 may be disposed in the non-display area NDA (e.g., see...). Figure 4 )middle.

[0194] The multiple protruding patterns 900 of the flow control layer 1000 may include main protruding patterns 910, 920, 930 and 940 and auxiliary protruding patterns 950. For example, the multiple protruding patterns 900 may include a first main protruding pattern 910, a second main protruding pattern 920, a third main protruding pattern 930, a fourth main protruding pattern 940 and multiple auxiliary protruding patterns 950.

[0195] In a plan view, multiple protruding patterns 900 may each have a DAA surrounding the display area (e.g., see...). Figure 4 (For example, around the periphery of the display area DAA) a closed loop shape. Multiple protruding patterns 900 can be positioned at different distances from the center of the display area DAA. The multiple protruding patterns 900 can have a larger area (or length) as they are positioned further away from the center of the display area DAA. For example, when the multiple protruding patterns 900 can surround a larger area (e.g., around the periphery of a larger area) as they are positioned further away from the center of the display area DAA.

[0196] In the plan view, the first main protruding pattern 910 may surround the display area DAA (e.g., around the periphery of the display area DAA). In the plan view, the second main protruding pattern 920 may surround the display area DAA and the first main protruding pattern 910 (e.g., around the periphery of the display area DAA and the first main protruding pattern 910). In the plan view, a plurality of auxiliary protruding patterns 950 may surround the display area DAA, the first main protruding pattern 910, and the second main protruding pattern 920 (e.g., around the periphery of the display area DAA, the first main protruding pattern 910, and the second main protruding pattern 920). In the plan view, the plurality of auxiliary protruding patterns 950 may have a greater length (e.g., a length in the first direction DR1) as the plurality of auxiliary protruding patterns 950 are positioned away from the display area DAA. In a plan view, a third main protruding pattern 930 may surround the display area DAA, the first main protruding pattern 910, the second main protruding pattern 920, and a plurality of auxiliary protruding patterns 950 (e.g., around the periphery of the display area DAA, the first main protruding pattern 910, the second main protruding pattern 920, and the plurality of auxiliary protruding patterns 950). In a plan view, a fourth main protruding pattern 940 may surround the display area DAA, the first main protruding pattern 910, the second main protruding pattern 920, the plurality of auxiliary protruding patterns 950, and the third main protruding pattern 930 (e.g., around the periphery of the display area DAA, the first main protruding pattern 910, the second main protruding pattern 920, the plurality of auxiliary protruding patterns 950, and the third main protruding pattern 930).

[0197] The first main protruding pattern 910, the second main protruding pattern 920, the third main protruding pattern 930 and the fourth main protruding pattern 940 can be sequentially arranged in the non-display area NDA from the center of the display area DAA along the direction facing the edge of the display panel 100 (e.g., the substrate SSUB). For example, among the first main protruding pattern 910, the second main protruding pattern 920, the third main protruding pattern 930, and the fourth main protruding pattern 940, the first main protruding pattern 910 can be set closest to the center of the display area DAA. The second main protruding pattern 920 can then be set closest to the center of the display area DAA. The third main protruding pattern 930 can then be set closest to the center of the display area DAA. And the fourth main protruding pattern 940 can then be set closest to the center of the display area DAA.

[0198] Multiple auxiliary protruding patterns 950 may be sequentially arranged in the non-display area NDA from the center of the display area DAA along the edge facing the display panel 100 (e.g., the substrate SSUB). In this case, the multiple auxiliary protruding patterns 950 may be positioned between the second main protruding pattern 920 and the third main protruding pattern 930.

[0199] The width of each of the main protruding patterns 910, 920, 930, and 940 may be greater than the width W2 of each of the plurality of auxiliary protruding patterns 950. For example, the width W1 of the second main protruding pattern 920 may be greater than the width W2 of each of the plurality of auxiliary protruding patterns 950.

[0200] The width of each of the main protruding patterns 910, 920, 930 and 940 may be the same as or substantially the same as each other. For example, the width of the first main protruding pattern 910, the width W1 of the second main protruding pattern 920, the width of the third main protruding pattern 930 and the width of the fourth main protruding pattern 940 may be the same as or substantially the same as each other.

[0201] The width W2 of each of the multiple auxiliary protruding patterns 950 can be the same as or substantially the same as each other.

[0202] The spacing between the auxiliary protruding patterns 950 can be the same or substantially the same as each other. For example, the spacing between two adjacent auxiliary protruding patterns 950 can be the same or substantially the same as the spacing between two other adjacent auxiliary protruding patterns 950.

[0203] exist Figure 8 and Figure 9 The diagram shows four main protruding patterns 910, 920, 930 and 940 and four auxiliary protruding patterns 950, but the number of main protruding patterns 910, 920, 930 and 940 and the number of auxiliary protruding patterns 950 are not limited thereto, and various modifications can be made as needed or desired.

[0204] The groove 810 can be provided between multiple protruding patterns 900. For example, multiple grooves 810 can be defined by a substrate layer 800 and multiple protruding patterns 900.

[0205] Multiple trenches 810 may have a shape such that they are recessed along a direction from the flow control layer 1000 toward the substrate SSUB (e.g., the opposite direction to the third direction DR3 or the third opposite direction). Multiple trenches 810 may be disposed in the non-display area NDA of the substrate SSUB.

[0206] For example, the multiple trenches 810 of the flow control layer 1000 may include a first main trench 801, a second main trench 802, and an auxiliary trench 803.

[0207] In a plan view, the plurality of trenches 810 may each have a closed-loop shape surrounding the display area DAA (e.g., around the outer periphery of the display area DAA). The plurality of trenches 810 may be located at different distances from the center of the display area DAA. The plurality of trenches 810 may have a larger area (e.g., length) as the plurality of trenches 810 are located further away from the center of the display area DAA. For example, the plurality of trenches 810 may surround a larger area (e.g., around the periphery of a larger area) as the plurality of trenches 810 are located further away from the center of the display area DAA.

[0208] In the plan view, the first main trench 801 may surround the display area DAA (e.g., around the periphery of the display area DAA). In the plan view, a plurality of auxiliary trenches 803 may surround the display area DAA and the first main trench 801 (e.g., around the periphery of the display area DAA and the first main trench 801). In the plan view, the plurality of auxiliary trenches 803 may have a greater length as they are positioned away from the display area DAA. In the plan view, the second main trench 802 may surround the display area DAA, the first main trench 801, and the plurality of auxiliary trenches 803 (e.g., around the periphery of the display area DAA, the first main trench 801, and the plurality of auxiliary trenches 803).

[0209] The first main trench 801 and the second main trench 802 can be sequentially arranged in the non-display area NDA from the center of the display area DAA along the edge facing the display panel 100 (e.g., the substrate SSUB). For example, the first main trench 801 of the first main trench 801 and the second main trench 802 can be located closest to the center of the display area DAA, and the second main trench 802 can be located next to the center of the display area DAA.

[0210] Multiple auxiliary trenches 803 can be sequentially arranged in the non-display area NDA from the center of the display area DAA along the edge facing the display panel 100 (e.g., the substrate SSUB). In this case, the multiple auxiliary trenches 803 can be disposed between the first main trench 801 and the second main trench 802.

[0211] The first main groove 801 can be disposed between adjacent first main protruding patterns 910 and second main protruding patterns 920. Figure 9 In the cross-sectional view, the first main groove 801 can be a U-shaped space defined by the first main protruding pattern 910 and the second main protruding pattern 920.

[0212] The second main groove 802 can be disposed between the third main protruding pattern 930 and the fourth main protruding pattern 940. Figure 9In the cross-sectional view, the second main groove 802 can be a U-shaped space defined by the third main protruding pattern 930 and the fourth main protruding pattern 940.

[0213] The outermost auxiliary grooves 803 located on both sides of the plurality of auxiliary grooves 803 can be disposed between adjacent main protruding patterns and auxiliary protruding patterns 950. For example, an outermost auxiliary groove 803 located at one edge (hereinafter referred to as the first outermost auxiliary groove 803) can be disposed between the second main protruding pattern 920 and the adjacent auxiliary protruding pattern 950 (hereinafter referred to as the first outermost auxiliary protruding pattern 950), and another outermost auxiliary groove 803 located at the other edge (hereinafter referred to as the second outermost auxiliary groove 803) can be disposed between the third main protruding pattern 930 and the adjacent auxiliary protruding pattern 950 (hereinafter referred to as the second outermost auxiliary protruding pattern 950). Figure 9 In the cross-sectional view, the first outermost auxiliary groove 803 can be a U-shaped space defined by the substrate layer 800, the second main protruding pattern 920, and the first outermost auxiliary protruding pattern 950. Furthermore, in Figure 9 In the cross-sectional view, the second outermost auxiliary groove 803 can be a U-shaped space defined by the substrate layer 800, the third main protruding pattern 930, and the second outermost auxiliary protruding pattern 950.

[0214] Among the multiple auxiliary grooves 803, the auxiliary groove 803 between the first outermost auxiliary groove 803 and the second outermost auxiliary groove 803 (hereinafter referred to as the intermediate auxiliary groove 803) can be provided between adjacent auxiliary protruding patterns 950. Figure 9 In the cross-sectional view, the intermediate auxiliary groove 803 can be a U-shaped space defined by any one of the substrate layer 800, the auxiliary protrusion pattern 950, and another adjacent auxiliary protrusion pattern 950 adjacent to the one auxiliary protrusion pattern 950.

[0215] Although according to the embodiment Figure 8 and Figure 9 The diagram shows two main trenches 801 and 802 and five auxiliary trenches 803, but the number of main trenches 801 and 802 and the number of auxiliary trenches 803 are not limited thereto and can be modified in various ways as needed or desired.

[0216] The first main trench 801 and the auxiliary trench 803 can have different widths. For example, the width W11 of the first main trench 801 can be greater than the width W33 of the auxiliary trench 803.

[0217] The second main trench 802 and the auxiliary trench 803 can have different widths. For example, the width W22 of the second main trench 802 can be greater than the width W33 of the auxiliary trench 803.

[0218] The width W11 of the first main trench 801 and the width W22 of the second main trench 802 can be the same as or substantially the same as each other.

[0219] The auxiliary grooves 803 may have the same or substantially the same width W33 as each other.

[0220] The spacing between the auxiliary trenches 803 can be the same or substantially the same as each other. For example, the spacing between two adjacent auxiliary trenches 803 and the spacing between two other adjacent auxiliary trenches 803 can be the same or substantially the same as each other.

[0221] As described above, because the flow control layer 1000 includes protruding patterns 900 and grooves 810, the flow control layer 1000 can have an uneven shape.

[0222] A pixel-defining film (e.g., a second pixel-defining film PDL2) may be disposed on the flow control layer 1000. The second pixel-defining film PDL2 may be disposed on the protruding pattern 900 of the flow control layer 1000. Furthermore, the second pixel-defining film PDL2 may be disposed in the trench 810 of the flow control layer 1000.

[0223] The first encapsulating inorganic film TFE1 can be disposed on the second pixel defining film PDL2. The first encapsulating inorganic film TFE1 can be disposed on the second pixel defining film PDL2 to overlap with the protruding pattern 900 and the trench 810 of the flow control layer 1000. In this case, the first encapsulating inorganic film TFE1 can be disposed in the trench 810 of the flow control layer 1000.

[0224] The residual membrane RSL of the encapsulated organic membrane TFE2 can be disposed on the first encapsulated inorganic membrane TFE1. For example, the residual membrane RSL can be disposed in at least one trench 810 of the flow control layer 1000. Figure 8 and Figure 9As shown, at least a portion of the encapsulating organic film TFE2 (e.g., the residual film RSL of the encapsulating organic film TFE2) can be disposed in each of the first main trench 801 and the two auxiliary trenches 803. In this case, the encapsulating organic films TFE2 may not be connected to each other. For example, the residual film RSL overlapping the first main trench 801, the residual film RSL overlapping any one of the auxiliary trenches 803, and the residual film RSL overlapping the other auxiliary trench 803 may not be connected to each other and may be separated from or spaced apart from each other. Furthermore, the residual film RSL overlapping each trench 810 may not be connected to the encapsulating organic film TFE2 of the display area DAA and may be separated from or spaced apart from the encapsulating organic film TFE2 of the display area DAA.

[0225] According to an embodiment, the residual membrane RSL disposed in the main trenches 801 and 802 may have a different thickness than the residual membrane RSL disposed in the auxiliary trench 803. For example, as Figure 9 As shown, the thickness of the residual membrane RSL disposed in the first main trench 801 can be less than the thickness of the residual membrane RSL disposed in the auxiliary trench 803. The thickness can be a dimension (e.g., length) on the third-direction DR3.

[0226] According to an embodiment, the residual membrane RSL may not be provided in all the trenches 810 of the flow control layer 1000.

[0227] The second encapsulating inorganic film TFE3 can be disposed on the first encapsulating inorganic film TFE1 and the residual film RSL. The second encapsulating inorganic film TFE3 can be disposed on the residual film RSL to overlap with the protruding pattern 900 and the trench 810 of the flow control layer 1000. In this case, the second encapsulating inorganic film TFE3 can be disposed in the trench 810 of the flow control layer 1000.

[0228] When the residual film RSL is disposed in the trench 810, the second encapsulating inorganic film TFE3 can be disposed on the residual film RSL inside the trench 810. In this case, the second encapsulating inorganic film TFE3 can contact (e.g., directly contact) the residual film RSL inside the trench 810. When the residual film RSL is not disposed in the trench 810, the second encapsulating inorganic film TFE3 can be disposed on the first encapsulating inorganic film TFE1 inside the trench 810. In this case, the second encapsulating inorganic film TFE3 can contact (e.g., directly contact) the first encapsulating inorganic film TFE1 inside the trench 810.

[0229] According to an embodiment, the second encapsulated inorganic film TFE3 can contact the first encapsulated inorganic film TFE1 on the protruding pattern 900 (e.g., direct contact).

[0230] According to an embodiment, the second encapsulation inorganic film TFE3 disposed on adjacent protruding patterns 900 can contact each other (e.g., in direct contact). For example, the second encapsulation inorganic film TFE3 on the third main protruding pattern 930 (e.g., the second encapsulation inorganic film TFE3 overlapping the third main protruding pattern 930) and the second encapsulation inorganic film TFE3 on the auxiliary protruding pattern 950 adjacent to the third main protruding pattern 930 (e.g., the second encapsulation inorganic film TFE3 overlapping the second outermost auxiliary protruding pattern 950) can contact each other (e.g., in direct contact).

[0231] According to an embodiment, when the residual membrane RSL is not disposed in the trench 810, a cavity 999 or blank space surrounded by the second encapsulating inorganic membrane TFE3 (e.g., around the periphery of the second encapsulating inorganic membrane TFE3) can be formed inside the trench 810. For example, at least a portion of the cavity 999 can be disposed inside the trench (e.g., auxiliary trench 803).

[0232] According to an embodiment, at least one auxiliary trench 803 can be formed between the first main trench 801 and the second main trench 802, and therefore, during the process of forming the encapsulated organic film TFE2, the flow of raw materials (e.g., monomers) of the encapsulated organic film TFE2 to the edge of the substrate SSUB can be prevented or substantially prevented. For example, raw materials of the encapsulated organic film TFE2 applied at the center of the display area DAA of the substrate SSUB can flow toward the edge of the substrate SSUB, and the flow of raw materials of the encapsulated organic film TFE2 can be restricted as the raw materials of the encapsulated organic film TFE2 fill one or more of the plurality of auxiliary trenches 803 between the first main trench 801 and the second main trench 802. In this case, the raw materials of the encapsulated organic film TFE2 can also fill the first main trench 801 and the second main trench 802. Therefore, the flow of raw materials of the encapsulated organic film TFE2 can be controlled by the auxiliary trench 803 between the first main trench 801 and the second main trench 802 to prevent further diffusion to the edge of the second main trench 802. Therefore, because an encapsulating organic film TFE2 is not formed between the first encapsulating inorganic film TFE1 and the second encapsulating inorganic film TFE3 at the edge of the display panel 100 (e.g., the substrate SSUB), the bonding strength between the first encapsulating inorganic film TFE1 and the second encapsulating inorganic film TFE3 can be improved. Therefore, the encapsulating organic film TFE2 is not exposed at the edge of the display panel 100. Thus, the encapsulation state of the display panel 100 can be improved.

[0233] Furthermore, according to the embodiments, because as Figure 8 and Figure 9As shown, the width W33 of each of the plurality of auxiliary trenches 803 can be narrower than the width W11 or W22 of the main trenches 801 or 802, and the arrangement interval between the auxiliary trenches 803 can be narrower than the arrangement interval between the main trenches 801 and 802. Therefore, the residual film RSL disposed in the auxiliary trenches 803 can be kept in a separated state and not connected to the residual film RSL of another trench adjacent to the auxiliary trench 803. Thus, even when a portion of the encapsulating organic film TFE2 (e.g., the residual film RSL) is exposed at the edge of the display panel 100, the diffusion of moisture from the outside to the encapsulating organic film TFE2 disposed in the display area DAA of the display panel 100 can be prevented or substantially prevented.

[0234] Furthermore, according to the embodiment, by checking or verifying the presence or absence of residual film RSL disposed in the auxiliary trench 803, it is possible to more easily determine how far the raw material used to encapsulate the organic film TFE2 has moved from the center of the display area DAA. For example, the auxiliary trench 803 can be used as a ruler to check the extent of diffusion of the raw material used to encapsulate the organic film TFE2.

[0235] exist Figure 9 In the middle, refer to the above. Figure 7 At least one of a plurality of components between the described substrate SSUB (e.g., semiconductor substrate SSUB) and the first pixel defining film PDL1 may be disposed between the substrate SSUB and the flow control layer 1000. For example, Figure 7 At least one of the plurality of semiconductor insulating films SINS1 to SINS3 and insulating films INS1 to INS11 can be disposed between the substrate SSUB and the flow control layer 1000. Furthermore, the layers disposed with... Figure 7 At least one conductive layer at the same layer (e.g., in the middle or on top) as at least one of the multiple conductive layers ML1 to ML8 may be further disposed between the substrate SSUB and the flow control layer 1000. Furthermore, at least one conductive layer disposed with... Figure 7 At least one of the multiple reflective electrodes RL1 to RL4 may be further disposed between the substrate SSUB and the flow control layer 1000 at the same layer (e.g., in the middle or on top).

[0236] Figure 10 This is a cross-sectional view of a display device according to an embodiment.

[0237] Figure 10 The display device 10 shown (for example, see...) Figure 1 (Refer to the above) Figure 9 The difference in the described display device 10 is that the multiple auxiliary trenches 803 may have different sizes from each other, and therefore, their redundant description will not be repeated below, and the differences will be described in more detail below.

[0238] like Figure 10 As shown, the auxiliary trench 803 may have a width that gradually increases from the center of the display area DAA along the edge facing the display panel 100 (e.g., the substrate SSUB).

[0239] For example, among the four auxiliary trenches 803, the auxiliary trench 803 closest to the center of the display area DAA can have the smallest width W33-1. Among the four auxiliary trenches 803, the auxiliary trench 803 furthest from the center of the display area DAA can have the largest width W33-4. When Figure 10 When the four auxiliary grooves 803 are defined as first auxiliary groove 803, second auxiliary groove 803, third auxiliary groove 803 and fourth auxiliary groove 803 in the order closest to the first main groove 801, the width W33-2 of the second auxiliary groove 803 can be greater than the width W33-1 of the first auxiliary groove 803, the width W33-3 of the third auxiliary groove 803 can be greater than the width W33-2 of the second auxiliary groove 803, and the width W33-4 of the fourth auxiliary groove 803 can be greater than the width W33-3 of the third auxiliary groove 803.

[0240] According to an embodiment, Figure 10 The auxiliary protruding patterns 950 can have the same or substantially the same width as each other.

[0241] Figure 11 This is a cross-sectional view of a display device according to an embodiment.

[0242] Figure 11 The display device 10 (for example, see...) Figure 1 (Refer to the above) Figure 9 The difference in the described display device 10 is that the multiple auxiliary trenches 803 may have different sizes from each other, and therefore, their redundant description will not be repeated below, and the differences will be described in more detail below.

[0243] like Figure 11 As shown, the auxiliary trench 803 may have a width that gradually decreases from the center of the display area DAA along the direction facing the edge (e.g., the substrate SSUB) of the display panel 100.

[0244] For example, among the four auxiliary trenches 803, the auxiliary trench 803 closest to the center of the display area DAA can have the largest width W33-1. Among the four auxiliary trenches 803, the auxiliary trench 803 furthest from the center of the display area DAA can have the smallest width W33-4. When Figure 11When the four auxiliary grooves 803 are defined as first auxiliary groove 803, second auxiliary groove 803, third auxiliary groove 803 and fourth auxiliary groove in the order closest to the first main groove 801, the width W33-2 of the second auxiliary groove 803 can be smaller than the width W33-1 of the first auxiliary groove 803, the width W33-3 of the third auxiliary groove 803 can be smaller than the width W33-2 of the second auxiliary groove 803, and the width W33-4 of the fourth auxiliary groove 803 can be smaller than the width W33-3 of the third auxiliary groove 803.

[0245] According to an embodiment, Figure 11 The auxiliary protruding patterns 950 can have the same or substantially the same width as each other.

[0246] Figures 12 to 14 This is a diagram illustrating some processes of a method for manufacturing a display device according to an embodiment.

[0247] First, refer to Figure 12 A flow control layer 1000, comprising multiple protruding patterns 900 and multiple trenches 810, can be formed on a substrate SSUB. A second pixel defining film PDL2 can be formed on the flow control layer 1000, and a first encapsulating inorganic film TFE1 can be formed on the second pixel defining film PDL2.

[0248] Next, refer to Figure 13 An encapsulating organic film TFE2 can be formed on a first encapsulating inorganic film TFE1. For example, a raw material including monomers for the encapsulating organic film TFE2 can be applied to the first encapsulating inorganic film TFE1. In this case, the raw material for the encapsulating organic film TFE2 can be applied to the first encapsulating inorganic film TFE1 by deposition or inkjet printing. Subsequently, by curing the raw material applied to the first encapsulating inorganic film TFE1, the encapsulating organic film TFE2 can be formed on the first encapsulating inorganic film TFE1.

[0249] Subsequently, reference Figure 14 The portion of the encapsulating organic film TFE2 disposed at the edge of the substrate SSUB including the trench 810 can be selectively removed. For example, the encapsulating organic film TFE2 at the edge of the substrate SSUB can be removed by an ashing process. In this case, as... Figure 14 As shown, the portion of the encapsulated organic film TFE2 outside the trench 810 can be removed. In this case, because the width of the auxiliary trench 803 can be relatively narrow and the depth of the auxiliary trench 803 can be relatively deep, the portion of the encapsulated organic film TFE2 inside the auxiliary trench 803 can be retained without removal even after the ashing process. For example, the portion of the encapsulated organic film TFE2 inside the auxiliary trench 803 can be retained as residual film RSL.

[0250] Next, refer to Figure 9 A second encapsulating inorganic film TFE3 can be formed on the entire surface or substantially the entire surface of the substrate SSUB, including the residual film RSL. For example, the second encapsulating inorganic film TFE3 can be formed on the first encapsulating inorganic film TFE1 and the encapsulating organic film TFE2 (e.g., the residual film RSL).

[0251] According to an embodiment, a protruding protrusion can be formed instead of a carved groove 810.

[0252] Furthermore, according to embodiments, the encapsulation layer TFE can have a four-layer structure. For example, the encapsulation layer TFE may also include a second encapsulation inorganic film TFE3 and an organic film APL (e.g., see...). Figure 7 An auxiliary inorganic film between the components. For example, the auxiliary inorganic film may include titanium dioxide (TiO2). x ) or aluminum oxide (AlO x (For example, Al2O3). Auxiliary inorganic films can be formed using atomic layer deposition (ALD) processes.

[0253] The display device according to some embodiments can be applied to a variety of suitable electronic devices. The electronic device according to some embodiments may include the display device as described above, and may also include various suitable modules or devices having additional functions beyond those of the display device.

[0254] Figure 15 This is a block diagram of an electronic device according to an embodiment. (Reference) Figure 15 The electronic device 50 according to the embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14. The electronic device 50 may also include an input module 15, a non-image output module 16, and / or a communication module 17.

[0255] Electronic device 50 can output various suitable information in the form of images through display module 11. When processor 12 executes an application stored in memory 13, the image information provided by the application can be provided to the user through display module 11. Power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power for the operation of electronic device 50. Input module 15 can provide input information to processor 12 and / or display module 11. Non-image output module 16 can receive information other than images (such as sound, touch, and light) transmitted from processor 12 and can provide information to the user. Communication module 17 can be responsible for sending and receiving information between electronic device 50 and external devices, and may include receiving unit and sending unit.

[0256] At least one of the multiple components of the electronic device 50 described above may be included in the display device according to the embodiment described above. Furthermore, some of the various modules functionally included in a single module may be included in the display device, and other modules may be provided separately from the display device. For example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 50 besides the display device.

[0257] Figure 16 Schematic diagrams of some electronic devices according to some embodiments are shown. Figure 17 Schematic diagrams of some electronic devices according to some embodiments are shown. Figure 18 Schematic diagrams of some electronic devices according to some embodiments are shown. Figures 16 to 18 Examples of various suitable electronic devices to which the display device described above according to some embodiments can be applied are shown.

[0258] Figure 16 Examples of electronic devices shown include a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a television (TV) 10_1d, and a desktop monitor 10_1e.

[0259] In addition to the display module, the smartphone 10_1a may include an input module such as a touch sensor and a communication module. The smartphone 10_1a can process information received through the communication module or other input modules, and can display the information through the display module of the display device.

[0260] Similar to the display and input modules of the smartphone 10_1a, the tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, and desktop monitor 10_1e may also include display and input modules, and in some cases may additionally include communication modules.

[0261] Figure 17 An example of an electronic device is shown, including a display module for use in wearable electronic devices. The wearable electronic device may be smart glasses 10_2a, a head-mounted display 10_2b, or a smartwatch 10_2c, etc.

[0262] The smart glasses 10_2a and the head-mounted display 10_2b may include a display module that emits a display image and a reflector that reflects the emitted display image and provides the emitted display image to the user's eyes, thereby providing the user with virtual reality or augmented reality images.

[0263] The smartwatch 10_2c includes a biometric sensor as an input device and can provide the user with biometric information identified by the biometric sensor through a display module.

[0264] Figure 18 The diagram shows an electronic device 10_3 including a display module for use in a vehicle. For example, the electronic device 10_3 can be applied to the vehicle's dashboard and central instrument panel, or to a central information display (CID) placed on the vehicle's dashboard, or to an interior mirror display that replaces the side mirrors.

[0265] The foregoing is a description of some embodiments of this disclosure and should not be construed as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications are possible in the embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be apparent to those skilled in the art that, unless specifically instructed otherwise, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it will be understood that the foregoing is a description of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, wherein, The display device includes: Base; The first electrode is located in the display area of ​​the substrate; A light-emitting layer is located on the first electrode; A pixel-defining film is applied to a portion of the first electrode. The second electrode is on the pixel defining film; and The flow control layer includes: The first main trench is located in the non-display area of ​​the substrate; The second main trench is located in the non-display area; and An auxiliary trench is located between the first main trench and the second main trench in the non-display area.

2. The display device according to claim 1, wherein, The width of the auxiliary trench is different from the width of the first main trench.

3. The display device according to claim 2, wherein, The width of the auxiliary trench is smaller than the width of the first main trench.

4. The display device according to claim 1, wherein, The width of the first main groove and the width of the second main groove are the same.

5. The display device according to claim 1, wherein, The display device further includes: A first encapsulated inorganic film is placed on the flow control layer; An organic encapsulation film is placed on the first encapsulation inorganic film; and The second encapsulation inorganic film is placed on the encapsulation organic film.

6. The display device according to claim 5, wherein, The residual film of the encapsulated organic film is located in at least one of the first main trench, the second main trench, and the auxiliary trench of the flow control layer.

7. The display device according to claim 6, wherein, The auxiliary trench includes multiple auxiliary trenches, and The residual membrane includes multiple residual membranes in the plurality of auxiliary trenches, and the multiple residual membranes are spaced apart from each other.

8. The display device according to claim 5, wherein, The residual film located in at least one of the first main trench and the second main trench has a thickness different from that of the residual film located in the auxiliary trench.

9. The display device according to claim 8, wherein, The thickness of the residual film in the auxiliary trench is greater than the thickness of the residual film in at least one of the first main trench and the second main trench.

10. The display device according to claim 5, wherein, The cavity surrounded by the second encapsulating inorganic film is located in the auxiliary trench.

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