Display device

Abstract

Disclosed is a display device including: a substrate having a display area and a non-display area, and including a first flexible substrate, an intermediate layer, and a second flexible substrate; the transistor and the light-emitting device are located in the display area; the driving chip is located in the non-display area, and the middle layer is arranged between the first flexible substrate and the second flexible substrate and is arranged to be not overlapped with the edge part of at least one side of the driving chip in the non-display area. The display device may prevent reliability degradation of the driving chip and minimize film peeling and cracking, thereby minimizing deformation of the display device and improving reliability of the display device.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0143767, filed on October 21, 2024, which is incorporated herein by reference as fully set forth herein. Technical Field

[0002] This disclosure relates to a display device, and more specifically, to a display device capable of improving reliability. Background Technology

[0003] Display devices, such as TVs, monitors, smartphones, tablets, and laptops, are used in a variety of ways and forms to display images.

[0004] The display device includes a display panel having a plurality of light-emitting devices or liquid crystals for displaying images, and transistors for controlling the operation of each light-emitting device or liquid crystal to display images on demand via the light-emitting devices or liquid crystals.

[0005] Self-emissive organic light-emitting display devices are thinner than display devices with embedded individual light sources and do not require individual light sources, making it possible to manufacture flexible or various designs of display devices.

[0006] With the advent of the information age, the field of display devices that visually display electrical information signals is developing rapidly, and research is still underway to develop various performance indicators for display devices, such as thinness, low power consumption, or high reliability. Summary of the Invention

[0007] One object of this disclosure is to provide a display device that prevents charge from flowing into the driver chip and prevents the reliability degradation of the driver chip due to charge accumulation or storage in the display device.

[0008] Another object of this disclosure is to provide a display device with improved reliability by minimizing cracking and preventing crack propagation and moisture penetration.

[0009] Another object of this disclosure is to provide a display device with improved robustness and durability by reducing film peeling defects and display panel deformation.

[0010] Another object of this disclosure is to provide a display device that can utilize the same process to minimize defects in the display device, reduce energy consumption in the production of the display device, reduce the use of hazardous or regulated materials, and facilitate the realization of a recyclable and environmentally friendly display device.

[0011] One embodiment of this disclosure provides a display device, comprising: a substrate having a display area and a non-display area, and including a first flexible substrate, an intermediate layer, and a second flexible substrate; a transistor and a light-emitting device disposed in the display area; and a driving chip disposed in the non-display area, wherein the intermediate layer is disposed between the first flexible substrate and the second flexible substrate, and is configured not to overlap with at least one edge portion of the driving chip in the non-display area.

[0012] The intermediate layer can be disposed inside the substrate in a manner that does not overlap with the four sides of the lower surface of the driver chip.

[0013] A display device according to an embodiment of the present disclosure may further include pads disposed on a substrate in the region where a driver chip is disposed, and bumps disposed below the driver chip corresponding to the pads. An intermediate layer may be configured not to overlap with the region between at least one edge of the driver chip and the outermost pad among a plurality of pads. Alternatively, the intermediate layer may be configured not to overlap with the region between at least one edge of the driver chip and the outermost bump among a plurality of bumps.

[0014] The intermediate layer may include multiple interlayer patterns disposed between the first flexible substrate and the second flexible substrate in the area where the driver chip is mounted.

[0015] Interlayer patterns can be set between the first flexible substrate and the second flexible substrate so as to overlap with the multiple bumps of the driver chip, but not with the gaps between the bumps.

[0016] Interlayer patterns can be set between the first flexible substrate and the second flexible substrate so that they overlap with multiple pads disposed on the substrate corresponding to the driver chip, but do not overlap with the gaps between the pads.

[0017] Intermediate layers or interlayer patterns may contain silicon oxide.

[0018] Another embodiment of this disclosure provides a display device, comprising: a substrate having a display area and a non-display area, and including a first flexible substrate, an intermediate layer, and a second flexible substrate; a transistor and a light-emitting device disposed in the display area; and a driving chip disposed in the non-display area, wherein the intermediate layer is disposed between the first flexible substrate and the second flexible substrate and is configured not to overlap with at least one edge portion of the driving chip in the non-display area, and the display device further includes an insulating film disposed by stacking multiple layers in the non-display area of ​​the substrate, an anisotropic conductive film disposed between the driving chip and the insulating film, and a plurality of anti-crack patterns spaced apart from the driving chip and the anisotropic conductive film and disposed on the insulating film.

[0019] The crack-resistant pattern can be set in the form of a relief pattern that includes metal.

[0020] The anti-crack pattern may contain the same material as the source / drain or gate of the transistor that makes up the display area.

[0021] The anti-crack pattern can be disposed on the same layer as the pads on the substrate, or it can contain the same material as the pads on the substrate.

[0022] The display device may further include: a first pad disposed in the region where the driver chip is disposed in a direction toward the display area; and a second pad disposed in the region where the driver chip is disposed in a direction opposite to that direction toward the display area and facing the first pad, wherein a plurality of anti-crack patterns overlap with the intermediate layer, are spaced apart from the first pad and the second pad in a manner that does not overlap with the first pad and the second pad, and are spaced apart from the edge of a short side of the driver chip.

[0023] The transistors located in the display area contain oxide semiconductors. Attached Figure Description

[0024] The accompanying drawings are included to provide a further understanding of this disclosure. The drawings are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0025] Figure 1 This is a plan view of a display device according to one embodiment;

[0026] Figure 2 According to one embodiment Figure 1 A plan view of the display panel in its unfolded state before the bending process;

[0027] Figure 3 This is a circuit diagram of a sub-pixel according to one embodiment;

[0028] Figure 4 It is a cross-sectional view of a sub-pixel according to one embodiment;

[0029] Figure 5 According to one embodiment Figure 2 An enlarged partial plan view of part A;

[0030] Figure 6 According to one embodiment, along Figure 5 A cross-sectional view taken from line I-I';

[0031] Figure 7 According to one embodiment, along Figure 5 A cross-sectional view taken from line II-II';

[0032] Figure 8 According to another embodiment, along Figure 5 A cross-sectional view taken from line I-I';

[0033] Figure 9 According to another embodiment, along Figure 5 A cross-sectional view taken from line II-II';

[0034] Figure 10 According to another embodiment Figure 2 An enlarged partial plan view of part A; and

[0035] Figure 11 According to one embodiment, along Figure 10 The cross-sectional view taken from line III-III'. Detailed Implementation

[0036] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0037] The same reference numerals denote the same parts. Furthermore, to effectively explain the technical content, the thickness, proportions, and dimensions of parts may be exaggerated in the drawings. For ease of explanation, the proportions of the parts shown in the drawings differ from the actual proportions, and this disclosure is not limited to the proportions shown in the drawings.

[0038] In this article, when a component (or region, layer, section, etc.) is referred to as being “on” or “connected” or “coupled” to another component, it means that one component can be directly connected to / coupled to another component, or that a third component can be inserted between them.

[0039] "And / or" includes any combination of one or more of the related components that can be defined.

[0040] Terms such as "first," "second," etc., may be used to describe various components, but should not be construed as limiting these components. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of this embodiment, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0041] The terms “below,” “under,” “lower,” “above,” “upper,” etc., are used to describe the relationship between the components shown in the accompanying drawings. These terms are relative concepts and are interpreted based on the orientation shown in the drawings. For example, one or more other parts may be located between two components unless “only” or “directly” is used. As shown in the drawings, spatially related terms such as “below,” “under,” “lower,” “above,” “upper,” etc., can be used to readily describe the relationship between one element or component and another. Spatially related terms should be understood to include different orientations of the element in use or operation other than those shown in the drawings. For example, when the elements shown in the drawings are flipped, an element described as “below” or “under” another element may ultimately be positioned “above” another element. Therefore, the exemplary terms “below” or “under” can include both downward and upward directions.

[0042] It should be understood that the terms “comprising” or “having” are intended to describe the presence of the features, quantities, steps, operations, components, parts or combinations thereof described herein, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0043] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be combined or integrated with each other in whole or in part, and may interoperate with each other and be technically driven in various ways. Embodiments of this disclosure may be performed independently of each other, or may be performed together in a manner of mutual dependence.

[0044] In the following, a detailed description of the display device of this disclosure will be given with reference to the accompanying drawings and embodiments. Figure 1 This is a plan view of a display device according to one embodiment. Figure 2 It is in the unfolded state according to one embodiment. Figure 1 A floor plan of the display panel. Figure 3 This is a circuit diagram of a sub-pixel according to one embodiment. Figure 4 It is a cross-sectional view of a sub-pixel according to one embodiment;

[0045] refer to Figure 1 and Figure 2 A display device 100 according to an embodiment of the present disclosure includes: a display panel 110, the display panel 110 including a display area AA and a non-display area NA; and a light-emitting device 135 (e.g., Figure 4The display panel 110 includes a light-emitting device 135 disposed in the display area AA, and a driver chip 107 disposed in the non-display area NA. The driver chip 107 may be disposed in the driving circuit area 109 outside the curved area BA, which includes the curved line BL, in the non-display area NA. For example, the driver chip 107 may be a data driving circuit or a data driver, but the embodiments are not limited thereto. According to one embodiment, the driver chip 107 may be part of a gate driver, a touch controller, a timing controller, a power management circuit, etc. The display device 100 further includes a cover member 20 disposed on the display panel 110.

[0046] The cover member 20 can be disposed on top of the display panel 110 to cover the front surface of the display panel 110 and protect the display panel 110 from external impacts. The edge portion of the cover member 20 can have a curved portion or a curved surface portion that bends in the rearward direction (e.g., the -Z-axis direction) of the display device 100. Therefore, the cover member 20 can be configured to cover the side areas of the display panel 110 disposed on the rear surface, so that the display panel 110 can be protected from external impacts not only on the front surface of the display device 100 but also on the side surfaces.

[0047] The cover member 20 may be formed of a transparent material so as to overlap with the area where the image is displayed (e.g., display area AA). For example, the cover member 20 may be made of a transparent plastic material that can transmit images, reinforced glass made of transparent glass material, reinforced plastic, etc., but this disclosure is not limited thereto.

[0048] The display area AA of the display device 100 is the area where the image is displayed, and the area other than the display area AA can be called the non-display area NA. The display area AA can be called the "active area", and the non-display area NA can be called the "non-active area". The display area AA and the non-display area NA of the display device 100 can be applied to the display panel 110 in the same way.

[0049] Multiple subpixels SP are set in the display area AA of the display panel 110, and images can be displayed using the subpixels SP. The area where subpixels SP are set to display images is called the display area AA, and the area outside the display area AA can be called the non-display area NA.

[0050] refer to Figure 3 At least one sub-pixel SP among a plurality of pixels may include a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light-emitting diode OLED.

[0051] The first electrode (e.g., drain) of the switching transistor SW is electrically connected to the data line DL, and the second electrode (e.g., source) of the switching transistor SW is electrically connected to the first node N1. The gate of the switching transistor SW is electrically connected to the gate line GL. The switching transistor SW is used to transmit a data signal supplied through the data line DL to the first node N1 in response to a scan signal supplied through the gate line GL.

[0052] Capacitor Cst is electrically connected to the first node N1 and is charged to apply the voltage to the first node N1.

[0053] The first electrode (e.g., drain) of the driving transistor DR receives a high-potential driving voltage EVDD, and the second electrode (e.g., source) is electrically connected to the first electrode (e.g., anode) of the organic light-emitting diode (OLED). The driving transistor DR can be used to control the amount of driving current flowing to the OLED in response to the voltage applied to the gate.

[0054] The semiconductor layer of the switching transistor SW and / or the driving transistor DR may contain silicon (e.g., amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or low-temperature polycrystalline silicon (poly-Si)), or may contain an oxide semiconductor such as IGZO (indium gallium zinc oxide).

[0055] Organic light-emitting diodes (OLEDs), or light-emitting devices, are used to output light corresponding to a driving current. OLEDs can output light corresponding to any color selected from red, green, blue, and white.

[0056] An organic light-emitting diode (OLED) may include a first electrode, a light-emitting layer disposed on the first electrode, and a second electrode configured to supply a common voltage. The light-emitting layer may be configured to emit light of the same color (e.g., white light) for each pixel, or to emit light of a different color (e.g., red, green, or blue light) for each sub-pixel (SP).

[0057] The first electrode can be used as the anode, and the second electrode can be used as the cathode. An organic light-emitting diode (OLED) can be a top-emitting diode or a bottom-emitting diode. An organic light-emitting diode (OLED) is similar to the light-emitting device 135 described below. Figure 4 They are basically the same.

[0058] A compensation circuit can be located at the sub-pixel SP to compensate for the threshold voltage of the driving transistor DR, etc. The compensation circuit can consist of one or more transistors. The compensation circuit may include one or more transistors and capacitors, and can be configured in various ways depending on the compensation method. Pixels including compensation circuits can have various structures such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0059] refer to Figure 4 This describes the structure disposed in the display area AA of the display panel 110. The display panel 110 includes a transistor TR disposed on a substrate 111 of the display area AA, a light-emitting device 135 disposed on the transistor TR, and an encapsulation layer 150 disposed on the light-emitting device 135.

[0060] The substrate 111 is used to support and protect the components of the display device 100 disposed on the substrate 111. The substrate 111 is formed of a flexible plastic material and may have flexible properties.

[0061] Within the display area AA, the substrate 111 may have a multilayer stacked structure including a first flexible substrate 1111 and a second flexible substrate 1112, with an intermediate layer 117 located between the first flexible substrate 1111 and the second flexible substrate 1112.

[0062] The first flexible substrate 1111 can form the upper surface of the substrate 111, and the second flexible substrate 1112 can form the lower surface of the substrate 111. For example, the first flexible substrate 1111 and the second flexible substrate 1112 can be made of polyimide.

[0063] The intermediate layer 117 may contain an inorganic insulating material. For example, the intermediate layer 117 containing an inorganic insulating material may be disposed between a first flexible substrate 1111 containing polyimide and a second flexible substrate 1112 containing polyimide.

[0064] The first flexible substrate 1111 and the second flexible substrate 1112 contain polyimide, and due to the properties of polyimide, the first flexible substrate 1111 and / or the second flexible substrate 1112 may be charged. This charge may form a reverse bias voltage, and the formed reverse bias voltage may affect components such as transistors TR on the substrate 111.

[0065] However, the substrate 111 according to this disclosure can be configured such that an intermediate layer 117 comprising an inorganic insulating material is disposed between the first flexible substrate 1111 and the second flexible substrate 1112, preventing charge in the substrate 111 from moving to the upper part of the substrate 111 and minimizing the effect of charge on the transistor TR located on the upper surface of the substrate 111. Therefore, the intermediate layer 117 can prevent charge from being stored or accumulated in the substrate 111. In other words, the intermediate layer 117 comprising an inorganic insulating material can be disposed between the first flexible substrate 1111 and the second flexible substrate 1112 to prevent or minimize charge accumulation by preventing the movement of charge toward the transistor TR and other sensitive internal components.

[0066] The inorganic insulating material constituting the intermediate layer 117 may include silicon nitride (SiN). x) or silicon oxide (SiO) x For example, when the intermediate layer 117 contains silicon oxide (SiO2). x When the intermediate layer 117 has a lower rate of moisture transfer from the outside than the first flexible substrate 1111 and the second flexible substrate 1112 containing polyimide, the effect of moisture from the outside on the components on the substrate can be prevented or minimized.

[0067] The first flexible substrate 1111 and the second flexible substrate 1112 are bonded to each other through an intermediate layer 117.

[0068] For example, when the intermediate layer 117 contains silicon oxide (SiO2) x When the intermediate layer 117 is bonded to the oxygen (O) of the intermediate layer 117 and the hydrogen (H) of the first flexible substrate 1111 and the second flexible substrate 1112 containing polyimide, the adhesion can be enhanced.

[0069] The intermediate layer 117 can be disposed within the entire display area AA between the first flexible substrate 1111 and the second flexible substrate 1112.

[0070] The insulating film 120 can be disposed in the display area AA of the substrate 111 in a multilayer stacked structure. The insulating film 120 may include a first insulating film 121, a second insulating film 122 and a third insulating film 123.

[0071] The first insulating film 121 can be referred to as a buffer film and can have the same function as buffer films known in the art. The first insulating film 121 can be disposed on the substrate 111 to protect the structure on the substrate 111 that is susceptible to moisture penetration from the effects of moisture penetrating through the substrate 111, and to make the surface of the substrate 111 flat or planar.

[0072] The first insulating film 121 can be a single-layer inorganic film, or it can be configured as multiple inorganic films stacked on top of each other. For example, the first insulating film 121 may include a silicon oxide film (SiO2). x ), silicon nitride film (SiN) x ) or silicon nitride oxide film (SiO) x N y It may include at least one inorganic membrane, or may include a multilayer membrane having the aforementioned inorganic membrane stacked on top of it.

[0073] The transistor TR can be disposed on the first insulating film 121. The transistor TR can be... Figure 3 The switching transistor SW or driving transistor DR described herein. The transistor TR may include a gate, a source, a drain, and an active layer. The active layer may contain a semiconductor material. The semiconductor material may be made of silicon-based semiconductor material or oxide-based semiconductor material.

[0074] The transistor TR located within the display area AA can be a transistor TR containing silicon-based semiconductor materials or a transistor TR containing oxide-based semiconductor materials, depending on its function. Each sub-pixel SP can be equipped with a transistor TR containing a different semiconductor material.

[0075] A second insulating film 122 is disposed on the first insulating film 121. The second insulating film 122 can be disposed within the display area AA to space transistors TR containing different semiconductor materials from each other or to prevent short circuits between electrodes. The second insulating film 122 may include an inorganic film, such as a silicon oxide film (SiO2). x ), silicon nitride film (SiN) x ) or a stack of its multilayer films.

[0076] The third insulating film 123 is disposed on the second insulating film 122. The third insulating film 123 may be disposed within the display area AA to insulate the electrodes of the transistor TR constituting the substrate 111 from each other, or to insulate the electrodes from the active layer. The third insulating film 123 may be referred to as an interlayer insulating film, and may function as an interlayer insulating film as known in the art.

[0077] The third insulating film 123 may comprise an inorganic material. For example, the inorganic material may comprise a silicon oxide film (SiO2). x ), silicon nitride film (SiN) x ) or silicon nitride oxide film (SiO) x N y It may include at least one inorganic membrane, or may include a multilayer membrane having the aforementioned inorganic membrane stacked on top of it.

[0078] Organic film 140 can be disposed on transistor TR or insulating film 120 to protect transistor TR and mitigate step differences caused by transistor TR. Organic film 140 can be disposed between the structure or element of transistor TR and light-emitting device 135 to reduce parasitic capacitance between them. Transistor TR can be covered by organic film 140, or organic film 140 can be disposed on insulating film 120 to achieve surface planarization.

[0079] The organic membrane 140 may have a single-layer or multi-layer structure made of organic materials. The organic membrane 140 may include a first organic membrane 141 and a second organic membrane 142 located on the first organic membrane 141.

[0080] Within the display area AA, one electrode of the transistor TR is covered by a first organic film 141 to make the upper surface flat. The first organic film 141 may contain an organic material. The organic material may include at least one of acrylic resin, phenolic resin, polyimide resin, unsaturated polyester resin, polyamide resin, benzocyclobutene resin, polystyrene resin, or polyphenylene sulfide resin.

[0081] Within the display area AA, the transistor TR and the first organic film 141 are covered by a second organic film 142 to make the upper surface flat or planarized. The second organic film 142 may contain an organic material. The organic material may include at least one of acrylic resin, phenolic resin, polyimide resin, unsaturated polyester resin, polyamide resin, benzocyclobutene resin, polystyrene resin, or polyphenylene sulfide resin.

[0082] In addition to the insulating film 120 described above, various functional organic or inorganic films can be further disposed between the substrate 111 and the organic film 140.

[0083] The light-emitting device 135 is disposed on the organic film 140 within the display area AA. The light-emitting device 135 can be electrically connected to the transistor TR through the organic film 140. The light-emitting device 135 includes a first electrode E1, a light-emitting layer EL, and a second electrode E2.

[0084] The first electrode E1 can be used as an anode. The first electrode E1 can be connected to the transistor TR via the organic film 140.

[0085] The first electrode E1 may comprise a metallic material with high reflectivity. For example, the first electrode E1 may comprise a multilayer structure such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and ITO (ITO / Al / ITO), an APC (Ag / Pd / Cu) alloy, a stacked structure of APC alloy and ITO (ITO / APC / ITO), or a stacked structure of silver (Ag) and molybdenum / titanium alloy (Ag / MoTi). Alternatively, it may comprise a single-layer structure made of any one or an alloy of two or more materials selected from silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca), and barium (Ba). The first electrode E1 may be referred to as a reflective electrode.

[0086] The light-emitting layer EL is disposed on the first electrode E1. The light-emitting layer EL may include a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer.

[0087] When a voltage is applied to the first electrode E1 and the second electrode E2, holes and electrons move to the organic light-emitting layer through the hole injection layer and the hole transport layer, and the electron injection layer and the electron transport layer, respectively, and combine with each other in the organic light-emitting layer to emit light.

[0088] Although the light-emitting layer EL is shown in the accompanying drawings as being disposed within the opening area, the hole injection layer, hole transport layer, electron transport layer and electron injection layer constituting the light-emitting layer EL can be disposed together on the front surface of the display area AA (e.g., as a common layer laid across multiple sub-pixels).

[0089] The light-emitting layer EL can be composed of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, and a blue light-emitting layer that emits blue light. The red, green, and blue light-emitting layers can be provided for each sub-pixel SP on the first electrode E1. The red light-emitting layer can be patterned and disposed in the red sub-pixel, the green light-emitting layer can be patterned and disposed in the green sub-pixel, and the blue light-emitting layer can be patterned and disposed in the blue sub-pixel. However, this disclosure is not necessarily limited to this; at least two organic light-emitting layers selected from the red, green, and blue light-emitting layers can be stacked and disposed in one sub-pixel SP.

[0090] The emitting layer EL can be a white emitting layer that emits white light. In this way, the organic emitting layer of the emitting layer EL can be a common layer that is commonly set in the sub-pixels SP, rather than a patterned form.

[0091] As described above, the light-emitting layer EL can be arranged in a series structure of two or more stacked layers. Thus, each light-emitting device 135 can include a charge-generating layer disposed between the stacked layers. The charge-generating layer can be a common layer disposed on the front surface of the display area AA.

[0092] The second electrode E2 is disposed on the light-emitting layer EL. The second electrode E2 can be used as a cathode. The second electrode E2 can be disposed not only within the light-emitting area of ​​the sub-pixel SP, but also across the entire display area AA (e.g., as a common layer laid across multiple sub-pixels). When the display area AA is functionally divided, the second electrode E2 can be arranged in a pattern.

[0093] The second electrode E2 can be a common layer disposed on the sub-pixel SP to apply the same voltage. For this purpose, the second electrode E2 can be configured as a portion extending from the display area AA to the non-display area NA.

[0094] The second electrode E2 can be a transparent electrode. The second electrode E2 can contain a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode E2 contains a semi-transmissive conductive material, light extraction efficiency can be improved through microcavity design.

[0095] The top-emitting type light-emitting device 135 has been described above. However, the light-emitting device 135 of this disclosure is not limited thereto, and can be configured as a bottom-emitting type where light emitted from the light-emitting layer EL is emitted toward the substrate 111. In this way, the first electrode E1 can be made of a transparent or translucent electrode material, and the second electrode E2 can be made of a reflective electrode material. The transparent or translucent electrode material and the reflective electrode material can include the materials described above.

[0096] The third organic film 143 can be disposed on the second organic film 142 to cover the end of the first electrode E1 of the light-emitting device 135. For example, the outer edge of the first electrode E1 can overlap with a portion of the third organic film 143.

[0097] The third organic membrane 143 can be referred to as the embankment that defines the luminescent region.

[0098] The third organic film 143 is configured such that the first electrode E1 of the light-emitting region opens for each sub-pixel SP (e.g., has an opening region or hole), and the first electrodes E1 between adjacent sub-pixels SP can be electrically insulated from each other. Using a halftone mask, the third organic film 143 can be configured to have not only dikes but also gaps between the dikes. The gaps can be used to support the deposition mask so that the dikes and the structures below the dikes do not contact each other during the deposition of the light-emitting layer EL.

[0099] The third organic film 143 can be configured as a portion extending from the display area AA to the non-display area NA. The third organic film 143 can be patterned according to its function within the non-display area NA.

[0100] The third organic membrane 143 may contain any organic material selected from polyimide resin, acrylic resin, epoxy resin, phenolic resin and polyamide resin.

[0101] An encapsulation layer 150 is disposed on the light-emitting device 135. The encapsulation layer 150 extends from the display area AA and is also disposed on the non-display area NA. The display area AA and the non-display area NA can be covered by the encapsulation layer 150 to prevent oxygen or moisture from penetrating into structures such as the light-emitting device 135 and the transistor TR on the substrate 111. According to an embodiment, other layers such as a cover layer can be further interposed between the encapsulation layer 150 and the second electrode E2.

[0102] The encapsulation layer 150 may have a multilayer structure. The encapsulation layer 150 may be configured such that inorganic and organic films are alternately stacked. According to one embodiment of this disclosure, the encapsulation layer 150 may include a first encapsulation layer 151, a second encapsulation layer 152, and an organic encapsulation layer 154 interposed between the first encapsulation layer 151 and the second encapsulation layer 152. The first encapsulation layer 151 and the second encapsulation layer 152 may be inorganic encapsulation films. The first encapsulation layer 151 may be disposed adjacent to the light-emitting device 135, and the second encapsulation layer 152 may be disposed on the uppermost surface of the encapsulation layer 150.

[0103] The first encapsulation layer 151 may be disposed on the entire upper surface of the transistor TR and the light-emitting device 135 within the display area AA. The light-emitting device 135 may be completely covered by the first encapsulation layer 151 to seal or surround the light-emitting device 135. The first encapsulation layer 151 may be configured to extend from the display area AA to a portion of the non-display area NA.

[0104] The first encapsulation layer 151 may be made of an inorganic insulating material. For example, the first encapsulation layer 151 may contain an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride.

[0105] An organic encapsulation layer 154 is disposed on the first encapsulation layer 151, and the organic encapsulation layer 154 is used to flatten or planarize the upper surface to minimize cracking that may be caused by step coverage due to the structure below the organic encapsulation layer 154.

[0106] The organic encapsulation layer 154 may contain at least one organic material selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate and hexamethyldisiloxane.

[0107] The second encapsulation layer 152 can be disposed on the organic encapsulation layer 154. The second encapsulation layer 152 can be configured to extend from the display area AA to a portion of the non-display area NA.

[0108] The second encapsulation layer 152 may be made of an inorganic insulating material. For example, the second encapsulation layer 152 may contain an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride.

[0109] A back plate 31 may be disposed on the rear surface of the substrate 111. The back plate 31 enables the substrate 111 to remain flat and serves to support the substrate 111. The back plate 31 may be attached to the rear surface of the substrate 111 using an adhesive (not shown) or the like. The back plate 31 is configured to extend from the display area AA to the non-display area NA.

[0110] The backsheet 31 may be made of a rigid plastic film. For example, the backsheet 31 may contain any one selected from polyethylene terephthalate (PET), polyimide (PI), and polyethylene naphthalate (PEN).

[0111] like Figure 2 As shown, the non-display area NA may correspond to the area surrounding the display area AA of the displayed image. The non-display area NA may include a driving circuit area 109 for driving multiple sub-pixels SP, and at least one driving chip 107 may be disposed within the driving circuit area 109.

[0112] The driver chip 107 can be provided in the form of a driver integrated circuit (D-IC). The driver chip 107 can be mounted within the drive circuit area 109, excluding the curved area BA (including the curved line BL), within the non-display area NA of the display panel 110 using a chip-on-panel (COP) method. The curved area BA is located in the area between the driver chip 107 and the display area AA. The driver chip 107 can be used as a data drive circuit.

[0113] The driving circuit region 109 may further include a gate driving circuit (not shown) disposed in the non-display region NA in the form of a gate in panel (GIP).

[0114] Figure 5 According to one embodiment Figure 2 An enlarged partial plan view of part A. Figure 6 and Figure 8 According to the embodiments along Figure 5 A cross-sectional view taken from line I-I'. Figure 7 and Figure 9 According to the embodiments along Figure 5 The cross-sectional view taken from line II-II'.

[0115] refer to Figure 5 This describes the structure disposed within the non-display area NA of the display panel 110. The display panel 110 may further include pads PAD located on the substrate 111 and electrically connected to a driver chip 107 mounted within the non-display area NA, and multiple wirings W1, W2, W4 disposed within the non-display area NA and electrically connected to the pads PAD or the driver chip 107. Thus, multiple pads PAD can be disposed, and the multiple pads PAD may include a first pad PAD1 and a second pad PAD2.

[0116] The driver chip 107 can be positioned within the non-display area NA of the display panel 110 using the COP (Chip-on-Plate) method. The COP method involves using... Figure 6 The anisotropic conductive film (ACF) 103 shown attaches a driver chip 107 in the form of a driver IC to a pad PAD on a substrate 111. For example, the anisotropic conductive film (ACF) 103 can provide mechanical bonding and electrical interconnection between components. The AFC film can exhibit anisotropic conductivity, such as being configured to conduct electricity in a vertical direction (e.g., the Z-axis) through conductive particles when compressed, while the spacing of these particles can ensure electrical insulation in the horizontal direction (e.g., the XY plane) to prevent short circuits between adjacent terminals.

[0117] The driver chip 107 receives signals required to drive the display panel 110 from an external source and provides or transmits these signals to the display panel 110. The driver chip 107 can be used to transmit data signals to the data lines DL of the display area AA. The driver chip 107 can also receive signals from the display area AA of the display panel 110.

[0118] The driver chip 107 is electrically connected to external signals and the display panel 110 via the second pad PAD2 and the first pad PAD1. Specifically, the driver chip 107 receives signals from the outside via the second wiring W2 and the second pad PAD2. The driver chip 107 can be used to transmit signals received from the outside to the display area AA via the first pad PAD1 and the first wiring W1.

[0119] The first pad PAD1 is positioned closer to the display area AA than the second pad PAD2. The first pad PAD1 can be arranged in multiple rows. Multiple first pads PAD1 arranged in a single row are spaced apart from each other. For example, the first pads PAD1 can be arranged in three rows, but this disclosure is not limited thereto; the first pads PAD1 can be arranged in two or fewer rows or four or more rows. The first pads PAD1 can have a short side and a long side. Additionally, some pad groups can be arranged diagonally, while other pad groups can be arranged in a vertical direction, but the embodiments are not limited thereto.

[0120] The first pad PAD1 is connected to the first wiring W1. The first pad PAD1 can be connected to its corresponding first wiring W1. The first wiring W1 can be connected to the data line DL of the display area AA.

[0121] The first pad PAD1 can be disposed on the same layer as any one of a plurality of adjacent traces (e.g., first trace W1, second trace W2, and fourth trace W4). The first pad PAD1 can be made of the same material as any one of the adjacent traces (e.g., first trace W1, second trace W2, and fourth trace W4).

[0122] The first pad PAD1 is connected to the anisotropic conductive film 103. Figure 6 ) is connected to the driver chip 107. Thus, the bump 105 ( ) provided on the driver chip 107 Figure 6 ) and the first pad PAD1 are connected through anisotropic conductive film 103 ( Figure 6 Electrical connection.

[0123] The first pad PAD1 can be connected to its respective bump 105. Therefore, the first pad PAD1 can receive voltages and / or signals applied to the driver chip 107 through the bump 105.

[0124] like Figure 5As shown, the second pad PAD2 can be set up in a single row. Second pads PAD2 set in a row are spaced apart from each other. For example, the second pads PAD2 can be set up in one row, but this disclosure is not limited thereto; the second pads PAD2 can also be set up in two or more rows. The second pads PAD2 can have a short side and a long side.

[0125] The second pad PAD2 is connected to the second trace W2. The second pad PAD2 can be connected to its corresponding second trace W2. The second trace W2 can be connected to an external circuit board (not shown).

[0126] The second pad PAD2 can be disposed on the same layer as any one of the first wiring W1, the second wiring W2, and the fourth wiring W4. The second pad PAD2 can be made of the same material as any one of the first wiring W1, the second wiring W2, and the fourth wiring W4.

[0127] The second pad PAD2 is connected to the driver chip 107 via an anisotropic conductive film 103. Thus, the bumps 105 on the driver chip 107 are electrically connected to the second pad PAD2. The second pad PAD2 can be connected to its respective bump 105. Therefore, the second pad PAD2 can provide external voltage and / or signals to the driver chip 107 through the bumps 105.

[0128] The first pad PAD1 and the second pad PAD2 can have the same stack-up structure.

[0129] The first wiring W1 can be used to connect the first pad PAD1 and a portion of the signal lines (e.g., data lines DL). The first wiring W1 and the fourth wiring W4 can be located on the same layer. The first wiring W1 and the fourth wiring W4 can be made of the same material.

[0130] The second wiring W2 is disposed at one end of the display panel 110 and is used to connect the second pad PAD2 and an external circuit board (not shown). For example, the external circuit board may be a flexible printed circuit board (FPC). The second wiring W2 may be disposed along the direction intersecting the long side of the driver chip 107.

[0131] The second wiring W2 and the first wiring W1 can be located on the same layer. The second wiring W2 and the first wiring W1 can be made of the same material.

[0132] The fourth wiring W4 can be positioned along the direction intersecting the short side of the driver chip 107. The fourth wiring W4 can be a multiplexer driver line or a test line. The fourth wiring W4 can be positioned on the same layer as the first wiring W1 or the second wiring W2. The fourth wiring W4 and the first wiring W1 or the second wiring W2 can be made of the same material.

[0133] refer to Figure 6 and Figure 7 An anisotropic conductive film 103 is disposed between the driver chip 107 and the pad PAD.

[0134] The anisotropic conductive film 103 includes an adhesive member 101 and a plurality of conductive balls 102. The adhesive member 101 enables the driver chip 107 to be attached to the display panel 110, and the conductive balls 102 are irregularly distributed in the adhesive member 101 so that the driver chip 107 is electrically connected to the first pad PAD1.

[0135] The conductive ball 102 can be a particle that uses only conductive particles, a polymer resin particle coated with a metal layer, or a particle in which insulating resin is coated onto the surface of conductive particles or the surface of particles coated with a metal layer. For example, the metal layer can be made of a material such as nickel (Ni), gold (Au), etc.

[0136] The substrate 111 of the non-display area NA has the form of the substrate 111 of the display area AA extending to the non-display area NA, and is formed of a flexible plastic material so that it can have flexible properties.

[0137] The substrate 111 of the non-display area NA may have a multilayer stacked structure including a first flexible substrate 1111 and a second flexible substrate 1112, with an intermediate layer 117 located between the first flexible substrate 1111 and the second flexible substrate 1112. Alternatively, according to one embodiment, the first flexible substrate 1111, the second flexible substrate 1112, and the intermediate layer 117 may be referred to as a first flexible insulating film 1111, a second flexible insulating film 1112, and an insulating intermediate layer 117, but the embodiment is not limited thereto.

[0138] A first flexible substrate 1111 can form the upper surface of substrate 111, and a second flexible substrate 1112 can form the lower surface of substrate 111. A first flexible substrate 1111 and a second flexible substrate 1112 comprising polyimide can be provided.

[0139] The intermediate layer 117 disposed between the first flexible substrate 1111 and the second flexible substrate 1112 may contain an inorganic insulating material. For example, the intermediate layer 117 containing an inorganic insulating material may be disposed between the first flexible substrate 1111 containing polyimide and the second flexible substrate 1112 containing polyimide.

[0140] The intermediate layer 117 can be configured not to overlap with at least one edge portion of the driver chip 107 within the non-display area NA. The intermediate layer 117 may also not overlap with the edge of the lower surface of the driver chip 107. The intermediate layer 117 is disposed within the substrate 111 so as not to overlap with all four sides of the lower surface of the driver chip 107.

[0141] Specifically, the intermediate layer 117 can be configured not to overlap with the edge of at least one side of the driver chip 107 and the area between the outermost pads of the plurality of pads 105. Furthermore, the intermediate layer 117 can be configured not to overlap with the edge of at least one side of the driver chip 107 and the area between the outermost bumps 105 of the plurality of bumps 105. For example, the intermediate layer 117 can be configured not to extend into the area between the lateral edge of the driver chip 107 and the outermost edge of the corresponding plurality of pads 105. For example, the intermediate layer 117 can have an opening corresponding to the area between the edge of the driver chip 107 and the outermost pad and its corresponding bump.

[0142] The inorganic insulating material constituting the intermediate layer 117 may include silicon nitride (SiN). x ) or silicon oxide (SiO) x ).

[0143] For example, when the intermediate layer 117 contains silicon oxide (SiO2) x When the intermediate layer 117 has a lower rate of moisture transfer from the outside than the first flexible substrate 1111 and the second flexible substrate 1112 containing polyimide, the effect of moisture from the outside on the components on the substrate can be prevented or minimized.

[0144] When the intermediate layer 117 contains silicon oxide (SiO) x When the intermediate layer 117 is bonded to the oxygen (O) of the intermediate layer 117 and the hydrogen (H) of the first flexible substrate 1111 and the second flexible substrate 1112 containing polyimide, the adhesion can be enhanced.

[0145] refer to Figure 8 and Figure 9 The intermediate layer 117 may include a plurality of interlayer patterns 117P disposed between the first flexible substrate 1111 and the second flexible substrate 1112 in the area where the driver chip 107 is mounted.

[0146] Interlayer pattern 117P can be disposed between the first flexible substrate 1111 and the second flexible substrate 1112 to overlap with the plurality of pads (PADs) corresponding to the driver chip 107 disposed on the substrate 111, but not to overlap with the gaps between the pads (PADs). For example, interlayer pattern 117P can be disposed between the first flexible substrate 1111 and the second flexible substrate 1112 and aligned with and overlapped with the plurality of pads (PADs), while avoiding gaps between the pads. Interlayer pattern 117P can correspond one-to-one with the pads, but the embodiments are not limited thereto.

[0147] In addition, the interlayer pattern 117P can be disposed between the first flexible substrate 1111 and the second flexible substrate 1112 so as to overlap with the plurality of bumps 105 of the driving chip 107, but not with the gap between the bumps 105.

[0148] The interlayer pattern 117P can be set to correspond to the respective bump 105, or it can be set to correspond to the respective pad PAD.

[0149] When the first flexible substrate 1111 and the second flexible substrate 1112 contain polyimide, due to the properties of polyimide, the first flexible substrate 1111 and / or the second flexible substrate 1112 may be charged, and this charge may move to the outside of the substrate 111 or to the metal.

[0150] According to the present disclosure, the substrate 111 can be configured such that an intermediate layer 117 or interlayer pattern 117P including a silicon oxide film is disposed within the substrate 111 between a first flexible substrate 1111 and a second flexible substrate 1112 to correspond to the bumps 105 or pads of the driver chip 107, preventing charges in the substrate 111 from moving to the metal pads or to the outside of the substrate 111.

[0151] Specifically, by combining the oxygen in the intermediate layer 117 or interlayer pattern 117P, which includes a silicon oxide film, with the charge in the first flexible substrate 1111 or the second flexible substrate 1112, charge flow into the driver chip 107 can be prevented, and the reliability degradation of the driver chip 107 due to charge can be minimized.

[0152] The interlayer pattern 117P can be disposed on the same layer as the intermediate layer 117 disposed inside the substrate 111 in the display area, or it can be formed of the same material as the intermediate layer 117.

[0153] The interlayer patterns 117P can be spaced apart from each other, such that the first flexible substrate 1111 is exposed between the interlayer patterns 117P. The first flexible substrate 1111 and the second flexible substrate 1112 can be in direct contact with each other between the interlayer patterns 117P. For example, the interlayer patterns 117P can be spaced apart from each other, defining an area where the first flexible substrate 1111 and the second flexible substrate 1112 can be in direct contact with each other.

[0154] In the region where the intermediate layer 117 and the interlayer pattern 117P are provided, the first flexible substrate 1111 and the second flexible substrate 1112 are connected through the intermediate layer 117 and the interlayer pattern 117P. In the region where the intermediate layer 117 and the interlayer pattern 117P are not provided, the first flexible substrate 1111 and the second flexible substrate 1112 are directly connected to each other.

[0155] Specifically, on the outside of the driver chip 107, the first flexible substrate 1111 and the second flexible substrate 1112 are connected by an intermediate layer 117, and in the area that overlaps with at least one edge portion of the lower surface of the driver chip 107, the first flexible substrate 1111 and the second flexible substrate 1112 are in direct contact with each other.

[0156] The intermediate layer 117 and the interlayer pattern 117P are not disposed on the edge portion of the driver chip 107 so as not to overlap with the lower surface of one edge of the driver chip 107 in the region where the driver chip 107 is disposed, or with the outermost pad PAD or bump 105 in the pad PAD or bump 105. For example, the intermediate layer 117 may have an opening that overlaps with or corresponds to the edge portion of the driver chip 107.

[0157] Since the driver chip 107 is electrically connected to the first pad PAD1 through the conductive ball 102, pressure is applied when the driver chip 107 is installed, so that the conductive ball 102 contacts the bump 105 and the first pad PAD1.

[0158] Since the intermediate layer 117 and the interlayer pattern 117P do not overlap with the four sides or outer periphery of the lower surface of the driver chip 107, film peeling of the intermediate layer 117 inside the substrate 111 due to bonding pressure or extrusion applied to the edge portion of the driver chip 107 during mounting of the driver chip 107 can be reduced, and cracking of the edge portion of the driver chip 107 can be prevented. In other words, arranging the intermediate layer 117 and the interlayer pattern 117P away from the outer periphery of the driver chip 107 can reduce the risk of film peeling or detachment within the substrate 111 and prevent cracking of the driver chip edge, which could otherwise be caused by bonding pressure applied during mounting (e.g., a flexible buffer area can be provided around the driver chip).

[0159] The display device 100 according to this disclosure can be configured such that the intermediate layer 117 and the interlayer pattern 117P are set to not overlap with the four sides of the lower surface of the driving chip 107, to prevent film peeling and cracking, thereby reducing moisture penetration and deformation of the display panel 110, and thus improving robustness and durability.

[0160] The first flexible substrate 1111 and the second flexible substrate 1112, which correspond to the edge region of the driver chip 107, can be in direct contact with each other.

[0161] The additional interlayer pattern 117P can be disposed in the substrate 111 corresponding to the edge portion of the driver chip 107 and the area between the bumps. In this way, the width and size of the additional interlayer pattern 117P can be smaller than the width and size of the interlayer pattern 117P disposed corresponding to the bump 105 or the pad PAD.

[0162] In this way, multiple additional interlayer patterns 117P can be disposed inside the substrate 111. The gap between the interlayer patterns 117P corresponding to the bumps 105 or pads can be greater than the gap between the additional interlayer patterns 117P disposed corresponding to the edge portion of the driver chip 107 and the area between the bumps 105.

[0163] The additional interlayer pattern 1 17P is not provided in the area corresponding to the edge portion of the driver chip 107, thereby reducing the film peeling of the intermediate layer 117 inside the substrate 111 due to the bonding pressure or extrusion applied to the edge portion of the driver chip 107 during the mounting of the driver chip 107 (e.g., providing an area with more elasticity or buffering around the driver chip 107).

[0164] The additional interlayer pattern 117P can be used to disperse stress caused by bonding pressure at the edge portion of the driver chip 107, and can change the cracking path inside the substrate 111 so that even if cracking occurs, the crack can be prevented or minimized from extending into the interior.

[0165] In the display device 100 according to the present disclosure, the intermediate layer 117 is not disposed along the edge of the lower surface of the driving chip 107, and a plurality of interlayer patterns 117P are disposed in other areas to minimize cracking and prevent crack propagation and moisture penetration, thereby improving reliability.

[0166] The display device 100 according to this disclosure can minimize the occurrence of defects in the display device, thereby reducing energy consumption in the production of the display device and reducing the use of hazardous or regulated materials, thus facilitating the realization of recycling and environmentally friendly display devices.

[0167] refer to Figure 10 and Figure 11 According to the present disclosure, the display device 100 may further include a plurality of anti-crack patterns CPP disposed in the non-display area NA of the substrate 111.

[0168] The anti-crack pattern CPP is spaced apart from the driver chip 107 and the anisotropic conductive film 103, and is disposed on the insulating film 120. The anti-crack pattern CPP is disposed on the insulating film 120 so as to overlap with the intermediate layer 117 in the region adjacent to the driver chip 107.

[0169] Here, the insulating film 120 may have the same stacked structure as the insulating film 120 disposed in the display area AA, or it may have a structure that omits at least one layer of the insulating film 120 disposed in the display area AA.

[0170] The anti-crack pattern CPP can be spaced apart from the driver chip 107 along a direction parallel to the short side of the driver chip 107, and can be disposed within the non-display area NA of the display panel 110. The length of the long side of the anti-crack pattern CPP can be less than the length of the short side of the driver chip 107, but the embodiment is not limited to this.

[0171] The anti-crack pattern CPP overlaps with the intermediate layer 117, is spaced apart from the first pad PAD1 and the second pad PAD2 to avoid overlapping with them, and is spaced apart from the edge of a short side of the driver chip 107. The anti-crack pattern CPP can be formed in the form of an embossed pattern based on the upper surface of the substrate 111 of the display panel 110.

[0172] As described above, since the IC-form driver chip 107 is attached to the substrate 111 using the COP method, an indentation test or similar procedure is performed to check the connection status of the driver chip 107. Furthermore, a relatively high pressure must be applied when attaching the driver chip 107 to the substrate 111 to prevent poor connection of the driver chip 107. According to this disclosure, the anti-crack pattern CPP is positioned adjacent to the short side of the driver chip 107 where stress may occur due to pressure or other factors during installation. This reduces deformation of the display panel 110 caused by stress during driver chip installation or cracking caused by interference from the driver chip 107.

[0173] The anti-crack pattern CPP according to this disclosure can be used to prevent cracking around the driver chip 107 when bonding the driver chip 107, thereby preventing moisture penetration due to cracks and film peeling of the surrounding insulating film due to moisture penetration, and also preventing cracking of the surrounding insulating film due to film peeling.

[0174] The anti-crack pattern CPP disclosed herein can be used to prevent the insulating film surrounding the driver chip 107 from cracking, thereby preventing corrosion or cracking of the surrounding pads PAD1, PAD2 or multiple wirings W1, W2, W4 due to moisture penetration caused by cracks in the insulating film.

[0175] The anti-crack pattern CPP disclosed herein can be used to prevent cracking and moisture penetration, thereby reducing deformation of the display panel 110.

[0176] The anti-crack pattern CPP may contain metal. When the anti-crack pattern CPP containing metal is provided, rigidity can be ensured to support the pressure applied when the driver chip 107 is installed, thereby more effectively preventing cracking around the driver chip 107 and reducing deformation of the display panel 110.

[0177] The anti-crack pattern CPP may contain the same material as the source / drain or gate of the transistor TR constituting the display area AA. The anti-crack pattern CPP and the pad PAD of the non-display area NA may be disposed on the same layer or may contain the same material. The anti-crack pattern CPP and any one of the wirings W1, W2, W4 disposed in the non-display area NA may be disposed on the same layer or may be made of the same material.

[0178] In this way, when the anti-crack pattern CPP is set by the same process as that used to form the pads PAD or wiring W1, W2, W4 of the electrodes set in the display area AA or the non-display area NA, the number of manufacturing steps of the display device can be reduced, thereby reducing energy consumption during the manufacturing process and reducing greenhouse gas generation, thus achieving ESG (Environmental, Social and Governance) goals.

[0179] The anti-crack pattern CPP is set using electrode or wiring technology, but it is floating, so that no voltage or signal is applied. The anti-crack pattern CPP may be covered with an insulating material 149. The insulating material 149 may be combined with the organic film 140 disposed within the display area AA. Figure 4 At least one of the layers of the stacked material is disposed in the same layer, or may contain the same material.

[0180] Features of the various embodiments of this disclosure may be combined or integrated with each other in whole or in part, and may interoperate with and be technically driven by each other in various ways. Embodiments of this disclosure may be performed independently of each other, or may be performed together in a mutually dependent manner.

[0181] As can be clearly seen from the above, according to the embodiments of this disclosure, the intermediate layer or interlayer pattern can be disposed between the first flexible substrate and the second flexible substrate so as to overlap with the bumps or pads of the driver chip, prevent charge from flowing into the driver chip, and mitigate the degradation of component reliability due to accumulated charge.

[0182] According to embodiments of this disclosure, the intermediate layer and interlayer pattern can be disposed between the first flexible substrate and the second flexible substrate so as not to overlap with the edge portion of at least one side of the driving chip, thereby minimizing cracking and preventing crack propagation and moisture penetration, thus improving reliability.

[0183] According to embodiments of this disclosure, an intermediate layer may be disposed between a first flexible substrate and a second flexible substrate so as not to overlap with the four sides of the lower surface of the driver chip, thereby reducing substrate peeling defects and display panel deformation, thus providing a stable display device and improving the durability of the display device.

[0184] The display devices according to the embodiments of this disclosure use the same process setup, which can minimize the occurrence of defects in the display devices, reduce the energy consumption in the production of display devices, and reduce the use of hazardous or regulated materials, thus facilitating the realization of recycling and environmentally friendly display devices.

[0185] The embodiments described herein are for illustrative purposes only and not for limiting the scope of this disclosure. This disclosure is not limited to the embodiments and accompanying drawings. The features, structures, effects, etc., exemplified in the various embodiments can be implemented through combinations or modifications. Therefore, such combinations and modifications should be interpreted as being within the scope of this disclosure.

Claims

1. A display device, comprising: A substrate having a display area and a non-display area, and comprising a first flexible substrate, an intermediate layer, and a second flexible substrate; A transistor and a light-emitting device, wherein the transistor and the light-emitting device are disposed in the display area; as well as The driver chip is located in the non-display area. The intermediate layer is disposed between the first flexible substrate and the second flexible substrate, and is configured not to overlap with the edge portion of at least one side of the driver chip in the non-display area.

2. The display device according to claim 1, wherein, The intermediate layer is disposed inside the substrate in a manner that does not overlap with the four sides of the lower surface of the driver chip.

3. The display device according to claim 1, further comprising: The pads are disposed on the substrate in the area where the driver chip is located; as well as The bumps, corresponding to the pads, are disposed below the driver chip. The intermediate layer is configured not to overlap with the area between at least one edge of the driver chip and the outermost pad among a plurality of pads, or The intermediate layer is configured not to overlap with the area between the edge of at least one side of the driver chip and the outermost bump among the plurality of bumps.

4. The display device according to claim 1, wherein, The intermediate layer includes multiple interlayer patterns disposed between the first flexible substrate and the second flexible substrate in the region where the driver chip is mounted.

5. The display device according to claim 4, wherein, The plurality of interlayer patterns are disposed between the first flexible substrate and the second flexible substrate, and The multiple interlayer patterns overlap with the multiple bumps of the driver chip but do not overlap with the gaps between the multiple bumps.

6. The display device according to claim 4, wherein, The plurality of interlayer patterns are disposed between the first flexible substrate and the second flexible substrate, and The multiple interlayer patterns overlap with the multiple pads disposed on the substrate corresponding to the driver chip, but do not overlap with the gaps between the multiple pads.

7. The display device according to claim 4, wherein, The intermediate layer or the plurality of interlayer patterns comprise silicon oxide.

8. The display device according to claim 1, wherein, The first flexible substrate and the second flexible substrate are connected to each other through the intermediate layer in the outer region of the driving chip, and are in direct contact with each other in the region where they overlap with at least one edge portion of the lower surface of the driving chip.

9. The display device according to claim 1, further comprising: An insulating film comprising multiple layers stacked on top of each other in the non-display area of ​​the substrate; An anisotropic conductive film is disposed between the driving chip and the insulating film; as well as Multiple anti-crack patterns are disposed on the insulating film, and the multiple anti-crack patterns are spaced apart from the driving chip and the anisotropic conductive film.

10. The display device according to claim 9, wherein, The multiple anti-crack patterns overlap with the intermediate layer.

11. The display device according to claim 9, wherein, The plurality of anti-crack patterns are raised and recessed patterns containing metal.

12. The display device according to claim 9, wherein, The plurality of anti-crack patterns contain the same material as the material in the source / drain or gate of the transistor at the display area.

13. The display device according to claim 9, wherein, The plurality of anti-crack patterns are disposed on the same layer as the pads disposed on the substrate, or the plurality of anti-crack patterns contain the same material as the pads.

14. The display device according to claim 9, further comprising: The first pad is provided in the area where the driver chip is located, in the direction toward the display area; as well as The second pad is disposed in the region where the driver chip is located, in a direction opposite to the direction toward the display area, and faces the first pad. The plurality of anti-crack patterns overlap with the intermediate layer, are spaced apart from the first and second pads in a manner that does not overlap with the first and second pads, and are spaced apart from the edge of a short side of the driver chip.

15. The display device according to claim 1, wherein, The transistor disposed in the display area comprises an oxide semiconductor.

16. A display device, comprising: Multiple subpixels are configured to display an image; The driving chip is spaced apart from the plurality of sub-pixels; A first flexible layer is disposed below the plurality of sub-pixels and the driving chip; A second flexible layer is disposed on the first flexible layer; as well as An intermediate layer is disposed between the first flexible layer and the second flexible layer. The intermediate layer includes at least one opening corresponding to the edge of the driver chip.

17. The display device according to claim 16, wherein, The at least one opening in the intermediate layer is a single continuous opening corresponding to the entire outer periphery of the driver chip.

18. The display device according to claim 16, further comprising: Multiple pads are disposed on the second flexible layer and configured to be electrically connected to the driver chip. Wherein, the at least one opening in the intermediate layer extends from the edge of the driver chip to the edge of the outermost pad among the plurality of pads.

19. The display device according to claim 16, further comprising: Multiple anti-crack patterns are disposed adjacent to the driving chip, and the multiple anti-crack patterns contain metallic material.

20. The display device according to claim 16, further comprising: Multiple pads are disposed on the second flexible layer and configured to be electrically connected to the driver chip. The intermediate layer includes multiple openings corresponding to multiple gaps between the multiple pads.

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